From 4350a1fa00d6185fec28f2dfad44f83564ee6fca Mon Sep 17 00:00:00 2001 From: Jyotheeswar Reddy Date: Sun, 12 Apr 2015 20:24:22 -0700 Subject: [PATCH] sw_apps:zynqmp_pmufw: Clear IPI0 status register during core init swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db IPI0 is used by PMUFW for PM requests and the mask is used for determining the Master. There are chances of IPIs being triggered before FW Init but un-handled or even bits that are not cleared by ROM, causing a corruption of the ISR mask. So PMUFW should cleanup these bits during startup Signed-off-by: Jyotheeswar Reddy --- lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c index 9c90fc81..f2418ec7 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c @@ -90,7 +90,8 @@ XStatus XPfw_CoreConfigure(void) /* We are ready to take interrupts now */ CorePtr->IsReady = CORE_IS_READY; - /* FIXME: Enable IPI0 for PM-> Do it elsewhere */ + /* FIXME: Clear IPI0 status and Enable IPI0 for PM-> Do it elsewhere */ + XPfw_Write32(IPI_PMU_0_ISR, MASK32_ALL_HIGH); XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK); XPfw_InterruptStart(); #ifdef ENABLE_PM /* ENABLE_PM */