diff --git a/ThirdParty/sw_services/lwip141/data/lwip141.tcl b/ThirdParty/sw_services/lwip141/data/lwip141.tcl
index 205ac56b..4e0f2e3d 100644
--- a/ThirdParty/sw_services/lwip141/data/lwip141.tcl
+++ b/ThirdParty/sw_services/lwip141/data/lwip141.tcl
@@ -877,7 +877,15 @@ proc update_axi_ethernet_topology {emac processor topologyvar} {
 
 	# find intc to which the interrupt line is connected
 	set emac_intr_port [hsi::get_pins -of_objects [hsi::get_cells -hier $emac] INTERRUPT]
-    set intc_handle [::hsi::utils::get_connected_intr_cntrl $emac $emac_intr_port]
+       set intc_handle [::hsi::utils::get_connected_intr_cntrl $emac $emac_intr_port]
+       if { $intc_handle == "" } {
+               set topology(intc_baseaddr) "0x0"
+               set topology(scugic_baseaddr) "0x0"
+               set topology(scugic_emac_intr) "0x0"
+               puts "Info: Target Periph Interrupt is not connected to interrupt controller"
+               return
+       }
+
     set intc_periph_type [common::get_property IP_NAME $intc_handle]
     set intc_name [common::get_property NAME $intc_handle]
     set proc_connected_periphs [::hsm::utils::get_proc_slave_periphs $processor]
diff --git a/ThirdParty/sw_services/lwip141/src/ChangeLog b/ThirdParty/sw_services/lwip141/src/ChangeLog
index e72b6c50..a57a77d0 100644
--- a/ThirdParty/sw_services/lwip141/src/ChangeLog
+++ b/ThirdParty/sw_services/lwip141/src/ChangeLog
@@ -1,7 +1,7 @@
 Change Log for lwip
 =================================
-2015-07-19
-	* Add support for Zynq Ultrascale MPSoC emacps
+2015-07-15
+	* Add Support for Axi ethernet with fifo on zynq.
 2015-06-15
 	* Update the lwip tcl for Hier IP(To support User parameters).
 2015-05-15
diff --git a/ThirdParty/sw_services/lwip141/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c b/ThirdParty/sw_services/lwip141/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c
index 9dbdb938..d3df1401 100644
--- a/ThirdParty/sw_services/lwip141/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c
+++ b/ThirdParty/sw_services/lwip141/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c
@@ -42,7 +42,19 @@
 #include "netif/xadapter.h"
 #include "netif/xaxiemacif.h"
 
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#include "xscugic.h"
+#else
 #include "xintc_l.h"
+#endif
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#define AXIFIFO_INTR_PRIORITY_SET_IN_GIC	0xA0
+#define AXIETH_INTR_PRIORITY_SET_IN_GIC		0xA0
+#define TRIG_TYPE_RISING_EDGE_SENSITIVE		0x3
+#define INTC_DIST_BASE_ADDR	XPAR_SCUGIC_DIST_BASEADDR
+#endif
+
 #include "xstatus.h"
 
 #include "xaxiemacif_fifo.h"
@@ -205,6 +217,29 @@ XStatus init_axi_fifo(struct xemac_s *xemac)
 	/* enable fifo interrupts */
 	XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
 
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+	XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+				xaxiemacif->axi_ethernet.Config.TemacIntr,
+				(XInterruptHandler)xaxiemac_error_handler,
+				&xaxiemacif->axi_ethernet);
+	XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+				xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+				(XInterruptHandler)xllfifo_intr_handler,
+				xemac);
+	XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+			xaxiemacif->axi_ethernet.Config.TemacIntr,
+			AXIETH_INTR_PRIORITY_SET_IN_GIC,
+			TRIG_TYPE_RISING_EDGE_SENSITIVE);
+	XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+			xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+			AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
+			TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+	XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+				xaxiemacif->axi_ethernet.Config.TemacIntr);
+	XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+				xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
+#else
 #if NO_SYS
 #if XPAR_INTC_0_HAS_FAST == 1
 	/* Register temac interrupt with interrupt controller */
@@ -255,6 +290,7 @@ XStatus init_axi_fifo(struct xemac_s *xemac)
 			(XInterruptHandler)xllfifo_intr_handler,
 			xemac);
 	enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
+#endif
 #endif
 
 	return 0;