diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/annotated.html
index 1bb08698..6597137c 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/annotated.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/annotated.html
@@ -42,4 +42,4 @@
XDp_TxTopology | |
XDp_TxTopologyNode | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/files.html
index 0b0df822..94067cfd 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/files.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/files.html
@@ -32,4 +32,4 @@
xdp_sinit.c | |
xdp_spm.c | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions.html
index 77baee89..7b40f77d 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions.html
@@ -107,7 +107,11 @@ Here is a list of all class members with links to the classes they belong to:
: XDp_TxMainStreamAttributesInputPort
: XDp_TxSbMsgLinkAddressReplyPortDetailIntrBwChangeCallbackRef
: XDp_RxIntrBwChangeHandler
-: XDp_RxIntrNoVideoCallbackRef
+: XDp_RxIntrExtPktCallbackRef
+: XDp_RxIntrExtPktHandler
+: XDp_RxIntrInfoPktCallbackRef
+: XDp_RxIntrInfoPktHandler
+: XDp_RxIntrNoVideoCallbackRef
: XDp_RxIntrNoVideoHandler
: XDp_RxIntrPowerStateCallbackRef
: XDp_RxIntrPowerStateHandler
@@ -229,4 +233,4 @@ Here is a list of all class members with links to the classes they belong to:
: XDp_TxMainStreamAttributesYCrCbEn
: XDp_ConfigYOnlyEn
: XDp_Config
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions_vars.html
index b8a43439..45a76336 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions_vars.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/functions_vars.html
@@ -107,7 +107,11 @@
: XDp_TxMainStreamAttributesInputPort
: XDp_TxSbMsgLinkAddressReplyPortDetailIntrBwChangeCallbackRef
: XDp_RxIntrBwChangeHandler
-: XDp_RxIntrNoVideoCallbackRef
+: XDp_RxIntrExtPktCallbackRef
+: XDp_RxIntrExtPktHandler
+: XDp_RxIntrInfoPktCallbackRef
+: XDp_RxIntrInfoPktHandler
+: XDp_RxIntrNoVideoCallbackRef
: XDp_RxIntrNoVideoHandler
: XDp_RxIntrPowerStateCallbackRef
: XDp_RxIntrPowerStateHandler
@@ -229,4 +233,4 @@
: XDp_TxMainStreamAttributesYCrCbEn
: XDp_ConfigYOnlyEn
: XDp_Config
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals.html
index 846751a9..a5cebf59 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals.html
@@ -47,4 +47,4 @@ Here is a list of all file members with links to the files they belong to:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x72.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x72.html
index e2fa55f4..f4609bcb 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x72.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x72.html
@@ -47,4 +47,4 @@ Here is a list of all file members with links to the files they belong to:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x74.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x74.html
index ca99eb2c..4bdd4729 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x74.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x74.html
@@ -48,4 +48,4 @@ Here is a list of all file members with links to the files they belong to:
TxResetValues
: xdp_selftest.cTxResetValuesMsa
: xdp_selftest.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x78.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x78.html
index 28cc41ff..0e7d5e9b 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x78.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_0x78.html
@@ -47,10 +47,10 @@ Here is a list of all file members with links to the files they belong to:
- XDP_AUX_MAX_DEFER_COUNT
: xdp.c
- XDP_AUX_MAX_TIMEOUT_COUNT
-: xdp.c
- XDp_CfgGetCoreType
-: xdp.h
- XDp_CfgInitialize()
+: xdp.c
- XDp_CfgInitialize()
: xdp.h, xdp.c
- XDp_ConfigTable
-: xdp_sinit.c
- XDP_DPCD_ADAPTER_CAP
+: xdp_sinit.c
- XDp_CoreType
+: xdp.h
- XDP_DPCD_ADAPTER_CAP
: xdp_hw.h
- XDP_DPCD_ADAPTER_CTRL
: xdp_hw.h
- XDP_DPCD_ADJ_REQ_LANE_0_1
: xdp_hw.h
- XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK
@@ -359,7 +359,8 @@ Here is a list of all file members with links to the files they belong to:
: xdp_hw.h
- XDP_EDID_EXT_BLOCK_TAG
: xdp_hw.h
- XDP_EDID_EXT_BLOCK_TAG_DISPID
: xdp_hw.h
- XDP_EDID_PTM
-: xdp_hw.h
- XDp_In32
+: xdp_hw.h
- XDp_GetCoreType
+: xdp.h
- XDp_In32
: xdp_hw.h
- XDp_Initialize()
: xdp.h, xdp.c
- XDp_InterruptHandler()
: xdp_intr.c, xdp.h
- XDp_IntrHandler
@@ -368,7 +369,7 @@ Here is a list of all file members with links to the files they belong to:
: xdp_sinit.c, xdp.h
- XDp_Out32
: xdp_hw.h
- XDp_ReadReg
: xdp_hw.h
- XDP_RX
-: xdp.h
- XDP_RX_AUDIO_CONTROL
+: xdp.h
- XDP_RX_AUDIO_CONTROL
: xdp_hw.h
- XDP_RX_AUDIO_EXT_DATA
: xdp_hw.h
- XDP_RX_AUDIO_INFO_DATA
: xdp_hw.h
- XDP_RX_AUDIO_MAUD
@@ -656,14 +657,19 @@ Here is a list of all file members with links to the files they belong to:
: xdp_hw.h
- XDP_RX_VERSION_CORE_VER_REV_SHIFT
: xdp_hw.h
- XDP_RX_VERSION_INTER_REV_MASK
: xdp_hw.h
- XDP_RX_VIDEO_UNSUPPORTED
-: xdp_hw.h
- XDp_RxCheckLinkStatus()
+: xdp_hw.h
- XDp_RxAudioDis()
+: xdp.h, xdp.c
- XDp_RxAudioEn()
+: xdp.h, xdp.c
- XDp_RxAudioReset()
+: xdp.h, xdp.c
- XDp_RxCheckLinkStatus()
: xdp.h, xdp.c
- XDp_RxDtgDis()
: xdp.h, xdp.c
- XDp_RxDtgEn()
: xdp.h, xdp.c
- XDp_RxGenerateHpdInterrupt()
: xdp_intr.c, xdp.h
- XDp_RxInterruptDisable()
: xdp_intr.c, xdp.h
- XDp_RxInterruptEnable()
: xdp_intr.c, xdp.h
- XDp_RxSetIntrBwChangeHandler()
-: xdp_intr.c, xdp.h
- XDp_RxSetIntrNoVideoHandler()
+: xdp_intr.c, xdp.h
- XDp_RxSetIntrExtPktHandler()
+: xdp_intr.c, xdp.h
- XDp_RxSetIntrInfoPktHandler()
+: xdp_intr.c, xdp.h
- XDp_RxSetIntrNoVideoHandler()
: xdp_intr.c, xdp.h
- XDp_RxSetIntrPowerStateHandler()
: xdp_intr.c, xdp.h
- XDp_RxSetIntrTp1Handler()
: xdp_intr.c, xdp.h
- XDp_RxSetIntrTp2Handler()
@@ -681,7 +687,7 @@ Here is a list of all file members with links to the files they belong to:
: xdp_selftest.c, xdp.h
- XDp_SetUserTimerHandler()
: xdp.h, xdp.c
- XDp_TimerHandler
: xdp.h
- XDP_TX
-: xdp.h
- XDP_TX_AUDIO_CHANNELS
+: xdp.h
- XDP_TX_AUDIO_CHANNELS
: xdp_hw.h
- XDP_TX_AUDIO_CONTROL
: xdp_hw.h
- XDP_TX_AUDIO_EXT_DATA
: xdp_hw.h
- XDP_TX_AUDIO_INFO_DATA
@@ -869,9 +875,15 @@ Here is a list of all file members with links to the files they belong to:
: xdp_hw.h
- XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_PHY_RESET_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK
-: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK
-: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK
: xdp_hw.h
- XDP_TX_PHY_POSTCURSOR_LANE_0
: xdp_hw.h
- XDP_TX_PHY_POSTCURSOR_LANE_1
@@ -1054,7 +1066,9 @@ Here is a list of all file members with links to the files they belong to:
: xdp_intr.c, xdp.h
- XDp_TxSetLaneCount()
: xdp.h, xdp.c
- XDp_TxSetLinkRate()
: xdp.h, xdp.c
- XDp_TxSetMsaValues()
-: xdp_spm.c, xdp.h
- XDp_TxSetScrambler()
+: xdp_spm.c, xdp.h
- XDp_TxSetPhyPolarityAll()
+: xdp.h, xdp.c
- XDp_TxSetPhyPolarityLane()
+: xdp.h, xdp.c
- XDp_TxSetScrambler()
: xdp.h, xdp.c
- XDp_TxSetStreamSelectFromSinkList()
: xdp_mst.c, xdp.h
- XDp_TxSetStreamSinkRad()
: xdp_mst.c, xdp.h
- XDp_TxSetVideoMode()
@@ -1066,9 +1080,7 @@ Here is a list of all file members with links to the files they belong to:
: xdp.h, xdp.c
- XDp_WriteReg
: xdp_hw.h
- XDPRX
: xdp.h
- XDprx
-: xdp.h
- XDprx_
-: xdp.h
- XDPRX_
-: xdp.h
- XDprx_CfgInitialize
+: xdp.h
- XDprx_CfgInitialize
: xdp.h
- XDprx_Config
: xdp.h
- XDprx_InitializeRx
: xdp.h
- XDprx_InterruptHandler
@@ -1080,14 +1092,11 @@ Here is a list of all file members with links to the files they belong to:
: xdp.h
- XDprx_TimerHandler
: xdp.h
- XDprx_WaitUs
: xdp.h
- XDprx_WriteReg
-: xdp.h
- XDptx
-: xdp.h
- XDPTX
-: xdp.h
- XDPTX_
-: xdp.h
- XDptx_
-: xdp.h
- XDptx_CfgInitialize
+: xdp.h
- XDPTX
+: xdp.h
- XDptx
+: xdp.h
- XDptx_CfgInitialize
: xdp.h
- XDptx_Config
-: xdp.h
- XDPTX_DPCD_
-: xdp.h
- XDptx_HpdEventHandler
+: xdp.h
- XDptx_HpdEventHandler
: xdp.h
- XDptx_HpdInterruptHandler
: xdp.h
- XDptx_HpdPulseHandler
: xdp.h
- XDptx_InitializeTx
@@ -1099,4 +1108,4 @@ Here is a list of all file members with links to the files they belong to:
: xdp.h
- XDptx_WaitUs
: xdp.h
- XDptx_WriteReg
: xdp.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_defs.html
index 1c5cf933..84c7626a 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_defs.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_defs.html
@@ -44,8 +44,7 @@
- XDP_AUX_MAX_DEFER_COUNT
: xdp.c
- XDP_AUX_MAX_TIMEOUT_COUNT
-: xdp.c
- XDp_CfgGetCoreType
-: xdp.h
- XDP_DPCD_ADAPTER_CAP
+: xdp.c
- XDP_DPCD_ADAPTER_CAP
: xdp_hw.h
- XDP_DPCD_ADAPTER_CTRL
: xdp_hw.h
- XDP_DPCD_ADJ_REQ_LANE_0_1
: xdp_hw.h
- XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK
@@ -354,12 +353,12 @@
: xdp_hw.h
- XDP_EDID_EXT_BLOCK_TAG
: xdp_hw.h
- XDP_EDID_EXT_BLOCK_TAG_DISPID
: xdp_hw.h
- XDP_EDID_PTM
-: xdp_hw.h
- XDp_In32
+: xdp_hw.h
- XDp_GetCoreType
+: xdp.h
- XDp_In32
: xdp_hw.h
- XDP_IS_CONNECTED_MAX_TIMEOUT_COUNT
: xdp.c
- XDp_Out32
: xdp_hw.h
- XDp_ReadReg
-: xdp_hw.h
- XDP_RX
-: xdp.h
- XDP_RX_AUDIO_CONTROL
+: xdp_hw.h
- XDP_RX_AUDIO_CONTROL
: xdp_hw.h
- XDP_RX_AUDIO_EXT_DATA
: xdp_hw.h
- XDP_RX_AUDIO_INFO_DATA
: xdp_hw.h
- XDP_RX_AUDIO_MAUD
@@ -648,8 +647,7 @@
: xdp_hw.h
- XDP_RX_VERSION_INTER_REV_MASK
: xdp_hw.h
- XDP_RX_VIDEO_UNSUPPORTED
: xdp_hw.h
- XDP_SEGPTR_ADDR
-: xdp_hw.h
- XDP_TX
-: xdp.h
- XDP_TX_AUDIO_CHANNELS
+: xdp_hw.h
- XDP_TX_AUDIO_CHANNELS
: xdp_hw.h
- XDP_TX_AUDIO_CONTROL
: xdp_hw.h
- XDP_TX_AUDIO_EXT_DATA
: xdp_hw.h
- XDP_TX_AUDIO_INFO_DATA
@@ -837,9 +835,15 @@
: xdp_hw.h
- XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_PHY_RESET_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK
-: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK
-: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK
+: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK
: xdp_hw.h
- XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK
: xdp_hw.h
- XDP_TX_PHY_POSTCURSOR_LANE_0
: xdp_hw.h
- XDP_TX_PHY_POSTCURSOR_LANE_1
@@ -955,9 +959,7 @@
: xdp_hw.h
- XDp_WriteReg
: xdp_hw.h
- XDPRX
: xdp.h
- XDprx
-: xdp.h
- XDprx_
-: xdp.h
- XDPRX_
-: xdp.h
- XDprx_CfgInitialize
+: xdp.h
- XDprx_CfgInitialize
: xdp.h
- XDprx_Config
: xdp.h
- XDprx_InitializeRx
: xdp.h
- XDprx_InterruptHandler
@@ -969,14 +971,11 @@
: xdp.h
- XDprx_TimerHandler
: xdp.h
- XDprx_WaitUs
: xdp.h
- XDprx_WriteReg
-: xdp.h
- XDptx
-: xdp.h
- XDPTX
-: xdp.h
- XDPTX_
-: xdp.h
- XDptx_
-: xdp.h
- XDptx_CfgInitialize
+: xdp.h
- XDPTX
+: xdp.h
- XDptx
+: xdp.h
- XDptx_CfgInitialize
: xdp.h
- XDptx_Config
-: xdp.h
- XDPTX_DPCD_
-: xdp.h
- XDptx_HpdEventHandler
+: xdp.h
- XDptx_HpdEventHandler
: xdp.h
- XDptx_HpdInterruptHandler
: xdp.h
- XDptx_HpdPulseHandler
: xdp.h
- XDptx_InitializeTx
@@ -988,4 +987,4 @@
: xdp.h
- XDptx_WaitUs
: xdp.h
- XDptx_WriteReg
: xdp.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_enum.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_enum.html
index dd06d221..c7cdf800 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_enum.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_enum.html
@@ -35,6 +35,7 @@
-- XDp_TxTrainingState
+
- XDp_CoreType
+: xdp.h
- XDp_TxTrainingState
: xdp.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_eval.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_eval.html
index f3c36c79..a837f5b1 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_eval.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_eval.html
@@ -35,11 +35,13 @@
-- XDP_TX_TS_ADJUST_LANE_COUNT
+
- XDP_RX
+: xdp.h
- XDP_TX
+: xdp.h
- XDP_TX_TS_ADJUST_LANE_COUNT
: xdp.c
- XDP_TX_TS_ADJUST_LINK_RATE
: xdp.c
- XDP_TX_TS_CHANNEL_EQUALIZATION
: xdp.c
- XDP_TX_TS_CLOCK_RECOVERY
: xdp.c
- XDP_TX_TS_FAILURE
: xdp.c
- XDP_TX_TS_SUCCESS
: xdp.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_func.html
index a184d8cd..b5a27fea 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_func.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_func.html
@@ -46,14 +46,19 @@
: xdp.h, xdp.cXDp_Initialize()
: xdp.h, xdp.cXDp_InterruptHandler()
: xdp_intr.c, xdp.hXDp_LookupConfig()
-: xdp_sinit.c, xdp.hXDp_RxCheckLinkStatus()
+: xdp_sinit.c, xdp.hXDp_RxAudioDis()
+: xdp.h, xdp.cXDp_RxAudioEn()
+: xdp.h, xdp.cXDp_RxAudioReset()
+: xdp.h, xdp.cXDp_RxCheckLinkStatus()
: xdp.h, xdp.cXDp_RxDtgDis()
: xdp.h, xdp.cXDp_RxDtgEn()
: xdp.h, xdp.cXDp_RxGenerateHpdInterrupt()
: xdp_intr.c, xdp.hXDp_RxInterruptDisable()
: xdp_intr.c, xdp.hXDp_RxInterruptEnable()
: xdp_intr.c, xdp.hXDp_RxSetIntrBwChangeHandler()
-: xdp_intr.c, xdp.hXDp_RxSetIntrNoVideoHandler()
+: xdp_intr.c, xdp.hXDp_RxSetIntrExtPktHandler()
+: xdp_intr.c, xdp.hXDp_RxSetIntrInfoPktHandler()
+: xdp_intr.c, xdp.hXDp_RxSetIntrNoVideoHandler()
: xdp_intr.c, xdp.hXDp_RxSetIntrPowerStateHandler()
: xdp_intr.c, xdp.hXDp_RxSetIntrTp1Handler()
: xdp_intr.c, xdp.hXDp_RxSetIntrTp2Handler()
@@ -132,7 +137,9 @@
: xdp_intr.c, xdp.hXDp_TxSetLaneCount()
: xdp.h, xdp.cXDp_TxSetLinkRate()
: xdp.h, xdp.cXDp_TxSetMsaValues()
-: xdp_spm.c, xdp.hXDp_TxSetScrambler()
+: xdp_spm.c, xdp.hXDp_TxSetPhyPolarityAll()
+: xdp.h, xdp.cXDp_TxSetPhyPolarityLane()
+: xdp.h, xdp.cXDp_TxSetScrambler()
: xdp.h, xdp.cXDp_TxSetStreamSelectFromSinkList()
: xdp_mst.c, xdp.hXDp_TxSetStreamSinkRad()
: xdp_mst.c, xdp.hXDp_TxSetVideoMode()
@@ -141,4 +148,4 @@
: xdp_mst.c, xdp.hXDp_TxWriteGuid()
: xdp_mst.c, xdp.hXDp_WaitUs()
: xdp.h, xdp.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_type.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_type.html
index 0ca6fe13..d37f84bb 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_type.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_type.html
@@ -38,4 +38,4 @@
XDp_IntrHandler
: xdp.hXDp_TimerHandler
: xdp.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_vars.html
index da3bf9a3..dda1a1c9 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_vars.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/globals_vars.html
@@ -41,4 +41,4 @@
: xdp_selftest.cTxResetValuesMsa
: xdp_selftest.cXDp_ConfigTable
: xdp_sinit.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/index.html
index 6c866924..883e0915 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/index.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/index.html
@@ -68,7 +68,8 @@ MST testing has been done at all possible link rate/lane count/topology/ resolut
Link rate: 1.62, 2.70, and 5.40Gbps per lane.Lane count: 1, 2, and 4 lanes.Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain configuration and in a configuration using a combination of a 1-to-3 hub and daisy-chain. Each stream was using the same resolution.Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024, 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.Color depths: 18, 24, 30, 36, and 48 bits per pixel.
Audio
-The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence in the TX mode of operation. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.
+The driver in RX mode of operation may received audio info and extension packets. When this happens, if interrupts are enabled, the appropriate handlers will be invoked. Control functions are available for enabling, disabling, and resetting audio in the DisplayPort RX core.
+The TX driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence in the TX mode of operation. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.
Asserts
Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.
Limitations: TX mode of operation
@@ -80,5 +81,5 @@ Asserts are used within all Xilinx drivers to enforce constraints on argument va
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
- 1.0 als 01/20/15 Initial release.
-
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+ 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
+ Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html
index 8b710a54..fc6e7ae0 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html
@@ -28,4 +28,4 @@
TxInstance | XDp | |
UserTimerPtr | XDp | |
UserTimerWaitUs | XDp | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp.html
index 98784329..3a1a7655 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp.html
@@ -154,4 +154,4 @@ Custom user function for delay/sleep.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction-members.html
index b9e0b35f..1d741f08 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction-members.html
@@ -26,4 +26,4 @@
CmdCode | XDp_AuxTransaction | |
Data | XDp_AuxTransaction | |
NumBytes | XDp_AuxTransaction | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction.html
index d48e3e44..69c05219 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___aux_transaction.html
@@ -99,4 +99,4 @@ The number of bytes that the AUX transaction will perform work on.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config-members.html
index 71b107f0..3dc6977b 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config-members.html
@@ -39,4 +39,4 @@
SecondaryChEn | XDp_Config | |
YCrCbEn | XDp_Config | |
YOnlyEn | XDp_Config | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config.html
index bafdfb53..ffdbc93d 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___config.html
@@ -322,4 +322,4 @@ YOnly format support by this core instance.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx-members.html
index 84e7f62d..6f93d329 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx-members.html
@@ -24,6 +24,10 @@
XDp_Rx Member List
This is the complete list of members for XDp_Rx, including all inherited members.Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx.html
index 280126f7..c4c74760 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx.html
@@ -55,6 +55,14 @@ The XDp driver instance data represent
void * | IntrVideoCallbackRef |
+XDp_IntrHandler | IntrInfoPktHandler |
+
+void * | IntrInfoPktCallbackRef |
+
+XDp_IntrHandler | IntrExtPktHandler |
+
+void * | IntrExtPktCallbackRef |
+
XDp_IntrHandler | IntrTrainingDoneHandler |
void * | IntrTrainingDoneCallbackRef |
@@ -107,6 +115,66 @@ A pointer to the user data passed to the bandwidth change callback function.
Callback function for bandwidth change interrupts.
+
+
+
+
+
+
+A pointer to the user data passed to the audio extension packet callback function.
+
+
+
+
+
+
+
+
+Callback function for audio extension packet received interrupts.
+
+
+
+
+
+
+
+
+A pointer to the user data passed to the audio info packet callback function.
+
+
+
+
+
+
+
+
+Callback function for audio info packet received interrupts.
+
+
@@ -424,4 +492,4 @@ Configuration structure for the main link.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config-members.html
index 81eaacd8..922b6a1a 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config-members.html
@@ -24,4 +24,4 @@
XDp_RxLinkConfig Member List
This is the complete list of members for
XDp_RxLinkConfig, including all inherited members.
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config.html
index e2fc3bd8..b5f38344 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___rx_link_config.html
@@ -67,4 +67,4 @@ The current link rate of the main link.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg-members.html
index b7dbfac6..ddbb2439 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg-members.html
@@ -24,4 +24,4 @@
XDp_SidebandMsg Member List
This is the complete list of members for XDp_SidebandMsg, including all inherited members.Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg.html
index 6fd2c720..1a7e58b3 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg.html
@@ -65,4 +65,4 @@ The header segment of the sideband message.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body-members.html
index 37f26231..50f4334b 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body-members.html
@@ -25,4 +25,4 @@
Crc | XDp_SidebandMsgBody | |
MsgData | XDp_SidebandMsgBody | |
MsgDataLength | XDp_SidebandMsgBody | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body.html
index 1c028415..60d4aee5 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_body.html
@@ -82,4 +82,4 @@ The number of data bytes stored as part of the sideband message body.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header-members.html
index 4c3137ec..8fca413f 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header-members.html
@@ -33,4 +33,4 @@
PathMsg | XDp_SidebandMsgHeader | |
RelativeAddress | XDp_SidebandMsgHeader | |
StartOfMsgTransaction | XDp_SidebandMsgHeader | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header.html
index 5f0258e8..2d791519 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_msg_header.html
@@ -218,4 +218,4 @@ This message is the first sideband message in the transaction.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply-members.html
index 4ed4db81..d8d64e60 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply-members.html
@@ -24,4 +24,4 @@
XDp_SidebandReply Member List
This is the complete list of members for XDp_SidebandReply, including all inherited members.Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply.html
index 913f96f3..5f6d2c51 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___sideband_reply.html
@@ -65,4 +65,4 @@ The number of bytes of reply data.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx-members.html
index d9e65ce8..dcbf644d 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx-members.html
@@ -36,4 +36,4 @@
SbMsgDelayUs | XDp_Tx | |
Topology | XDp_Tx | |
TrainAdaptive | XDp_Tx | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx.html
index c1bb45af..65720a7f 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx.html
@@ -271,4 +271,4 @@ Downshift lane count and link rate if necessary during training.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char-members.html
index cc8aecfb..c57c5a31 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char-members.html
@@ -26,4 +26,4 @@
TxPeLevels | XDp_TxBoardChar | |
TxVsLevels | XDp_TxBoardChar | |
TxVsOffset | XDp_TxBoardChar | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char.html
index 604dc070..9c09e56d 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_board_char.html
@@ -101,4 +101,4 @@ Voltage swing compensation offset used when pre-emphasis is used.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config-members.html
index 53f129cc..64faa7f8 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config-members.html
@@ -34,4 +34,4 @@
SupportDownspreadControl | XDp_TxLinkConfig | |
SupportEnhancedFramingMode | XDp_TxLinkConfig | |
VsLevel | XDp_TxLinkConfig | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config.html
index aee997d8..cf529f63 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_link_config.html
@@ -237,4 +237,4 @@ The current voltage swing level for each lane.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes-members.html
index fe3c31cc..b7a6d5c0 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes-members.html
@@ -40,4 +40,4 @@
VStart | XDp_TxMainStreamAttributes | |
Vtm | XDp_TxMainStreamAttributes | |
YCbCrColorimetry | XDp_TxMainStreamAttributes | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes.html
index 1264f243..aa6d4340 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_main_stream_attributes.html
@@ -339,4 +339,4 @@ The YCbCr colorimetry currently in use by the video stream.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream-members.html
index dd98475c..e7bdfda1 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream-members.html
@@ -26,4 +26,4 @@
MstPbn | XDp_TxMstStream | |
MstStreamEnable | XDp_TxMstStream | |
RelativeAddress | XDp_TxMstStream | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream.html
index 3ba52292..287f4eb5 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_mst_stream.html
@@ -101,4 +101,4 @@ The total number of DisplayPort links from the DisplayPort TX to the sink device
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info-members.html
index 3aa83abc..9e52ccb2 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info-members.html
@@ -27,4 +27,4 @@
PortDetails | XDp_TxSbMsgLinkAddressReplyDeviceInfo | |
ReplyType | XDp_TxSbMsgLinkAddressReplyDeviceInfo | |
RequestId | XDp_TxSbMsgLinkAddressReplyDeviceInfo | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info.html
index 7c85d28e..7e1dd859 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_device_info.html
@@ -118,4 +118,4 @@ The request identifier of the reply. This should correspond to the request ident
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail-members.html
index fabf0a82..8315c385 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail-members.html
@@ -32,4 +32,4 @@
NumSdpStreamSinks | XDp_TxSbMsgLinkAddressReplyPortDetail | |
PeerDeviceType | XDp_TxSbMsgLinkAddressReplyPortDetail | |
PortNum | XDp_TxSbMsgLinkAddressReplyPortDetail | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail.html
index fa16941e..56df0d7b 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sb_msg_link_address_reply_port_detail.html
@@ -203,4 +203,4 @@ The port number of this port.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config-members.html
index 101d2de4..e9f16d2b 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config-members.html
@@ -24,4 +24,4 @@
XDp_TxSinkConfig Member List
This is the complete list of members for XDp_TxSinkConfig, including all inherited members.Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config.html
index 3787d08c..dc826991 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_sink_config.html
@@ -67,4 +67,4 @@ This is a raw read of the RX device's status registers. The first 4 bytes corres
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology-members.html
index c14f63aa..161021b4 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology-members.html
@@ -26,4 +26,4 @@
NodeTotal | XDp_TxTopology | |
SinkList | XDp_TxTopology | |
SinkTotal | XDp_TxTopology | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology.html
index 7d5a7a0c..5f99f2c7 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology.html
@@ -101,4 +101,4 @@ The total number of sinks in the MST topology.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node-members.html
index 43f68d18..e50c6155 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node-members.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node-members.html
@@ -28,4 +28,4 @@
LinkCountTotal | XDp_TxTopologyNode | |
MsgCapStatus | XDp_TxTopologyNode | |
RelativeAddress | XDp_TxTopologyNode | |
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node.html
index 50f495ed..3b440940 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp___tx_topology_node.html
@@ -135,4 +135,4 @@ The relative address from the DisplayPort TX to this device.
The documentation for this struct was generated from the following file:
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8c.html
index 306c163e..f8ac1bad 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8c.html
@@ -28,7 +28,7 @@ Contains a minimal set of functions for the xdp.h"
@@ -110,6 +110,10 @@ Contains a minimal set of functions for the void XDp_TxResetPhy (XDp *InstancePtr, u32 Reset) |
+void | XDp_TxSetPhyPolarityAll (XDp *InstancePtr, u8 Polarity) |
+
+void | XDp_TxSetPhyPolarityLane (XDp *InstancePtr, u8 Lane, u8 Polarity) |
+
u32 | XDp_RxCheckLinkStatus (XDp *InstancePtr) |
void | XDp_RxDtgEn (XDp *InstancePtr) |
@@ -120,6 +124,12 @@ Contains a minimal set of functions for the void XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
+void | XDp_RxAudioEn (XDp *InstancePtr) |
+
+void | XDp_RxAudioDis (XDp *InstancePtr) |
+
+void | XDp_RxAudioReset (XDp *InstancePtr) |
+
void | XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
void | XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds) |
@@ -307,6 +317,90 @@ This function prepares the DisplayPort core for use depending on whether the cor
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_RxAudioDis |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function disables audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxAudioEn |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function enables audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxAudioReset |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function resets the RX core's reception of audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
@@ -1360,6 +1454,89 @@ This function sets the data rate to be used by the main link for both the Displa
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_TxSetPhyPolarityAll |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ u8 |
+ Polarity | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function sets the PHY polarity on all lanes.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | Polarity | is the value to set for the polarity (0 or 1). |
+
+
+
- Returns:
- None.
+
- Note:
- The individual PHY polarity option will be disabled if set.
+
+
+
+
+
+
+
+
+ void XDp_TxSetPhyPolarityLane |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ u8 |
+ Lane, |
+
+
+ |
+ |
+ u8 |
+ Polarity | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function sets the PHY polarity on a specified lane.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | Lane | is the lane number (0-3) to set the polarity for. |
+ | Polarity | is the value to set for the polarity (0 or 1). |
+
+
+
- Returns:
- None.
+
- Note:
- If individual lane polarity is used, it is recommended that this function is called for every lane in use.
+
@@ -1440,4 +1617,4 @@ This function is the delay/sleep function for the struct
XDp |
Defines |
-#define | XDP_TX 0 |
-
-#define | XDP_RX 1 |
-
-#define | XDp_CfgGetCoreType(ConfigPtr) ((ConfigPtr)->IsRx ? XDP_RX : XDP_TX) |
+#define | XDp_GetCoreType(InstancePtr) |
#define | XDptx_ReadReg XDp_ReadReg |
@@ -116,20 +112,10 @@
#define | XDprx_InterruptHandler XDp_InterruptHandler |
-#define | XDptx_ XDp_Tx |
-
-#define | XDprx_ XDp_Rx |
-
#define | XDptx XDp |
#define | XDprx XDp |
-#define | XDPTX_DPCD_ XDP_DPCD_ |
-
-#define | XDPTX_ XDP_TX_ |
-
-#define | XDPRX_ XDP_RX_ |
-
#define | XDPTX XDP_TX |
#define | XDPRX XDP_RX |
@@ -139,6 +125,11 @@
typedef void(*) | XDp_IntrHandler (void *InstancePtr) |
+
Enumerations |
+enum | XDp_CoreType { XDP_TX = 0,
+XDP_RX
+ } |
+
Functions |
XDp_Config * | XDp_LookupConfig (u16 DeviceId) |
@@ -194,6 +185,10 @@
void | XDp_TxResetPhy (XDp *InstancePtr, u32 Reset) |
+void | XDp_TxSetPhyPolarityAll (XDp *InstancePtr, u8 Polarity) |
+
+void | XDp_TxSetPhyPolarityLane (XDp *InstancePtr, u8 Lane, u8 Polarity) |
+
u32 | XDp_RxCheckLinkStatus (XDp *InstancePtr) |
void | XDp_RxDtgEn (XDp *InstancePtr) |
@@ -204,6 +199,12 @@
void | XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
+void | XDp_RxAudioEn (XDp *InstancePtr) |
+
+void | XDp_RxAudioDis (XDp *InstancePtr) |
+
+void | XDp_RxAudioReset (XDp *InstancePtr) |
+
u32 | XDp_TxGetEdid (XDp *InstancePtr, u8 *Edid) |
u32 | XDp_TxGetRemoteEdid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid) |
@@ -242,6 +243,10 @@
void | XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+void | XDp_RxSetIntrInfoPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+
+void | XDp_RxSetIntrExtPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+
void | XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
void | XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
@@ -338,61 +343,33 @@
Define Documentation
-
+
- #define XDp_CfgGetCoreType |
+ #define XDp_GetCoreType |
( |
- ConfigPtr |
+ InstancePtr |
|
) |
- ((ConfigPtr)->IsRx ? XDP_RX : XDP_TX) |
+ |
-This is function determines whether the DisplayPort core that the configuration structure represents is a transmitter (TX) or a receiver (RX).
+Value:
This is function determines whether the DisplayPort core, represented by the
XDp structure pointed to, is a transmitter (TX) or a receiver (RX).
- Parameters:
-
- | ConfigPtr | is a pointer to the DisplayPort core's configuration structure. |
+ | InstancePtr | is a pointer to the XDp instance. |
-
- Returns:
- XDP_RX if the configuration structure is for a core of type RX. XDP_TX if the configuration structure is for a core of type TX.
-
- Note:
- C-style signature: u32 XDp_CfgGetCoreType(XDp_Config *ConfigPtr)
-
-
-
-
-
-
-
@@ -424,36 +401,6 @@ This is function determines whether the DisplayPort core that the configuration
-
-
-
-
-
-
-
- #define XDPRX_ XDP_RX_ |
-
-
-
-
-
-
-
@@ -664,36 +611,6 @@ This is function determines whether the DisplayPort core that the configuration
-
-
-
-
-
-
-
- #define XDPTX_ XDP_TX_ |
-
-
-
-
-
-
-
@@ -724,21 +641,6 @@ This is function determines whether the DisplayPort core that the configuration
-
-
-
-
-
-
-
- #define XDPTX_DPCD_ XDP_DPCD_ |
-
-
-
-
@@ -950,6 +852,30 @@ Callback type which represents a custom timer wait handler. This is only used fo
- Note:
- None.
+
+
+
Enumeration Type Documentation
+
+
+
+
+
+
+This typedef enumerates the RX and TX modes of operation for the DisplayPort core.
- Enumerator:
-
+
+
+
Function Documentation
@@ -1082,6 +1008,90 @@ This function looks for the device configuration based on the unique device ID.
- Returns:
- A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_RxAudioDis |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function disables audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxAudioEn |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function enables audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxAudioReset |
+ ( |
+ XDp * |
+ InstancePtr |
+ ) |
+ |
+
+
+
+
+
+
+This function resets the RX core's reception of audio stream packets on the main link.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
@@ -1327,6 +1337,96 @@ This function installs a callback function for when a bandwidth change interrupt
- Returns:
- None.
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_RxSetIntrExtPktHandler |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ XDp_IntrHandler |
+ CallbackFunc, |
+
+
+ |
+ |
+ void * |
+ CallbackRef | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function installs a callback function for when an audio extension packet interrupt occurs.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | CallbackFunc | is the address to the callback function. |
+ | CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxSetIntrInfoPktHandler |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ XDp_IntrHandler |
+ CallbackFunc, |
+
+
+ |
+ |
+ void * |
+ CallbackRef | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function installs a callback function for when an audio info packet interrupt occurs.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | CallbackFunc | is the address to the callback function. |
+ | CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
@@ -4603,6 +4703,26 @@ This function will send a REMOTE_I2C_READ sideband message which will read from
+This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
+ | RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
+ | IicDeviceId | is the address on the I2C bus of the target device. |
+ | BytesToWrite | is the number of bytes to write to the I2C address. |
+ | WriteData | is a pointer to a buffer that will be written. |
+
+
+
- Returns:
+- XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
+
+
+- XST_DEVICE_NOT_FOUND if no RX device is connected.
+- XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
- XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
+
+
+
- Note:
- None.
@@ -4932,6 +5052,89 @@ This function sets the main stream attributes registers of the DisplayPort TX co
- Returns:
- None.
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_TxSetPhyPolarityAll |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ u8 |
+ Polarity | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function sets the PHY polarity on all lanes.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | Polarity | is the value to set for the polarity (0 or 1). |
+
+
+
- Returns:
- None.
+
- Note:
- The individual PHY polarity option will be disabled if set.
+
+
+
+
+
+
+
+
+ void XDp_TxSetPhyPolarityLane |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ u8 |
+ Lane, |
+
+
+ |
+ |
+ u8 |
+ Polarity | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function sets the PHY polarity on a specified lane.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | Lane | is the lane number (0-3) to set the polarity for. |
+ | Polarity | is the value to set for the polarity (0 or 1). |
+
+
+
- Returns:
- None.
+
- Note:
- If individual lane polarity is used, it is recommended that this function is called for every lane in use.
+
@@ -5273,4 +5476,4 @@ This function is the delay/sleep function for the xdp.h"
@@ -415,4 +415,4 @@ Search for and retrieve a downstream DisplayPort device's Tiled Display Topology
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html
index 6162fa8b..49c506c7 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html
@@ -28,189 +28,189 @@ This header file contains the identifiers and low-level driver functions (or mac
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
- 1.0 als 01/20/15 Initial release.
+ 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
#include "xil_io.h"
|
DPTX core registers: Link configuration field. |
-#define | XDP_TX_LINK_BW_SET 0x0000 |
+#define | XDP_TX_LINK_BW_SET 0x000 |
-#define | XDP_TX_LANE_COUNT_SET 0x0004 |
+#define | XDP_TX_LANE_COUNT_SET 0x004 |
-#define | XDP_TX_ENHANCED_FRAME_EN 0x0008 |
+#define | XDP_TX_ENHANCED_FRAME_EN 0x008 |
-#define | XDP_TX_TRAINING_PATTERN_SET 0x000C |
+#define | XDP_TX_TRAINING_PATTERN_SET 0x00C |
-#define | XDP_TX_LINK_QUAL_PATTERN_SET 0x0010 |
+#define | XDP_TX_LINK_QUAL_PATTERN_SET 0x010 |
-#define | XDP_TX_SCRAMBLING_DISABLE 0x0014 |
+#define | XDP_TX_SCRAMBLING_DISABLE 0x014 |
-#define | XDP_TX_DOWNSPREAD_CTRL 0x0018 |
+#define | XDP_TX_DOWNSPREAD_CTRL 0x018 |
-#define | XDP_TX_SOFT_RESET 0x001C |
+#define | XDP_TX_SOFT_RESET 0x01C |
DPTX core registers: Core enables. |
-#define | XDP_TX_ENABLE 0x0080 |
+#define | XDP_TX_ENABLE 0x080 |
-#define | XDP_TX_ENABLE_MAIN_STREAM 0x0084 |
+#define | XDP_TX_ENABLE_MAIN_STREAM 0x084 |
-#define | XDP_TX_ENABLE_SEC_STREAM 0x0088 |
+#define | XDP_TX_ENABLE_SEC_STREAM 0x088 |
-#define | XDP_TX_FORCE_SCRAMBLER_RESET 0x00C0 |
+#define | XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 |
-#define | XDP_TX_MST_CONFIG 0x00D0 |
+#define | XDP_TX_MST_CONFIG 0x0D0 |
DPTX core registers: Core ID. |
-#define | XDP_TX_VERSION 0x00F8 |
+#define | XDP_TX_VERSION 0x0F8 |
-#define | XDP_TX_CORE_ID 0x00FC |
+#define | XDP_TX_CORE_ID 0x0FC |
DPTX core registers: AUX channel interface. |
-#define | XDP_TX_AUX_CMD 0x0100 |
+#define | XDP_TX_AUX_CMD 0x100 |
-#define | XDP_TX_AUX_WRITE_FIFO 0x0104 |
+#define | XDP_TX_AUX_WRITE_FIFO 0x104 |
-#define | XDP_TX_AUX_ADDRESS 0x0108 |
+#define | XDP_TX_AUX_ADDRESS 0x108 |
-#define | XDP_TX_AUX_CLK_DIVIDER 0x010C |
+#define | XDP_TX_AUX_CLK_DIVIDER 0x10C |
-#define | XDP_TX_USER_FIFO_OVERFLOW 0x0110 |
+#define | XDP_TX_USER_FIFO_OVERFLOW 0x110 |
-#define | XDP_TX_INTERRUPT_SIG_STATE 0x0130 |
+#define | XDP_TX_INTERRUPT_SIG_STATE 0x130 |
-#define | XDP_TX_AUX_REPLY_DATA 0x0134 |
+#define | XDP_TX_AUX_REPLY_DATA 0x134 |
-#define | XDP_TX_AUX_REPLY_CODE 0x0138 |
+#define | XDP_TX_AUX_REPLY_CODE 0x138 |
-#define | XDP_TX_AUX_REPLY_COUNT 0x013C |
+#define | XDP_TX_AUX_REPLY_COUNT 0x13C |
-#define | XDP_TX_INTERRUPT_STATUS 0x0140 |
+#define | XDP_TX_INTERRUPT_STATUS 0x140 |
-#define | XDP_TX_INTERRUPT_MASK 0x0144 |
+#define | XDP_TX_INTERRUPT_MASK 0x144 |
-#define | XDP_TX_REPLY_DATA_COUNT 0x0148 |
+#define | XDP_TX_REPLY_DATA_COUNT 0x148 |
-#define | XDP_TX_REPLY_STATUS 0x014C |
+#define | XDP_TX_REPLY_STATUS 0x14C |
-#define | XDP_TX_HPD_DURATION 0x0150 |
+#define | XDP_TX_HPD_DURATION 0x150 |
DPTX core registers: Main stream attributes for SST / MST STREAM1. |
-#define | XDP_TX_STREAM1_MSA_START 0x0180 |
+#define | XDP_TX_STREAM1_MSA_START 0x180 |
-#define | XDP_TX_MAIN_STREAM_HTOTAL 0x0180 |
+#define | XDP_TX_MAIN_STREAM_HTOTAL 0x180 |
-#define | XDP_TX_MAIN_STREAM_VTOTAL 0x0184 |
+#define | XDP_TX_MAIN_STREAM_VTOTAL 0x184 |
-#define | XDP_TX_MAIN_STREAM_POLARITY 0x0188 |
+#define | XDP_TX_MAIN_STREAM_POLARITY 0x188 |
-#define | XDP_TX_MAIN_STREAM_HSWIDTH 0x018C |
+#define | XDP_TX_MAIN_STREAM_HSWIDTH 0x18C |
-#define | XDP_TX_MAIN_STREAM_VSWIDTH 0x0190 |
+#define | XDP_TX_MAIN_STREAM_VSWIDTH 0x190 |
-#define | XDP_TX_MAIN_STREAM_HRES 0x0194 |
+#define | XDP_TX_MAIN_STREAM_HRES 0x194 |
-#define | XDP_TX_MAIN_STREAM_VRES 0x0198 |
+#define | XDP_TX_MAIN_STREAM_VRES 0x198 |
-#define | XDP_TX_MAIN_STREAM_HSTART 0x019C |
+#define | XDP_TX_MAIN_STREAM_HSTART 0x19C |
-#define | XDP_TX_MAIN_STREAM_VSTART 0x01A0 |
+#define | XDP_TX_MAIN_STREAM_VSTART 0x1A0 |
-#define | XDP_TX_MAIN_STREAM_MISC0 0x01A4 |
+#define | XDP_TX_MAIN_STREAM_MISC0 0x1A4 |
-#define | XDP_TX_MAIN_STREAM_MISC1 0x01A8 |
+#define | XDP_TX_MAIN_STREAM_MISC1 0x1A8 |
-#define | XDP_TX_M_VID 0x01AC |
+#define | XDP_TX_M_VID 0x1AC |
-#define | XDP_TX_TU_SIZE 0x01B0 |
+#define | XDP_TX_TU_SIZE 0x1B0 |
-#define | XDP_TX_N_VID 0x01B4 |
+#define | XDP_TX_N_VID 0x1B4 |
-#define | XDP_TX_USER_PIXEL_WIDTH 0x01B8 |
+#define | XDP_TX_USER_PIXEL_WIDTH 0x1B8 |
-#define | XDP_TX_USER_DATA_COUNT_PER_LANE 0x01BC |
+#define | XDP_TX_USER_DATA_COUNT_PER_LANE 0x1BC |
-#define | XDP_TX_MAIN_STREAM_INTERLACED 0x01C0 |
+#define | XDP_TX_MAIN_STREAM_INTERLACED 0x1C0 |
-#define | XDP_TX_MIN_BYTES_PER_TU 0x01C4 |
+#define | XDP_TX_MIN_BYTES_PER_TU 0x1C4 |
-#define | XDP_TX_FRAC_BYTES_PER_TU 0x01C8 |
+#define | XDP_TX_FRAC_BYTES_PER_TU 0x1C8 |
-#define | XDP_TX_INIT_WAIT 0x01CC |
+#define | XDP_TX_INIT_WAIT 0x1CC |
-#define | XDP_TX_STREAM1 0x01D0 |
+#define | XDP_TX_STREAM1 0x1D0 |
-#define | XDP_TX_STREAM2 0x01D4 |
+#define | XDP_TX_STREAM2 0x1D4 |
-#define | XDP_TX_STREAM3 0x01D8 |
+#define | XDP_TX_STREAM3 0x1D8 |
-#define | XDP_TX_STREAM4 0x01DC |
+#define | XDP_TX_STREAM4 0x1DC |
DPTX core registers: PHY configuration status. |
-#define | XDP_TX_PHY_CONFIG 0x0200 |
+#define | XDP_TX_PHY_CONFIG 0x200 |
-#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 |
+#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220 |
-#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 |
+#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224 |
-#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 |
+#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228 |
-#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x022C |
+#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22C |
-#define | XDP_TX_PHY_TRANSMIT_PRBS7 0x0230 |
+#define | XDP_TX_PHY_TRANSMIT_PRBS7 0x230 |
-#define | XDP_TX_PHY_CLOCK_SELECT 0x0234 |
+#define | XDP_TX_PHY_CLOCK_SELECT 0x234 |
-#define | XDP_TX_PHY_POWER_DOWN 0x0238 |
+#define | XDP_TX_PHY_POWER_DOWN 0x238 |
-#define | XDP_TX_PHY_PRECURSOR_LANE_0 0x023C |
+#define | XDP_TX_PHY_PRECURSOR_LANE_0 0x23C |
-#define | XDP_TX_PHY_PRECURSOR_LANE_1 0x0240 |
+#define | XDP_TX_PHY_PRECURSOR_LANE_1 0x240 |
-#define | XDP_TX_PHY_PRECURSOR_LANE_2 0x0244 |
+#define | XDP_TX_PHY_PRECURSOR_LANE_2 0x244 |
-#define | XDP_TX_PHY_PRECURSOR_LANE_3 0x0248 |
+#define | XDP_TX_PHY_PRECURSOR_LANE_3 0x248 |
-#define | XDP_TX_PHY_POSTCURSOR_LANE_0 0x024C |
+#define | XDP_TX_PHY_POSTCURSOR_LANE_0 0x24C |
-#define | XDP_TX_PHY_POSTCURSOR_LANE_1 0x0250 |
+#define | XDP_TX_PHY_POSTCURSOR_LANE_1 0x250 |
-#define | XDP_TX_PHY_POSTCURSOR_LANE_2 0x0254 |
+#define | XDP_TX_PHY_POSTCURSOR_LANE_2 0x254 |
-#define | XDP_TX_PHY_POSTCURSOR_LANE_3 0x0258 |
+#define | XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 |
-#define | XDP_TX_PHY_STATUS 0x0280 |
+#define | XDP_TX_PHY_STATUS 0x280 |
-#define | XDP_TX_GT_DRP_COMMAND 0x02A0 |
+#define | XDP_TX_GT_DRP_COMMAND 0x2A0 |
-#define | XDP_TX_GT_DRP_READ_DATA 0x02A4 |
+#define | XDP_TX_GT_DRP_READ_DATA 0x2A4 |
-#define | XDP_TX_GT_DRP_CHANNEL_STATUS 0x02A8 |
+#define | XDP_TX_GT_DRP_CHANNEL_STATUS 0x2A8 |
DPTX core registers: DisplayPort audio. |
-#define | XDP_TX_AUDIO_CONTROL 0x0300 |
+#define | XDP_TX_AUDIO_CONTROL 0x300 |
-#define | XDP_TX_AUDIO_CHANNELS 0x0304 |
+#define | XDP_TX_AUDIO_CHANNELS 0x304 |
-#define | XDP_TX_AUDIO_INFO_DATA(NUM) (0x0308 + 4 * (NUM - 1)) |
+#define | XDP_TX_AUDIO_INFO_DATA(NUM) (0x308 + 4 * (NUM - 1)) |
-#define | XDP_TX_AUDIO_MAUD 0x0328 |
+#define | XDP_TX_AUDIO_MAUD 0x328 |
-#define | XDP_TX_AUDIO_NAUD 0x032C |
+#define | XDP_TX_AUDIO_NAUD 0x32C |
-#define | XDP_TX_AUDIO_EXT_DATA(NUM) (0x0330 + 4 * (NUM - 1)) |
+#define | XDP_TX_AUDIO_EXT_DATA(NUM) (0x330 + 4 * (NUM - 1)) |
DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. |
-#define | XDP_TX_STREAM2_MSA_START 0x0500 |
+#define | XDP_TX_STREAM2_MSA_START 0x500 |
#define | XDP_TX_STREAM2_MSA_START_OFFSET |
-#define | XDP_TX_STREAM3_MSA_START 0x0550 |
+#define | XDP_TX_STREAM3_MSA_START 0x550 |
#define | XDP_TX_STREAM3_MSA_START_OFFSET |
-#define | XDP_TX_STREAM4_MSA_START 0x05A0 |
+#define | XDP_TX_STREAM4_MSA_START 0x5A0 |
#define | XDP_TX_STREAM4_MSA_START_OFFSET |
@@ -437,12 +437,24 @@ This header file contains the identifiers and low-level driver functions (or mac
#define | XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0000200 |
-#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000400 |
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000800 |
#define | XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0001000 |
#define | XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 |
+#define | XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 |
+
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK 0x0010000 |
+
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK 0x0020000 |
+
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK 0x0040000 |
+
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK 0x0080000 |
+
+#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK 0x0100000 |
+
#define | XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 |
#define | XDP_TX_PHY_CLOCK_SELECT_162GBPS 0x1 |
@@ -1871,7 +1883,7 @@ This header file contains the identifiers and low-level driver functions (or mac
#define | XDp_Out32 Xil_Out32 |
Defines |
-#define | XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x0800 |
+#define | XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x800 |
#define | XDp_ReadReg(BaseAddress, RegOffset) XDp_In32((BaseAddress) + (RegOffset)) |
@@ -11051,7 +11063,7 @@ DPCD register bit to inform the DisplayPort TX that video data is not supported.
- #define XDP_TX_AUDIO_CHANNELS 0x0304 |
+ #define XDP_TX_AUDIO_CHANNELS 0x304 |
@@ -11066,7 +11078,7 @@ Used to input active channel count.
- #define XDP_TX_AUDIO_CONTROL 0x0300 |
+ #define XDP_TX_AUDIO_CONTROL 0x300 |
@@ -11086,7 +11098,7 @@ Enables audio stream packets in main link and buffer control.
NUM |
|
) |
- (0x0330 + 4 * (NUM - 1)) |
+ (0x330 + 4 * (NUM - 1)) |
@@ -11106,7 +11118,7 @@ Word formatted as per extension packet.
NUM |
|
) |
- (0x0308 + 4 * (NUM - 1)) |
+ (0x308 + 4 * (NUM - 1)) |
@@ -11121,7 +11133,7 @@ Word formatted as per CEA 861-C info frame.
- #define XDP_TX_AUDIO_MAUD 0x0328 |
+ #define XDP_TX_AUDIO_MAUD 0x328 |
@@ -11136,7 +11148,7 @@ M value of audio stream as computed by the DisplayPort TX core when audio and li
- #define XDP_TX_AUDIO_NAUD 0x032C |
+ #define XDP_TX_AUDIO_NAUD 0x32C |
@@ -11151,7 +11163,7 @@ N value of audio stream as computed by the DisplayPort TX core when audio and li
- #define XDP_TX_AUX_ADDRESS 0x0108 |
+ #define XDP_TX_AUX_ADDRESS 0x108 |
@@ -11166,7 +11178,7 @@ Specifies the address of current AUX command.
- #define XDP_TX_AUX_CLK_DIVIDER 0x010C |
+ #define XDP_TX_AUX_CLK_DIVIDER 0x10C |
@@ -11226,7 +11238,7 @@ Clock divider value.
- #define XDP_TX_AUX_CMD 0x0100 |
+ #define XDP_TX_AUX_CMD 0x100 |
@@ -11421,7 +11433,7 @@ AUX write command.
- #define XDP_TX_AUX_REPLY_CODE 0x0138 |
+ #define XDP_TX_AUX_REPLY_CODE 0x138 |
@@ -11526,7 +11538,7 @@ AUX command not ACKed.
- #define XDP_TX_AUX_REPLY_COUNT 0x013C |
+ #define XDP_TX_AUX_REPLY_COUNT 0x13C |
@@ -11541,7 +11553,7 @@ Number of reply transactions receieved over AUX.
- #define XDP_TX_AUX_REPLY_DATA 0x0134 |
+ #define XDP_TX_AUX_REPLY_DATA 0x134 |
@@ -11556,7 +11568,7 @@ Reply data received during the AUX reply.
- #define XDP_TX_AUX_WRITE_FIFO 0x0104 |
+ #define XDP_TX_AUX_WRITE_FIFO 0x104 |
@@ -11571,7 +11583,7 @@ Write data for the current AUX command.
- #define XDP_TX_CORE_ID 0x00FC |
+ #define XDP_TX_CORE_ID 0x0FC |
@@ -12291,7 +12303,7 @@ Core is a transmitter.
- #define XDP_TX_DOWNSPREAD_CTRL 0x0018 |
+ #define XDP_TX_DOWNSPREAD_CTRL 0x018 |
@@ -12306,7 +12318,7 @@ Enable a 0.5% spreading of the clock.
- #define XDP_TX_ENABLE 0x0080 |
+ #define XDP_TX_ENABLE 0x080 |
@@ -12321,7 +12333,7 @@ Enable the basic operations of the DisplayPort TX core or output stuffing symbol
- #define XDP_TX_ENABLE_MAIN_STREAM 0x0084 |
+ #define XDP_TX_ENABLE_MAIN_STREAM 0x084 |
@@ -12336,7 +12348,7 @@ Enable transmission of main link video info.
- #define XDP_TX_ENABLE_SEC_STREAM 0x0088 |
+ #define XDP_TX_ENABLE_SEC_STREAM 0x088 |
@@ -12351,7 +12363,7 @@ Enable the transmission of secondary link info.
- #define XDP_TX_ENHANCED_FRAME_EN 0x0008 |
+ #define XDP_TX_ENHANCED_FRAME_EN 0x008 |
@@ -12366,7 +12378,7 @@ Enable enhanced framing symbol sequence.
- #define XDP_TX_FORCE_SCRAMBLER_RESET 0x00C0 |
+ #define XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 |
@@ -12381,7 +12393,7 @@ Force a scrambler reset.
- #define XDP_TX_FRAC_BYTES_PER_TU 0x01C8 |
+ #define XDP_TX_FRAC_BYTES_PER_TU 0x1C8 |
@@ -12396,7 +12408,7 @@ The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register va
- #define XDP_TX_GT_DRP_CHANNEL_STATUS 0x02A8 |
+ #define XDP_TX_GT_DRP_CHANNEL_STATUS 0x2A8 |
@@ -12411,7 +12423,7 @@ Provides access to GT DRP channel status.
- #define XDP_TX_GT_DRP_COMMAND 0x02A0 |
+ #define XDP_TX_GT_DRP_COMMAND 0x2A0 |
@@ -12486,7 +12498,7 @@ Shift bits for DRP write data.
- #define XDP_TX_GT_DRP_READ_DATA 0x02A4 |
+ #define XDP_TX_GT_DRP_READ_DATA 0x2A4 |
@@ -12501,7 +12513,7 @@ Provides access to GT DRP read data.
- #define XDP_TX_HPD_DURATION 0x0150 |
+ #define XDP_TX_HPD_DURATION 0x150 |
@@ -12516,7 +12528,7 @@ Duration of the HPD pulse in microseconds.
- #define XDP_TX_INIT_WAIT 0x01CC |
+ #define XDP_TX_INIT_WAIT 0x1CC |
@@ -12531,7 +12543,7 @@ Number of initial wait cycles at the start of a new line by the framing logic, a
- #define XDP_TX_INTERRUPT_MASK 0x0144 |
+ #define XDP_TX_INTERRUPT_MASK 0x144 |
@@ -12636,7 +12648,7 @@ Mask reply received interrupt.
- #define XDP_TX_INTERRUPT_SIG_STATE 0x0130 |
+ #define XDP_TX_INTERRUPT_SIG_STATE 0x130 |
@@ -12711,7 +12723,7 @@ A request is currently being sent.
- #define XDP_TX_INTERRUPT_STATUS 0x0140 |
+ #define XDP_TX_INTERRUPT_STATUS 0x140 |
@@ -12816,7 +12828,7 @@ A reply timeout has occurred.
- #define XDP_TX_LANE_COUNT_SET 0x0004 |
+ #define XDP_TX_LANE_COUNT_SET 0x004 |
@@ -12876,7 +12888,7 @@ Lane count of 4.
- #define XDP_TX_LINK_BW_SET 0x0000 |
+ #define XDP_TX_LINK_BW_SET 0x000 |
@@ -12936,7 +12948,7 @@ Set main link bandwidth setting.
- #define XDP_TX_LINK_QUAL_PATTERN_SET 0x0010 |
+ #define XDP_TX_LINK_QUAL_PATTERN_SET 0x010 |
@@ -13011,7 +13023,7 @@ Symbol error rate measurement pattern transmitted.
- #define XDP_TX_M_VID 0x01AC |
+ #define XDP_TX_M_VID 0x1AC |
@@ -13026,7 +13038,7 @@ M value for the video stream as computed by the source core in asynchronous cloc
- #define XDP_TX_MAIN_STREAM_HRES 0x0194 |
+ #define XDP_TX_MAIN_STREAM_HRES 0x194 |
@@ -13041,7 +13053,7 @@ Number of active pixels per line (the horizontal resolution).
- #define XDP_TX_MAIN_STREAM_HSTART 0x019C |
+ #define XDP_TX_MAIN_STREAM_HSTART 0x19C |
@@ -13056,7 +13068,7 @@ Number of clocks between the leading edge of the horizontal sync and the start o
- #define XDP_TX_MAIN_STREAM_HSWIDTH 0x018C |
+ #define XDP_TX_MAIN_STREAM_HSWIDTH 0x18C |
@@ -13071,7 +13083,7 @@ Width of the horizontal sync pulse.
- #define XDP_TX_MAIN_STREAM_HTOTAL 0x0180 |
+ #define XDP_TX_MAIN_STREAM_HTOTAL 0x180 |
@@ -13086,7 +13098,7 @@ Total number of clocks in the horizontal framing period.
- #define XDP_TX_MAIN_STREAM_INTERLACED 0x01C0 |
+ #define XDP_TX_MAIN_STREAM_INTERLACED 0x1C0 |
@@ -13101,7 +13113,7 @@ Video is interlaced.
- #define XDP_TX_MAIN_STREAM_MISC0 0x01A4 |
+ #define XDP_TX_MAIN_STREAM_MISC0 0x1A4 |
@@ -13116,7 +13128,7 @@ Miscellaneous stream attributes.
- #define XDP_TX_MAIN_STREAM_MISC1 0x01A8 |
+ #define XDP_TX_MAIN_STREAM_MISC1 0x1A8 |
@@ -13131,7 +13143,7 @@ Miscellaneous stream attributes.
- #define XDP_TX_MAIN_STREAM_POLARITY 0x0188 |
+ #define XDP_TX_MAIN_STREAM_POLARITY 0x188 |
@@ -13146,7 +13158,7 @@ Polarity for the video sync signals.
- #define XDP_TX_MAIN_STREAM_VRES 0x0198 |
+ #define XDP_TX_MAIN_STREAM_VRES 0x198 |
@@ -13161,7 +13173,7 @@ Number of active lines (the vertical resolution).
- #define XDP_TX_MAIN_STREAM_VSTART 0x01A0 |
+ #define XDP_TX_MAIN_STREAM_VSTART 0x1A0 |
@@ -13176,7 +13188,7 @@ Number of lines between the leading edge of the vertical sync and the first line
- #define XDP_TX_MAIN_STREAM_VSWIDTH 0x0190 |
+ #define XDP_TX_MAIN_STREAM_VSWIDTH 0x190 |
@@ -13191,7 +13203,7 @@ Width of the vertical sync pulse.
- #define XDP_TX_MAIN_STREAM_VTOTAL 0x0184 |
+ #define XDP_TX_MAIN_STREAM_VTOTAL 0x184 |
@@ -13551,7 +13563,7 @@ Shift bits for polarity of the vertical sync pulse.
- #define XDP_TX_MIN_BYTES_PER_TU 0x01C4 |
+ #define XDP_TX_MIN_BYTES_PER_TU 0x1C4 |
@@ -13566,7 +13578,7 @@ The minimum number of bytes per transfer unit.
- #define XDP_TX_MST_CONFIG 0x00D0 |
+ #define XDP_TX_MST_CONFIG 0x0D0 |
@@ -13611,7 +13623,7 @@ The VC payload has been updated in the sink.
- #define XDP_TX_N_VID 0x01B4 |
+ #define XDP_TX_N_VID 0x1B4 |
@@ -13686,7 +13698,7 @@ Pre-emphasis level 3.
- #define XDP_TX_PHY_CLOCK_SELECT 0x0234 |
+ #define XDP_TX_PHY_CLOCK_SELECT 0x234 |
@@ -13746,7 +13758,7 @@ Instructs the PHY PLL to generate the proper clock frequency for the required li
- #define XDP_TX_PHY_CONFIG 0x0200 |
+ #define XDP_TX_PHY_CONFIG 0x200 |
@@ -13831,6 +13843,21 @@ Hold the PHY in reset.
Set TX_PHY_LOOPBACK.
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 |
+
+
+
+
+
+
+Shift bits for TX_PHY_LOOPBACK.
+
+
@@ -13861,12 +13888,87 @@ Hold TX_PHY_PCS reset.
Hold TX_PHY_PMA reset.
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK 0x0010000 |
+
+
+
+
+
+
+Set to enable individual lane polarity.
+
+
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK 0x0020000 |
+
+
+
+
+
+
+Set TX_PHY_POLARITY for lane 0.
+
+
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK 0x0040000 |
+
+
+
+
+
+
+Set TX_PHY_POLARITY for lane 1.
+
+
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK 0x0080000 |
+
+
+
+
+
+
+Set TX_PHY_POLARITY for lane 2.
+
+
+
+
+
+
+
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK 0x0100000 |
+
+
+
+
+
+
+Set TX_PHY_POLARITY for lane 3.
+
+
- #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000400 |
+ #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000800 |
@@ -13896,7 +13998,7 @@ Set TX_PHY_PRBSFORCEERR.
- #define XDP_TX_PHY_POSTCURSOR_LANE_0 0x024C |
+ #define XDP_TX_PHY_POSTCURSOR_LANE_0 0x24C |
@@ -13911,7 +14013,7 @@ Controls the post-cursor level.
- #define XDP_TX_PHY_POSTCURSOR_LANE_1 0x0250 |
+ #define XDP_TX_PHY_POSTCURSOR_LANE_1 0x250 |
@@ -13926,7 +14028,7 @@ Controls the post-cursor level.
- #define XDP_TX_PHY_POSTCURSOR_LANE_2 0x0254 |
+ #define XDP_TX_PHY_POSTCURSOR_LANE_2 0x254 |
@@ -13941,7 +14043,7 @@ Controls the post-cursor level.
- #define XDP_TX_PHY_POSTCURSOR_LANE_3 0x0258 |
+ #define XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 |
@@ -13956,7 +14058,7 @@ Controls the post-cursor level.
- #define XDP_TX_PHY_POWER_DOWN 0x0238 |
+ #define XDP_TX_PHY_POWER_DOWN 0x238 |
@@ -13971,7 +14073,7 @@ Controls PHY power down.
- #define XDP_TX_PHY_PRECURSOR_LANE_0 0x023C |
+ #define XDP_TX_PHY_PRECURSOR_LANE_0 0x23C |
@@ -13986,7 +14088,7 @@ Controls the pre-cursor level.
- #define XDP_TX_PHY_PRECURSOR_LANE_1 0x0240 |
+ #define XDP_TX_PHY_PRECURSOR_LANE_1 0x240 |
@@ -14001,7 +14103,7 @@ Controls the pre-cursor level.
- #define XDP_TX_PHY_PRECURSOR_LANE_2 0x0244 |
+ #define XDP_TX_PHY_PRECURSOR_LANE_2 0x244 |
@@ -14016,7 +14118,7 @@ Controls the pre-cursor level.
- #define XDP_TX_PHY_PRECURSOR_LANE_3 0x0248 |
+ #define XDP_TX_PHY_PRECURSOR_LANE_3 0x248 |
@@ -14031,7 +14133,7 @@ Controls the pre-cursor level.
- #define XDP_TX_PHY_STATUS 0x0280 |
+ #define XDP_TX_PHY_STATUS 0x280 |
@@ -14406,7 +14508,7 @@ Shift bits for TX error on lane 3.
- #define XDP_TX_PHY_TRANSMIT_PRBS7 0x0230 |
+ #define XDP_TX_PHY_TRANSMIT_PRBS7 0x230 |
@@ -14421,7 +14523,7 @@ Enable pseudo random bit sequence 7 pattern transmission for link quality assess
- #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 |
+ #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220 |
@@ -14436,7 +14538,7 @@ Controls the differential voltage swing.
- #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 |
+ #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224 |
@@ -14451,7 +14553,7 @@ Controls the differential voltage swing.
- #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 |
+ #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228 |
@@ -14466,7 +14568,7 @@ Controls the differential voltage swing.
- #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x022C |
+ #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22C |
@@ -14481,7 +14583,7 @@ Controls the differential voltage swing.
- #define XDP_TX_REPLY_DATA_COUNT 0x0148 |
+ #define XDP_TX_REPLY_DATA_COUNT 0x148 |
@@ -14496,7 +14598,7 @@ Total number of data bytes actually received during a transaction.
- #define XDP_TX_REPLY_STATUS 0x014C |
+ #define XDP_TX_REPLY_STATUS 0x14C |
@@ -14721,7 +14823,7 @@ AUX request is currently being transmitted.
- #define XDP_TX_SCRAMBLING_DISABLE 0x0014 |
+ #define XDP_TX_SCRAMBLING_DISABLE 0x014 |
@@ -14736,7 +14838,7 @@ Disable scrambler and transmit all symbols.
- #define XDP_TX_SOFT_RESET 0x001C |
+ #define XDP_TX_SOFT_RESET 0x01C |
@@ -14841,7 +14943,7 @@ Reset video logic for all streams.
- #define XDP_TX_STREAM1 0x01D0 |
+ #define XDP_TX_STREAM1 0x1D0 |
@@ -14856,7 +14958,7 @@ Average stream symbol timeslots per MTP config.
- #define XDP_TX_STREAM1_MSA_START 0x0180 |
+ #define XDP_TX_STREAM1_MSA_START 0x180 |
@@ -14871,7 +14973,7 @@ Start of the MSA registers for stream 1.
- #define XDP_TX_STREAM2 0x01D4 |
+ #define XDP_TX_STREAM2 0x1D4 |
@@ -14886,7 +14988,7 @@ Average stream symbol timeslots per MTP config.
- #define XDP_TX_STREAM2_MSA_START 0x0500 |
+ #define XDP_TX_STREAM2_MSA_START 0x500 |
@@ -14918,7 +15020,7 @@ Start of the MSA registers for stream 2.
- #define XDP_TX_STREAM3 0x01D8 |
+ #define XDP_TX_STREAM3 0x1D8 |
@@ -14933,7 +15035,7 @@ Average stream symbol timeslots per MTP config.
- #define XDP_TX_STREAM3_MSA_START 0x0550 |
+ #define XDP_TX_STREAM3_MSA_START 0x550 |
@@ -14965,7 +15067,7 @@ Start of the MSA registers for stream 3.
- #define XDP_TX_STREAM4 0x01DC |
+ #define XDP_TX_STREAM4 0x1DC |
@@ -14980,7 +15082,7 @@ Average stream symbol timeslots per MTP config.
- #define XDP_TX_STREAM4_MSA_START 0x05A0 |
+ #define XDP_TX_STREAM4_MSA_START 0x5A0 |
@@ -15072,7 +15174,7 @@ Start of the MSA registers for stream 4.
- #define XDP_TX_TRAINING_PATTERN_SET 0x000C |
+ #define XDP_TX_TRAINING_PATTERN_SET 0x00C |
@@ -15147,7 +15249,7 @@ Training pattern 3 used for channel equalization for cores with DP v1.2.
- #define XDP_TX_TU_SIZE 0x01B0 |
+ #define XDP_TX_TU_SIZE 0x1B0 |
@@ -15162,7 +15264,7 @@ Size of a transfer unit in the framing logic.
- #define XDP_TX_USER_DATA_COUNT_PER_LANE 0x01BC |
+ #define XDP_TX_USER_DATA_COUNT_PER_LANE 0x1BC |
@@ -15177,7 +15279,7 @@ Used to translate the number of pixels per line to the native internal 16-bit da
- #define XDP_TX_USER_FIFO_OVERFLOW 0x0110 |
+ #define XDP_TX_USER_FIFO_OVERFLOW 0x110 |
@@ -15192,7 +15294,7 @@ Indicates an overflow in user FIFO.
- #define XDP_TX_USER_PIXEL_WIDTH 0x01B8 |
+ #define XDP_TX_USER_PIXEL_WIDTH 0x1B8 |
@@ -15207,7 +15309,7 @@ Selects the width of the user data input port.
- #define XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x0800 |
+ #define XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x800 |
@@ -15222,7 +15324,7 @@ Virtual channel payload table (0xFF bytes).
- #define XDP_TX_VERSION 0x00F8 |
+ #define XDP_TX_VERSION 0x0F8 |
@@ -15691,4 +15793,4 @@ This is a low-level function that writes to the specified register.
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html
index 44ebc53e..e5167675 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html
@@ -28,7 +28,7 @@ This file contains functions related to XD
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
- 1.0 als 01/20/15 Initial release.
+ 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
#include "xdp.h"
@@ -59,6 +59,10 @@ This file contains functions related to XD
void | XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+void | XDp_RxSetIntrInfoPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+
+void | XDp_RxSetIntrExtPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
+
void | XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
void | XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
@@ -256,6 +260,96 @@ This function installs a callback function for when a bandwidth change interrupt
- Returns:
- None.
- Note:
- None.
+
+
+
+
+
+
+
+ void XDp_RxSetIntrExtPktHandler |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ XDp_IntrHandler |
+ CallbackFunc, |
+
+
+ |
+ |
+ void * |
+ CallbackRef | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function installs a callback function for when an audio extension packet interrupt occurs.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | CallbackFunc | is the address to the callback function. |
+ | CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
+
+
+
+
+
+
+
+ void XDp_RxSetIntrInfoPktHandler |
+ ( |
+ XDp * |
+ InstancePtr, |
+
+
+ |
+ |
+ XDp_IntrHandler |
+ CallbackFunc, |
+
+
+ |
+ |
+ void * |
+ CallbackRef | |
+
+
+ |
+ ) |
+ | | |
+
+
+
+
+
+
+This function installs a callback function for when an audio info packet interrupt occurs.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | CallbackFunc | is the address to the callback function. |
+ | CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+
+
+
- Returns:
- None.
+
- Note:
- None.
+
@@ -798,4 +892,4 @@ This function installs a callback function for when a hot-plug-detect pulse inte
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html
index 8ed2d836..5829e996 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html
@@ -26,7 +26,7 @@
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
- 1.0 als 01/20/15 Initial release.
+ 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
#include "string.h"
@@ -1459,6 +1459,26 @@ This function will send a REMOTE_I2C_READ sideband message which will read from
+This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device.
+
- Parameters:
-
+
+ | InstancePtr | is a pointer to the XDp instance. |
+ | LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
+ | RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
+ | IicDeviceId | is the address on the I2C bus of the target device. |
+ | BytesToWrite | is the number of bytes to write to the I2C address. |
+ | WriteData | is a pointer to a buffer that will be written. |
+
+
+
- Returns:
+- XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
+
+
+- XST_DEVICE_NOT_FOUND if no RX device is connected.
+- XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
- XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
+
+
+
- Note:
- None.
@@ -1719,4 +1739,4 @@ This function will write a global unique identifier (GUID) to the target Display
This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function.
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html
index 32b444c8..cfc1f7b4 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html
@@ -28,7 +28,7 @@ This file contains a diagnostic self-test function for the xdp.h"
@@ -145,4 +145,4 @@ This table contains the default values for the DisplayPort TX core's general usa
This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html
index 4df51c60..962ccd24 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html
@@ -28,7 +28,7 @@ This file contains static initialization methods for the xdp.h"
@@ -87,4 +87,4 @@ This function looks for the device configuration based on the unique device ID.
A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html
index faaa5791..0284a844 100644
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html
@@ -28,7 +28,7 @@ This file contains the stream policy maker functions for the
Ver Who Date Changes
----- ---- -------- -----------------------------------------------
- 1.0 als 01/20/15 Initial release.
+ 1.0 als 01/20/15 Initial release. TX code merged from the dptx driver.
#include "xdp.h"
@@ -483,4 +483,4 @@ This function clears the main stream attributes registers of the DisplayPort TX
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
+Copyright @ 1995-2015 Xilinx, Inc. All rights reserved.