From 46350e52d27a54b721b2931384dbb74557d5ee7f Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Fri, 6 Nov 2015 15:51:01 +0530 Subject: [PATCH] dprxss: Modified the order of execution in training pattern 1 callback This patch modifies the order of execution in training pattern 1 callback as DP159 programming for training pattern 1 and then link bandwidth callback. This modification require for few GPUs (Intel) to allow DP159 programming for training pattern 1 before link bandwidth callback. Signed-off-by: Shadul Shaikh Acked-by: Srikanth Vemula --- XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c index a66132af..7cfe6bbd 100644 --- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c +++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c @@ -51,6 +51,8 @@ * Protected HDCP under macro number of instances. * 2.00 sha 10/15/15 Generate a HPD interrupt whenever RX cable * disconnect/unplug interrupt is detected. +* 2.00 sha 11/06/15 Modified the order of execution in TP1 callback as DP159 +* config for TP1 and then link bandwidth callback. * * ******************************************************************************/ @@ -1213,16 +1215,16 @@ static void StubTp1Callback(void *InstancePtr) XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr, XDPRXSS_DPCD_LANE_COUNT_SET); - /* Link bandwidth callback */ - if (DpRxSsPtr->LinkBwCallback) { - DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef); - } - /* DP159 config for TP1 */ XVidC_Dp159Config(DpRxSsPtr->IicPtr, XVIDC_DP159_CT_TP1, DpRxSsPtr->UsrOpt.LinkRate, DpRxSsPtr->UsrOpt.LaneCount); + /* Link bandwidth callback */ + if (DpRxSsPtr->LinkBwCallback) { + DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef); + } + XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr, XDPRXSS_RX_PHY_CONFIG, 0x3800000);