From 46fa02ba07f2a6438cb9a2197a36e56b3e8e2df0 Mon Sep 17 00:00:00 2001 From: Om Mishra Date: Tue, 13 Jan 2015 14:34:22 +0530 Subject: [PATCH] emacps_v3_0: modification has been done with respect to versioin id register This patch has modified source code of emacps_v3_0 driver on Zynq and Zynq ultrascale MP Signed-off-by: Om Mishra --- XilinxProcessorIPLib/drivers/emacps/src/xemacps.c | 8 ++++---- XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c index 41b3784b..5df69d2d 100644 --- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c +++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c @@ -198,7 +198,7 @@ void XEmacPs_Start(XEmacPs *InstancePtr) (u32)XEMACPS_IXR_TXCOMPL_MASK)); /* Enable TX Q1 Interrupts */ - if (InstancePtr->Version == 7) + if (InstancePtr->Version > 2) XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); /* Mark as started */ @@ -317,7 +317,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr) ((u32)XEMACPS_NWCFG_100_MASK | (u32)XEMACPS_NWCFG_FDEN_MASK | (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK)); - if (InstancePtr->Version == 7) { + if (InstancePtr->Version > 2) { XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | XEMACPS_NWCFG_DWIDTH_64_MASK)); @@ -336,7 +336,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr) /* Single bursts */ /* FIXME: Why Single bursts? */ - if (InstancePtr->Version == 7) { + if (InstancePtr->Version > 2) { XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | (u32)XEMACPS_DMACR_INCR4_AHB_BURST)); @@ -352,7 +352,7 @@ void XEmacPs_Reset(XEmacPs *InstancePtr) XEMACPS_TXSR_OFFSET, 0x0U); XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); - if (InstancePtr->Version == 7) + if (InstancePtr->Version > 2) XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c index 40bde82b..de01f79b 100644 --- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c +++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_intr.c @@ -162,7 +162,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr) /* Read Transmit Q1 ISR */ - if (InstancePtr->Version == 7) + if (InstancePtr->Version > 2) RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_INTQ1_STS_OFFSET); @@ -182,7 +182,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr) } /* Transmit Q1 complete interrupt */ - if ((InstancePtr->Version == 7) && + if ((InstancePtr->Version > 2) && ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) { /* Clear TX status register TX complete indication but preserve * error bits if there is any */ @@ -235,7 +235,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr) * Have to distinguish this bit to handle the real error condition. */ /* Transmit Q1 error conditions interrupt */ - if ((InstancePtr->Version == 7) && + if ((InstancePtr->Version > 2) && ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) && ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) { /* Clear Interrupt Q1 status register */