From 52e9d348e4879dda38091e6e5bba8e1049c79c08 Mon Sep 17 00:00:00 2001 From: Sarat Chand Savitala Date: Wed, 18 Feb 2015 12:09:17 +0530 Subject: [PATCH] sw_apps:zynqmp_fsbl: Changes in naming for psu Changes done to replace all ps8 and pss references to psu. Signed-off-by: Sarat Chand Savitala --- lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl | 14 ++-- lib/sw_apps/zynqmp_fsbl/src/Makefile | 8 +- lib/sw_apps/zynqmp_fsbl/src/lscript.ld | 62 +++++++------- lib/sw_apps/zynqmp_fsbl/src/lscript_a53.ld | 74 ++++++++-------- lib/sw_apps/zynqmp_fsbl/src/xfsbl_error.h | 8 +- lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c | 6 +- lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h | 2 +- .../zynqmp_fsbl/src/xfsbl_initialization.c | 84 +++++++------------ .../zynqmp_fsbl/src/xfsbl_misc_drivers.c | 2 +- lib/sw_apps/zynqmp_fsbl/src/xfsbl_nand.c | 14 ++-- lib/sw_apps/zynqmp_fsbl/src/xfsbl_qspi.c | 12 +-- 11 files changed, 130 insertions(+), 156 deletions(-) diff --git a/lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl b/lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl index 92ba7f88..65c054e7 100755 --- a/lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl +++ b/lib/sw_apps/zynqmp_fsbl/data/zynqmp_fsbl.tcl @@ -76,7 +76,7 @@ proc swapp_is_supported_hw {} { set proc_type [common::get_property IP_NAME [get_cells $hw_processor]]; - if { $proc_type != "pss_cortexr5" && $proc_type != "pss_cortexa53" } { + if { $proc_type != "psu_cortexr5" && $proc_type != "psu_cortexa53" } { error "This application is supported only for CortexA53/CortexR5 processors."; } @@ -91,19 +91,19 @@ proc get_stdout {} { } proc check_stdout_hw {} { - set ps_uarts [get_cells -filter "IP_NAME=pss_uart"]; + set pu_uarts [get_cells -filter "IP_NAME=psu_uart"]; } proc swapp_generate {} { # generate/copy ps init files ::hsi::utils::generate_psinit - #delete unnecessary files (only pss_init.c & pss_init.h are needed for FSBL) + #delete unnecessary files (only psu_init.c & psu_init.h are needed for FSBL) - set files(0) "pss_init.html" - set files(1) "pss_init.tcl" - set files(2) "pss_init_gpl.c" - set files(3) "pss_init_gpl.h" + set files(0) "psu_init.html" + set files(1) "psu_init.tcl" + set files(2) "psu_init_gpl.c" + set files(3) "psu_init_gpl.h" foreach init_file [array get files] { file delete -force $init_file diff --git a/lib/sw_apps/zynqmp_fsbl/src/Makefile b/lib/sw_apps/zynqmp_fsbl/src/Makefile index 309a8d6d..7b6ba1c8 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/Makefile +++ b/lib/sw_apps/zynqmp_fsbl/src/Makefile @@ -57,8 +57,8 @@ CFLAGS = -Wall -O0 -g3 -fmessage-length=0 \ -mcpu=cortex-r5 -mfloat-abi=softfp LSCRIPT := -Tlscript.ld EXEC := ron_r5_fsbl.elf -INCLUDEPATH := -I$(BSP_DIR)/ps8_cortexr5_0/include -I. -LIBPATH := $(BSP_DIR)/ps8_cortexr5_0/lib +INCLUDEPATH := -I$(BSP_DIR)/psu_cortexr5_0/include -I. +LIBPATH := $(BSP_DIR)/psu_cortexr5_0/lib LDFLAGS := -Wl,--start-group,-lxil,-lxilffs,-lgcc,-lc,--end-group -L$(LIBPATH) -L./ -Wl,--build-id=none endif @@ -72,8 +72,8 @@ CFLAGS = -Wall -O0 -g3 -fmessage-length=0 \ -march=armv8-a -DXFSBL_A53 LSCRIPT := -Tlscript_a53.ld EXEC := ron_a53_fsbl.elf -INCLUDEPATH := -I$(BSP_DIR)/ps8_cortexa53_0/include -I. -LIBPATH := $(BSP_DIR)/ps8_cortexa53_0/lib +INCLUDEPATH := -I$(BSP_DIR)/psu_cortexa53_0/include -I. +LIBPATH := $(BSP_DIR)/psu_cortexa53_0/lib LDFLAGS := -Wl,--start-group,-lxil,-lxilffs,-lgcc,-lc,--end-group -L$(LIBPATH) -L./ -Wl,--build-id=none endif diff --git a/lib/sw_apps/zynqmp_fsbl/src/lscript.ld b/lib/sw_apps/zynqmp_fsbl/src/lscript.ld index b69bcbe8..93732cc9 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/lscript.ld +++ b/lib/sw_apps/zynqmp_fsbl/src/lscript.ld @@ -49,8 +49,8 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; MEMORY { - ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0xfffc0000, LENGTH = 0x0002FF00 - ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xffff0040, LENGTH = 0x0000FE00 + psu_ram_0_S_AXI_BASEADDR : ORIGIN = 0xfffc0000, LENGTH = 0x0002FF00 + psu_ram_1_S_AXI_BASEADDR : ORIGIN = 0xffff0040, LENGTH = 0x0000FE00 } /* Specify the default entry point to the program */ @@ -75,15 +75,15 @@ SECTIONS *(.vfp11_veneer) *(.ARM.extab) *(.gnu.linkonce.armextab.*) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .init : { KEEP (*(.init)) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .fini : { KEEP (*(.fini)) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .rodata : { __rodata_start = .; @@ -91,14 +91,14 @@ SECTIONS *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .rodata1 : { __rodata1_start = .; *(.rodata1) *(.rodata1.*) __rodata1_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .sdata2 : { __sdata2_start = .; @@ -106,7 +106,7 @@ SECTIONS *(.sdata2.*) *(.gnu.linkonce.s2.*) __sdata2_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .sbss2 : { __sbss2_start = .; @@ -114,7 +114,7 @@ SECTIONS *(.sbss2.*) *(.gnu.linkonce.sb2.*) __sbss2_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .data : { __data_start = .; @@ -125,18 +125,18 @@ SECTIONS *(.got) *(.got.plt) __data_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .data1 : { __data1_start = .; *(.data1) *(.data1.*) __data1_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .got : { *(.got) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .ctors : { __CTOR_LIST__ = .; @@ -147,7 +147,7 @@ SECTIONS KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .dtors : { __DTOR_LIST__ = .; @@ -158,67 +158,67 @@ SECTIONS KEEP (*(.dtors)) __DTOR_END__ = .; ___DTORS_END___ = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .fixup : { __fixup_start = .; *(.fixup) __fixup_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .eh_frame : { *(.eh_frame) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .eh_framehdr : { __eh_framehdr_start = .; *(.eh_framehdr) __eh_framehdr_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .gcc_except_table : { *(.gcc_except_table) -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .mmu_tbl (ALIGN(16384)) : { __mmu_tbl_start = .; *(.mmu_tbl) __mmu_tbl_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) *(.gnu.linkonce.armexidix.*.*) __exidx_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .preinit_array : { __preinit_array_start = .; KEEP (*(SORT(.preinit_array.*))) KEEP (*(.preinit_array)) __preinit_array_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .init_array : { __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .fini_array : { __fini_array_start = .; KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array)) __fini_array_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .ARM.attributes : { __ARM.attributes_start = .; *(.ARM.attributes) __ARM.attributes_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .sdata : { __sdata_start = .; @@ -226,7 +226,7 @@ SECTIONS *(.sdata.*) *(.gnu.linkonce.s.*) __sdata_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .sbss (NOLOAD) : { __sbss_start = .; @@ -234,7 +234,7 @@ SECTIONS *(.sbss.*) *(.gnu.linkonce.sb.*) __sbss_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .tdata : { __tdata_start = .; @@ -242,7 +242,7 @@ SECTIONS *(.tdata.*) *(.gnu.linkonce.td.*) __tdata_end = .; -} > ps7_ram_0_S_AXI_BASEADDR +} > psu_ram_0_S_AXI_BASEADDR .tbss : { __tbss_start = .; @@ -250,7 +250,7 @@ SECTIONS *(.tbss.*) *(.gnu.linkonce.tb.*) __tbss_end = .; -} > ps7_ram_1_S_AXI_BASEADDR +} > psu_ram_1_S_AXI_BASEADDR .bss (NOLOAD) : { __bss_start = .; @@ -261,7 +261,7 @@ SECTIONS *(COMMON) __bss_end = .; __bss_end__ = .; -} > ps7_ram_1_S_AXI_BASEADDR +} > psu_ram_1_S_AXI_BASEADDR _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); @@ -277,7 +277,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _HEAP_SIZE; _heap_end = .; HeapLimit = .; -} > ps7_ram_1_S_AXI_BASEADDR +} > psu_ram_1_S_AXI_BASEADDR .stack (NOLOAD) : { . = ALIGN(16); @@ -305,7 +305,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _UNDEF_STACK_SIZE; . = ALIGN(16); __undef_stack = .; -} > ps7_ram_1_S_AXI_BASEADDR +} > psu_ram_1_S_AXI_BASEADDR _end = .; } diff --git a/lib/sw_apps/zynqmp_fsbl/src/lscript_a53.ld b/lib/sw_apps/zynqmp_fsbl/src/lscript_a53.ld index aa940f4c..6269847b 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/lscript_a53.ld +++ b/lib/sw_apps/zynqmp_fsbl/src/lscript_a53.ld @@ -47,8 +47,8 @@ _EL3_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; MEMORY { - ps8_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x0002FF00 - ps8_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0040, LENGTH = 0x0000FE00 + psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x0002FF00 + psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0040, LENGTH = 0x0000FE00 } /* Specify the default entry point to the program */ @@ -72,27 +72,27 @@ SECTIONS *(.glue_7t) *(.ARM.extab) *(.gnu.linkonce.armextab.*) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .init (ALIGN(64)): { KEEP (*(.init)) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .fini (ALIGN(64)): { KEEP (*(.fini)) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .interp : { __interp_start = .; KEEP (*(.interp)) __interp_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .note-ABI-tag : { __note-ABI-tag_start = .; KEEP (*(.note-ABI-tag)) __note-ABI-tag_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .rodata (ALIGN(64)): { __rodata_start = .; @@ -100,14 +100,14 @@ SECTIONS *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .rodata1 (ALIGN(64)): { __rodata1_start = .; *(.rodata1) *(.rodata1.*) __rodata1_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .sdata2 (ALIGN(64)): { __sdata2_start = .; @@ -115,7 +115,7 @@ SECTIONS *(.sdata2.*) *(.gnu.linkonce.s2.*) __sdata2_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .sbss2 (ALIGN(64)): { __sbss2_start = .; @@ -123,7 +123,7 @@ SECTIONS *(.sbss2.*) *(.gnu.linkonce.sb2.*) __sbss2_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .data (ALIGN(64)): { __data_start = .; @@ -134,26 +134,26 @@ SECTIONS *(.got) *(.got.plt) __data_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .data1 (ALIGN(64)): { __data1_start = .; *(.data1) *(.data1.*) __data1_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .got : { *(.got) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .got1 : { *(.got1) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .got2 : { *(.got2) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .ctors (ALIGN(64)): { __CTOR_LIST__ = .; @@ -164,7 +164,7 @@ SECTIONS KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .dtors (ALIGN(64)): { __DTOR_LIST__ = .; @@ -175,79 +175,79 @@ SECTIONS KEEP (*(.dtors)) __DTOR_END__ = .; ___DTORS_END___ = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .fixup : { __fixup_start = .; *(.fixup) __fixup_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .eh_frame : { *(.eh_frame) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .eh_framehdr : { __eh_framehdr_start = .; *(.eh_framehdr) __eh_framehdr_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .gcc_except_table : { *(.gcc_except_table) -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .mmu_tbl0 (ALIGN(4096)) : { __mmu_tbl0_start = .; *(.mmu_tbl0) __mmu_tbl0_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .mmu_tbl1 (ALIGN(4096)) : { __mmu_tbl1_start = .; *(.mmu_tbl1) __mmu_tbl1_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .mmu_tbl2 (ALIGN(4096)) : { __mmu_tbl2_start = .; *(.mmu_tbl2) __mmu_tbl2_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) *(.gnu.linkonce.armexidix.*.*) __exidx_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .preinit_array (ALIGN(64)): { __preinit_array_start = .; KEEP (*(SORT(.preinit_array.*))) KEEP (*(.preinit_array)) __preinit_array_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .init_array (ALIGN(64)): { __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .fini_array (ALIGN(64)): { __fini_array_start = .; KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array)) __fini_array_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .ARM.attributes : { __ARM.attributes_start = .; *(.ARM.attributes) __ARM.attributes_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .sdata (ALIGN(64)): { __sdata_start = .; @@ -255,7 +255,7 @@ SECTIONS *(.sdata.*) *(.gnu.linkonce.s.*) __sdata_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .sbss (NOLOAD) : { . = ALIGN(64); @@ -265,7 +265,7 @@ SECTIONS *(.gnu.linkonce.sb.*) . = ALIGN(64); __sbss_end = .; -} > ps8_ocm_ram_1_S_AXI_BASEADDR +} > psu_ocm_ram_1_S_AXI_BASEADDR .tdata (ALIGN(64)): { __tdata_start = .; @@ -273,7 +273,7 @@ SECTIONS *(.tdata.*) *(.gnu.linkonce.td.*) __tdata_end = .; -} > ps8_ocm_ram_0_S_AXI_BASEADDR +} > psu_ocm_ram_0_S_AXI_BASEADDR .tbss (ALIGN(64)): { __tbss_start = .; @@ -281,7 +281,7 @@ SECTIONS *(.tbss.*) *(.gnu.linkonce.tb.*) __tbss_end = .; -} > ps8_ocm_ram_1_S_AXI_BASEADDR +} > psu_ocm_ram_1_S_AXI_BASEADDR .bss (NOLOAD) : { . = ALIGN(64); @@ -292,7 +292,7 @@ SECTIONS *(COMMON) . = ALIGN(64); __bss_end__ = .; -} > ps8_ocm_ram_1_S_AXI_BASEADDR +} > psu_ocm_ram_1_S_AXI_BASEADDR _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); @@ -308,7 +308,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _HEAP_SIZE; _heap_end = .; HeapLimit = .; -} > ps8_ocm_ram_1_S_AXI_BASEADDR +} > psu_ocm_ram_1_S_AXI_BASEADDR .stack (NOLOAD) : { . = ALIGN(64); @@ -327,7 +327,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _EL0_STACK_SIZE; . = ALIGN(64); __el0_stack = .; -} > ps8_ocm_ram_1_S_AXI_BASEADDR +} > psu_ocm_ram_1_S_AXI_BASEADDR _end = .; } diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_error.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_error.h index 09c99952..baa7f6bf 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_error.h +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_error.h @@ -78,8 +78,8 @@ extern "C" { * 11 -> Error at stage 4 * x4x5x6 -> Error source for next 10 bits * 000 -> FSBL error code - * 001 -> ps8 init failure - * 010 -> ps8 postconfig failure + * 001 -> psu init failure + * 010 -> psu postconfig failure * 011 -> Driver error code * x7x8 -> */ @@ -89,8 +89,8 @@ extern "C" { #define XFSBL_ERROR_STAGE_3 (0x4000U) #define XFSBL_ERROR_STAGE_4 (0x6000U) -#define XFSBL_PS8_INIT_FAILED (0x0800U) -#define XFSBL_PS8_POSTCONFIG_FAILED (0x1000U) +#define XFSBL_PSU_INIT_FAILED (0x0800U) +#define XFSBL_PSU_POSTCONFIG_FAILED (0x1000U) #define XFSBL_SUCCESS (0x0U) #define XFSBL_STATUS_JTAG (0x1U) diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c index d75acdfb..f624aa2f 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c @@ -53,7 +53,7 @@ /***************************** Include Files *********************************/ #include "xfsbl_hw.h" #include "xil_cache.h" -#include "pss_init.h" +#include "psu_init.h" #include "xfsbl_main.h" #include "xfsbl_image_header.h" @@ -652,10 +652,6 @@ u32 XFsbl_Handoff (XFsblPs * FsblInstancePtr) u32 RunningCpuExecState=0U; s32 RunningCpuHandoffAddressPresent=FALSE; - /** - * post config from ps8_init.c - */ - /** * if JTAG bootmode, be in while loop as of now * Check if Process can be parked in HALT state diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h index f9b1e5aa..2713c546 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h @@ -431,7 +431,7 @@ extern "C" { /** * Definition for NAND to be included */ -#if (!defined(FSBL_NAND_EXCLUDE) && defined(XPAR_XNANDPS8_0_DEVICE_ID)) +#if (!defined(FSBL_NAND_EXCLUDE) && defined(XPAR_XNANDPSU_0_DEVICE_ID)) #define XFSBL_NAND #endif diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c index 4e9d0984..46ce9f3c 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_initialization.c @@ -54,7 +54,7 @@ #include "xfsbl_hw.h" #include "xfsbl_main.h" #include "xfsbl_misc_drivers.h" -#include "pss_init.h" +#include "psu_init.h" #include "xfsbl_qspi.h" @@ -121,11 +121,10 @@ u32 XFsbl_Initialize(XFsblPs * FsblInstancePtr) u32 Status = XFSBL_SUCCESS; /** - * Configure the system as in PS8 + * Configure the system as in PSU */ Status = XFsbl_SystemInit(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -143,8 +142,7 @@ u32 XFsbl_Initialize(XFsblPs * FsblInstancePtr) * Initialize the processor */ Status = XFsbl_ProcessorInit(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -152,8 +150,7 @@ u32 XFsbl_Initialize(XFsblPs * FsblInstancePtr) * Validate the reset reason */ Status = XFsbl_ResetValidation(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -181,8 +178,7 @@ u32 XFsbl_BootDeviceInitAndValidate(XFsblPs * FsblInstancePtr) * Configure the primary boot device */ Status = XFsbl_PrimaryBootDeviceInit(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -190,8 +186,7 @@ u32 XFsbl_BootDeviceInitAndValidate(XFsblPs * FsblInstancePtr) * Read and Validate the header */ Status = XFsbl_ValidateHeader(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -205,11 +200,9 @@ u32 XFsbl_BootDeviceInitAndValidate(XFsblPs * FsblInstancePtr) * Configure the secondary boot device if required */ if (FsblInstancePtr->SecondaryBootDevice != - FsblInstancePtr->PrimaryBootDevice) - { + FsblInstancePtr->PrimaryBootDevice) { Status = XFsbl_SecondaryBootDeviceInit(FsblInstancePtr); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } } @@ -250,13 +243,11 @@ static u32 XFsbl_ProcessorInit(XFsblPs * FsblInstancePtr) XFsbl_Printf(DEBUG_INFO,"Cluster ID 0x%0lx\n\r", ClusterId); - if (XFSBL_PLATFORM == XFSBL_PLATFORM_QEMU) - { + if (XFSBL_PLATFORM == XFSBL_PLATFORM_QEMU) { /** * Remmaping for R5 in QEMU */ - if (ClusterId == 0x80000004U) - { + if (ClusterId == 0x80000004U) { ClusterId = 0xC0000100U; } } @@ -265,15 +256,13 @@ static u32 XFsbl_ProcessorInit(XFsblPs * FsblInstancePtr) * store the processor ID based on the cluster ID * Need a check for unsupported Cluster ID */ - if ((ClusterId & XFSBL_CLUSTER_ID_MASK) == XFSBL_A53_PROCESSOR) - { + if ((ClusterId & XFSBL_CLUSTER_ID_MASK) == XFSBL_A53_PROCESSOR) { XFsbl_Printf(DEBUG_GENERAL,"Running on A53-0 Processor \n\r"); FsblInstancePtr->ProcessorID = XIH_PH_ATTRB_DEST_CPU_A53_0; } else { RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL); - if ((RegValue & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK) == 0U) - { + if ((RegValue & RPU_RPU_GLBL_CNTL_SLSPLIT_MASK) == 0U) { XFsbl_Printf(DEBUG_GENERAL, "Running on R5 Processor in Lockstep \n\r"); FsblInstancePtr->ProcessorID = @@ -288,8 +277,7 @@ static u32 XFsbl_ProcessorInit(XFsblPs * FsblInstancePtr) /** * Update the Vector locations in R5 TCM */ - while (Index<32U) - { + while (Index<32U) { XFsbl_Out32(Index, 0U); XFsbl_Out32(Index, XFSBL_R5_VECTOR_VALUE); Index += 4; @@ -341,8 +329,7 @@ static u32 XFsbl_ResetValidation(XFsblPs * FsblInstancePtr) /* WDT reset is missing in reset reason */ if (((ResetReasonValue & CRL_APB_RESET_REASON_FPD_SWDT_MASK) == CRL_APB_RESET_REASON_FPD_SWDT_MASK) && - (FsblErrorStatus == XFSBL_RUNNING)) - { + (FsblErrorStatus == XFSBL_RUNNING)) { /** * reset is due to System WDT. * Do a fallback @@ -356,8 +343,7 @@ static u32 XFsbl_ResetValidation(XFsblPs * FsblInstancePtr) * Mark FSBL running in error status register to * detect the WDT reset while FSBL execution */ - if (FsblErrorStatus != XFSBL_RUNNING) - { + if (FsblErrorStatus != XFSBL_RUNNING) { XFsbl_Out32(XFSBL_ERROR_STATUS_REGISTER_OFFSET, XFSBL_RUNNING); } @@ -374,7 +360,7 @@ END: /*****************************************************************************/ /** - * This function initializes the system using the ps8_init() + * This function initializes the system using the psu_init() * * @param FsblInstancePtr is pointer to the XFsbl Instance * @@ -387,17 +373,16 @@ static u32 XFsbl_SystemInit(XFsblPs * FsblInstancePtr) u32 Status = XFSBL_SUCCESS; /** - * ps8 initialization + * psu initialization */ - Status = (u32 )pss_init(); - if (XFSBL_SUCCESS != Status) - { - XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PS8_INIT_FAILED\n\r"); + Status = (u32)psu_init(); + if (XFSBL_SUCCESS != Status) { + XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PSU_INIT_FAILED\n\r"); /** * Need to check a way to communicate both FSBL code - * and PS8 init error code + * and PSU init error code */ - Status = XFSBL_PS8_INIT_FAILED + Status; + Status = XFSBL_PSU_INIT_FAILED + Status; goto END; } @@ -407,7 +392,7 @@ static u32 XFsbl_SystemInit(XFsblPs * FsblInstancePtr) /** - * Poweroff the unused blocks as per PS8 + * Poweroff the unused blocks as per PSU */ END: @@ -445,15 +430,13 @@ static u32 XFsbl_PrimaryBootDeviceInit(XFsblPs * FsblInstancePtr) (BootMode == XFSBL_QSPI32_BOOT_MODE) || (BootMode == XFSBL_NAND_BOOT_MODE) || (BootMode == XFSBL_SD_BOOT_MODE) || - (BootMode == XFSBL_EMMC_BOOT_MODE) ) - { + (BootMode == XFSBL_EMMC_BOOT_MODE) ) { /** * Initialize the WDT and CSU drivers */ #ifdef XFSBL_WDT_PRESENT Status = XFsbl_InitWdt(); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { XFsbl_Printf(DEBUG_GENERAL,"WDT initialization failed \n\r"); goto END; } @@ -595,8 +578,7 @@ static u32 XFsbl_PrimaryBootDeviceInit(XFsblPs * FsblInstancePtr) /** * In case of error or Jtag boot, goto end */ - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -604,8 +586,7 @@ static u32 XFsbl_PrimaryBootDeviceInit(XFsblPs * FsblInstancePtr) * Initialize the Device Driver */ Status = FsblInstancePtr->DeviceOps.DeviceInit(); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -650,8 +631,7 @@ static u32 XFsbl_ValidateHeader(XFsblPs * FsblInstancePtr) Status = FsblInstancePtr->DeviceOps.DeviceCopy(FlashImageOffsetAddress + XIH_BH_IMAGE_ATTRB_OFFSET, (PTRSIZE ) &BootHdrAttrb, XIH_FIELD_LEN); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { XFsbl_Printf(DEBUG_GENERAL,"Device Copy Failed \n\r"); goto END; } @@ -663,8 +643,7 @@ static u32 XFsbl_ValidateHeader(XFsblPs * FsblInstancePtr) Status = XFsbl_ReadImageHeader(&FsblInstancePtr->ImageHeader, &FsblInstancePtr->DeviceOps, FlashImageOffsetAddress); - if (XFSBL_SUCCESS != Status) - { + if (XFSBL_SUCCESS != Status) { goto END; } @@ -675,8 +654,7 @@ static u32 XFsbl_ValidateHeader(XFsblPs * FsblInstancePtr) EfuseCtrl = XFsbl_In32(EFUSE_SEC_CTRL); if (((EfuseCtrl & EFUSE_SEC_CTRL_RSA_EN_MASK) != 0) || ((BootHdrAttrb & XIH_BH_IMAGE_ATTRB_RSA_MASK) - == XIH_BH_IMAGE_ATTRB_RSA_MASK)) - { + == XIH_BH_IMAGE_ATTRB_RSA_MASK)) { XFsbl_Printf(DEBUG_INFO,"Authentication Enabled\r\n"); #ifdef XFSBL_RSA diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c index dad3724b..5834b64a 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c @@ -177,7 +177,7 @@ u32 XFsbl_ConvertTime_WdtCounter(u32 seconds) PrescalerValue = 4096; } - time = (double)(PrescalerValue) / (double)XPAR_PS8_WDT_0_WDT_CLK_FREQ_HZ; + time = (double)(PrescalerValue) / (double)XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ; CounterValue = seconds / time; diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_nand.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_nand.c index 0044d8b7..f45c0872 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_nand.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_nand.c @@ -54,7 +54,7 @@ #ifdef XFSBL_NAND -#include "xnandps8.h" +#include "xnandpsu.h" /************************** Constant Definitions *****************************/ @@ -67,9 +67,9 @@ /************************** Variable Definitions *****************************/ -XNandPs8_Config *Config; -XNandPs8 NandInstance; /* XNand Instance */ -XNandPs8 *NandInstPtr = &NandInstance; +XNandPsu_Config *Config; +XNandPsu NandInstance; /* XNand Instance */ +XNandPsu *NandInstPtr = &NandInstance; /*****************************************************************************/ @@ -85,7 +85,7 @@ u32 XFsbl_NandInit(void ) { u32 Status = XFSBL_SUCCESS; - Config = XNandPs8_LookupConfig(NAND_DEVICE_ID); + Config = XNandPsu_LookupConfig(NAND_DEVICE_ID); if (Config == NULL) { Status = XFSBL_ERROR_NAND_INIT; XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_NAND_INIT\r\n"); @@ -94,7 +94,7 @@ u32 XFsbl_NandInit(void ) /** * Initialize the NAND flash driver. */ - Status = (u32 )XNandPs8_CfgInitialize(NandInstPtr, Config, + Status = (u32)XNandPsu_CfgInitialize(NandInstPtr, Config, Config->BaseAddress); if (Status != XST_SUCCESS) { Status = XFSBL_ERROR_NAND_INIT; @@ -129,7 +129,7 @@ u32 XFsbl_NandCopy(u32 SrcAddress, PTRSIZE DestAddress, u32 Length) { u32 Status = XFSBL_SUCCESS; - Status = (u32 )XNandPs8_Read(NandInstPtr, (u64)SrcAddress, (u64)Length, + Status = (u32)XNandPsu_Read(NandInstPtr, (u64)SrcAddress, (u64)Length, (u8 *) DestAddress); if (Status != XST_SUCCESS) { Status = XFSBL_ERROR_NAND_READ; diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_qspi.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_qspi.c index a6eb0036..ae951a13 100644 --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_qspi.c +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_qspi.c @@ -238,7 +238,7 @@ u32 XFsbl_Qspi24Init() * Configure the the qspi in IO mode */ - switch (XPAR_PS8_QSPI_0_QSPI_MODE) { + switch (XPAR_PSU_QSPI_0_QSPI_MODE) { case XQSPIPS_CONNECTION_MODE_SINGLE: { @@ -310,8 +310,8 @@ u32 XFsbl_Qspi24Init() /** * add code: For a Stacked connection, read second Flash ID */ - if ((XPAR_PS8_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_PARALLEL) || - (XPAR_PS8_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_STACKED) ) { + if ((XPAR_PSU_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_PARALLEL) || + (XPAR_PSU_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_STACKED)) { QspiFlashSize = 2 * QspiFlashSize; } @@ -338,10 +338,10 @@ END: ******************************************************************************/ static u32 XFsbl_GetQspiAddr(u32 Address ) { - u32 LqspiCr=0; - u32 QspiAddr=0; + u32 LqspiCr = 0; + u32 QspiAddr = 0; - switch(XPAR_PS8_QSPI_0_QSPI_MODE) { + switch(XPAR_PSU_QSPI_0_QSPI_MODE) { case XQSPIPS_CONNECTION_MODE_SINGLE: QspiAddr = Address;