diff --git a/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h b/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h new file mode 100644 index 00000000..df47fba5 --- /dev/null +++ b/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h @@ -0,0 +1,366 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xilskey_eps_zynqmp.h +* Contains the function prototypes, defines and macros for ZynqMP efusePs +* functionality. +* +* @note None. +* +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- -------------------------------------------------------- +* 4.0 vns 10/01/15 First release +* +* +*****************************************************************************/ + +#ifndef XILSKEY_EPS_ZYNQMP_H +#define XILSKEY_EPS_ZYNQMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xilskey_utils.h" + +/************************** Constant Definitions *****************************/ + +/* Key length definitions for ZynqMP eFuse */ +#define XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES (32) +#define XSK_ZYNQMP_EFUSEPS_USER_KEY_LEN_IN_BYTES (32) +#define XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES (48) +#define XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BYTES (4) +#define XSK_ZYNQMP_EFUSEPS_JTAG_USER_CODE_LEN_IN_BYTES (4) +#define XSK_ZYNQMP_EFUSEPS_DNA_LEN_IN_BYTES (12) + +/* ZynqMP eFuse PS keys lengths in bits */ +#define XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS (256) +#define XSK_ZYNQMP_EFUSEPS_USER_KEY_LEN_IN_BITS (256) +#define XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS (384) +#define XSK_ZYNQMP_EFUSEPS_PPK_SHA2HASH_LEN_IN_BITS (256) +#define XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS (32) +#define XSK_ZYNQMP_EFUSEPS_USR_CODE_LEN_IN_BITS (32) + +/* ZynqMP eFuse maximum bits in a row */ +#define XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW (32) + +/* No of Registers allocated for PPK sha3 hash */ +#define XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM (12) +#define XSK_ZYNQMP_EFUSEPS_USR_KEY_REG_NUM (8) + +/* Row numbers of Efuse PS of Zynq MP */ +#define XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW (7) +#define XSK_ZYNQMP_EFUSEPS_USR_KEY_START_ROW (8) +#define XSK_ZYNQMP_EFUSEPS_USR_KEY_END_ROW (15) +#define XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW (16) +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW (22) +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW (23) +#define XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW (24) +#define XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW (31) + +#define XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW (40) +#define XSK_ZYNQMP_EFUSEPS_PPK0_SHA2_HASH_END_ROW (47) +#define XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW (51) + +#define XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW (52) +#define XSK_ZYNQMP_EFUSEPS_PPK1_SHA2_HASH_END_ROW (59) +#define XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW (63) + +#define XSK_ZYNQMP_EFUSEPS_TBITS_ROW (0) +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_BITS_ROW (21) + +#define XSK_ZYNQMP_EFUSEPS_TBITS_MASK (0xF) +#define XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT (28) + +#define XSK_ZYNQMP_EFUSEPS_CRC_AES_ZEROS (0x6858A3D5) + +/* Timer related macros */ +#define XilSKey_ZynqMp_EfusePs_Tprgrm(RefClk) \ + XilSKey_Ceil(((float)5 * RefClk) / (float)1000000) +#define XilSKey_ZynqMp_EfusePs_Trd(RefClk) \ + XilSKey_Ceil(((float)15 * RefClk) / (float)100000000) +#define XilSKey_ZynqMp_EfusePs_TsuHPs(RefClk) \ + XilSKey_Ceil(((float)67 * RefClk) / (float)1000000000) +#define XilSKey_ZynqMp_EfusePs_TsuHPsCs(RefClk) \ + XilSKey_Ceil(((float)46 * RefClk) / (float)1000000000) +#define XilSKey_ZynqMp_EfusePs_TsuHCs(RefClk) \ + XilSKey_Ceil(((float)30 * RefClk) / (float)1000000000) + +/** @name efuse types + * @{ + */ +typedef enum { + XSK_ZYNQMP_EFUSEPS_EFUSE_0, + XSK_ZYNQMP_EFUSEPS_EFUSE_2 = 2, + XSK_ZYNQMP_EFUSEPS_EFUSE_3 = 3 +}XskEfusePs_Type; +/*@}*/ + +/** @name efuse secure control bits + * @{ + */ +typedef enum { + XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK, + XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK, + XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY, + XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS, + XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS, + XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS, + XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2, + XSK_ZYNQMP_EFUSEPS_SEC_LOCK, + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN = 24, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK = 26, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD = 27, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK = 29, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD +}XskEfusePS_SecCtrlBits; +/*@}*/ + +/** @name efuse misc user control bits + * @{ + */ +typedef enum { + XSK_ZYNQMP_EFUSEPS_USR_WRLK_0, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_1, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_2, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_3, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_4, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_5, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_6, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_7, +}XskEfusePS_MiscUserBits; +/*@}*/ + +/** @name xilinx specific bits + * @{ + */ +typedef enum { + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT1 = 28, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT2, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT3, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT4 +}XskEfusePS_XilinxSpecificBits; +/*@}*/ + +/** +* +* This typedef contains secure control features of efusePs +*/ +typedef struct { + /* Secure and control bits */ + u8 AesKeyRead; + u8 AesKeyWrite; + u8 UseAESOnly; + u8 BbramDisable; + u8 PMUError; + u8 JtagDisable; + u8 DFTDisable; + u8 ProgGate0; + u8 ProgGate1; + u8 ProgGate2; + u8 SecureLock; + u8 RSAEnable; + u8 PPK0WrLock; + u8 PPK0Revoke; + u8 PPK1WrLock; + u8 PPK1Revoke; + + /* User control bits */ + u8 UserWrLk0; + u8 UserWrLk1; + u8 UserWrLk2; + u8 UserWrLk3; + u8 UserWrLk4; + u8 UserWrLk5; + u8 UserWrLk6; + u8 UserWrLk7; + + /* Xilinx specific bits */ + u8 XilinxSpecfBit1; + u8 XilinxSpecfBit2; + u8 XilinxSpecfBit3; + u8 XilinxSpecfBit4; + +} XilSKey_SecCtrlBits; +/*@}*/ + +/** + * XilSKey_ZynqMpEPs is the PS eFUSE driver instance. Using this + * structure, user can define the eFUSE bits of Zynq MP ultrascale to be + * blown. + */ +typedef struct { + + XilSKey_SecCtrlBits PrgrmgSecCtrlBits; + /* For writing into eFuse */ + u8 PrgrmAesKey; + u8 PrgrmUserKey; + u8 PrgrmPpk0Hash; + u8 PrgrmPpk1Hash; + u8 PrgrmSpkID; + u8 PrgrmJtagUserCode; + + u8 IsPpk0Sha3Hash; + u8 IsPpk1Sha3Hash; + + u8 AESKey[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BYTES]; + u8 UserKey[XSK_ZYNQMP_EFUSEPS_USER_KEY_LEN_IN_BYTES]; + u8 Ppk0Hash[XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES]; + u8 Ppk1Hash[XSK_ZYNQMP_EFUSEPS_PPK_HASH_LEN_IN_BYTES]; + u8 SpkId[XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BYTES]; + u8 JtagUserCode[XSK_ZYNQMP_EFUSEPS_JTAG_USER_CODE_LEN_IN_BYTES]; + + XilSKey_SecCtrlBits ReadBackSecCtrlBits; + + u8 IntialisedTimer; + +}XilSKey_ZynqMpEPs; + +/***************** Macros (Inline Functions) Definitions *******************/ +/***************************************************************************/ +/** +* This macro is used to Unlock the eFuse controller. +* +* @return None +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePs_CtrlrUnLock() \ + (XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET, \ + XSK_ZYNQMO_EFUSEP_WR_UNLOCK_VALUE)) + +/***************************************************************************/ +/** +* This macro is used to Lock the eFuse controller. +* +* @return None +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePs_CtrlrLock() \ + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET, \ + XSK_ZYNQMP_EFUSEPS_WR_LOCK_RSTVAL) + +/***************************************************************************/ +/** +* This macro is used to tell the lock status of eFuse controller. +* +* @return +* - TRUE if controller is locked +* - FALSE if controller is Unlocked +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePs_CtrlrLockStatus() \ + (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET) ? 1 : 0) + +/***************************************************************************/ +/** +* This macro is used to tells the status of eFuse controller. +* +* @return +* - TRUE if controller is locked +* - FALSE if controller is Unlocked +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePs_Status() \ + (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_STS_OFFSET)) + +/***************************************************************************/ +/** +* This macro enables the programming of efuse +* +* @return None +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePS_PrgrmEn() \ + (XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, \ + (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) | XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK))) + +/***************************************************************************/ +/** +* This macro disables programming of efuse +* +* @return None. +* +* @note None +* +****************************************************************************/ +#define XilSKey_ZynqMp_EfusePS_PrgrmDisable() \ + (XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, \ + (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, \ + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) & \ + (~XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK)))) + +/****************************Prototypes***************************************/ +/* Ps eFuse interface functions of Zynq MP */ +u32 XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(u32 CrcValue); +u32 XilSKey_ZynqMp_EfusePs_ReadUserKey(u32 *UseKeyPtr, u8 ReadOption); +u32 XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(u32 *Ppk0Hash, u8 ReadOption); +u32 XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(u32 *Ppk1Hash, u8 ReadOption); +u32 XilSKey_ZynqMp_EfusePs_ReadSpkId(u32 *SpkId, u8 ReadOption); +u32 XilSKey_ZynqMp_EfusePs_ReadJtagUsrCode(u32 *JtagUsrCode, u8 ReadOption); +void XilSKey_ZynqMp_EfusePs_ReadDna(u32 *DnaRead); + +u32 XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits( + XilSKey_SecCtrlBits *ReadBackSecCtrlBits, u8 ReadOption); +u32 XilSKey_ZynqMp_EfusePs_CacheLoad(); +u32 XilSKey_ZynqMp_EfusePs_Write(XilSKey_ZynqMpEPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* XILSKEY_EPS_ZYNQMP_H */ diff --git a/lib/sw_services/xilskey/src/include/xilskey_utils.h b/lib/sw_services/xilskey/src/include/xilskey_utils.h index 012def0a..084d392d 100644 --- a/lib/sw_services/xilskey/src/include/xilskey_utils.h +++ b/lib/sw_services/xilskey/src/include/xilskey_utils.h @@ -335,6 +335,12 @@ typedef enum { */ #define XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES (48) +/** + * ZynqMp efusePs ps Ref Clk frequency + */ +#define XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ (33330000) /**< Need to be + * from design */ + /************************** Variable Definitions ****************************/ /** * XADC Structure @@ -491,7 +497,13 @@ typedef enum { XSK_EFUSEPS_ERROR_PARAMETER_NULL, XSK_EFUSEPS_ERROR_STRING_INVALID, + XSK_EFUSEPS_ERROR_AES_ALREADY_PROGRAMMED, + XSK_EFUSEPS_ERROR_SPKID_ALREADY_PROGRAMMED, + XSK_EFUSEPS_ERROR_JTAG_USER_CODE_ALREADY_PROGRAMED, + XSK_EFUSEPS_ERROR_USER_KEY_ALREADY_PROGRAMMED, + XSK_EFUSEPS_ERROR_PROGRAMMING = 0x00A0, + XSK_EFUSEPS_ERROR_READ = 0x00B0, /** * XSKEfuse_Write/Read()common error codes */ @@ -521,6 +533,18 @@ typedef enum { */ XSK_EFUSEPS_ERROR_READ_RSA_HASH=0xA100, + XSK_EFUSEPS_ERROR_WRONG_TBIT_PATTERN = 0xA200, + XSK_EFUSEPS_ERROR_WRITE_AES_KEY = 0xA300, + XSK_EFUSEPS_ERROR_WRITE_SPK_ID = 0xA400, + XSK_EFUSEPS_ERROR_WRITE_USER_KEY = 0xA500, + XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH = 0xA600, + XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH = 0xA700, + XSK_EFUSEPS_ERROR_WRITE_JTAG_USERCODE = 0xA800, + XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING = 0xA900, + XSK_EFUSEPS_ERROR_PROGRAMMING_TBIT_PATTERN = 0XB100, + + XSK_EFUSEPS_ERROR_CACHE_LOAD = 0xB000, + }XSKEfusePs_ErrorCodes; /* diff --git a/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c new file mode 100644 index 00000000..72055b2a --- /dev/null +++ b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c @@ -0,0 +1,1933 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xilskey_eps_zynqmp.c +* This file contains the PS eFUSE API's of ZynqMp to program/read the +* eFUSE array. +* +* @note None. +* +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------ +* 4.0 vns 10/01/15 First release +* +* +*****************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xilskey_eps_zynqmp.h" +#include "xilskey_eps_zynqmp_hw.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ + + +/************************** Function Prototypes *****************************/ + +static inline u32 XilSKey_ZynqMp_EfusePsWrite_Checks( + XilSKey_ZynqMpEPs *InstancePtr); +static inline u32 XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(u8 *Data, + u8 RowStart, u8 RowEnd, XskEfusePs_Type EfuseType); +static inline u32 XilSKey_ZynqMp_EfusePs_PrgrmTbits(); +static inline u32 XilSKey_ZynqMp_EfusePs_WriteBit(u8 Row, u8 Column, + XskEfusePs_Type EfuseType); +static inline void XilSKey_ZynqMp_EfusePs_SetTimerValues( + XilSKey_ZynqMpEPs *InstancePtr); +static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrl( + XilSKey_ZynqMpEPs *InstancePtr); +static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits( + XilSKey_ZynqMpEPs *InstancePtr); +static inline u32 XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits( + XilSKey_ZynqMpEPs *InstancePtr); +static inline u32 XilSKey_ZynqMp_EfusePs_Write_XilinxSpecific_CntlBits( + XilSKey_ZynqMpEPs *InstancePtr); +static inline void XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs( + XilSKey_SecCtrlBits *ReadBackSecCtrlBits); +static inline u32 XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg( + XilSKey_ZynqMpEPs *InstancePtr); + +u32 XilSKey_ZynqMp_EfusePs_SetWriteConditions(); +u32 XilSKey_ZynqMp_EfusePs_ReadRow(u8 Row, XskEfusePs_Type EfuseType, + u32 *RowData); +u32 XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(u8 Row, u8 Column, + XskEfusePs_Type EfuseType); +u32 XilSKey_ZynqMp_EfusePs_CheckForZeros(u8 RowStart, u8 RowEnd, + XskEfusePs_Type EfuseType); + +/************************** Function Definitions *****************************/ + +/***************************************************************************/ +/** +* This function is used to program the PS efuse of ZynqMP. +* +* @param InstancePtr is the pointer to the XilSKey_ZynqMpEPs. +* +* @return +* - XST_SUCCESS if programs successfully. +* - Errorcode on failure +* +* @note Cache reload is required for obtaining updated values. +* +****************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_Write(XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 Status = XST_SUCCESS; + u8 AesKeyInBits[XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS] = {0}; + u8 UserKeyInBits[XSK_ZYNQMP_EFUSEPS_USER_KEY_LEN_IN_BITS] = {0}; + u8 Ppk0InBits[XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS] = {0}; + u8 Ppk1InBits[XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS] = {0}; + u8 UsrCodeInBits[XSK_ZYNQMP_EFUSEPS_USR_CODE_LEN_IN_BITS] = {0}; + u8 SpkIdInBits[XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS] = {0}; + + /* Conditions to check programming is possible or not */ + Status = XilSKey_ZynqMp_EfusePsWrite_Checks(InstancePtr); + if (Status != XST_SUCCESS) { + return (Status + XSK_EFUSEPS_ERROR_BEFORE_PROGRAMMING); + } + + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + /* Setting all the conditions for writing into eFuse */ + Status = XilSKey_ZynqMp_EfusePs_SetWriteConditions(InstancePtr); + if (Status != XST_SUCCESS) { + goto END; + } + + /* Check for Zeros for Programming eFuse */ + Status = XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg(InstancePtr); + if (Status != XST_SUCCESS) { + goto END; + } + + if (InstancePtr->PrgrmAesKey == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->AESKey, + AesKeyInBits, XSK_ZYNQMP_EFUSEPS_AES_KEY_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + AesKeyInBits,XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW, + XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + XSK_EFUSEPS_ERROR_WRITE_AES_KEY); + goto END; + } + } + if (InstancePtr->PrgrmUserKey == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->UserKey, + UserKeyInBits, XSK_ZYNQMP_EFUSEPS_USER_KEY_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + UserKeyInBits, XSK_ZYNQMP_EFUSEPS_USR_KEY_START_ROW, + XSK_ZYNQMP_EFUSEPS_USR_KEY_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + XSK_EFUSEPS_ERROR_WRITE_USER_KEY); + goto END; + } + } + if (InstancePtr->PrgrmJtagUserCode == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->JtagUserCode, + UsrCodeInBits, XSK_ZYNQMP_EFUSEPS_USR_CODE_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + UsrCodeInBits, XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW, + XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + + XSK_EFUSEPS_ERROR_WRITE_JTAG_USERCODE); + goto END; + } + } + if (InstancePtr->PrgrmSpkID == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->SpkId, + SpkIdInBits, XSK_ZYNQMP_EFUSEPS_SPKID_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + SpkIdInBits, XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW, + XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + XSK_EFUSEPS_ERROR_WRITE_SPK_ID); + goto END; + } + } + if (InstancePtr->PrgrmPpk0Hash == TRUE) { + /* Programming SHA3 hash(384 bit) into Efuse PPK0 */ + if (InstancePtr->IsPpk0Sha3Hash == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes( + InstancePtr->Ppk0Hash, Ppk0InBits, + XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS); + Status = + XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + Ppk0InBits, XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + + XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH); + goto END; + } + } + /* Programming SHA2 hash(256 bit) into Efuse PPK0 */ + else { + XilSKey_Efuse_ConvertBitsToBytes( + InstancePtr->Ppk0Hash, Ppk0InBits, + XSK_ZYNQMP_EFUSEPS_PPK_SHA2HASH_LEN_IN_BITS); + Status = + XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + Ppk0InBits, XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK0_SHA2_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + + XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH); + goto END; + } + } + } + if (InstancePtr->PrgrmPpk1Hash == TRUE) { + /* Programming SHA3 hash(384 bit) into Efuse PPK1 */ + if (InstancePtr->IsPpk1Sha3Hash == TRUE) { + XilSKey_Efuse_ConvertBitsToBytes( + InstancePtr->Ppk1Hash, Ppk1InBits, + XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + Ppk1InBits, XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + + XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH); + goto END; + } + } + /* Programming SHA2 hash(256 bit) into Efuse PPK1 */ + else { + XilSKey_Efuse_ConvertBitsToBytes( + InstancePtr->Ppk1Hash, Ppk1InBits, + XSK_ZYNQMP_EFUSEPS_PPK_SHA2HASH_LEN_IN_BITS); + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange( + Ppk1InBits, XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK1_SHA2_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + Status = (Status + + XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH); + goto END; + } + } + } + + /* Programming Secure and control bits */ + Status = XilSKey_ZynqMp_EfusePs_Write_SecCtrl(InstancePtr); + if (Status != XST_SUCCESS) { + goto END; + } + +END: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + XilSKey_ZynqMp_EfusePS_PrgrmDisable(); + + return Status; + +} + +/*****************************************************************************/ +/** +* This function is used to read the PS efuse secure control bits. +* +* @param ReadBackSecCtrlBits is the pointer to the XilSKey_SecCtrlBits +* which holds the read secure control bits. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* - XST_SUCCESS if reads successfully +* - XST_FAILURE if reading is failed +* +* @note Cache reload is required for obtaining updated values for +* ReadOption 0. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits( + XilSKey_SecCtrlBits *ReadBackSecCtrlBits, u8 ReadOption) +{ + u32 RegData; + u32 Status; + u8 DataInBits[32]; + + if (ReadOption == 0) { + XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs( + ReadBackSecCtrlBits); + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + Status = XilSKey_ZynqMp_EfusePs_ReadRow( + XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0, &RegData); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RegData, DataInBits, + XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW); + ReadBackSecCtrlBits->UserWrLk0 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_0]; + ReadBackSecCtrlBits->UserWrLk1 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_1]; + ReadBackSecCtrlBits->UserWrLk2 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_2]; + ReadBackSecCtrlBits->UserWrLk3 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_3]; + ReadBackSecCtrlBits->UserWrLk4 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_4]; + ReadBackSecCtrlBits->UserWrLk5 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_5]; + ReadBackSecCtrlBits->UserWrLk6 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_6]; + ReadBackSecCtrlBits->UserWrLk7 = + DataInBits[XSK_ZYNQMP_EFUSEPS_USR_WRLK_7]; + + Status = XilSKey_ZynqMp_EfusePs_ReadRow( + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0, &RegData); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RegData, DataInBits, + XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW); + ReadBackSecCtrlBits->AesKeyRead = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK]; + ReadBackSecCtrlBits->AesKeyWrite = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK]; + ReadBackSecCtrlBits->UseAESOnly = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY]; + ReadBackSecCtrlBits->BbramDisable = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS]; + ReadBackSecCtrlBits->PMUError = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS]; + ReadBackSecCtrlBits->JtagDisable = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS]; + ReadBackSecCtrlBits->DFTDisable = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS]; + ReadBackSecCtrlBits->ProgGate0 = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0]; + ReadBackSecCtrlBits->ProgGate1 = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1]; + ReadBackSecCtrlBits->ProgGate2 = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2]; + ReadBackSecCtrlBits->SecureLock = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_LOCK]; + ReadBackSecCtrlBits->RSAEnable = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN]; + ReadBackSecCtrlBits->PPK0WrLock = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK]; + ReadBackSecCtrlBits->PPK0Revoke = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD]; + ReadBackSecCtrlBits->PPK1WrLock = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK]; + ReadBackSecCtrlBits->PPK1Revoke = + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD]; + + Status = XilSKey_ZynqMp_EfusePs_ReadRow( + XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_BITS_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0, &RegData); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + XilSKey_Efuse_ConvertBitsToBytes((u8 *)&RegData, DataInBits, + XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW); + ReadBackSecCtrlBits->XilinxSpecfBit1 = + DataInBits[XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT1]; + ReadBackSecCtrlBits->XilinxSpecfBit2 = + DataInBits[XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT2]; + ReadBackSecCtrlBits->XilinxSpecfBit3 = + DataInBits[XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT3]; + ReadBackSecCtrlBits->XilinxSpecfBit4 = + DataInBits[XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT4]; + +UNLOCK: + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + } + + return Status; + +} + +/*****************************************************************************/ +/** +* This function is used to read the PS efuse secure control bits from cache. +* +* @param ReadBackSecCtrlBits is the pointer to the XilSKey_SecCtrlBits +* which holds the read secure control bits. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static inline void XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits_Regs( + XilSKey_SecCtrlBits *ReadBackSecCtrlBits) +{ + + u32 RegData; + + RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET); + ReadBackSecCtrlBits->UserWrLk0 = + RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_MASK; + ReadBackSecCtrlBits->UserWrLk1 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_SHIFT; + ReadBackSecCtrlBits->UserWrLk2 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_SHIFT; + ReadBackSecCtrlBits->UserWrLk3 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_SHIFT; + ReadBackSecCtrlBits->UserWrLk4 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_SHIFT; + ReadBackSecCtrlBits->UserWrLk5 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_SHIFT; + ReadBackSecCtrlBits->UserWrLk6 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_SHIFT; + ReadBackSecCtrlBits->UserWrLk7 = + (RegData & XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_MASK) >> + XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_SHIFT; + + RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET); + ReadBackSecCtrlBits->AesKeyRead = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_MASK); + ReadBackSecCtrlBits->AesKeyWrite = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_SHIFT; + ReadBackSecCtrlBits->UseAESOnly = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_SHIFT; + ReadBackSecCtrlBits->BbramDisable = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_SHIFT; + ReadBackSecCtrlBits->PMUError = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_SHIFT; + ReadBackSecCtrlBits->JtagDisable = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_SHIFT; + ReadBackSecCtrlBits->DFTDisable = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_SHIFT; + ReadBackSecCtrlBits->ProgGate0 = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_SHIFT; + ReadBackSecCtrlBits->ProgGate1 = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_SHIFT; + ReadBackSecCtrlBits->ProgGate2 = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_SHIFT; + ReadBackSecCtrlBits->SecureLock = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_SHIFT; + ReadBackSecCtrlBits->RSAEnable = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_SHIFT; + ReadBackSecCtrlBits->PPK0WrLock = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_SHIFT; + ReadBackSecCtrlBits->PPK0Revoke = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_SHIFT; + ReadBackSecCtrlBits->PPK1WrLock = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_SHIFT; + ReadBackSecCtrlBits->PPK1Revoke = + (RegData & XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_MASK) >> + XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_SHIFT; + + RegData = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_ROW); + ReadBackSecCtrlBits->XilinxSpecfBit1 = + (RegData & XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT1_MASK) >> + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT1_SHIFT; + ReadBackSecCtrlBits->XilinxSpecfBit2 = + (RegData & XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT2_MASK) >> + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT2_SHIFT; + ReadBackSecCtrlBits->XilinxSpecfBit3 = + (RegData & XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT3_MASK) >> + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT3_SHIFT; + ReadBackSecCtrlBits->XilinxSpecfBit4 = + (RegData & XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT4_MASK) >> + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT4_SHIFT; + +} + +/*****************************************************************************/ +/** +* This function performs pre checks for programming all the specified bits. +* +* @param InstancePtr is the pointer to the XilSKey_ZynqMpEPs. +* +* @return +* XST_SUCCESS - if all the conditions for programming is satisfied +* Errorcode - if any of the conditions are not met +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePsWrite_Checks( + XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 RowOffset; + /* Read secure and control bits */ + XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits( + &(InstancePtr->ReadBackSecCtrlBits), 0); + if (InstancePtr->PrgrmAesKey == TRUE) { + if (InstancePtr->ReadBackSecCtrlBits.AesKeyWrite == + TRUE) { + return (XSK_EFUSEPS_ERROR_WRITE_AES_KEY); + } + } + if (InstancePtr->PrgrmSpkID == TRUE) { + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_PGM_LOCK_OFFSET) != 0x00) { + return (XSK_EFUSEPS_ERROR_WRITE_SPK_ID); + } + /* Check for Zeros */ + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET) != 0x00) { + return ( + XSK_EFUSEPS_ERROR_SPKID_ALREADY_PROGRAMMED); + } + } + if (InstancePtr->PrgrmUserKey == TRUE) { + if ((InstancePtr->ReadBackSecCtrlBits.UserWrLk0 == + TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk1 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk2 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk3 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk4 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk5 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk6 == TRUE) || + (InstancePtr->ReadBackSecCtrlBits.UserWrLk7 == TRUE)) { + return (XSK_EFUSEPS_ERROR_WRITE_USER_KEY); + } + /* Check for Zeros */ + for (RowOffset = XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET; + RowOffset < XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET; + RowOffset = RowOffset + 4) { + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + RowOffset) != 0x00) { + return ( + XSK_EFUSEPS_ERROR_USER_KEY_ALREADY_PROGRAMMED); + } + } + } + if (InstancePtr->PrgrmPpk0Hash == TRUE) { + if (InstancePtr->ReadBackSecCtrlBits.PPK0WrLock == + TRUE) { + return (XSK_EFUSEPS_ERROR_WRITE_PPK0_HASH); + } + /* Check for Zeros */ + for (RowOffset = XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET; + RowOffset < XSK_ZYNQMP_EFUSEPS_PPK0_11_OFFSET; + RowOffset = RowOffset + 4) { + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + RowOffset) != 0x00) { + return ( + XSK_EFUSEPS_ERROR_RSA_HASH_ALREADY_PROGRAMMED); + } + } + } + if (InstancePtr->PrgrmPpk1Hash == TRUE) { + if (InstancePtr->ReadBackSecCtrlBits.PPK1WrLock == + TRUE) { + return (XSK_EFUSEPS_ERROR_WRITE_PPK1_HASH); + } + /* Check for Zeros */ + for (RowOffset = XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET; + RowOffset < XSK_ZYNQMP_EFUSEPS_PPK1_11_OFFSET; + RowOffset = RowOffset + 4) { + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + RowOffset) != 0x00) { + return ( + XSK_EFUSEPS_ERROR_RSA_HASH_ALREADY_PROGRAMMED); + } + } + } + if (InstancePtr->PrgrmJtagUserCode == TRUE) { + /* Check for Zeros */ + if (XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_USRCODE_OFFSET) != 0x00) { + return ( + XSK_EFUSEPS_ERROR_JTAG_USER_CODE_ALREADY_PROGRAMED); + } + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* This function programs and verifys the Row range provided with provided data. +* +* @param Data is a pointer to an array which contains data to be +* programmed. +* @param RowStart holds the row number from which data programming has to +* be started. +* @param RowEnd holds the row number till which data programming has to +* be performed. +* @param EfuseType holds the type of the efuse in which programming rows +* resides in. +* +* @return +* XST_SUCCESS - On success +* XST_FAILURE - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_WriteAndVerify_RowRange(u8 *Data, + u8 RowStart, u8 RowEnd, XskEfusePs_Type EfuseType) +{ + u8 Row; + u8 Column; + u32 Status; + u32 Bit; + + for (Row = RowStart; Row <= RowEnd; Row++) { + for (Column = 0; Column < 32; Column++) { + Bit = (Row - RowStart) * XSK_ZYNQMP_EFUSEPS_MAX_BITS_IN_ROW; + Bit += Column; + if (Data[Bit]) { + Status = + XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + Column, EfuseType); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/* This function programs Tbits +* +* @param None. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_PrgrmTbits() +{ + u32 RowData; + u32 Status; + u8 Column; + u32 TbitsPrgrmReg; + + /* Enable TBITS programming bit */ + TbitsPrgrmReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_OFFSET); + + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_OFFSET, + (TbitsPrgrmReg & (~XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_MASK))); + + Status = XilSKey_ZynqMp_EfusePs_ReadRow(XSK_ZYNQMP_EFUSEPS_TBITS_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0, &RowData); + if (Status != XST_SUCCESS) { + return Status; + } + if (((RowData >> XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT) & + XSK_ZYNQMP_EFUSEPS_TBITS_MASK) != 0x00) { + return XSK_EFUSEPS_ERROR_PROGRAMMING_TBIT_PATTERN; + } + + Status = XilSKey_ZynqMp_EfusePs_ReadRow(XSK_ZYNQMP_EFUSEPS_TBITS_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_2, &RowData); + if (Status != XST_SUCCESS) { + return Status; + } + if (((RowData >> XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT) & + XSK_ZYNQMP_EFUSEPS_TBITS_MASK) != 0x00) { + return XSK_EFUSEPS_ERROR_PROGRAMMING_TBIT_PATTERN; + } + + Status = XilSKey_ZynqMp_EfusePs_ReadRow(XSK_ZYNQMP_EFUSEPS_TBITS_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_3, &RowData); + if (Status != XST_SUCCESS) { + return Status; + } + if (((RowData >> XSK_ZYNQMP_EFUSEPS_TBITS_SHIFT) & + XSK_ZYNQMP_EFUSEPS_TBITS_MASK) != 0x00) { + return XSK_EFUSEPS_ERROR_PROGRAMMING_TBIT_PATTERN; + } + + /* Programming Tbits */ + for (Column = 28; Column <= 31; Column++) { + if ((Column == 28) || (Column == 30)) { + continue; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit( + XSK_ZYNQMP_EFUSEPS_TBITS_ROW, Column, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return Status; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit( + XSK_ZYNQMP_EFUSEPS_TBITS_ROW, Column, + XSK_ZYNQMP_EFUSEPS_EFUSE_2); + if (Status != XST_SUCCESS) { + return Status; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit( + XSK_ZYNQMP_EFUSEPS_TBITS_ROW, Column, + XSK_ZYNQMP_EFUSEPS_EFUSE_3); + if (Status != XST_SUCCESS) { + return Status; + } + } + + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_OFFSET, TbitsPrgrmReg); + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* This function programs and verifys the particular bit of efuse array +* +* @param Row specifies the row number. +* @param Column specifies the column number. +* @param EfuseType specifies the efuse type. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(u8 Row, u8 Column, + XskEfusePs_Type EfuseType) +{ + u32 RowData; + u32 Status; + + /* + * TBD temperature and voltage check once the sysmon driver is ready + * it will be added here + */ + + /* Programming bit */ + Status = XilSKey_ZynqMp_EfusePs_WriteBit(Row, Column, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET, + XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET)); + + /* + * If Row Belongs to AES key can't verify the bit + * as AES key can be checked only CRC + */ + if ((Row >= XSK_ZYNQMP_EFUSEPS_AES_KEY_START_ROW) && + (Row <= XSK_ZYNQMP_EFUSEPS_AES_KEY_END_ROW)) { + return XST_SUCCESS; + } + + /* verifying the programmed bit */ + Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, EfuseType, &RowData); + + if (Status != XST_SUCCESS) { + return Status; + } + + if (((RowData >> Column) & 0x01) == 0x00) { + return XSK_EFUSEPS_ERROR_VERIFICATION; + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function returns particular row data directly from efuse array. +* +* @param Row specifies the row number to read. +* @param EfuseType specifies the efuse type. +* @param RowData is a pointer to 32 bit variable to hold the data read +* from provided data +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadRow(u8 Row, XskEfusePs_Type EfuseType, + u32 *RowData) +{ + u32 WriteValue; + u32 ReadValue; + + WriteValue = ((EfuseType << XSK_ZYNQMP_EFUSEPS_RD_ADDR_SHIFT) & + XSK_ZYNQMP_EFUSEPS_RD_ADDR_MASK) | + ((Row << XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_SHIFT) & + XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_MASK); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_RD_ADDR_OFFSET, WriteValue); + + /* Check for read completion */ + ReadValue = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET) & + (XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK | + XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK); + while (ReadValue == 0x00) { + ReadValue = + XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET) & + (XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK | + XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK); + } + if (ReadValue & XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK) { + return XSK_EFUSEPS_ERROR_READ; + } + + *RowData = + XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_RD_DATA_OFFSET); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/* +* This function programs a particular bit. +* +* @param Row specifies the row number to program. +* @param Column specifies the column number to program. +* @param EfuseType specifies the efuse type. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_WriteBit(u8 Row, u8 Column, + XskEfusePs_Type EfuseType) +{ + + u32 WriteValue; + u32 ReadValue; + + WriteValue = ((EfuseType << XSK_ZYNQMP_EFUSEPS_PGM_ADDR_SHIFT) & + XSK_ZYNQMP_EFUSEPS_PGM_ADDR_MASK) | + ((Row << XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_SHIFT) & + XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_MASK) | + (Column & XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_MASK); + + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_PGM_ADDR_OFFSET, WriteValue); + + ReadValue = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET) & + (XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK | + XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK); + while (ReadValue == 0x00) { + ReadValue = + XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET) & + (XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK | + XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK); + } + + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET, + XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET)); + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function reloads the cache of efuse so that can be directly read from +* cache. +* +* @param None. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_CacheLoad() +{ + volatile u32 CacheStatus; + + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + } + + /* Reload cache */ + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_OFFSET, + XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_MASK); + + CacheStatus = XilSKey_ZynqMp_EfusePs_Status() & + (XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK | + XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK); + + /* Waiting for cache loading completion */ + while(CacheStatus == XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK) { + CacheStatus = XilSKey_ZynqMp_EfusePs_Status() & + (XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK); + if ((CacheStatus) == XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK) { + break; + } + } + + CacheStatus = XilSKey_ZynqMp_EfusePs_Status(); + if ((CacheStatus & XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK) == 0x00) { + return XSK_EFUSEPS_ERROR_CACHE_LOAD; + } + + CacheStatus = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_ISR_OFFSET); + if ((CacheStatus & XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK) == + XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK) { + return XSK_EFUSEPS_ERROR_CACHE_LOAD; + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function sets all the required parameters to program efuse array. +* +* @param InstancePtr is an instance of efuseps of Zynq MP. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_SetWriteConditions(XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 ReadReg; + u32 Status; + + /* + * TBD temperature and voltage check once the sysmon driver is ready + * it will be added here + */ + + /* Enable Program enable bit */ + XilSKey_ZynqMp_EfusePS_PrgrmEn(); + + /* Setting Timing Constraints */ + if (InstancePtr->IntialisedTimer != TRUE) { + XilSKey_ZynqMp_EfusePs_SetTimerValues(InstancePtr); + } + + /* Read status and verify Tbits are read properly or not */ + ReadReg = XilSKey_ZynqMp_EfusePs_Status(); + if ((ReadReg & (XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK | + XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK | + XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK)) != + (XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK | + XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK | + XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK)) { + /* program Tbits */ + Status = XilSKey_ZynqMp_EfusePs_PrgrmTbits(); + if (Status != XST_SUCCESS) { + return Status; + } + XilSKey_ZynqMp_EfusePs_CacheLoad(); + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function sets timers for programming and reading from efuse. +* +* @param InstancePtr is an instance of efuseps of Zynq MP. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static inline void XilSKey_ZynqMp_EfusePs_SetTimerValues( + XilSKey_ZynqMpEPs *InstancePtr) +{ + float RefClk; + u32 ReadReg; + + ReadReg = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET) & + ~(XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK); + ReadReg = ReadReg | + ((XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_2_RD << + XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_SHIFT) | + (XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK)); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_CFG_OFFSET, ReadReg); + + /* Initialized Timer */ + RefClk = XSK_ZYNQMP_EFUSEPS_PS_REF_CLK_FREQ; + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TPGM_OFFSET, + ((u32)XilSKey_ZynqMp_EfusePs_Tprgrm(RefClk) & + XSK_ZYNQMP_EFUSEPS_TPGM_VAL_MASK)); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TRD_OFFSET, + ((u32)XilSKey_ZynqMp_EfusePs_Trd(RefClk) & + XSK_ZYNQMP_EFUSEPS_TRD_VAL_MASK)); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TSU_H_PS_OFFSET, + ((u32)XilSKey_ZynqMp_EfusePs_TsuHPs(RefClk) & + XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_MASK)); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_OFFSET, + ((u32)XilSKey_ZynqMp_EfusePs_TsuHPsCs(RefClk) & + XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_MASK)); + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_TSU_H_CS_OFFSET, + ((u32)XilSKey_ZynqMp_EfusePs_TsuHCs(RefClk) & + XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_DEFVAL)); + + InstancePtr->IntialisedTimer = TRUE; +} + +/*****************************************************************************/ +/* +* This function programs secure control bits specified by user. +* +* @param InstancePtr is an instance of efuseps of Zynq MP. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrl( + XilSKey_ZynqMpEPs *InstancePtr) +{ + + u32 Status; + + /* Programming Secure and control bits of eFuse */ + Status = XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits(InstancePtr); + if (Status != XST_SUCCESS) { + return Status; + } + + /* Programming User control bits */ + Status = XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits(InstancePtr); + if (Status != XST_SUCCESS) { + return Status; + } + + /* Programming Xilinx specific control bits */ + Status = + XilSKey_ZynqMp_EfusePs_Write_XilinxSpecific_CntlBits(InstancePtr); + if (Status != XST_SUCCESS) { + return Status; + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function programs secure control bits of efuse +* +* @param InstancePtr is an instance of efuseps of ZynqMp. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits( + XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 Status; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + u32 Row; + + Row = XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW; + if ((InstancePtr->PrgrmgSecCtrlBits.AesKeyRead != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.AesKeyRead == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_AES_RDLK, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.AesKeyWrite != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.AesKeyWrite == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_AES_WRLK, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UseAESOnly != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UseAESOnly == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_ENC_ONLY, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.BbramDisable != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.BbramDisable == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_BRAM_DIS, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.PMUError != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.PMUError == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_ERR_DIS, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.JtagDisable != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.JtagDisable == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_JTAG_DIS, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.DFTDisable != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.DFTDisable == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_DFT_DIS, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.ProgGate0 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.ProgGate0 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE0, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.ProgGate1 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.ProgGate1 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.ProgGate2 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.ProgGate2 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.SecureLock != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.SecureLock == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_LOCK, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.RSAEnable != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.RSAEnable == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + (XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN + 1), EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.PPK0WrLock != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.PPK0WrLock == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.PPK0Revoke != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.PPK0Revoke == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + (XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD + 1), EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.PPK1WrLock != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.PPK1WrLock == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.PPK1Revoke != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.PPK1Revoke == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD + 1, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function programs misc user control bits of efuse +* +* @param InstancePtr is an instance of efuseps of ZynqMp. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits( + XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 Status; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + u32 Row = XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW; + + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk0 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk0 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_0, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk1 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk1 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_1, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk2 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk2 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_2, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk3 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk3 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_3, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk4 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk4 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_4, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk5 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk5 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_5, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk6 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk6 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_6, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.UserWrLk7 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.UserWrLk7 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_USR_WRLK_7, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function programs Xilinx control bits of efuse +* +* @param InstancePtr is an instance of efuseps of ZynqMp. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_Write_XilinxSpecific_CntlBits( + XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 Status; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + u32 Row = XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_BITS_ROW; + + if ((InstancePtr->PrgrmgSecCtrlBits.XilinxSpecfBit1 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.XilinxSpecfBit1 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT1, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.XilinxSpecfBit2 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.XilinxSpecfBit2 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT2, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.XilinxSpecfBit3 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.XilinxSpecfBit3 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT3, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + if ((InstancePtr->PrgrmgSecCtrlBits.XilinxSpecfBit4 != 0x00) && + (InstancePtr->ReadBackSecCtrlBits.XilinxSpecfBit4 == 0x00)) { + Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, + XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_BIT4, EfuseType); + if (Status != XST_SUCCESS) { + return Status; + } + } + + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/* +* This function performs CRC check of AES key +* +* @param CrcValue is a 32 bit CRC of AES key. +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note For Calculating CRC of AES key key use XilSKey_CrcCalculation() +* API. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc(u32 CrcValue) +{ + + u32 Status = XST_SUCCESS; + u32 ReadReg; + + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + } + + /* writing CRC value to check AES key's CRC */ + XilSKey_WriteReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_AES_CRC_OFFSET, + (CrcValue & XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_MASK)); + + /* Poll for CRC Done bit */ + ReadReg = XilSKey_ZynqMp_EfusePs_Status(); + + while ((ReadReg & XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_MASK) == 0x00) { + ReadReg = XilSKey_ZynqMp_EfusePs_Status(); + } + + if ((ReadReg & XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_MASK) == 0x00) { + Status = XST_FAILURE; + } + + + return Status; + +} + +/*****************************************************************************/ +/* +* This function is used to read user key from efuse based on read option. +* +* @param UserkeyPtr is a pointer to an array which holds the readback +* userkey in. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadUserKey(u32 *UseKeyPtr, u8 ReadOption) +{ + u32 Status = XST_SUCCESS; + u32 Row; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + u32 RegNum; + + if (ReadOption == 0) { + for (RegNum = 0; + RegNum < XSK_ZYNQMP_EFUSEPS_USR_KEY_REG_NUM; RegNum++) { + *UseKeyPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET + + (RegNum * 4)); + UseKeyPtr++; + } + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + for (Row = XSK_ZYNQMP_EFUSEPS_USR_KEY_START_ROW; + Row <= XSK_ZYNQMP_EFUSEPS_USR_KEY_END_ROW; Row++) { + Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, EfuseType, + UseKeyPtr); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + UseKeyPtr++; + } + +UNLOCK: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + } + + return Status; + +} + +/*****************************************************************************/ +/* +* This function is used to read PPK0 hash from efuse based on read option. +* +* @param Ppk0Hash is a pointer to an array which holds the readback +* PPK0 hash in. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadPpk0Hash(u32 *Ppk0Hash, u8 ReadOption) +{ + u32 Status = XST_SUCCESS; + u32 Row; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + s32 RegNum; + u32 DataRead; + + if (ReadOption == 0) { + for (RegNum = (XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM - 1); + RegNum >= 0; RegNum--) { + DataRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET + + (RegNum * 4)); + XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk0Hash, 8); + Ppk0Hash++; + } + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + for (Row = XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW; + Row >= XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW; + Row--) { + Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, + EfuseType, &DataRead); + XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk0Hash, 8); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + Ppk0Hash++; + } + +UNLOCK: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + } + + return Status; + +} + +/*****************************************************************************/ +/* +* This function is used to read PPK1 hash from efuse based on read option. +* +* @param Ppk1Hash is a pointer to an array which holds the readback +* PPK1 hash in. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadPpk1Hash(u32 *Ppk1Hash, u8 ReadOption) +{ + u32 Status = XST_SUCCESS; + u32 Row; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + s32 RegNum; + u32 DataRead; + + if (ReadOption == 0) { + for (RegNum = (XSK_ZYNQMP_EFUSEPS_PPK_HASH_REG_NUM - 1); + RegNum >= 0; + RegNum--) { + DataRead = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET + + (RegNum * 4)); + XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk1Hash, 8); + Ppk1Hash++; + } + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + for (Row = XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW; + Row >= XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW; Row--) { + Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, + EfuseType, &DataRead); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + XilSKey_EfusePs_ConvertBytesBeToLe((u8 *)&DataRead, (u8 *)Ppk1Hash, 8); + Ppk1Hash++; + } + +UNLOCK: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + } + + return Status; + +} + +/*****************************************************************************/ +/* +* This function is used to read SPKID from efuse based on read option. +* +* @param SPK ID is a pointer to a 32 bit variable which holds SPK ID. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadSpkId(u32 *SpkId, u8 ReadOption) +{ + u32 Status = XST_SUCCESS; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + + if (ReadOption == 0) { + *SpkId = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET); + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + Status = XilSKey_ZynqMp_EfusePs_ReadRow( + XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW, EfuseType, SpkId); + if (Status != XST_SUCCESS) { + goto UNLOCK; + } + +UNLOCK: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + + } + + return Status; +} + +/*****************************************************************************/ +/* +* This function is used to read JTAG user code from efuse based on read option. +* +* @param JtagUsrCode is a pointer to 32 bit variable which holds the +* readback JTAG user code in. +* @param ReadOption is a u8 variable which has to be provided by user +* based on this input reading is happend from cache or from efuse +* array. +* - 0 Reads from cache +* - 1 Reads from efuse array +* +* @return +* XST_SUCCESS - On success +* ErrorCode - on Failure +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_ReadJtagUsrCode(u32 *JtagUsrCode, u8 ReadOption) +{ + u32 Status = XST_SUCCESS; + XskEfusePs_Type EfuseType = XSK_ZYNQMP_EFUSEPS_EFUSE_0; + + if (ReadOption == 0) { + *JtagUsrCode = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_USRCODE_OFFSET); + } + else { + /* Unlock the controller */ + XilSKey_ZynqMp_EfusePs_CtrlrUnLock(); + /* Check the unlock status */ + if (XilSKey_ZynqMp_EfusePs_CtrlrLockStatus()) { + return (XSK_EFUSEPS_ERROR_CONTROLLER_LOCK); + } + + Status = XilSKey_ZynqMp_EfusePs_ReadRow( + XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW, EfuseType, JtagUsrCode); + if (Status != XST_SUCCESS) { + goto END; + } + +END: + /* Lock the controller back */ + XilSKey_ZynqMp_EfusePs_CtrlrLock(); + + } + + return Status; + +} + +/*****************************************************************************/ +/* +* This function is used to read DNA from efuse. +* +* @param DnaRead is a pointer to 32 bit variable which holds the +* readback DNA in. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XilSKey_ZynqMp_EfusePs_ReadDna(u32 *DnaRead) +{ + u32 *DnaPtr = DnaRead; + + *DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_DNA_0_OFFSET); + DnaPtr++; + *DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_DNA_1_OFFSET); + DnaPtr++; + *DnaPtr = XilSKey_ReadReg(XSK_ZYNQMP_EFUSEPS_BASEADDR, + XSK_ZYNQMP_EFUSEPS_DNA_2_OFFSET); + +} + +/*****************************************************************************/ +/* +* This function is used verify efuse keys for Zeros +* +* @param RowStart is row number from which verification has to be +* started. +* @param RowEnd is row number till which verification has to be +* ended. +* @param EfuseType is the type of the efuse in which these rows reside. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +u32 XilSKey_ZynqMp_EfusePs_CheckForZeros(u8 RowStart, u8 RowEnd, + XskEfusePs_Type EfuseType) +{ + + u32 Status = XST_SUCCESS; + u8 Row; + u32 RowData; + + for (Row = RowStart; Row <= RowEnd; Row++) { + Status = XilSKey_ZynqMp_EfusePs_ReadRow(Row, EfuseType, + &RowData); + if (Status != XST_SUCCESS) { + return Status; + } + if (RowData != 0x00) { + return XST_FAILURE; + } + } + + return Status; +} + +/*****************************************************************************/ +/* +* This function is used verify efuse keys for Zeros before programming. +* +* @param InstancePtr is a pointer to efuse ps instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static inline u32 XilSKey_ZynqMp_EfusePs_CheckZeros_BfrPrgrmg( + XilSKey_ZynqMpEPs *InstancePtr) +{ + u32 Status; + + /* Check for AES key with All zeros */ + if (InstancePtr->PrgrmAesKey == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc( + XSK_ZYNQMP_EFUSEPS_CRC_AES_ZEROS); + if (Status != XST_SUCCESS) { + return XST_FAILURE;/* Error code of AES is non zero */ + } + } + + /* Check for User Key Zeros*/ + if (InstancePtr->PrgrmUserKey == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckForZeros( + XSK_ZYNQMP_EFUSEPS_USR_KEY_START_ROW, + XSK_ZYNQMP_EFUSEPS_USR_KEY_START_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* Check for JTAG user code zeros */ + if (InstancePtr->PrgrmJtagUserCode == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckForZeros( + XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW, + XSK_ZYNQMP_EFUSEPS_JTAG_USERCODE_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* Check for JTAG user code zeros */ + if (InstancePtr->PrgrmSpkID == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckForZeros( + XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW, + XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* Check Zeros for PPK0 hash */ + if (InstancePtr->PrgrmPpk0Hash == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckForZeros( + XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK0_SHA3_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* Check Zeros for PPK0 hash */ + if (InstancePtr->PrgrmPpk1Hash == TRUE) { + Status = XilSKey_ZynqMp_EfusePs_CheckForZeros( + XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW, + XSK_ZYNQMP_EFUSEPS_PPK1_SHA3_HASH_END_ROW, + XSK_ZYNQMP_EFUSEPS_EFUSE_0); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; + +} diff --git a/lib/sw_services/xilskey/src/xilskey_eps_zynqmp_hw.h b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp_hw.h new file mode 100644 index 00000000..9ec1fac9 --- /dev/null +++ b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp_hw.h @@ -0,0 +1,1054 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xilskey_eps_zynqmp_hw.h +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx ZynqMp eFuse controller. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 4.0   vns     10/01/15 First release
+*
+* +******************************************************************************/ + +#ifndef __XSK_EPS_ZYNQMP_HW_H__ +#define __XSK_EPS_ZYNQMP_HW_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name eFuse PS Base Address + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_BASEADDR 0xFFCC0000U/**< Efuse PS base address */ +/*@}*/ + +/** @name Write lock register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_OFFSET 0x00000000U +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_RSTVAL 0x00000001U + +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_WIDTH 16U +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_MASK 0x0000ffffU +#define XSK_ZYNQMP_EFUSEPS_WR_LOCK_DEFVAL 0x1U +#define XSK_ZYNQMO_EFUSEP_WR_UNLOCK_VALUE 0xDF0D +/*@}*/ + +/** @name Cfg register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_CFG_OFFSET 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_CFG_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_MASK 0x00000020U +#define XSK_ZYNQMP_EFUSEPS_CFG_SLVERR_EN_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_MASK 0x0000000cU +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_RD_DEFVAL 0x0U +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_1_RD 0x01 +#define XSK_ZYNQMP_EFUSEPS_CFG_MARGIN_2_RD 0x02 +#define XSK_ZYNQMP_EFUSEPS_CFG_NORMAL_RD 0x00 + +#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_CFG_PGM_EN_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_CFG_CLK_SEL_DEFVAL 0x0U +/*@}*/ + +/** @name Status register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_STS_OFFSET 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_STS_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_SHIFT 7U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_MASK 0x00000080U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_PASS_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_SHIFT 6U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_MASK 0x00000040U +#define XSK_ZYNQMP_EFUSEPS_STS_AES_CRC_DONE_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_MASK 0x00000020U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_DONE_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_STS_CACHE_LOAD_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_STS_3_TBIT_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_STS_2_TBIT_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_STS_0_TBIT_DEFVAL 0x0U +/*@}*/ + +/** @name program address register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_OFFSET 0x0000000CU +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_SHIFT 11U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_MASK 0x00001800U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_WIDTH 6U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_MASK 0x000007e0U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_ROW_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_WIDTH 5U +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_MASK 0x0000001fU +#define XSK_ZYNQMP_EFUSEPS_PGM_ADDR_COL_DEFVAL 0x0U +/*@}*/ + +/** @name read address register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_OFFSET 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_SHIFT 11U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_MASK 0x00001800U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_WIDTH 6U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_MASK 0x000007e0U +#define XSK_ZYNQMP_EFUSEPS_RD_ADDR_ROW_DEFVAL 0x0U +/*@}*/ + +/** @name read data register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_OFFSET 0x00000014U +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_RD_DATA_DEFVAL 0x0U +/*@}*/ + +/** @name TPGM register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TPGM_OFFSET 0x00000018U +#define XSK_ZYNQMP_EFUSEPS_TPGM_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_WIDTH 16U +#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_MASK 0x0000ffffU +#define XSK_ZYNQMP_EFUSEPS_TPGM_VAL_DEFVAL 0x0U +/*@}*/ + +/** @name TRD register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TRD_OFFSET 0x0000001CU +#define XSK_ZYNQMP_EFUSEPS_TRD_RSTVAL 0x00000022U + +#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_WIDTH 8U +#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_MASK 0x000000ffU +#define XSK_ZYNQMP_EFUSEPS_TRD_VAL_DEFVAL 0x22U +/*@}*/ + +/** @name TSU_H_PS register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_OFFSET 0x00000020U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_RSTVAL 0x000000ffU + +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_WIDTH 8U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_MASK 0x000000ffU +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_VAL_DEFVAL 0xffU +/*@}*/ + +/** @name TSU H PS register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_OFFSET 0x00000024U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_RSTVAL 0x0000000bU + +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_WIDTH 8U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_MASK 0x000000ffU +#define XSK_ZYNQMP_EFUSEPS_TSU_H_PS_CS_VAL_DEFVAL 0xbU +/*@}*/ + +/** @name TSU H CS register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_OFFSET 0x0000002CU +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_RSTVAL 0x00000007U + +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_WIDTH 4U +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_MASK 0x0000000fU +#define XSK_ZYNQMP_EFUSEPS_TSU_H_CS_VAL_DEFVAL 0x7U +/*@}*/ + +/** @name ISR register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_ISR_OFFSET 0x00000030U +#define XSK_ZYNQMP_EFUSEPS_ISR_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_SHIFT 31U +#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_MASK 0x80000000U +#define XSK_ZYNQMP_EFUSEPS_ISR_APB_SLVERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_ISR_CACHE_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_ISR_RD_DONE_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_ISR_PGM_DONE_DEFVAL 0U +/*@}*/ + +/** @name IMR register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_IMR_OFFSET 0x00000034U +#define XSK_ZYNQMP_EFUSEPS_IMR_RSTVAL 0x8000001fU + +#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_SHIFT 31U +#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_MASK 0x80000000U +#define XSK_ZYNQMP_EFUSEPS_IMR_APB_SLVERR_DEFVAL 0x1U + +#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_IMR_CACHE_ERR_DEFVAL 0x1U + +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_ERR_DEFVAL 0x1U + +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_IMR_RD_DONE_DEFVAL 0x1U + +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_ERR_DEFVAL 0x1U + +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_IMR_PGM_DONE_DEFVAL 0x1U +/*@}*/ + +/** @name IER register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_IER_OFFSET 0x00000038U +#define XSK_ZYNQMP_EFUSEPS_IER_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_SHIFT 31U +#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_MASK 0x80000000U +#define XSK_ZYNQMP_EFUSEPS_IER_APB_SLVERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_IER_CACHE_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_IER_RD_DONE_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_IER_PGM_DONE_DEFVAL 0x0U +/*@}*/ + +/** @name IDR register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_IDR_OFFSET 0x0000003CU +#define XSK_ZYNQMP_EFUSEPS_IDR_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_SHIFT 31U +#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_MASK 0x80000000U +#define XSK_ZYNQMP_EFUSEPS_IDR_APB_SLVERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_IDR_CACHE_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_IDR_RD_DONE_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_ERR_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_IDR_PGM_DONE_DEFVAL 0x0U +/*@}*/ + +/** @name Cache load register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_OFFSET 0x00000040U +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_CACHE_LOAD_DEFVAL 0x0U +/*@}*/ + +/** @name Program lock register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_OFFSET 0x00000044U +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_PGM_LOCK_SPK_ID_DEFVAL 0x0U +/*@}*/ + +/** @name AES CRC register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_OFFSET 0x00000048U +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_AES_CRC_VAL_DEFVAL 0x0U +/*@}*/ + +/** @name Tbits programming enable register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_OFFSET 0x00000100 +#define XSK_ZYNQMP_EFUSEPS_TBITS_PRGRMG_EN_MASK 0x00000008 +/*@}*/ + +/** @name DNA 0 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_DNA_0_OFFSET 0x0000100CU +#define XSK_ZYNQMP_EFUSEPS_DNA_0_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_DNA_0_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_DNA_0_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_DNA_0_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_DNA_0_DEFVAL 0x0U +/*@}*/ + +/** @name DNA 1 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_DNA_1_OFFSET 0x00001010U +#define XSK_ZYNQMP_EFUSEPS_DNA_1_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_DNA_1_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_DNA_1_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_DNA_1_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_DNA_1_DEFVAL 0x0U +/*@}*/ + +/** @name DNA 2 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_DNA_2_OFFSET 0x00001014U +#define XSK_ZYNQMP_EFUSEPS_DNA_2_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_DNA_2_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_DNA_2_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_DNA_2_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_DNA_2_DEFVAL 0x0U +/*@}*/ + +/** @name user code register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USRCODE_OFFSET 0x0000101CU +#define XSK_ZYNQMP_EFUSEPS_USRCODE_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USRCODE_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USRCODE_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USRCODE_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USRCODE_DEFVAL 0x0U +/*@}*/ + +/** @name User_0 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_0_OFFSET 0x00001020U +#define XSK_ZYNQMP_EFUSEPS_USER_0_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_0_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_0_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_0_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_0_DEFVAL 0x0U +/*@}*/ + +/** @name User_1 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_1_OFFSET 0x00001024U +#define XSK_ZYNQMP_EFUSEPS_USER_1_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_1_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_1_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_1_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_1_DEFVAL 0x0U +/*@}*/ + +/** @name User_2 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_2_OFFSET 0x00001028U +#define XSK_ZYNQMP_EFUSEPS_USER_2_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_2_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_2_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_2_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_2_DEFVAL 0x0U +/*@}*/ + +/** @name User_3 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_3_OFFSET 0x0000102CU +#define XSK_ZYNQMP_EFUSEPS_USER_3_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_3_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_3_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_3_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_3_DEFVAL 0x0U +/*@}*/ + +/** @name User_4 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_4_OFFSET 0x00001030U +#define XSK_ZYNQMP_EFUSEPS_USER_4_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_4_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_4_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_4_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_4_DEFVAL 0x0U +/*@}*/ + +/** @name User_5 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_5_OFFSET 0x00001034U +#define XSK_ZYNQMP_EFUSEPS_USER_5_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_5_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_5_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_5_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_5_DEFVAL 0x0U +/*@}*/ + +/** @name User_6 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_6_OFFSET 0x00001038U +#define XSK_ZYNQMP_EFUSEPS_USER_6_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_6_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_6_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_6_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_6_DEFVAL 0x0U +/*@}*/ + +/** @name User_7 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_USER_7_OFFSET 0x0000103CU +#define XSK_ZYNQMP_EFUSEPS_USER_7_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_USER_7_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_USER_7_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_USER_7_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_USER_7_DEFVAL 0x0U +/*@}*/ + +/** @name Misc user control register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_OFFSET 0x00001040U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_SHIFT 7U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_MASK 0x00000080U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_7_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_SHIFT 6U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_MASK 0x00000040U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_6_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_MASK 0x00000020U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_5_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_4_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_3_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_2_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_1_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_MISC_USER_CTRL_USR_WRLK_0_DEFVAL 0x0U +/*@}*/ + +/** @name Secure control register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_OFFSET 0x00001058U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_SHIFT 30U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_MASK 0xc0000000U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_INVLD_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_SHIFT 29U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_MASK 0x20000000U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK1_WRLK_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_SHIFT 27U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_MASK 0x18000000U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_INVLD_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_SHIFT 26U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_MASK 0x04000000U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PPK0_WRLK_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_SHIFT 24U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_WIDTH 2U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_MASK 0x03000000U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_RSA_EN_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_SHIFT 10U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_MASK 0x00000400U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_LOCK_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_SHIFT 9U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_MASK 0x00000200U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_2_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_SHIFT 8U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_MASK 0x00000100U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_1_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_SHIFT 7U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_MASK 0x00000080U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_PROG_GATE_0_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_SHIFT 6U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_MASK 0x00000040U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_DFT_DIS_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_SHIFT 5U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_MASK 0x00000020U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_JTAG_DIS_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_SHIFT 4U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_MASK 0x00000010U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ERR_DIS_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_SHIFT 3U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_MASK 0x00000008U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_BBRAM_DIS_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_SHIFT 2U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_MASK 0x00000004U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ENC_ONLY_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_SHIFT 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_MASK 0x00000002U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_WRLK_DEFVAL 0x0U + +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_WIDTH 1U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_MASK 0x00000001U +#define XSK_ZYNQMP_EFUSEPS_SEC_CTRL_AES_RDLK_DEFVAL 0x0U +/*@}*/ + +/** @name SPK ID register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_OFFSET 0x0000105CU +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_SPK_ID_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_0 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_OFFSET 0x000010A0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_0_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_1 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_OFFSET 0x000010A4U +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_1_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_2 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_OFFSET 0x000010A8U +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_2_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_3 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_OFFSET 0x000010ACU +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_3_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_4 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_OFFSET 0x000010B0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_4_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_5 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_OFFSET 0x000010B4U +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_5_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_6 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_OFFSET 0x000010B8U +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_6_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_7 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_OFFSET 0x000010BCU +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_7_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_8 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_OFFSET 0x000010C0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_8_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_9 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_OFFSET 0x000010C4U +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_9_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_10 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_OFFSET 0x000010C8U +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_10_DEFVAL 0x0U +/*@}*/ + +/** @name PPK0_11 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_OFFSET 0x000010CCU +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK0_11_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_0 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_OFFSET 0x000010D0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_0_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_1 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_OFFSET 0x000010D4U +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_1_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_2 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_OFFSET 0x000010D8U +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_2_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_3 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_OFFSET 0x000010DCU +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_3_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_4 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_OFFSET 0x000010E0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_4_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_5 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_OFFSET 0x000010E4U +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_5_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_6 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_OFFSET 0x000010E8U +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_6_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_7 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_OFFSET 0x000010ECU +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_7_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_8 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_OFFSET 0x000010F0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_8_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_8 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_OFFSET 0x000010F4U +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_9_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_10 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_OFFSET 0x000010F8U +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_10_DEFVAL 0x0U +/*@}*/ + +/** @name PPK1_11 register + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_OFFSET 0x000010FCU +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_RSTVAL 0x00000000U + +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_SHIFT 0U +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_WIDTH 32U +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_MASK 0xffffffffU +#define XSK_ZYNQMP_EFUSEPS_PPK1_11_DEFVAL 0x0U +/*@}*/ + +/** @name Xilinx Specific control bits + * @{ + */ +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_ROW 0x00001054 + +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT1_MASK 0x10000000 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT1_SHIFT 28 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT2_MASK 0x20000000 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT2_SHIFT 29 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT3_MASK 0x40000000 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT3_SHIFT 30 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT4_MASK 0x80000000 +#define XSK_ZYNQMP_EFUSEPS_XILINX_SPECFC_CTRLBIT4_SHIFT 31 +/*@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __XSK_EPS_ZYNQMP_HW_H__ */