From 54d7a3f1daaf68d5d4bdd4793ee6c86109ee2954 Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Fri, 11 Jul 2014 12:42:35 +0530 Subject: [PATCH] rgb2ycrcb: Deprecated rgb2ycrcb_v6_0 driver. Deprecated rgb2ycrcb_v6_0 driver and added active rgb2ycrcb_v7_0 driver. Signed-off-by: Shadul Shaikh Acked-by: Srikanth Vemula --- .../drivers/rgb2ycrcb/data/rgb2ycrcb.mdd | 45 ++ .../drivers/rgb2ycrcb/data/rgb2ycrcb.tcl | 42 ++ .../drivers/rgb2ycrcb/examples/example.c | 195 ++++++++ .../drivers/rgb2ycrcb/examples/index.html | 17 + .../drivers/rgb2ycrcb/src/Makefile | 29 ++ .../drivers/rgb2ycrcb/src/rgb2ycrcb.c | 265 +++++++++++ .../drivers/rgb2ycrcb/src/rgb2ycrcb.h | 427 ++++++++++++++++++ 7 files changed, 1020 insertions(+) create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.mdd create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.tcl create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/example.c create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/index.html create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/src/Makefile create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.c create mode 100755 XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.h diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.mdd b/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.mdd new file mode 100755 index 00000000..bb722e9e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.mdd @@ -0,0 +1,45 @@ +############################################################################### +# +# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +OPTION psf_version = 2.1; + +BEGIN driver rgb2ycrcb + + OPTION supported_peripherals = (v_rgb2ycrcb); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION VERSION = 7.0; + OPTION NAME = rgb2ycrcb; + +END driver + + diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.tcl b/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.tcl new file mode 100755 index 00000000..5c3d624e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/data/rgb2ycrcb.tcl @@ -0,0 +1,42 @@ +############################################################################### +# +# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +# +# MODIFICATION HISTORY: +# Ver Who Date Changes +# -------- ------ -------- ------------------------------------ +# 6.0 adk 12/10/13 Updated as per the New Tcl API's +################################################################## + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "RGB2YCRCB" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_HAS_CLIP" "C_HAS_CLAMP" "C_ACOEF" "C_BCOEF" "C_CCOEF" "C_DCOEF" "C_YOFFSET" "C_CBOFFSET" "C_CROFFSET" "C_YMAX" "C_YMIN" "C_CBMAX" "C_CBMIN" "C_CRMAX" "C_CRMIN" + xdefine_canonical_xpars $drv_handle "xparameters.h" "RGB2YCRCB" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_HAS_CLIP" "C_HAS_CLAMP" "C_ACOEF" "C_BCOEF" "C_CCOEF" "C_DCOEF" "C_YOFFSET" "C_CBOFFSET" "C_CROFFSET" "C_YMAX" "C_YMIN" "C_CBMAX" "C_CBMIN" "C_CRMAX" "C_CRMIN" +} diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/example.c b/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/example.c new file mode 100755 index 00000000..cd8b9d26 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/example.c @@ -0,0 +1,195 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file example.c + * + * This file demonstrates how to use Xilinx RGB to YCrCb Color Space Converter + * (RGB2YCRCB) driver on Xilinx RGB to YCrCb Color Space Converter (RGB2YCRCB) + * core. This code does not cover the Xilinx TimeBase setup and any other + * configuration which might be required to get the YCRCB2RGB device working properly. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 5.00a tb   02/27/12 Updates for the v5.00.a release
+ *
+ * + * *************************************************************************** + */ + +#include "rgb2ycrcb.h" +#include "xparameters.h" + +/***************************************************************************/ +// RGB to YCrCb Color Space Converter Register Reading Example +// This function provides an example of how to read the current configuration +// settings of the RGB2YCRCB core. +/***************************************************************************/ +void report_rgb_settings(u32 BaseAddress) { + xil_printf("RGB to YCrCb Color Space Converter Core Configuration:\r\n"); + xil_printf(" Version: 0x%08x\r\n", RGB_ReadReg(BaseAddress, RGB_VERSION)); + xil_printf(" Enable Bit: %1d\r\n", RGB_ReadReg(BaseAddress, RGB_CONTROL) & RGB_CTL_EN_MASK); + + xil_printf(" Register Update Bit: %1d\r\n", (RGB_ReadReg(BaseAddress, RGB_CONTROL) & RGB_CTL_RUE_MASK) >> 1); + + xil_printf(" Reset Bit: %1d\r\n", (RGB_ReadReg(BaseAddress, RGB_CONTROL) & RGB_RST_RESET) >> 31); + + xil_printf(" AutoReset Bit: %1d\r\n", (RGB_ReadReg(BaseAddress, RGB_CONTROL) & RGB_RST_AUTORESET) >> 30); + + xil_printf(" Columns=0x%8x, Rows=0x%8x\r\n", + (RGB_ReadReg(BaseAddress, RGB_ACTIVE_SIZE)>>16), + (RGB_ReadReg(BaseAddress, RGB_ACTIVE_SIZE)&0xFFFF)); + + xil_printf(" Acoef=0x%8x, Bcoef=0x%8x, Ccoef=0x%8x, Dcoef=0x%8x\r\n", + RGB_ReadReg(BaseAddress, RGB_ACOEF), + RGB_ReadReg(BaseAddress, RGB_BCOEF), + RGB_ReadReg(BaseAddress, RGB_CCOEF), + RGB_ReadReg(BaseAddress, RGB_DCOEF)); + + xil_printf(" Y Offset=0x%8x, Cb Offset=0x%8x, Cr Offset=0x%8x\r\n", + RGB_ReadReg(BaseAddress, RGB_YOFFSET), + RGB_ReadReg(BaseAddress, RGB_CBOFFSET), + RGB_ReadReg(BaseAddress, RGB_CROFFSET)); + + xil_printf(" Y Max=0x%8x, Y Min=0x%8x\r\n", + RGB_ReadReg(BaseAddress, RGB_YMAX), + RGB_ReadReg(BaseAddress, RGB_YMIN)); + + xil_printf(" Cb Max=0x%8x, Cb Min=0x%8x\r\n", + RGB_ReadReg(BaseAddress, RGB_CBMAX), + RGB_ReadReg(BaseAddress, RGB_CBMIN)); + + xil_printf(" Cr Max=0x%8x, Cr Min=0x%8x\r\n", + RGB_ReadReg(BaseAddress, RGB_CRMAX), + RGB_ReadReg(BaseAddress, RGB_CRMIN)); +} + + + +/***************************************************************************/ +// RGB to YCrCb Color Space Converter Register Update Example +// This function provides an example of the process used to update +// the coefficient and offset registers in the RGB2YCrCb core. +// In most video systems, it is expected that this process would be executed +// in response to an interrupt connected to the SOF timing signal +// or a timeout signal associated with a watchdog timer. +/***************************************************************************/ +void RGB_Update_Example() { + //Enable the RGB2YCRCB software enable + RGB_Enable(XPAR_RGB2YCRCB_0_BASEADDR); + + //Disable register updates. + //This is the default operating mode for the CCM core, and allows + //registers to be updated without effecting the core's behavior. + RGB_RegUpdateDisable(XPAR_RGB2YCRCB_0_BASEADDR); + + //Set the Active Columns and Rows + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_ACTIVE_SIZE, (1280<<16)+720); //1280x720 + + //Set the coefficients + // These values are floating point values in the range: [0.0, 1.0) + // These are represented as integers by multiplying by 2^16, + // resulting in an integer value in the range from [0, 65535] + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_ACOEF, 19595); //ACOEF = 0.299 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_BCOEF, 7471); //BCOEF = 0.114 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CCOEF, 46727); //CCOEF = 0.713 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_DCOEF, 36962); //DCOEF = 0.564 + + //Set the offsets + // For 8-bit color: Valid range = [ -256, 255] + // For 10-bit color: Valid range = [ -1024, 1023] + // For 12-bit color: Valid range = [ -4096, 4095] + // For 16-bit color: Valid range = [-65536, 65535] + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_YOFFSET, 16); //YOFFSET = 16 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CBOFFSET, 128); //CBOFFSET = 128 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CROFFSET, 128); //CROFFSET = 128 + + //Set the Clip/Clamp + // For 8-bit color: Valid range = [0, 255] + // For 10-bit color: Valid range = [0, 1023] + // For 12-bit color: Valid range = [0, 4095] + // For 16-bit color: Valid range = [0, 65535] + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_YMAX, 240); //YMAX = 240 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_YMIN, 16); //YMIN = 16 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CBMAX, 240); //CBMAX = 240 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CBMIN, 16); //CBMIN = 16 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CRMAX, 240); //CRMAX = 240 + RGB_WriteReg(XPAR_RGB2YCRCB_0_BASEADDR, RGB_CRMIN, 16); //CRMIN = 16 + + //Enable register updates. + //This mode will cause the coefficient and offset registers internally + //to the CCM core to automatically be updated on the next SOF. + RGB_RegUpdateEnable(XPAR_RGB2YCRCB_0_BASEADDR); + +} + + +/*****************************************************************************/ +// +// This is the main function for the RGB2YCrCb example. +// +/*****************************************************************************/ +int main(void) +{ + struct rgb_coef_inputs coef_in; + struct rgb_coef_outputs coef_out; + + // Print the current settings for the RGB2YCrCb core + report_rgb_settings(XPAR_RGB2YCRCB_0_BASEADDR); + + // Call the RGB2YCrCb example, specify the Device ID generated in xparameters.h + RGB_Update_Example(XPAR_RGB2YCRCB_0_BASEADDR); + + // Read the current RGB2YCrCb core coefficients + RGB_get_coefficients(XPAR_RGB2YCRCB_0_BASEADDR, &coef_out); + + // Setup coef_in for SD_ITU_601, 16_to_235_for_Studio_Equipment + // and data width of 8-bits + RGB_select_standard(0, 1, XPAR_RGB2YCRCB_0_M_AXIS_VIDEO_DATA_WIDTH, &coef_in); + + // Translate into RGB2YCrCb core coefficients + RGB_coefficient_translation(&coef_in, &coef_out,XPAR_RGB2YCRCB_0_M_AXIS_VIDEO_DATA_WIDTH); + + // Program the new RGB2YCrCb core coefficients + RGB_set_coefficients(XPAR_RGB2YCRCB_0_BASEADDR, &coef_out); + + // Print the current settings for the RGB2YCrCb core + report_rgb_settings(XPAR_RGB2YCRCB_0_BASEADDR); + + return 0; +} + + diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/index.html b/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/index.html new file mode 100755 index 00000000..03af02aa --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/examples/index.html @@ -0,0 +1,17 @@ + + + + + +Driver example applications + + + +

Example Applications for the driver rgb2ycrcb_v6_0

+
+ +

Copyright � 1995-2014 Xilinx, Inc. All rights reserved.

+ + \ No newline at end of file diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/Makefile b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/Makefile new file mode 100755 index 00000000..b808e77a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/Makefile @@ -0,0 +1,29 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a +LEVEL=0 + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c + +OUTS = *.o + +libs: + echo "Compiling rgb2ycrcb" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} + diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.c b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.c new file mode 100755 index 00000000..0ab47689 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.c @@ -0,0 +1,265 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file rgb2ycrcb.c +* +* This is main code of Xilinx RGB to YCrCb Color Space Converter (RGB2YCRCB) +* device driver. Please see rgb2ycrcb.h for more details of the driver. +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 5.00a tb 02/27/12 Updated for RGB2YCRCB v5.00.a +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "rgb2ycrcb.h" +#include "xenv.h" +#include "stdio.h" + + +/*****************************************************************************/ +// Note: Most of the functions are currently implemented as high-performance +// macros within rgb2ycrcb.h +/*****************************************************************************/ + +/*****************************************************************************/ +/** +* +* Select input coefficients for 4 supported Standards and 3 Input Ranges. +* +* @param standard_sel is the standards selection: 0 = SD_ITU_601 +* 1 = HD_ITU_709__1125_NTSC +* 2 = HD_ITU_709__1250_PAL +* 3 = YUV +* @param input_range is the limit on the range of the data: 0 = 16_to_240_for_TV, +* 1 = 16_to_235_for_Studio_Equipment, +* 3 = 0_to_255_for_Computer_Graphics +* @param data_width has a valid range of [8,10,12,16] +* @param coef_in is a pointer to a rgb_coef_inputs data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_select_standard(u32 standard_sel, u32 input_range, u32 data_width, struct rgb_coef_inputs *coef_in) +{ + double acoef[4][3] = {{0.299, 0.299, 0.2568}, {0.299, 0.299, 0.2568}, {0.2126, 0.2126, 0.1819}, {0.299, 0.299, 0.299}}; + double bcoef[4][3] = {{0.114, 0.114, 0.0979}, {0.114, 0.114, 0.0979}, {0.0722, 0.0722, 0.0618}, {0.114, 0.114, 0.114}}; + double ccoef[4][3] = {{0.713, 0.7295, 0.5910}, {0.713, 0.7295, 0.5910}, {0.6350, 0.6495, 0.6495}, {0.877283, 0.877283, 0.877283}}; + double dcoef[4][3] = {{0.564, 0.5772, 0.5772}, {0.564, 0.5772, 0.5772}, {0.5389, 0.5512, 0.5512}, {0.492111, 0.492111, 0.492111}}; + u32 yoffset = 1<<(data_width-4); + u32 coffset = 1<<(data_width-1); + u32 max[3] = {(240*(1<<(data_width-8))), (235*(1<<(data_width-8))), ((1<acoef = acoef[standard_sel][input_range]; + coef_in->bcoef = bcoef[standard_sel][input_range]; + coef_in->ccoef = ccoef[standard_sel][input_range]; + coef_in->dcoef = dcoef[standard_sel][input_range]; + coef_in->yoffset = yoffset; + coef_in->cboffset = coffset; + coef_in->croffset = coffset; + coef_in->ymax = max[input_range]; + coef_in->ymin = min[input_range]; + coef_in->cbmax = max[input_range]; + coef_in->cbmin = min[input_range]; + coef_in->crmax = max[input_range]; + coef_in->crmin = min[input_range]; +} + + +/*****************************************************************************/ +/** +* +* Translate input coefficients into coefficients that can be programmed into the +* RGB2YCrCb core. +* +* @param coef_in is a pointer to a rgb_coef_inputs data structure. +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return The 32-bit value: bit(0)= Acoef + Bcoef > 1.0 +* bit(1)= Y Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(2)= Cb Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(3)= Cr Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(4)= Y Max outside data width range [0, (2^data_width)-1] +* bit(5)= Y Min outside data width range [0, (2^data_width)-1] +* bit(6)= Cb Max outside data width range [0, (2^data_width)-1] +* bit(7)= Cb Min outside data width range [0, (2^data_width)-1] +* bit(8)= Cr Max outside data width range [0, (2^data_width)-1] +* bit(9)= Cr Min outside data width range [0, (2^data_width)-1] +* +* @note +* +******************************************************************************/ +u32 RGB_coefficient_translation(struct rgb_coef_inputs *coef_in, struct rgb_coef_outputs *coef_out, u32 data_width) +{ + u32 ret_val = 0; + + if((coef_in->acoef + coef_in->bcoef) > 1.0) { + printf("WARNING: Acoef (%1f) + Bcoef (%1f) can not be more then 1.0\r\n",coef_in->acoef, coef_in->bcoef); + ret_val = ret_val | 0x1; + } + if(coef_in->yoffset < -(1<yoffset > (1<yoffset, (unsigned int)-(1<cboffset < -(1<cboffset > (1<cboffset, (unsigned int)-(1<croffset < -(1<croffset > (1<croffset, (unsigned int)-(1<ymax < 0 || coef_in->ymax > (1<ymax, (unsigned int)(1<ymin < 0 || coef_in->ymin > (1<ymin, (unsigned int)(1<cbmax < 0 || coef_in->cbmax > (1<cbmax, (unsigned int)(1<cbmin < 0 || coef_in->cbmin > (1<cbmin, (unsigned int)(1<crmax < 0 || coef_in->crmax > (1<crmax, (unsigned int)(1<crmin < 0 || coef_in->crmin > (1<crmin, (unsigned int)(1<acoef = coef_in->acoef * (1<<16); + coef_out->bcoef = coef_in->bcoef * (1<<16); + coef_out->ccoef = coef_in->ccoef * (1<<16); + coef_out->dcoef = coef_in->dcoef * (1<<16); + coef_out->yoffset = coef_in->yoffset; + coef_out->cboffset = coef_in->cboffset; + coef_out->croffset = coef_in->croffset; + coef_out->ymax = coef_in->ymax; + coef_out->ymin = coef_in->ymin; + coef_out->cbmax = coef_in->cbmax; + coef_out->cbmin = coef_in->cbmin; + coef_out->crmax = coef_in->crmax; + coef_out->crmin = coef_in->crmin; + + return ret_val; +} + +/*****************************************************************************/ +/** +* +* Program the RGB2YCrCb coefficient/offset registers. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_set_coefficients(u32 BaseAddress, struct rgb_coef_outputs *coef_out) +{ + RGB_WriteReg(BaseAddress, RGB_ACOEF, coef_out->acoef); //ACOEF + RGB_WriteReg(BaseAddress, RGB_BCOEF, coef_out->bcoef); //BCOEF + RGB_WriteReg(BaseAddress, RGB_CCOEF, coef_out->ccoef); //CCOEF + RGB_WriteReg(BaseAddress, RGB_DCOEF, coef_out->dcoef); //DCOEF + RGB_WriteReg(BaseAddress, RGB_YOFFSET, coef_out->yoffset); //YOFFSET + RGB_WriteReg(BaseAddress, RGB_CBOFFSET, coef_out->cboffset); //CBOFFSET + RGB_WriteReg(BaseAddress, RGB_CROFFSET, coef_out->croffset); //CROFFSET + RGB_WriteReg(BaseAddress, RGB_YMAX, coef_out->ymax); //YMAX + RGB_WriteReg(BaseAddress, RGB_YMIN, coef_out->ymin); //YMIN + RGB_WriteReg(BaseAddress, RGB_CBMAX,coef_out->cbmax); //CBMAX + RGB_WriteReg(BaseAddress, RGB_CBMIN, coef_out->cbmin); //CBMIN + RGB_WriteReg(BaseAddress, RGB_CRMAX, coef_out->crmax); //CRMAX + RGB_WriteReg(BaseAddress, RGB_CRMIN, coef_out->crmin); //CRMIN + +} + +/*****************************************************************************/ +/** +* +* Read the RGB2YCrCb coefficient/offset registers. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_get_coefficients(u32 BaseAddress, struct rgb_coef_outputs *coef_out) +{ + coef_out->acoef = RGB_ReadReg(BaseAddress, RGB_ACOEF); + coef_out->bcoef = RGB_ReadReg(BaseAddress, RGB_BCOEF); + coef_out->ccoef = RGB_ReadReg(BaseAddress, RGB_CCOEF); + coef_out->dcoef = RGB_ReadReg(BaseAddress, RGB_DCOEF); + + coef_out->yoffset = RGB_ReadReg(BaseAddress, RGB_YOFFSET); + coef_out->cboffset = RGB_ReadReg(BaseAddress, RGB_CBOFFSET); + coef_out->croffset = RGB_ReadReg(BaseAddress, RGB_CROFFSET); + + coef_out->ymax = RGB_ReadReg(BaseAddress, RGB_YMAX); + coef_out->ymin = RGB_ReadReg(BaseAddress, RGB_YMIN); + + coef_out->cbmax = RGB_ReadReg(BaseAddress, RGB_CBMAX); + coef_out->cbmax = RGB_ReadReg(BaseAddress, RGB_CBMIN); + + coef_out->crmax = RGB_ReadReg(BaseAddress, RGB_CRMAX); + coef_out->crmax = RGB_ReadReg(BaseAddress, RGB_CRMIN); + +} diff --git a/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.h b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.h new file mode 100755 index 00000000..dce5da41 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/rgb2ycrcb/src/rgb2ycrcb.h @@ -0,0 +1,427 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file rgb2ycrcb.h +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx RGB to YCrCb Color Space Converter +* (RGB2YCRCB) device. +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 5.00a tb 02/27/12 Updated for RGB2YCRCB V5.00.a +* 5.01a bao 12/28/12 Converted from xio.h to xil_io.h, translating basic types, +* MB cache functions, exceptions and assertions to xil_io +* format +* 6.0 adk 19/12/13 Updated as per the New Tcl API's +* +******************************************************************************/ + +#ifndef RGB2YCRCB_DRIVER_H /* prevent circular inclusions */ +#define RGB2YCRCB_DRIVER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** + * Register Offsets + */ +/* General Control Registers */ +#define RGB_CONTROL 0x000 /**< Control */ +#define RGB_STATUS 0x004 /**< Status */ +#define RGB_ERROR 0x008 /**< Error */ +#define RGB_IRQ_EN 0x00C /**< IRQ Enable */ +#define RGB_VERSION 0x010 /**< Version */ +#define RGB_SYSDEBUG0 0x014 /**< System Debug 0 */ +#define RGB_SYSDEBUG1 0x018 /**< System Debug 1 */ +#define RGB_SYSDEBUG2 0x01C /**< System Debug 2 */ +/* Timing Control Registers */ +#define RGB_ACTIVE_SIZE 0x020 /**< Active Size (V x H) */ +#define RGB_TIMING_STATUS 0x024 /**< Timing Measurement Status */ +/* Core Specific Registers */ +#define RGB_YMAX 0x100 /**< Luma Clipping */ +#define RGB_YMIN 0x104 /**< Luma Clamping */ +#define RGB_CBMAX 0x108 /**< Cb Clipping */ +#define RGB_CBMIN 0x10C /**< Cb Clamping */ +#define RGB_CRMAX 0x110 /**< Cr Clipping */ +#define RGB_CRMIN 0x114 /**< Cr Clamping */ +#define RGB_YOFFSET 0x118 /**< Lumma Offset */ +#define RGB_CBOFFSET 0x11C /**< Cb Offset */ +#define RGB_CROFFSET 0x120 /**< Cr Offset */ +#define RGB_ACOEF 0x124 /**< Matrix Coversion Coefficient */ +#define RGB_BCOEF 0x128 /**< Matrix Coversion Coefficient */ +#define RGB_CCOEF 0x12C /**< Matrix Coversion Coefficient */ +#define RGB_DCOEF 0x130 /**< Matrix Coversion Coefficient */ + +/* + * CCM Control Register bit definition + */ +#define RGB_CTL_EN_MASK 0x00000001 /**< CCM Enable */ +#define RGB_CTL_RUE_MASK 0x00000002 /**< CCM Register Update Enable */ + +/* + * CCM Reset Register bit definition + */ +#define RGB_RST_RESET 0x80000000 /**< Software Reset - Instantaneous */ +#define RGB_RST_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define RGB_In32 Xil_In32 +#define RGB_Out32 Xil_Out32 + + +/*****************************************************************************/ +/** +* +* This macro enables a RGB2YCrCb device. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_Enable(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_Enable(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, \ + RGB_ReadReg(BaseAddress, RGB_CONTROL) | \ + RGB_CTL_EN_MASK) + +/*****************************************************************************/ +/** +* +* This macro disables a RGB2YCrCb device. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_Disable(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_Disable(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, \ + RGB_ReadReg(BaseAddress, RGB_CONTROL) & \ + ~RGB_CTL_EN_MASK) + +/*****************************************************************************/ +/** +* +* This macro tells a RGB2YCrCb device to pick up all the register value changes +* made so far by the software. The registers will be automatically updated +* on the next SOF signal on the core. +* It is up to the user to manually disable the register update after a sufficient +* amount if time. +* +* This function only works when the RGB2YCrCb core is enabled. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_RegUpdateEnable(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_RegUpdateEnable(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, \ + RGB_ReadReg(BaseAddress, RGB_CONTROL) | \ + RGB_CTL_RUE_MASK) + +/*****************************************************************************/ +/** +* +* This macro tells a RGB2YCrCb device not to update it's configuration registers made +* so far by the software. When disabled, changes to other configuration registers +* are stored, but do not effect the core's behavior. +* +* This function only works when the RGB2YCrCb core is enabled. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_RegUpdateDisable(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_RegUpdateDisable(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, \ + RGB_ReadReg(BaseAddress, RGB_CONTROL) & \ + ~RGB_CTL_RUE_MASK) + +/*****************************************************************************/ +/** +* +* This macro resets a RGB2YCrCb device. This reset effects the core immediately, +* and may cause image tearing. +* +* This reset resets the RGB2YCrCb's configuration registers, and holds the core's outputs +* in their reset state until RGB_ClearReset() is called. +* +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_Reset(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_Reset(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, RGB_RST_RESET) \ + +/*****************************************************************************/ +/** +* +* This macro clears the RGB2YCrCb's reset flag (which is set using RGB_Reset(), and +* returns it to normal operation. This ClearReset effects the core immediately, +* and may cause image tearing. +* +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_ClearReset(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_ClearReset(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, 0) \ + + +/*****************************************************************************/ +/** +* +* This macro resets a RGB2YCrCb device, but differs from RGB_Reset() in that it +* automatically synchronizes to the VBlank_in input of the core to prevent tearing. +* +* On the next rising-edge of VBlank_in following a call to RGB_AutoSyncReset(), +* all of the core's configuration registers and outputs will be reset, then the +* reset flag will be immediately released, allowing the core to immediately resume +* default operation. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* +* @return None. +* +* @note +* C-style signature: +* void RGB_Reset(u32 BaseAddress); +* +******************************************************************************/ +#define RGB_AutoSyncReset(BaseAddress) \ + RGB_WriteReg(BaseAddress, RGB_CONTROL, RGB_RST_AUTORESET) \ + +/*****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param RegOffset is the register offset of the register (defined at top of this file) +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 RGB_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define RGB_ReadReg(BaseAddress, RegOffset) \ + RGB_In32((BaseAddress) + (RegOffset)) + +/*****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param RegOffset is the register offset of the register (defined at top of this file) +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void RGB_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define RGB_WriteReg(BaseAddress, RegOffset, Data) \ + RGB_Out32((BaseAddress) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +struct rgb_coef_inputs +{ + /* Pre-translated coefficient/offset data */ + double acoef; //@- [ 0.0 - 1.0 ] 0.0 < ACOEFF + BCOEFF < 1.0 + double bcoef; //@- [ 0.0 - 1.0 ] 0.0 < ACOEFF + BCOEFF < 1.0 + double ccoef; //@- [ 0.0 - 0.9 ] + double dcoef; //@- [ 0.0 - 0.9 ] + u32 yoffset; //@- Offset for the Luminance Channel + u32 cboffset; //@- Offset for the Chrominance Channels + u32 croffset; //@- Offset for the Chrominance Channels + u32 ymax; //@- Y Clipping + u32 ymin; //@- Y Clamping + u32 cbmax; //@- Cb Clipping + u32 cbmin; //@- Cb Clamping + u32 crmax; //@- Cr Clipping + u32 crmin; //@- Cr Clamping +}; + +struct rgb_coef_outputs +{ + /* Translated coefficient/offset data */ + u32 acoef; //@- Translated ACoef + u32 bcoef; //@- Translated BCoef + u32 ccoef; //@- Translated CCoef + u32 dcoef; //@- Translated DCoef + u32 yoffset; //@- Translated Offset for the Luminance Channel + u32 cboffset; //@- Translated Offset for the Chrominance Channels + u32 croffset; //@- Translated Offset for the Chrominance Channels + u32 ymax; //@- Translated Y Clipping + u32 ymin; //@- Translated Y Clamping + u32 cbmax; //@- Translated Cb Clipping + u32 cbmin; //@- Translated Cb Clamping + u32 crmax; //@- Translated Cr Clipping + u32 crmin; //@- Translated Cr Clamping +}; + +/*****************************************************************************/ +/** +* +* Select input coefficients for 4 supported Standards and 3 Input Ranges. +* +* @param standard_sel is the standards selection: 0 = SD_ITU_601 +* 1 = HD_ITU_709__1125_NTSC +* 2 = HD_ITU_709__1250_PAL +* 3 = YUV +* @param input_range is the limit on the range of the data: 0 = 16_to_240_for_TV, +* 1 = 16_to_235_for_Studio_Equipment, +* 3 = 0_to_255_for_Computer_Graphics +* @param data_width has a valid range of [8, 10,12,16] +* @param coef_in is a pointer to a rgb_coef_inputs data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_select_standard(u32 standard_sel, u32 input_range, u32 data_width, struct rgb_coef_inputs *coef_in); + + +/*****************************************************************************/ +/** +* +* Translate input coefficients into coefficients that can be programmed into the +* RGB2YCrCb core. +* +* @param coef_in is a pointer to a rgb_coef_inputs data structure. +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return The 32-bit value: bit(0)= Acoef + Bcoef > 1.0 +* bit(1)= Y Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(2)= Cb Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(3)= Cr Offset outside data width range [-2^data_width, (2^data_width)-1] +* bit(4)= Y Max outside data width range [0, (2^data_width)-1] +* bit(5)= Y Min outside data width range [0, (2^data_width)-1] +* bit(6)= Cb Max outside data width range [0, (2^data_width)-1] +* bit(7)= Cb Min outside data width range [0, (2^data_width)-1] +* bit(8)= Cr Max outside data width range [0, (2^data_width)-1] +* bit(9)= Cr Min outside data width range [0, (2^data_width)-1] +* +* @note +* +******************************************************************************/ +u32 RGB_coefficient_translation(struct rgb_coef_inputs *coef_in, struct rgb_coef_outputs *coef_out, u32 data_width); + + +/*****************************************************************************/ +/** +* +* Program the RGB2YCrCb coefficient/offset registers. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_set_coefficients(u32 BaseAddress, struct rgb_coef_outputs *coef_out); + + +/*****************************************************************************/ +/** +* +* Read the RGB2YCrCb coefficient/offset registers. +* +* @param BaseAddress is the Xilinx EDK base address of the RGB2YCrCb core (from xparameters.h) +* @param coef_out is a pointer to a rgb_coef_output data structure. +* +* @return None. +* +* @note +* +******************************************************************************/ +void RGB_get_coefficients(u32 BaseAddress, struct rgb_coef_outputs *coef_out); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */