diff --git a/lib/bsp/standalone/data/standalone.mld b/lib/bsp/standalone/data/standalone.mld new file mode 100644 index 00000000..4423d7db --- /dev/null +++ b/lib/bsp/standalone/data/standalone.mld @@ -0,0 +1,55 @@ +############################################################################## +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################## + +OPTION psf_version = 2.1; + +BEGIN OS standalone +OPTION drc = standalone_drc; +OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"; +OPTION DESC = "Standalone is a simple, low-level software layer. It provides access to basic processor features such as caches, interrupts and exceptions as well as the basic features of a hosted environment, such as standard input and output, profiling, abort and exit."; +OPTION copyfiles = all; +OPTION OS_STATE = ACTIVE; +OPTION VERSION = 5.2; +OPTION NAME = standalone; + +PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm); +PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm); +BEGIN CATEGORY sw_intrusive_profiling + PARAM name = enable_sw_intrusive_profiling, type = bool, default = false, desc = "Enable S/W Intrusive Profiling on Hardware Targets", permit = user; + PARAM name = profile_timer, type = peripheral_instance, range = (opb_timer, xps_timer, axi_timer), default = none, desc = "Specify the Timer to use for Profiling. For PowerPC system, specify none to use PIT timer. For ARM system, specify none to use SCU timer"; +END CATEGORY + +BEGIN CATEGORY microblaze_exceptions + PARAM name = microblaze_exceptions, type = bool, default = false, desc = "Enable MicroBlaze Exceptions", permit = user; + PARAM name = predecode_fpu_exceptions, desc = "(MicroBlaze) Predecode FPU exceptions and save operand info before invoking user registered exception handler.", type = bool, default = false, permit = user; +END CATEGORY +END OS diff --git a/lib/bsp/standalone/data/standalone.mss b/lib/bsp/standalone/data/standalone.mss new file mode 100644 index 00000000..d18a3e70 --- /dev/null +++ b/lib/bsp/standalone/data/standalone.mss @@ -0,0 +1,8 @@ + +PARAMETER VERSION = 2.2.0 + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER STDIN = * + PARAMETER STDOUT = * +END diff --git a/lib/bsp/standalone/data/standalone.tcl b/lib/bsp/standalone/data/standalone.tcl new file mode 100644 index 00000000..d13d5502 --- /dev/null +++ b/lib/bsp/standalone/data/standalone.tcl @@ -0,0 +1,750 @@ +############################################################################## +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################## + +# ---------------------------------------------------------------------------- +# The following are hardcoded for Zynq. +# We can obtain the scu timer/gic baseaddr from the xml, but other parameters +# need to be hardcoded. hardcode everything.. +# ---------------------------------------------------------------------------- +#TODO these hardcoding parameters can be removed. It can directly come from PS7 IP +set scutimer_baseaddr 0xF8F00600 +set scutimer_intr 29 +set scugic_cpu_base 0xF8F00100 +set scugic_dist_base 0xF8F01000 + +# -------------------------------------- +# Tcl procedure standalone_drc +# ------------------------------------- +proc standalone_drc {os_handle} { +} + +# -------------------------------------- +# Tcl procedure generate +# ------------------------------------- +proc generate {os_handle} { + global env + + set need_config_file "false" + # Copy over the right set of files as src based on processor type + set sw_proc_handle [hsi::get_sw_processor] + set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ] + set proctype [common::get_property IP_NAME $hw_proc_handle] + set procname [common::get_property NAME $hw_proc_handle] + + set enable_sw_profile [common::get_property CONFIG.enable_sw_intrusive_profiling $os_handle] + set mb_exceptions false + + # proctype should be "microblaze" or psu_cortexa53 or psu_cortexr5 or ps7_cortexa9 + set mbsrcdir "./src/microblaze" + set cortexa53srcdir "./src/cortexa53" + set cortexr5srcdir "./src/cortexr5" + set cortexa9srcdir "./src/cortexa9" + set procdrv [hsi::get_sw_processor] + set commonsrcdir "./src/common" + + foreach entry [glob -nocomplain [file join $commonsrcdir *]] { + file copy -force $entry "./src" + } + + # Only processor specific file should be copied to specified standalone folder + # write a API which needs compiler, + switch $proctype { + "microblaze" { + foreach entry [glob -nocomplain [file join $mbsrcdir *]] { + # Copy over only files that are not related to exception handling. All such files have exception in their names + file copy -force $entry "./src/" + } + set need_config_file "true" + set mb_exceptions [mb_has_exceptions $hw_proc_handle] + } + "psu_microblaze" { + foreach entry [glob -nocomplain [file join $mbsrcdir *]] { + # Copy over only files that are not related to exception handling. All such files have exception in their names + file copy -force $entry "./src/" + } + set need_config_file "true" + set mb_exceptions [mb_has_exceptions $hw_proc_handle] + } + "psu_cortexa53" { + set procdrv [hsi::get_sw_processor] + set ccdir "./src/cortexa53/gcc" + foreach entry [glob -nocomplain [file join $cortexa53srcdir *]] { + file copy -force $entry "./src/" + } + foreach entry [glob -nocomplain [file join $ccdir *]] { + file copy -force $entry "./src/" + } + + file delete -force "./src/gcc" + file delete -force "./src/profile" + if { $enable_sw_profile == "true" } { + error "ERROR: Profiling is not supported for A53" + } + set file_handle [::hsi::utils::open_include_file "xparameters.h"] + puts $file_handle "#include \"xparameters_ps.h\"" + puts $file_handle "" + close $file_handle + } + "psu_cortexr5" { + set procdrv [hsi::get_sw_processor] + set ccdir "./src/cortexr5/gcc" + foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] { + file copy -force $entry "./src/" + } + foreach entry [glob -nocomplain [file join $ccdir *]] { + file copy -force $entry "./src/" + } + + file delete -force "./src/gcc" + file delete -force "./src/profile" + if { $enable_sw_profile == "true" } { + error "ERROR: Profiling is not supported for R5" + } + set file_handle [::hsi::utils::open_include_file "xparameters.h"] + puts $file_handle "#include \"xparameters_ps.h\"" + puts $file_handle "" + close $file_handle + } + "ps7_cortexa9" { + set procdrv [hsi::get_sw_processor] + set compiler [common::get_property CONFIG.compiler $procdrv] + if {[string compare -nocase $compiler "armcc"] == 0} { + set ccdir "./src/cortexa9/armcc" + } elseif {[string compare -nocase $compiler "iccarm"] == 0} { + set ccdir "./src/cortexa9/iccarm" + } else { + set ccdir "./src/cortexa9/gcc" + } + foreach entry [glob -nocomplain [file join $cortexa9srcdir *]] { + file copy -force $entry "./src/" + } + foreach entry [glob -nocomplain [file join $ccdir *]] { + file copy -force $entry "./src/" + } + file delete -force "./src/armcc" + file delete -force "./src/gcc" + file delete -force "./src/iccarm" + if {[string compare -nocase $compiler "armcc"] == 0} { + file delete -force "./src/profile" + set enable_sw_profile "false" + } + if {[string compare -nocase $compiler "iccarm"] == 0} { + file delete -force "./src/profile" + set enable_sw_profile "false" + } + set file_handle [::hsi::utils::open_include_file "xparameters.h"] + puts $file_handle "#include \"xparameters_ps.h\"" + puts $file_handle "" + close $file_handle + } + "default" {puts "unknown processor type $proctype\n"} + } + + # Write the Config.make file + set makeconfig [open "./src/config.make" w] +# print_generated_header_tcl $makeconfig "Configuration parameters for Standalone Makefile" + if { $proctype == "microblaze" || $proctype == "psu_microblaze" } { + puts $makeconfig "LIBSOURCES = *.c *.S" + puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_mb.o" + } elseif { $proctype == "psu_cortexr5" } { + puts $makeconfig "LIBSOURCES = *.c *.S" + } elseif { $proctype == "psu_cortexa53" } { + puts $makeconfig "LIBSOURCES = *.c *.s *.S" + } elseif { $proctype == "ps7_cortexa9" } { + if {[string compare -nocase $compiler "armcc"] == 0} { + puts $makeconfig "LIBSOURCES = *.c *.s" + } elseif {[string compare -nocase $compiler "iccarm"] == 0} { + puts $makeconfig "LIBSOURCES = *.c *.s" + } else { + puts $makeconfig "LIBSOURCES = *.c *.S" + puts $makeconfig "PROFILE_ARCH_OBJS = profile_mcount_arm.o" + } + } else { + error "ERROR: processor $proctype is not supported" + } + if { $enable_sw_profile == "true" } { + puts $makeconfig "LIBS = standalone_libs profile_libs" + } else { + puts $makeconfig "LIBS = standalone_libs" + } + close $makeconfig + + # Remove microblaze, cortexr5, cortexa53 and common directories... + file delete -force $mbsrcdir + file delete -force $cortexr5srcdir + file delete -force $cortexa53srcdir + file delete -force $cortexa9srcdir + file delete -force $commonsrcdir + + # Handle stdin and stdout + ::hsi::utils::handle_stdin $os_handle + ::hsi::utils::handle_stdout $os_handle + + #Handle Profile configuration + if { $enable_sw_profile == "true" } { + handle_profile $os_handle $proctype + } + + set file_handle [::hsi::utils::open_include_file "xparameters.h"] + puts $file_handle "\n/******************************************************************/\n" + close $file_handle + + # Create config file for microblaze interrupt handling + if { [string compare -nocase $need_config_file "true"] == 0 } { + xhandle_mb_interrupts + } + + # Create config files for Microblaze exception handling + if { $proctype == "microblaze" && [mb_has_exceptions $hw_proc_handle] } { + xcreate_mb_exc_config_file $os_handle + } + + # Create bspconfig file + set bspcfg_fn [file join "src" "bspconfig.h"] + file delete $bspcfg_fn + set bspcfg_fh [open $bspcfg_fn w] + ::hsi::utils::write_c_header $bspcfg_fh "Configurations for Standalone BSP" + + if { $proctype == "microblaze" && [mb_has_pvr $hw_proc_handle] } { + + set pvr [common::get_property CONFIG.C_PVR $hw_proc_handle] + + switch $pvr { + "0" { + puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE" + } + "1" { + puts $bspcfg_fh "#define MICROBLAZE_PVR_BASIC" + } + "2" { + puts $bspcfg_fh "#define MICROBLAZE_PVR_FULL" + } + "default" { + puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE" + } + } + } else { + puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE" + } + + close $bspcfg_fh +} + +# -------------------------------------- +# Tcl procedure xhandle_mb_interrupts +# -------------------------------------- +proc xhandle_mb_interrupts {} { + + set default_interrupt_handler "XNullHandler" + set default_arg "XNULL" + + set source_interrupt_handler $default_interrupt_handler + set source_handler_arg $default_arg + + # Handle the interrupt pin + set sw_proc_handle [hsi::get_sw_processor] + set periph [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ] + set source_ports [::hsi::utils::get_interrupt_sources $periph] + if {[llength $source_ports] > 1} { + error "ERROR: Too many interrupting ports on the MicroBlaze. Should only find 1" "" "hsi_error" + return + } + if { [llength $source_ports] != 0 } { + set source_periph [hsi::get_cells -of_objects $source_ports] + if { [llength $source_periph] != 0 } { + set source_driver [hsi::get_drivers -filter "HW_INSTANCE==$source_periph"] + if { [llength $source_driver] != 0 } { + set intr_array [hsi::get_arrays -of_objects $source_driver -filter "NAME==interrupt_handler"] + if { [llength $intr_array] != 0 } { + set array_size [common::get_property PROPERTY.size $intr_array] + for { set i 0 } { $i < $array_size } { incr i } { + set int_port [lindex [common::get_property PARAM.int_port $intr_array] $i] + if { [llength $int_port] != 0 } { + if { [string compare -nocase $int_port $source_ports] == 0 } { + set source_interrupt_handler [lindex [common::get_property PARAM.int_handler $intr_array] $i] + set source_handler_arg [lindex [common::get_property PARAM.int_handler_arg $intr_array] $i] + if { [string compare -nocase $source_handler_arg DEVICE_ID] == 0 } { + set source_handler_arg [::hsi::utils::get_ip_param_name $source_periph "DEVICE_ID"] + } else { + set source_handler_arg [::hsi::utils::get_ip_param_name $source_periph "C_BASEADDR"] + } + } + } + } + } + } + } + } + + # Generate microblaze_interrupts_g.c file... + xcreate_mb_intr_config_file $source_interrupt_handler $source_handler_arg +} +# ------------------------------------------- +# Tcl procedure xcreate_mb_intr_config file +# ------------------------------------------- +proc xcreate_mb_intr_config_file {handler arg} { + + set mb_table "MB_InterruptVectorTable" + + set filename [file join "src" "microblaze_interrupts_g.c"] + file delete $filename + set config_file [open $filename w] + + ::hsi::utils::write_c_header $config_file "Interrupt Handler Table for MicroBlaze Processor" + + puts $config_file "#include \"microblaze_interrupts_i.h\"" + puts $config_file "#include \"xparameters.h\"" + puts $config_file "\n" + puts $config_file [format "extern void %s (void *);" $handler] + puts $config_file "\n/*" + puts $config_file "* The interrupt handler table for microblaze processor" + puts $config_file "*/\n" + puts $config_file [format "%sEntry %s\[\] =" $mb_table $mb_table] + puts $config_file "\{" + puts -nonewline $config_file [format "\{\t%s" $handler] + puts -nonewline $config_file [format ",\n\t(void*) %s\}" $arg] + puts -nonewline $config_file "\n\};" + puts $config_file "\n" + close $config_file +} + +# ------------------------------------------- +# Tcl procedure xcreate_mb_exc_config file +# ------------------------------------------- +proc xcreate_mb_exc_config_file {os_handle} { + + set hfilename [file join "src" "microblaze_exceptions_g.h"] + file delete $hfilename + set hconfig_file [open $hfilename w] + ::hsi::utils::write_c_header $hconfig_file "Exception Handling Header for MicroBlaze Processor" + set sw_proc_handle [hsi::get_sw_processor] + set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ] + set procvlnv [common::get_property VLNV $hw_proc_handle] + set procvlnv [split $procvlnv :] + set procver [lindex $procvlnv 3] + set ibus_ee [common::get_property CONFIG.C_M_AXI_I_BUS_EXCEPTION $hw_proc_handle] + set dbus_ee [common::get_property CONFIG.C_M_AXI_D_BUS_EXCEPTION $hw_proc_handle] + set ill_ee [common::get_property CONFIG.C_ILL_OPCODE_EXCEPTION $hw_proc_handle] + set unalign_ee [common::get_property CONFIG.C_UNALIGNED_EXCEPTIONS $hw_proc_handle] + set div0_ee [common::get_property CONFIG.C_DIV_ZERO_EXCEPTION $hw_proc_handle] + set mmu_ee [common::get_property CONFIG.C_USE_MMU $hw_proc_handle] + if { $mmu_ee == "" } { + set mmu_ee 0 + } + set fsl_ee [common::get_property CONFIG.C_FSL_EXCEPTION $hw_proc_handle] + if { $fsl_ee == "" } { + set fsl_ee 0 + } + if { [mb_has_fpu_exceptions $hw_proc_handle] } { + set fpu_ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle] + } else { + set fpu_ee 0 + } + set sp_ee [common::get_property CONFIG.C_USE_STACK_PROTECTION $hw_proc_handle] + if { $sp_ee == "" } { + set sp_ee 0 + } + set ft_ee [common::get_property CONFIG.C_FAULT_TOLERANT $hw_proc_handle] + if { $ft_ee == "" } { + set ft_ee 0 + } + + if { $ibus_ee == 0 && $dbus_ee == 0 && $ill_ee == 0 && $unalign_ee == 0 + && $div0_ee == 0 && $fpu_ee == 0 && $mmu_ee == 0 && $fsl_ee == 0 + && $sp_ee == 0 && $ft_ee == 0} { + ;# NO exceptions are enabled + ;# Do not generate any info in either the header or the C file + close $hconfig_file + return + } + + puts $hconfig_file "\#define MICROBLAZE_EXCEPTIONS_ENABLED 1" + if { [mb_can_handle_exceptions_in_delay_slots $procver] } { + puts $hconfig_file "#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS" + } + if { $unalign_ee == 0 } { + puts $hconfig_file "\#define NO_UNALIGNED_EXCEPTIONS 1" + } + if { $ibus_ee == 0 && $dbus_ee == 0 && $ill_ee == 0 && $div0_ee == 0 + && $fpu_ee == 0 && $mmu_ee == 0 && $fsl_ee == 0 } { + ;# NO other exceptions are enabled + puts $hconfig_file "\#define NO_OTHER_EXCEPTIONS 1" + } + + if { $fpu_ee != 0 } { + puts $hconfig_file "\#define MICROBLAZE_FP_EXCEPTION_ENABLED 1" + set predecode_fpu_exceptions [common::get_property CONFIG.predecode_fpu_exceptions $os_handle] + if {$predecode_fpu_exceptions != false } { + puts $hconfig_file "\#define MICROBLAZE_FP_EXCEPTION_DECODE 1" + } + } + + puts $hconfig_file "\n" + close $hconfig_file +} + + +# -------------------------------------- +# Tcl procedure post_generate +# +# This proc removes _interrupt_handler.o +# from libxil.a +# -------------------------------------- +proc post_generate {os_handle} { + + set sw_proc_handle [hsi::get_sw_processor] + set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle] ] + + set procname [common::get_property NAME $hw_proc_handle] + set proctype [common::get_property IP_NAME $hw_proc_handle] + + if {[string compare -nocase $proctype "microblaze"] == 0} { + + set procdrv [hsi::get_sw_processor] + # Remove _interrupt_handler.o from libxil.a for mb-gcc + set archiver [common::get_property CONFIG.archiver $procdrv] + set libgloss_a [file join .. .. lib libgloss.a] + if { ![file exists $libgloss_a] } { + set libgloss_a [file join .. .. lib libxil.a] + } + exec $archiver -d $libgloss_a _interrupt_handler.o + + # Remove _hw_exception_handler.o from libgloss.a for microblaze_v3_00_a + if { [mb_has_exceptions $hw_proc_handle] } { + exec $archiver -d $libgloss_a _hw_exception_handler.o + } + } +} + +# -------------------------------------- +# Return true if this MB has +# exception handling support +# -------------------------------------- +proc mb_has_exceptions { hw_proc_handle } { + + # Check if the following parameters exist on this MicroBlaze's MPD + set ee [common::get_property CONFIG.C_UNALIGNED_EXCEPTIONS $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_ILL_OPCODE_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_IOPB_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_DOPB_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_IPLB_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_DPLB_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_M_AXI_I_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_M_AXI_D_BUS_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_DIV_BY_ZERO_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_DIV_ZERO_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_FSL_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + set ee [common::get_property CONFIG.C_USE_MMU $hw_proc_handle] + if { $ee != ""} { + return true + } + + set ee [common::get_property CONFIG.C_USE_STACK_PROTECTION $hw_proc_handle] + if { $ee != ""} { + return true + } + + set ee [common::get_property CONFIG.C_FAULT_TOLERANT $hw_proc_handle] + if { $ee != ""} { + return true + } + + return false +} +# -------------------------------------- +# Return true if this MB has +# FPU exception handling support +# -------------------------------------- +proc mb_has_fpu_exceptions { hw_proc_handle } { + + # Check if the following parameters exist on this MicroBlaze's MPD + set ee [common::get_property CONFIG.C_FPU_EXCEPTION $hw_proc_handle] + if { $ee != "" } { + return true + } + + return false +} + +# -------------------------------------- +# Return true if this MB has PVR support +# -------------------------------------- +proc mb_has_pvr { hw_proc_handle } { + + # Check if the following parameters exist on this MicroBlaze's MPD + set pvr [common::get_property CONFIG.C_PVR $hw_proc_handle] + if { $pvr != "" } { + return true + } + + return false +} + +# -------------------------------------- +# Return true if MB ver 'procver' has +# support for handling exceptions in +# delay slots +# -------------------------------------- +proc mb_can_handle_exceptions_in_delay_slots { procver } { + + if { [string compare -nocase $procver "5.00.a"] >= 0 } { + return true + } else { + return false + } +} + +# -------------------------------------- +# Generate Profile Configuration +# -------------------------------------- +proc handle_profile { os_handle proctype } { + global env + variable scutimer_baseaddr + variable scutimer_intr + variable scugic_cpu_base + variable scugic_dist_base + + set proc [hsi::get_sw_processor] + + if {$proctype == "ps7_cortexa9"} { + set sw_proc_handle [hsi::get_sw_processor] + set hw_proc_handle [hsi::get_cells [common::get_property HW_INSTANCE $sw_proc_handle]] + set cpu_freq [common::get_property CONFIG.C_CPU_CLK_FREQ_HZ $hw_proc_handle] + if { [string compare -nocase $cpu_freq ""] == 0 } { + puts "WARNING :: CPU Clk Frequency not specified, Assuming 666Mhz" + set cpu_freq 666000000 + } + } else { + set cpu_freq [common::get_property CONFIG.C_FREQ [hsi::get_cells $proc]] + if { [string compare -nocase $cpu_freq ""] == 0 } { + puts "WARNING :: CPU Clk Frequency not specified, Assuming 100Mhz" + set cpu_freq 100000000 + } + } + set filename [file join "src" "profile" "profile_config.h"] + file delete -force $filename + set config_file [open $filename w] + + ::hsi::utils::write_c_header $config_file "Profiling Configuration parameters. These parameters +* can be overwritten thru run configuration in SDK" + puts $config_file "#ifndef _PROFILE_CONFIG_H" + puts $config_file "#define _PROFILE_CONFIG_H\n" + + puts $config_file "#define BINSIZE 4" + puts $config_file "#define CPU_FREQ_HZ $cpu_freq" + puts $config_file "#define SAMPLE_FREQ_HZ 100000" + puts $config_file "#define TIMER_CLK_TICKS [expr $cpu_freq / 100000]" + + # proctype should be "microblaze" or "psu_cortexa9" + switch $proctype { + "microblaze" { + # Microblaze Processor. + puts $config_file "#define PROC_MICROBLAZE 1" + set timer_inst [common::get_property CONFIG.profile_timer $os_handle] + if { [string compare -nocase $timer_inst "none"] == 0 } { + # Profile Timer Not Selected + error "ERROR : Timer for Profiling NOT selected.\nS/W Intrusive Profiling on MicroBlaze requires an axi_timer." "" "mdt_error" + } else { + handle_profile_opbtimer $config_file $timer_inst + } + } + "ps7_cortexa9" { + # Cortex A9 Processor. + + puts $config_file "#define PROC_CORTEXA9 1" + set timer_inst [common::get_property CONFIG.profile_timer $os_handle] + if { [string compare -nocase $timer_inst "none"] == 0 } { + # SCU Timer + puts $config_file "#define ENABLE_SCU_TIMER 1" + puts $config_file "#define ENABLE_SYS_INTR 1" + puts $config_file "#define PROFILE_TIMER_BASEADDR $scutimer_baseaddr" + puts $config_file "#define PROFILE_TIMER_INTR_ID $scutimer_intr" + puts $config_file "#define SCUGIC_CPU_BASEADDR $scugic_cpu_base" + puts $config_file "#define SCUGIC_DIST_BASEADDR $scugic_dist_base" + } + } + "default" {error "ERROR: unknown processor type\n"} + } + + puts $config_file "\n#endif" + puts $config_file "\n/******************************************************************/\n" + close $config_file +} + + #***--------------------------------***-----------------------------------*** + # Utility process to call a command and pipe it's output to screen. + # Used instead of Tcl's exec +proc execpipe {COMMAND} { + + if { [catch {open "| $COMMAND 2>@stdout"} FILEHANDLE] } { + return "Can't open pipe for '$COMMAND'" + } + + set PIPE $FILEHANDLE + fconfigure $PIPE -buffering none + + set OUTPUT "" + + while { [gets $PIPE DATA] >= 0 } { + append OUTPUT $DATA "\n" + } + + if { [catch {close $PIPE} ERRORMSG] } { + + if { [string compare "$ERRORMSG" "child process exited abnormally"] == 0 } { + # this error means there was nothing on stderr (which makes sense) and + # there was a non-zero exit code - this is OK as we intentionally send + # stderr to stdout, so we just do nothing here (and return the output) + } else { + return "Error '$ERRORMSG' on closing pipe for '$COMMAND'" + } + + } + + regsub -all -- "\n$" $OUTPUT "" STRIPPED_STRING + return "$STRIPPED_STRING" + +} +# - The xps/opb_timer can be connected directly to Microblaze External Intr Pin. +# - (OR) xps/opb_timer can be connected to xps/opb_intc +proc handle_profile_opbtimer { config_file timer_inst } { + set timer_handle [hsi::get_cells $timer_inst] + set timer_baseaddr [common::get_property CONFIG.C_BASEADDR $timer_handle] + puts $config_file "#define PROFILE_TIMER_BASEADDR [::hsi::utils::format_addr_string $timer_baseaddr "C_BASEADDR"]" + + # Figure out how Timer is connected. + set timer_intr [hsi::get_pins -of_objects [hsi::get_cells $timer_handle] Interrupt] + if { [string compare -nocase $timer_intr ""] == 0 } { + error "ERROR :: Timer Interrupt PORT is not specified" "" "mdt_error" + } + #set mhs_handle [xget_handle $timer_handle "parent"] + # CR 302300 - There can be multiple "sink" for the interrupt. So need to iterate through the list + set intr_port_list [::hsi::utils::get_sink_pins [hsi::get_pins -of_objects [hsi::get_cells $timer_intr] INTERRUPT]] + set timer_connection 0 + foreach intr_port $intr_port_list { + set intc_handle [hsi::get_cells -of_object $intr_port] + # Check if the Sink is a Global Port. If so, Skip the Port Connection + + if { [::hsi::utils::is_external_pin $intr_port] } { + continue + } + set iptype [common::get_property CONFIG.EDK_IPTYPE $intc_handle] + if { [string compare -nocase $iptype "PROCESSOR"] == 0 } { + # Timer Directly Connected to the Processor + puts $config_file "#define ENABLE_SYS_INTR 1" + set timer_connection 1 + break + } + + set ipsptype [common::get_property CONFIG.EDK_SPECIAL $intc_handle] + if { [string compare -nocase $iptype "PERIPHERAL"] == 0 && + [string compare -nocase $ipsptype "INTR_CTRL"] == 0 } { + # Timer connected to Interrupt controller + puts $config_file "#define TIMER_CONNECT_INTC 1" + puts $config_file "#define INTC_BASEADDR [xget_value $intc_handle "PARAMETER" "C_BASEADDR"]" + set num_intr_inputs [common::get_property CONFIG.C_NUM_INTR_INPUTS $intc_handle] + # if { $num_intr_inputs == 1 } { ## Always enable system interrupt CR 472288 + puts $config_file "#define ENABLE_SYS_INTR 1" + # } + + #set signals [split [xget_value $intr_port "VALUE"] "&"] + set signals [::hsi::utils::get_source_pins $intr_port] + set i 1 + foreach signal $signals { + set signal [string trim $signal] + if {[string compare -nocase $signal $timer_intr] == 0} { + set timer_id [expr ($num_intr_inputs - $i)] + set timer_mask [expr 0x1 << $timer_id] + puts $config_file "#define PROFILE_TIMER_INTR_ID $timer_id" + puts $config_file "#define PROFILE_TIMER_INTR_MASK [format "0x%x" $timer_mask]" + break + } + incr i + } + set timer_connection 1 + break + } + } + + if { $timer_connection == 0 } { + error "ERROR :: Profile Timer Interrupt Signal Not Connected Properly" + } +} diff --git a/lib/bsp/standalone/src/changelog.txt b/lib/bsp/standalone/src/changelog.txt new file mode 100644 index 00000000..0949aafc --- /dev/null +++ b/lib/bsp/standalone/src/changelog.txt @@ -0,0 +1,235 @@ +/***************************************************************************** + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- --------------------------------------------------- + * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros + * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs + * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but + * cacheable regions + * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK + * generated by the cpu driver, for enabling caches + * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/ + * write-thru caches + * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC + * Updated the MMU table to mark OCM in high address space + * as inner cacheable and reserved space as Invalid + * 3.03a sdm 08/20/11 Changes to support FreeRTOS + * Updated the MMU table to mark upper half of the DDR as + * non-cacheable + * Setup supervisor and abort mode stacks + * Do not initialize/enable L2CC in case of AMP + * Initialize UART1 for 9600bps in case of AMP + * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC + * in case of AMP + * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event + * counters + * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include + * xparameters.h file for CR630532 - Xil_DCacheFlush()/ + * Xil_DCacheFlushRange() functions in standalone BSP v3_02a + * for MicroBlaze will invalidate data in the cache instead + * of flushing it for writeback caches + * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7 + * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values + * Remove redundant dsb/dmb instructions in cache maintenance + * APIs + * Remove redundant dsb in mcr instruction + * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable + * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through + * driver tcl in xparameters.h. Update the gcc/translationtable.s + * for the QSPI complete address range - DT644567 + * Removed profile directory for armcc compiler and changed + * profiling setting to false in standalone_v2_1_0.tcl file + * Deleting boot.S file after preprocessing for armcc compiler + * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to + * invalidate the caches before enabling back the MMU and + * D cache. + * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file + * xil_mmu.c. Now we invalidate UTLB, Branch predictor + * array, flush the D-cache before changing the attributes + * in translation table. The user need not call Xil_DisableMMU + * before calling Xil_SetTlbAttributes. + * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART + * sgd initialization is present. Changes for this were done in + * uart.c and xil-crt0.s. + * Made changes in xil_io.c to use volatile pointers. + * Made changes in xil_mmu.c to correct the function + * Xil_SetTlbAttributes. + * Changes are made xil-crt0.s to initialize the static + * C++ constructors. + * Changes are made in boot.s, to fix the TTBR settings, + * correct the L2 Cache Auxiliary register settings, L2 cache + * latency settings. + * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c + * sgd usleep.c to use global timer intstead of CP15. + * Made changes in cortexa9/gcc/translation_table.s to map + * the peripheral devices as shareable device memory. + * Made changes in cortexa9/gcc/xil-crt0.s to initialize + * the global timer. + * Made changes in cortexa9/armcc/boot.S to initialize + * the global timer. + * Made changes in cortexa9/armcc/translation_table.s to + * map the peripheral devices as shareable device memory. + * Made changes in cortexa9/gcc/boot.S to optimize the + * L2 cache settings. Changes the section properties for + * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S + * and cortexa9/gcc/translation_table.S. + * Made changes in cortexa9/xil_cache.c to change the + * cache invalidation order. + * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove + * compilation/linking issues for C++ compiler. + * Made changes in mb_interface.h to remove compilation/ + * linking issues for C++ compiler. + * Added macros for swapb and swaph microblaze instructions + * mb_interface.h + * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c + * for CortexA9. + * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address + * 3.07a asa 08/31/12 Added xil_printf.h include + * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings + * Corrected L2 cache sequence disable sequence + * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option + * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for + * irq/fiq handling. + * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This + * fixes the CR #692094. + * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552. + * 3.10a srt 04/18/13 Implemented ARM Erratas. + * Cortex A9 Errata - 742230, 743622, 775420, 794073 + * L2Cache PL310 Errata - 588369, 727915, 759370 + * Please refer to file 'xil_errata.h' for errata + * description. + * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older + * cache APIs were corresponding to only Layer 1 cache + * memories. New APIs were now added and the existing cache + * related APIs were changed to provide a uniform interface + * to flush/invalidate/enable/disable the complete cache + * system which includes both L1 and L2 caches. The changes + * for these were done in: + * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h + * files. + * Four new files were added for supporting L2 cache. They are: + * microblaze_flush_cache_ext.S-> Flushes L2 cache + * microblaze_flush_cache_ext_range.S -> Flushes a range of + * memory in L2 cache. + * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache + * microblaze_invalidate_cache_ext_range -> Invalidates a + * range of memory in L2 cache. + * These changes are done to implement PR #697214. + * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to + * fix the CR #706464. L2 cache disabling happens independent + * of L1 data cache disable operation. Changes are done in the + * same file in cache handling APIs to do a L2 cache sync + * (poll reg7_?cache_?sync). This fixes CR #700542. + * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested + * interrupts for ARM. These are done to fix the CR#699680. + * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach + * sync operation. This fixes the CR# 716781. + * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support + * for armcc toolchain. + * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to + * fix issues related to NEON context saving. The assembly + * routines for IRQ and FIQ handling are modified. + * Deprecated the older BSP (3.10a). + * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid + * various potential issues. Made changes in the function + * Xil_SetAttributes in file xil_mmu.c. + * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h + * in src\cortexa9 and src\microblaze folders. + * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of + * L2 cache sync operation and to fix issues around complete + * L2 cache flush/invalidation by ways. + * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h + * to fix linking issues with armcc/DS-5. Modified the armcc + * makefile to fix issues. + * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB. + * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. + * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler + * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and + * src\cortexa9\armcc\) to fix CR#767251 + * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and + * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs. + * Few cache lines were missed to invalidate when unaligned address + * invalidation was accommodated in Xil_DCacheInvalidateRange. + * In Xil_L1DCacheInvalidate, while invalidating all L1D cache + * stack memory (which contains return address) was invalidated. So + * stack memory is flushed first and then L1D cache is invalidated. + * This is done to fix CR #763829 + * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from + * mblaze_nt_types.h file and replace uint32_t with u32 in the + * profile_hist.c to fix the above CR. + * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a + * instead of libxil.a and added prototypes for + * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in + * mb_interface.h + * 4.1 hk 04/18/14 Add sleep function. + * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed + * some of the *.s files inMB BSP source to *.S. + * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c. + * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist + * CR#794205 + * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and + * common/xil_testcache.c + * Fix for CR#764881. + * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to + * output the DEBUG logs when -DDEBUG flag is enabled in BSP. + * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm. + * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243. + * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and + * cortexa9/armcc/boot.s. Added default exception handlers for data + * abort and prefetch abort using handlers called + * DataAbortHandler and PrefetchAbortHandler respectively in + * cortexa9/xil_exception.c to fix CR#802862. + * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the + * issue of improper linking of translation_table.s + * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present + * in tool chain to avoid conflicts into some special cases + * 4.2 pkp 07/21/14 Corrected reset value of event counter in function + * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275 + * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function + * containing type def u32 defined in xil_types.g to resolve issue of + * CR#805869 + * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as + * it is not possible to generate timer in nanosecond due to limited + * cpu frequency + * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of + * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s + * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also + * removed function definition of XSmc_NorInit and XSmc_NorInit from + * cortexa9/smc.h + * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_ + * cache_ext_range declarations in mb_interface.h CR#783821. + * Modified profile_mcount_mb.S to fix CR#808412. + * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in + * cortexa9/iccarm to fix CR#816701 + * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s, + * armcc/translation_table.s and iccarm/translation_table.s + * to properly defined reserved entries according to address map for + * fixing CR#820146 + * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s + * and cortexa9/armcc/translation_table.s to resolve compilation + * error for solving CR#822897 + * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for + * MISRA-C:2012 compliance. + * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by + * adding src/common/xplatform_info.*s + * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and + * removed incorrect initialization of TLB lockdown register to fix + * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S + * and iccarm/boot.s + * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile + * for iccarm and armcc compiler of cortexA9 + * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s + * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and + * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling + * of L2Cache is done later. + * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and + * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily + * taking long time to fix CR#853097. L2CacheSync is added into + * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and + * Xil_L2CacheInvalidate APIs are modified to flush the complete stack + * instead of just System Stack + * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler + * to update ECC_FLAGS and also take the compiler and archiver as specified + * in settings instead of hardcoding it. + *****************************************************************************************/ diff --git a/lib/bsp/standalone/src/common/xbasic_types.h b/lib/bsp/standalone/src/common/xbasic_types.h new file mode 100644 index 00000000..07e3db39 --- /dev/null +++ b/lib/bsp/standalone/src/common/xbasic_types.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* +* @note Dummy File for backwards compatibility +* + +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 
+* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xdebug.h b/lib/bsp/standalone/src/common/xdebug.h new file mode 100644 index 00000000..650946bd --- /dev/null +++ b/lib/bsp/standalone/src/common/xdebug.h @@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/lib/bsp/standalone/src/common/xenv.h b/lib/bsp/standalone/src/common/xenv.h new file mode 100644 index 00000000..c2f76ee2 --- /dev/null +++ b/lib/bsp/standalone/src/common/xenv.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 
+* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xenv_standalone.h b/lib/bsp/standalone/src/common/xenv_standalone.h new file mode 100644 index 00000000..edab9db7 --- /dev/null +++ b/lib/bsp/standalone/src/common/xenv_standalone.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 
+* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef s32 XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + *

+ * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */ diff --git a/lib/bsp/standalone/src/common/xil_assert.c b/lib/bsp/standalone/src/common/xil_assert.c new file mode 100644 index 00000000..6c2686f3 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_assert.c @@ -0,0 +1,146 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.c +* +* This file contains basic assert related functions for Xilinx software IP. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/** + * This variable allows testing to be done easier with asserts. An assert + * sets this variable such that a driver can evaluate this variable + * to determine if an assert occurred. + */ +u32 Xil_AssertStatus; + +/** + * This variable allows the assert functionality to be changed for testing + * such that it does not wait infinitely. Use the debugger to disable the + * waiting during testing of asserts. + */ +/*s32 Xil_AssertWait = 1*/ + +/* The callback function to be invoked when an assert is taken */ +static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Implement assert. Currently, it calls a user-defined callback function +* if one has been set. Then, it potentially enters an infinite loop depending +* on the value of the Xil_AssertWait variable. +* +* @param file is the name of the filename of the source +* @param line is the linenumber within File +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Assert(const char8 *File, s32 Line) +{ + s32 Xil_AssertWait = 1; + /* if the callback has been set then invoke it */ + if (Xil_AssertCallbackRoutine != 0) { + (*Xil_AssertCallbackRoutine)(File, Line); + } + + /* if specified, wait indefinitely such that the assert will show up + * in testing + */ + while (Xil_AssertWait != 0) { + } +} + +/*****************************************************************************/ +/** +* +* Set up a callback function to be invoked when an assert occurs. If there +* was already a callback installed, then it is replaced. +* +* @param routine is the callback to be invoked when an assert is taken +* +* @return None. +* +* @note This function has no effect if NDEBUG is set +* +******************************************************************************/ +void Xil_AssertSetCallback(Xil_AssertCallback Routine) +{ + Xil_AssertCallbackRoutine = Routine; +} + +/*****************************************************************************/ +/** +* +* Null handler function. This follows the XInterruptHandler signature for +* interrupt handlers. It can be used to assign a null handler (a stub) to an +* interrupt controller vector table. +* +* @param NullParameter is an arbitrary void pointer and not used. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XNullHandler(void *NullParameter) +{ + (void *) NullParameter; +} diff --git a/lib/bsp/standalone/src/common/xil_assert.h b/lib/bsp/standalone/src/common/xil_assert.h new file mode 100644 index 00000000..6d3f96a8 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_assert.h @@ -0,0 +1,189 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* This file contains assert related functions. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern void Xil_Assert(const char8 *File, s32 Line); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param Expression is the expression to evaluate. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the Xil_AssertWait boolean can be used to accomodate tests +* so that asserts which fail allow execution to continue. +* +* @param Expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xil_cache_vxworks.h b/lib/bsp/standalone/src/common/xil_cache_vxworks.h new file mode 100644 index 00000000..64ae0fd9 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_cache_vxworks.h @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/common/xil_hal.h b/lib/bsp/standalone/src/common/xil_hal.h new file mode 100644 index 00000000..e29d2a79 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_hal.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif diff --git a/lib/bsp/standalone/src/common/xil_macroback.h b/lib/bsp/standalone/src/common/xil_macroback.h new file mode 100644 index 00000000..f5316efb --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_macroback.h @@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif diff --git a/lib/bsp/standalone/src/common/xil_testcache.c b/lib/bsp/standalone/src/common/xil_testcache.c new file mode 100644 index 00000000..43732a4d --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testcache.c @@ -0,0 +1,366 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.c +* +* Contains utility functions to test cache. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 
+* +* @note +* +* This file contain functions that all operate on HAL. +* +******************************************************************************/ +#ifdef __ARM__ +#include "xil_cache.h" +#include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif + +#include "xil_types.h" + +extern void xil_printf(const char8 *ctrl1, ...); + +#define DATA_LENGTH 128 + +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); +#else +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); +#endif + +/** +* Perform DCache range related API test such as Xil_DCacheFlushRange and +* Xil_DCacheInvalidateRange. This test function writes a constant value +* to the Data array, flushes the range, writes a new value, then invalidates +* the corresponding range. +* +* @return +* +* - 0 is returned for a pass +* - -1 is returned for a failure +*/ +s32 Xil_TestDCacheRange(void) +{ + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; + + xil_printf("-- Cache Range Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A00505; + + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" flush range done\r\n"); + + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A00505) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + + if (!Status) { + xil_printf(" Invalidate worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache range not working\r\n"); + } + xil_printf("-- Cache Range Test Complete --\r\n"); + return Status; + +} + +/** +* Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, then invalidates +* the DCache. +* +* @return +* - 0 is returned for a pass +* - -1 is returned for a failure +*/ +s32 Xil_TestDCacheAll(void) +{ + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; + + xil_printf("-- Cache All Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50500A0A; + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlush(); + xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidate(); + + xil_printf(" invalidate all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0x50CFA0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Invalidate all worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache all not working\r\n"); + } + + xil_printf("-- DCache all Test Complete --\n\r"); + + return Status; +} + + +/** +* Perform Xil_ICacheInvalidateRange() on a few function pointers. +* +* @return +* +* - 0 is returned for a pass +* The function will hang if it fails. +*/ +s32 Xil_TestICacheRange(void) +{ + + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); + + xil_printf("-- Invalidate icache range done --\r\n"); + + return 0; +} + +/** +* Perform Xil_ICacheInvalidate(). +* +* @return +* +* - 0 is returned for a pass +* The function will hang if it fails. +*/ +s32 Xil_TestICacheAll(void) +{ + Xil_ICacheInvalidate(); + xil_printf("-- Invalidate icache all done --\r\n"); + return 0; +} +#endif diff --git a/lib/bsp/standalone/src/common/xil_testcache.h b/lib/bsp/standalone/src/common/xil_testcache.h new file mode 100644 index 00000000..0ec0ea87 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testcache.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* This file contains utility functions to test cache. +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 07/29/09 First release +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xil_testio.c b/lib/bsp/standalone/src/common/xil_testio.c new file mode 100644 index 00000000..4eaea4e5 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testio.c @@ -0,0 +1,301 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmemend.c +* +* Contains the memory test utility functions. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testio.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + + + +/** + * + * Endian swap a 16-bit word. + * @param Data is the 16-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u16 Swap16(u16 Data) +{ + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); +} + +/** + * + * Endian swap a 32-bit word. + * @param Data is the 32-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u32 Swap32(u32 Data) +{ + u16 Lo16; + u16 Hi16; + + u16 Swap16Lo; + u16 Swap16Hi; + + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); + + Swap16Lo = Swap16(Lo16); + Swap16Hi = Swap16(Hi16); + + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); +} + +/*****************************************************************************/ +/** +* +* Perform a destructive 8-bit wide register IO test where the register is +* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing +* values. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Length is the Length of the block. +* @param Value is the constant used for writting the memory. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) +{ + u8 ValueIn; + s32 Index; + s32 Status = 0; + + for (Index = 0; Index < Length; Index++) { + Xil_Out8((INTPTR)Addr, Value); + + ValueIn = Xil_In8((INTPTR)Addr); + + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; + } + } + return Status; + +} + +/*****************************************************************************/ +/** +* +* Perform a destructive 16-bit wide register IO test. Each location is tested +* by sequentially writing a 16-bit wide register, reading the register, and +* comparing value. This function tests three kinds of register IO functions, +* normal register IO, little-endian register IO, and big-endian register IO. +* When testing little/big-endian IO, the function performs the following +* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values, +* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the +* read-in value before comparing is controlled by the 5th argument. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Length is the Length of the block. +* @param Value is the constant used for writting the memory. +* @param Kind is the test kind. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap indicates whether to byte swap the read-in value. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) +{ + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out16LE((INTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((INTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((INTPTR)TempAddr16, Value); + break; + } + + ValueIn = Xil_In16((INTPTR)TempAddr16); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out16((INTPTR)TempAddr16, Value); + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((INTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((INTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((INTPTR)TempAddr16); + break; + } + + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + TempAddr16 += sizeof(u16); + } + return 0; +} + + +/*****************************************************************************/ +/** +* +* Perform a destructive 32-bit wide register IO test. Each location is tested +* by sequentially writing a 32-bit wide regsiter, reading the register, and +* comparing value. This function tests three kinds of register IO functions, +* normal register IO, little-endian register IO, and big-endian register IO. +* When testing little/big-endian IO, the function perform the following +* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, +* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value +* before comparing is controlled by the 5th argument. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Length is the Length of the block. +* @param Value is the constant used for writting the memory. +* @param Kind is the test kind. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap indicates whether to byte swap the read-in value. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) +{ + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out32LE((INTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((INTPTR)TempAddr, Value); + break; + default: + Xil_Out32((INTPTR)TempAddr, Value); + break; + } + + ValueIn = Xil_In32((INTPTR)TempAddr); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out32((INTPTR)TempAddr, Value); + + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((INTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((INTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((INTPTR)TempAddr); + break; + } + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + TempAddr += sizeof(u32); + } + return 0; +} diff --git a/lib/bsp/standalone/src/common/xil_testio.h b/lib/bsp/standalone/src/common/xil_testio.h new file mode 100644 index 00000000..2fd4d579 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testio.h @@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmemend.h +* +* This file contains utility functions to teach endian related memory +* IO functions. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xil_testmem.c b/lib/bsp/standalone/src/common/xil_testmem.c new file mode 100644 index 00000000..ef38d6d2 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testmem.c @@ -0,0 +1,882 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.c +* +* Contains the memory test utility functions. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testmem.h" +#include "xil_io.h" +#include "xil_assert.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + +static u32 RotateLeft(u32 Input, u8 Width); + +/* define ROTATE_RIGHT to give access to this functionality */ +/* #define ROTATE_RIGHT */ +#ifdef ROTATE_RIGHT +static u32 RotateRight(u32 Input, u8 Width); +#endif /* ROTATE_RIGHT */ + + +/*****************************************************************************/ +/** +* +* Perform a destructive 32-bit wide memory test. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Words is the length of the block. +* @param Pattern is the constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest is the test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - 0 is returned for a pass +* - -1 is returned for a failure +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u32 Val; + u32 FirtVal; + u32 WordMem32; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + *(Addr+I) = Val; + Val++; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + WordMem32 = *(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)32; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1U << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)32; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u32) RotateLeft(Val, 32U); + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1U << j; + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (u32)32; I++) { + /* read memory location */ + + WordMem32 = *(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, 32U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)32; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1U << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)32; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1U << j); + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (u32)32; I++) { + /* read memory location */ + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u32) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* Read the location */ + WordMem32 = *(Addr+I); + Val = (u32) (~((INTPTR) (&Addr[I]))); + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + + /* read memory location */ + + WordMem32 = *(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* Perform a destructive 16-bit wide memory test. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Words is the length of the block. +* @param Pattern is the constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest is the test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u16 Val; + u16 FirtVal; + u16 WordMem16; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)16; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u16)RotateLeft(Val, 16U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)16; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, 16U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (u32)16; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u16)RotateLeft(~Val, 16U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)16; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~Val, 16U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u16) (~((INTPTR)(&Addr[I]))); + *(Addr+I) = Val; + } + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + Val = (u16) (~((INTPTR) (&Addr[I]))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem16 = *(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* Perform a destructive 8-bit wide memory test. +* +* @param Addr is a pointer to the region of memory to be tested. +* @param Words is the length of the block. +* @param Pattern is the constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest is the test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u8 Val; + u8 FirtVal; + u8 WordMem8; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + Xil_AssertNonvoid(Addr != NULL); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < (u32)8; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)8; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, 8U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < (u32)8; I++) { + /* write memory location */ + *(Addr+I) = Val; + Val = ~((u8)RotateLeft(~Val, 8U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (u32)8; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~Val, 8U)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u8) (~((INTPTR) (&Addr[I]))); + *(Addr+I) = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + Val = (u8) (~((INTPTR) (&Addr[I]))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + *(Addr+I) = Val; + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = *(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* Rotates the provided value to the left one bit position +* +* @param Input is value to be rotated to the left +* @param Width is the number of bits in the input data +* +* @return +* +* The resulting unsigned long value of the rotate left +* +* @note +* +* None. +* +*****************************************************************************/ +static u32 RotateLeft(u32 Input, u8 Width) +{ + u32 Msb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << (u32)1) - (u32)1; + + /* + * set the Width of the Input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + Msb = LocalInput & MsbMask; + + ReturnVal = LocalInput << 1U; + + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} + +#ifdef ROTATE_RIGHT +/*****************************************************************************/ +/** +* +* Rotates the provided value to the right one bit position +* +* @param Input is value to be rotated to the right +* @param Width is the number of bits in the input data +* +* @return +* +* The resulting u32 value of the rotate right +* +* @note +* +* None. +* +*****************************************************************************/ +static u32 RotateRight(u32 Input, u8 Width) +{ + u32 Lsb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << 1U) - 1U; + + /* + * set the width of the input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + ReturnVal = LocalInput >> 1U; + + Lsb = LocalInput & 0x00000001U; + + if (Lsb != 0x00000000U) { + ReturnVal = ReturnVal | MsbMask; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} +#endif /* ROTATE_RIGHT */ diff --git a/lib/bsp/standalone/src/common/xil_testmem.h b/lib/bsp/standalone/src/common/xil_testmem.h new file mode 100644 index 00000000..1b67a521 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_testmem.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* +* This file contains utility functions to test memory. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* Subtest descriptions: +*
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* 
+* +* WARNING +* +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xil_types.h b/lib/bsp/standalone/src/common/xil_types.h new file mode 100644 index 00000000..b9ef3c18 --- /dev/null +++ b/lib/bsp/standalone/src/common/xil_types.h @@ -0,0 +1,184 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* This file contains basic types for Xilinx software IP. + +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 
+* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include +#include + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */ + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/** + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/** + * xbasic_types.h does not typedef s* or u64 + */ + +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; + +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include +#endif + + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/*@}*/ + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xplatform_info.c b/lib/bsp/standalone/src/common/xplatform_info.c new file mode 100644 index 00000000..1a55b2f8 --- /dev/null +++ b/lib/bsp/standalone/src/common/xplatform_info.c @@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.c +* +* This file contains information about hardware for which the code is built +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This API is used to provide information about platform +* +* @param None. +* +* @return The information about platform defined in xplatform_info.h +* +* @note None. +* +******************************************************************************/ +u32 XGetPlatform_Info() +{ + u32 reg; +#if defined (ARMR5) || (__aarch64__) + return XPLAT_ZYNQ_ULTRA_MP; +#elif (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif +} + +/*****************************************************************************/ +/** +* +* This API is used to provide information about zynq ultrascale MP platform +* +* @param None. +* +* @return The information about zynq ultrascale MP platform defined in +* xplatform_info.h +* +* @note None. +* +******************************************************************************/ +#if defined (ARMR5) || (__aarch64__) +u32 XGet_Zynq_UltraMp_Platform_info() +{ + u32 reg; + reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK); + return reg; +} +#endif \ No newline at end of file diff --git a/lib/bsp/standalone/src/common/xplatform_info.h b/lib/bsp/standalone/src/common/xplatform_info.h new file mode 100644 index 00000000..d71a692c --- /dev/null +++ b/lib/bsp/standalone/src/common/xplatform_info.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* This file contains definitions for various platforms available +* +******************************************************************************/ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPLAT_INFO_MASK (0xF) +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/common/xstatus.h b/lib/bsp/standalone/src/common/xstatus.h new file mode 100644 index 00000000..308d71b7 --- /dev/null +++ b/lib/bsp/standalone/src/common/xstatus.h @@ -0,0 +1,430 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/gcc/Makefile b/lib/bsp/standalone/src/cortexa53/gcc/Makefile new file mode 100644 index 00000000..7f051ce5 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/Makefile @@ -0,0 +1,75 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +include config.make + +AS=aarch64-none-elf-as +CC=aarch64-none-elf-gcc +AR=aarch64-none-elf-ar +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + + +#The following flags are required for PEEP. We can remove them later +ECC_FLAGS += -march=armv8-a + + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone A53" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + +.PHONY: include +include: standalone_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OUTS} + $(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_exit.c b/lib/bsp/standalone/src/cortexa53/gcc/_exit.c new file mode 100644 index 00000000..77806d1b --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_exit.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) + { + __asm__("wfi"); + } +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_open.c b/lib/bsp/standalone/src/cortexa53/gcc/_open.c new file mode 100644 index 00000000..a4b7f824 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_open.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c new file mode 100644 index 00000000..5911b058 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/_sbrk.c @@ -0,0 +1,70 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + heap += incr; + + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; + } + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/abort.c b/lib/bsp/standalone/src/cortexa53/gcc/abort.c new file mode 100644 index 00000000..f6450940 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/abort.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S new file mode 100644 index 00000000..2d779f5a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/asm_vectors.S @@ -0,0 +1,208 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A53 processor +* Currently NEON registers are not saved on stack if interrupt is taken. +* It will be implemented. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00	pkp	5/21/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + + +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SErrorInterrupt +.globl SynchronousInterrupt + + +.org 0 + +.section .vectors, "a" + +_vector_table: + +.set VBAR, _vector_table +.org VBAR + b _boot +.org (VBAR + 0x200) + b SynchronousInterruptHandler + +.org (VBAR + 0x280) + b IRQInterruptHandler + +.org (VBAR + 0x300) + b FIQInterruptHandler + +.org (VBAR + 0x380) + b SErrorInterruptHandler + + +SynchronousInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SynchronousInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +IRQInterruptHandler: + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl IRQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +FIQInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl FIQInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +SErrorInterruptHandler: + + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + bl SErrorInterrupt + + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 + + eret + +.end diff --git a/lib/bsp/standalone/src/cortexa53/gcc/boot.S b/lib/bsp/standalone/src/cortexa53/gcc/boot.S new file mode 100644 index 00000000..807f80c3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/boot.S @@ -0,0 +1,265 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* This file contains the initial startup code for the Cortex A53 processor +* Currently the processor starts at EL3 and boot code, startup and main +* code will run on secure EL3. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	5/21/14 Initial version
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+.globl MMUTableL0
+.globl MMUTableL1
+.globl MMUTableL2
+.global _prestart
+.global _boot
+
+.global __el3_stack
+.global __el2_stack
+.global __el1_stack
+.global __el0_stack
+.global _vector_table
+
+
+.set EL3_stack,		__el3_stack
+.set EL2_stack,		__el2_stack
+.set EL1_stack,		__el1_stack
+.set EL0_stack,		__el0_stack
+
+.set TT_S1_FAULT,	0x0
+.set TT_S1_TABLE,	0x3
+
+.set L0Table,	MMUTableL0
+.set L1Table,	MMUTableL1
+.set L2Table,	MMUTableL2
+.set vector_base,	_vector_table
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+	mov      x0, #0
+	mov      x1, #0
+	mov      x2, #0
+	mov      x3, #0
+	mov      x4, #0
+	mov      x5, #0
+	mov      x6, #0
+	mov      x7, #0
+	mov      x8, #0
+	mov      x9, #0
+	mov      x10, #0
+	mov      x11, #0
+	mov      x12, #0
+	mov      x13, #0
+	mov      x14, #0
+	mov      x15, #0
+	mov      x16, #0
+	mov      x17, #0
+	mov      x18, #0
+	mov      x19, #0
+	mov      x20, #0
+	mov      x21, #0
+	mov      x22, #0
+	mov      x23, #0
+	mov      x24, #0
+	mov      x25, #0
+	mov      x26, #0
+	mov      x27, #0
+	mov      x28, #0
+	mov      x29, #0
+	mov      x30, #0
+#if 0 //dont put other a53 cpus in wfi
+   //Which core am I
+   // ----------------
+	mrs      x0, MPIDR_EL1
+	and      x0, x0, #0xFF                     //Mask off to leave Aff0
+	cbz      x0, OKToRun                          //If core 0, run the primary init code
+EndlessLoop0:
+	wfi
+	b        EndlessLoop0
+#endif
+OKToRun:
+
+	/*Set vector table base address*/
+	ldr	x1, =vector_base
+	msr	VBAR_EL3,x1
+
+	/*Define stack pointer for current exception level*/
+	ldr	 x2,=EL3_stack
+	mov	 sp,x2
+
+
+	/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
+	mov      x0, #0                 // Clear all trap bits
+	msr      CPTR_EL3, x0
+
+
+	/* Configure SCR_EL3 */
+	mov      w1, #0              	//; Initial value of register is unknown
+	orr      w1, w1, #(1 << 11)  	//; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
+	orr      w1, w1, #(1 << 10)  	//; Set RW bit (EL1 is AArch64, as this is the Secure world)
+	orr      w1, w1, #(1 << 3)   	//; Set EA bit (SError routed to EL3)
+	orr      w1, w1, #(1 << 2)   	//; Set FIQ bit (FIQs routed to EL3)
+	orr      w1, w1, #(1 << 1)   	//; Set IRQ bit (IRQs routed to EL3)
+	msr      SCR_EL3, x1
+
+	/*Enable ECC protection*/
+	mrs	x0, S3_1_C11_C0_2  	// register L2CTLR_EL1
+	orr	x0, x0, #(1<<22)
+	msr	S3_1_C11_C0_2, x0
+
+	/*configure cpu auxiliary control register EL1 */
+	ldr	x0,=0x80CA000 		// L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
+	msr	S3_1_C15_C2_0, x0 	//CPUACTLR_EL1
+
+
+	/*Enable hardware coherency between cores*/
+	mrs      x0, S3_1_c15_c2_1  	//Read EL1 CPU Extended Control Register
+	orr      x0, x0, #(1 << 6)  	//Set the SMPEN bit
+	msr      S3_1_c15_c2_1, x0  	//Write EL1 CPU Extended Control Register
+	isb
+
+	tlbi 	ALLE3
+	ic      IALLU                  	//; Invalidate I cache to PoU
+	bl 	invalidate_dcaches
+	dsb	 sy
+	isb
+
+	ldr      x1, =L0Table 		//; Get address of level 0 for TTBR0_EL1
+	msr      TTBR0_EL3, x1		//; Set TTBR0_EL3 (NOTE: There is no TTBR1 at EL1)
+
+
+	/**********************************************
+	* Set up memory attributes
+	* This equates to:
+	* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
+	* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
+	* 2 = b00000000 = Device-nGnRnE
+	**********************************************/
+	ldr      x1, =0x000000000000FF44
+	msr      MAIR_EL3, x1
+
+        /**********************************************
+        * Set up TCR_EL3
+	* Physical Address Size PS =  010 -> 40bits 1TB
+	* Granual Size TG0 = 00 -> 4KB
+        * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
+        ***************************************************/
+        ldr     x1,=0x80823518
+        msr     TCR_EL3, x1
+        isb
+
+	/* Configure SCTLR_EL3 */
+	mov      x1, #0                //Most of the SCTLR_EL3 bits are unknown at reset
+	orr      x1, x1, #(1 << 12)	//Enable I cache
+	orr      x1, x1, #(1 << 3)	//Enable SP alignment check
+	orr      x1, x1, #(1 << 2)	//Enable caches
+	orr      x1, x1, #(1 << 0)	//Enable MMU
+	msr      SCTLR_EL3, x1
+	dsb	 sy
+	isb
+
+	bl 	 _startup		//jump to start
+
+loop:	b	loop
+
+
+invalidate_dcaches:
+
+	dmb     ISH
+	mrs     x0, CLIDR_EL1          //; x0 = CLIDR
+	ubfx    w2, w0, #24, #3        //; w2 = CLIDR.LoC
+	cmp     w2, #0                 //; LoC is 0?
+	b.eq    invalidateCaches_end   //; No cleaning required and enable MMU
+	mov     w1, #0                 //; w1 = level iterator
+
+invalidateCaches_flush_level:
+	add     w3, w1, w1, lsl #1     //; w3 = w1 * 3 (right-shift for cache type)
+	lsr     w3, w0, w3             //; w3 = w0 >> w3
+	ubfx    w3, w3, #0, #3         //; w3 = cache type of this level
+	cmp     w3, #2                 //; No cache at this level?
+	b.lt    invalidateCaches_next_level
+
+	lsl     w4, w1, #1
+	msr     CSSELR_EL1, x4         //; Select current cache level in CSSELR
+	isb                            //; ISB required to reflect new CSIDR
+	mrs     x4, CCSIDR_EL1         //; w4 = CSIDR
+
+	ubfx    w3, w4, #0, #3
+	add    	w3, w3, #2             //; w3 = log2(line size)
+	ubfx    w5, w4, #13, #15
+	ubfx    w4, w4, #3, #10        //; w4 = Way number
+	clz     w6, w4                 //; w6 = 32 - log2(number of ways)
+
+invalidateCaches_flush_set:
+	mov     w8, w4                 //; w8 = Way number
+invalidateCaches_flush_way:
+	lsl     w7, w1, #1             //; Fill level field
+	lsl     w9, w5, w3
+	orr     w7, w7, w9             //; Fill index field
+	lsl     w9, w8, w6
+	orr     w7, w7, w9             //; Fill way field
+	dc      CISW, x7               //; Invalidate by set/way to point of coherency
+	subs    w8, w8, #1             //; Decrement way
+	b.ge    invalidateCaches_flush_way
+	subs    w5, w5, #1             //; Descrement set
+	b.ge    invalidateCaches_flush_set
+
+invalidateCaches_next_level:
+	add     w1, w1, #1             //; Next level
+	cmp     w2, w1
+	b.gt    invalidateCaches_flush_level
+
+invalidateCaches_end:
+	ret
+
+.end
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/close.c b/lib/bsp/standalone/src/cortexa53/gcc/close.c
new file mode 100644
index 00000000..38bc6dca
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/close.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/errno.c b/lib/bsp/standalone/src/cortexa53/gcc/errno.c
new file mode 100644
index 00000000..c0b1d14f
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c b/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
new file mode 100644
index 00000000..63d390af
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/fstat.c b/lib/bsp/standalone/src/cortexa53/gcc/fstat.c
new file mode 100644
index 00000000..a1d394c9
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/getpid.c b/lib/bsp/standalone/src/cortexa53/gcc/getpid.c
new file mode 100644
index 00000000..73c7902a
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c b/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c
new file mode 100644
index 00000000..4571f492
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/initialise_monitor_handles.c
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file initialise_monitor_handles.c
+*
+* Contains blank function to avoid compilation error
+*
+* @note
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+******************************************************************************/ +__attribute__((weak)) void initialise_monitor_handles(){ + +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/isatty.c b/lib/bsp/standalone/src/cortexa53/gcc/isatty.c new file mode 100644 index 00000000..d0a8a825 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/isatty.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _isatty(sint32 fd); +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/kill.c b/lib/bsp/standalone/src/cortexa53/gcc/kill.c new file mode 100644 index 00000000..fdbcb600 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/kill.c @@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _kill(s32 pid, s32 sig); +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) s32 kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/lseek.c b/lib/bsp/standalone/src/cortexa53/gcc/lseek.c new file mode 100644 index 00000000..0a3a1fa8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/lseek.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/open.c b/lib/bsp/standalone/src/cortexa53/gcc/open.c new file mode 100644 index 00000000..04a136c6 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/open.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode); +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/read.c b/lib/bsp/standalone/src/cortexa53/gcc/read.c new file mode 100644 index 00000000..d0fe15eb --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/read.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* read.c -- read bytes from a input device. + */ + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c b/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c new file mode 100644 index 00000000..78b58091 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/sbrk.c @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) char8 *sbrk (s32 nbytes); +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if(heap_ptr != NULL) { + heap_ptr += nbytes; + } + +/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ + if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s b/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s new file mode 100644 index 00000000..ad5686a2 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/translation_table.s @@ -0,0 +1,170 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file translation_table.s +* +* This file contains the initialization for the MMU table in RAM +* needed by the Cortex A53 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  05/21/14 Initial version
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+	.globl  MMUTableL0
+	.globl  MMUTableL1
+	.globl  MMUTableL2
+
+	.set reserved,	0x0 					/* Fault*/
+	.set Memory,	0x405 | (3 << 8) | (0x0)		/* normal writeback write allocate inner shared read write */
+	.set Device,	0x409 | (1 << 53)| (1 << 54) |(0x0)	/* strongly ordered read write non executable*/
+	.section .mmu_tbl0,"a"
+
+MMUTableL0:
+
+.set SECT, MMUTableL1
+.8byte	SECT + 0x3
+.set SECT, MMUTableL1+0x1000
+.8byte	SECT + 0x3
+
+	.section .mmu_tbl1,"a"
+
+MMUTableL1:
+
+.set SECT, MMUTableL2			/*1GB DDR*/
+.8byte	SECT + 0x3
+
+.rept	0x3				/*1GB DDR, 1GB PL, 2GB other devices n memory*/
+.set SECT, SECT + 0x1000
+.8byte	SECT + 0x3
+.endr
+
+.set SECT,0x100000000
+.rept	0xC
+.8byte	SECT + reserved
+.set SECT, SECT + 0x40000000	/*12GB Reserved*/
+.endr
+
+.rept	0x10
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*8GB PL, 8GB PCIe*/
+
+.endr
+
+.rept	0x20
+.8byte	SECT + Memory
+
+.set SECT, SECT + 0x40000000	/*32GB DDR*/
+.endr
+
+
+.rept	0xC0
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*192GB PL*/
+.endr
+
+
+.rept	0x100
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*256GB PL/PCIe*/
+.endr
+
+
+.rept	0x200
+.8byte	SECT + Device
+.set SECT, SECT + 0x40000000	/*512GB PL/DDR*/
+.endr
+
+
+.section .mmu_tbl2,"a"
+
+MMUTableL2:
+
+.set SECT, 0
+
+.rept	0x0400			/*2GB DDR */
+.8byte	SECT + Memory
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x0200			/*1GB lower PL*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x0100			/*512MB QSPI*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x080			/*256MB lower PCIe*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x040			/*128MB Reserved*/
+.8byte	SECT + reserved
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB coresight*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*16MB RPU low latency port*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x022			/*68MB Device*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+.rept	0x8			/*8MB FPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.rept	0x4			/*16MB LPS*/
+.8byte	SECT + Device
+.set	SECT, SECT+0x200000
+.endr
+
+.8byte	SECT + Device 		/*2MB PMU/CSU */
+.set	SECT, SECT+0x200000
+.8byte  SECT + Memory		/*2MB OCM/TCM*/
+.end
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/unlink.c b/lib/bsp/standalone/src/cortexa53/gcc/unlink.c
new file mode 100644
index 00000000..1fef9683
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) s32 unlink(char8 *path)
+{
+  (void *)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/write.c b/lib/bsp/standalone/src/cortexa53/gcc/write.c
new file mode 100644
index 00000000..57c53eb2
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/write.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) s32
+write (s32 fd, char8* buf, s32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_write (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
new file mode 100644
index 00000000..eab93d18
--- /dev/null
+++ b/lib/bsp/standalone/src/cortexa53/gcc/xil-crt0.S
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00	pkp  05/21/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start__ + +.Lbss_end: + .long __bss_end__ + + + + .globl _startup +_startup: + + mov x0, #0 + + /* clear sbss */ + ldr w1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr w2,.Lsbss_end /* calculate end of the SBSS */ + uxtw x1, w1 /*zero extension to w1 register*/ + uxtw x2, w2 /*zero extension to w2 register*/ + +.Lloop_sbss: + cmp x1,x2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str x0, [x1], #8 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr w1,.Lbss_start /* calculate beginning of the BSS */ + ldr w2,.Lbss_end /* calculate end of the BSS */ + uxtw x1, w1 /*zero extension to w1 register*/ + uxtw x2, w2 /*zero extension to w2 register*/ + +.Lloop_bss: + cmp x1,x2 + bge .Lenclbss /* If no BSS, no clearing required */ + str x0, [x1], #8 + b .Lloop_bss + +.Lenclbss: + + bl Init_Uart /* Initialize UART */ + + + /* make sure argc and argv are valid */ + mov x0, #0 + mov x1, #0 + + bl main /* Jump to main C code */ + + + + bl _exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _startup,.Lstart-_startup \ No newline at end of file diff --git a/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h new file mode 100644 index 00000000..5f0e9c25 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/gcc/xpseudo_asm_gcc.h @@ -0,0 +1,169 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() asm ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() asm("dsb sy") + +/* Data Memory Barrier */ +#define dmb() asm("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) +#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) asm("ic " #reg) +#define mtcptlbi(reg) asm("tlbi " #reg) +#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u32 rval;\ + asm("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val)) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/lib/bsp/standalone/src/cortexa53/print.c b/lib/bsp/standalone/src/cortexa53/print.c new file mode 100644 index 00000000..31d7b198 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/print.c @@ -0,0 +1,32 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char8 *ptr) +{ +#ifdef STDOUT_BASEADDRESS + while (*ptr != (char8)0) { + outbyte (*ptr); + *ptr++; + } +#else +(void)ptr; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa53/putnum.c b/lib/bsp/standalone/src/cortexa53/putnum.c new file mode 100644 index 00000000..ec0dc37e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/putnum.c @@ -0,0 +1,59 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* + * putnum -- print a 32 bit number in hex + */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) +{ + char8 buf[9]; + u32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 7U ; cnt >= 0U ; cnt--) { + digit = ((num >> (cnt * 4U)) & 0x0000000FU); + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } + print (buf); +} diff --git a/lib/bsp/standalone/src/cortexa53/sleep.c b/lib/bsp/standalone/src/cortexa53/sleep.c new file mode 100644 index 00000000..e8aedafb --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/sleep.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex A53 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +/*****************************************************************************/ +/* +* +* This API is used to provide delays in seconds +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +****************************************************************************/ +s32 sleep(u32 seconds) +{ + XTime tEnd, tCur; + + /*write 50MHz frequency to System Time Stamp Generator Register*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ); + + /*Enable the counter*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN); + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + /*Disable the counter*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN))); + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa53/sleep.h b/lib/bsp/standalone/src/cortexa53/sleep.h new file mode 100644 index 00000000..8497d2fe --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/sleep.h @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa53/uart.c b/lib/bsp/standalone/src/cortexa53/uart.c new file mode 100644 index 00000000..894db7fc --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/uart.c @@ -0,0 +1,162 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file uart.c +* +* This file contains APIs for configuring the UART. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/* Register offsets */ +#define UART_CR_OFFSET 0x00000000U +#define UART_MR_OFFSET 0x00000004U +#define UART_BAUDGEN_OFFSET 0x00000018U +#define UART_BAUDDIV_OFFSET 0x00000034U + +#define MAX_BAUD_ERROR_RATE 3U /* max % error allowed */ +#define UART_BAUDRATE 115200U +#define CSU_VERSION_REG 0xFFCA0044U + +void Init_Uart(void); + +void Init_Uart(void) +{ +#ifdef STDOUT_BASEADDRESS + u8 IterBAUDDIV; /* Iterator for available baud divisor values */ + u32 BRGR_Value; /* Calculated value for baud rate generator */ + u32 CalcBaudRate; /* Calculated baud rate */ + u32 BaudError; /* Diff between calculated and requested baud + * rate */ + u32 Best_BRGR = 0U; /* Best value for baud rate generator */ + u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */ + u32 Best_Error = 0xFFFFFFFFU; + u32 PercentError; + u32 InputClk; + u32 BaudRate = UART_BAUDRATE; + + /* set CD and BDIV */ + +#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) + InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ; +#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) + InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ; +#else + /* STDIO is not set or axi_uart is being used for STDIO */ + return; +#endif +InputClk = 25000000U; + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) { + + /* + * Calculate the value for BRGR register + */ + BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 1U)); + + /* + * Calculate the baud rate from the BRGR value + */ + CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 1U)); + + /* + * Avoid unsigned integer underflow + */ + if (BaudRate > CalcBaudRate) { + BaudError = BaudRate - CalcBaudRate; + } else { + BaudError = CalcBaudRate - BaudRate; + } + + /* + * Find the calculated baud rate closest to requested baud rate. + */ + if (Best_Error > BaudError) { + + Best_BRGR = BRGR_Value; + Best_BAUDDIV = IterBAUDDIV; + Best_Error = BaudError; + } + } + + /* + * Make sure the best error is not too large. + */ + PercentError = (Best_Error * 100U) / BaudRate; + if (((u32)MAX_BAUD_ERROR_RATE) < PercentError) { + return; + } + + /* set CD and BDIV */ + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV); + + /* + * Veloce specific code + */ + if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) { + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 2U); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 4U); + } + + /* + * 8 data, 1 stop, 0 parity bits + * sel_clk=uart_clk=APB clock + */ + Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U); + + /* enable Tx/Rx and reset Tx/Rx data path */ + Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U); + + return; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa53/usleep.c b/lib/bsp/standalone/src/cortexa53/usleep.c new file mode 100644 index 00000000..7d0ff09f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/usleep.c @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex A53 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa53.h" + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND (COUNTS_PER_SECOND/1000000 ) + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ +s32 usleep(u32 useconds) +{ + XTime tEnd, tCur; + + /*write 50MHz frequency to System Time Stamp Generator Register*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),XIOU_SCNTRS_FREQ); + + /*Enable the counter*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),XIOU_SCNTRS_CNT_CNTRL_REG_EN); + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + /*Disable the counter*/ + Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),(~(XIOU_SCNTRS_CNT_CNTRL_REG_EN))); + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa53/vectors.c b/lib/bsp/standalone/src/cortexa53/vectors.c new file mode 100644 index 00000000..61d9f741 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/vectors.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex A53 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/************************** Function Prototypes ******************************/ + + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SynchronousInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SYNC_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SError Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SErrorInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data); +} diff --git a/lib/bsp/standalone/src/cortexa53/vectors.h b/lib/bsp/standalone/src/cortexa53/vectors.h new file mode 100644 index 00000000..8c508c3a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/vectors.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A53 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SynchronousInterrupt(void); +void SErrorInterrupt(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu0_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu0_cfg.h new file mode 100644 index 00000000..9029bead --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu0_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU0_CFG_H__ +#define __XDDR_XMPU0_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu0Cfg Base Address + */ +#define XDDR_XMPU0_CFG_BASEADDR 0xFD000000UL + +/** + * Register: XddrXmpu0CfgCtrl + */ +#define XDDR_XMPU0_CFG_CTRL ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU0_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgErrSts1 + */ +#define XDDR_XMPU0_CFG_ERR_STS1 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgErrSts2 + */ +#define XDDR_XMPU0_CFG_ERR_STS2 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgPoison + */ +#define XDDR_XMPU0_CFG_POISON ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU0_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU0_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIsr + */ +#define XDDR_XMPU0_CFG_ISR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU0_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgImr + */ +#define XDDR_XMPU0_CFG_IMR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU0_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgIen + */ +#define XDDR_XMPU0_CFG_IEN ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU0_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIds + */ +#define XDDR_XMPU0_CFG_IDS ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU0_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgLock + */ +#define XDDR_XMPU0_CFG_LOCK ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU0_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Strt + */ +#define XDDR_XMPU0_CFG_R00_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00End + */ +#define XDDR_XMPU0_CFG_R00_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU0_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Mstr + */ +#define XDDR_XMPU0_CFG_R00_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00 + */ +#define XDDR_XMPU0_CFG_R00 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU0_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Strt + */ +#define XDDR_XMPU0_CFG_R01_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01End + */ +#define XDDR_XMPU0_CFG_R01_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU0_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Mstr + */ +#define XDDR_XMPU0_CFG_R01_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01 + */ +#define XDDR_XMPU0_CFG_R01 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU0_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Strt + */ +#define XDDR_XMPU0_CFG_R02_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02End + */ +#define XDDR_XMPU0_CFG_R02_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU0_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Mstr + */ +#define XDDR_XMPU0_CFG_R02_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02 + */ +#define XDDR_XMPU0_CFG_R02 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU0_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Strt + */ +#define XDDR_XMPU0_CFG_R03_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03End + */ +#define XDDR_XMPU0_CFG_R03_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU0_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Mstr + */ +#define XDDR_XMPU0_CFG_R03_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03 + */ +#define XDDR_XMPU0_CFG_R03 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU0_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Strt + */ +#define XDDR_XMPU0_CFG_R04_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04End + */ +#define XDDR_XMPU0_CFG_R04_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU0_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Mstr + */ +#define XDDR_XMPU0_CFG_R04_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04 + */ +#define XDDR_XMPU0_CFG_R04 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU0_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Strt + */ +#define XDDR_XMPU0_CFG_R05_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05End + */ +#define XDDR_XMPU0_CFG_R05_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU0_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Mstr + */ +#define XDDR_XMPU0_CFG_R05_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05 + */ +#define XDDR_XMPU0_CFG_R05 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU0_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Strt + */ +#define XDDR_XMPU0_CFG_R06_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06End + */ +#define XDDR_XMPU0_CFG_R06_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU0_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Mstr + */ +#define XDDR_XMPU0_CFG_R06_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06 + */ +#define XDDR_XMPU0_CFG_R06 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU0_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Strt + */ +#define XDDR_XMPU0_CFG_R07_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07End + */ +#define XDDR_XMPU0_CFG_R07_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU0_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Mstr + */ +#define XDDR_XMPU0_CFG_R07_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07 + */ +#define XDDR_XMPU0_CFG_R07 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU0_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Strt + */ +#define XDDR_XMPU0_CFG_R08_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08End + */ +#define XDDR_XMPU0_CFG_R08_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU0_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Mstr + */ +#define XDDR_XMPU0_CFG_R08_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08 + */ +#define XDDR_XMPU0_CFG_R08 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU0_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Strt + */ +#define XDDR_XMPU0_CFG_R09_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09End + */ +#define XDDR_XMPU0_CFG_R09_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU0_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Mstr + */ +#define XDDR_XMPU0_CFG_R09_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09 + */ +#define XDDR_XMPU0_CFG_R09 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU0_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Strt + */ +#define XDDR_XMPU0_CFG_R10_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10End + */ +#define XDDR_XMPU0_CFG_R10_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU0_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Mstr + */ +#define XDDR_XMPU0_CFG_R10_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10 + */ +#define XDDR_XMPU0_CFG_R10 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU0_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Strt + */ +#define XDDR_XMPU0_CFG_R11_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11End + */ +#define XDDR_XMPU0_CFG_R11_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU0_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Mstr + */ +#define XDDR_XMPU0_CFG_R11_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11 + */ +#define XDDR_XMPU0_CFG_R11 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU0_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Strt + */ +#define XDDR_XMPU0_CFG_R12_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12End + */ +#define XDDR_XMPU0_CFG_R12_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU0_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Mstr + */ +#define XDDR_XMPU0_CFG_R12_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12 + */ +#define XDDR_XMPU0_CFG_R12 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU0_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Strt + */ +#define XDDR_XMPU0_CFG_R13_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13End + */ +#define XDDR_XMPU0_CFG_R13_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU0_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Mstr + */ +#define XDDR_XMPU0_CFG_R13_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13 + */ +#define XDDR_XMPU0_CFG_R13 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU0_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Strt + */ +#define XDDR_XMPU0_CFG_R14_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14End + */ +#define XDDR_XMPU0_CFG_R14_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU0_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Mstr + */ +#define XDDR_XMPU0_CFG_R14_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14 + */ +#define XDDR_XMPU0_CFG_R14 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU0_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Strt + */ +#define XDDR_XMPU0_CFG_R15_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15End + */ +#define XDDR_XMPU0_CFG_R15_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU0_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Mstr + */ +#define XDDR_XMPU0_CFG_R15_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15 + */ +#define XDDR_XMPU0_CFG_R15 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU0_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU0_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu1_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu1_cfg.h new file mode 100644 index 00000000..e2fa6d4a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu1_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU1_CFG_H__ +#define __XDDR_XMPU1_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu1Cfg Base Address + */ +#define XDDR_XMPU1_CFG_BASEADDR 0xFD010000UL + +/** + * Register: XddrXmpu1CfgCtrl + */ +#define XDDR_XMPU1_CFG_CTRL ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU1_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgErrSts1 + */ +#define XDDR_XMPU1_CFG_ERR_STS1 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgErrSts2 + */ +#define XDDR_XMPU1_CFG_ERR_STS2 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgPoison + */ +#define XDDR_XMPU1_CFG_POISON ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU1_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU1_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIsr + */ +#define XDDR_XMPU1_CFG_ISR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU1_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgImr + */ +#define XDDR_XMPU1_CFG_IMR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU1_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgIen + */ +#define XDDR_XMPU1_CFG_IEN ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU1_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIds + */ +#define XDDR_XMPU1_CFG_IDS ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU1_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgLock + */ +#define XDDR_XMPU1_CFG_LOCK ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU1_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Strt + */ +#define XDDR_XMPU1_CFG_R00_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00End + */ +#define XDDR_XMPU1_CFG_R00_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU1_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Mstr + */ +#define XDDR_XMPU1_CFG_R00_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00 + */ +#define XDDR_XMPU1_CFG_R00 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU1_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Strt + */ +#define XDDR_XMPU1_CFG_R01_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01End + */ +#define XDDR_XMPU1_CFG_R01_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU1_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Mstr + */ +#define XDDR_XMPU1_CFG_R01_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01 + */ +#define XDDR_XMPU1_CFG_R01 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU1_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Strt + */ +#define XDDR_XMPU1_CFG_R02_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02End + */ +#define XDDR_XMPU1_CFG_R02_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU1_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Mstr + */ +#define XDDR_XMPU1_CFG_R02_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02 + */ +#define XDDR_XMPU1_CFG_R02 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU1_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Strt + */ +#define XDDR_XMPU1_CFG_R03_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03End + */ +#define XDDR_XMPU1_CFG_R03_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU1_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Mstr + */ +#define XDDR_XMPU1_CFG_R03_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03 + */ +#define XDDR_XMPU1_CFG_R03 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU1_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Strt + */ +#define XDDR_XMPU1_CFG_R04_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04End + */ +#define XDDR_XMPU1_CFG_R04_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU1_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Mstr + */ +#define XDDR_XMPU1_CFG_R04_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04 + */ +#define XDDR_XMPU1_CFG_R04 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU1_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Strt + */ +#define XDDR_XMPU1_CFG_R05_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05End + */ +#define XDDR_XMPU1_CFG_R05_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU1_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Mstr + */ +#define XDDR_XMPU1_CFG_R05_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05 + */ +#define XDDR_XMPU1_CFG_R05 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU1_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Strt + */ +#define XDDR_XMPU1_CFG_R06_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06End + */ +#define XDDR_XMPU1_CFG_R06_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU1_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Mstr + */ +#define XDDR_XMPU1_CFG_R06_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06 + */ +#define XDDR_XMPU1_CFG_R06 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU1_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Strt + */ +#define XDDR_XMPU1_CFG_R07_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07End + */ +#define XDDR_XMPU1_CFG_R07_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU1_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Mstr + */ +#define XDDR_XMPU1_CFG_R07_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07 + */ +#define XDDR_XMPU1_CFG_R07 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU1_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Strt + */ +#define XDDR_XMPU1_CFG_R08_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08End + */ +#define XDDR_XMPU1_CFG_R08_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU1_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Mstr + */ +#define XDDR_XMPU1_CFG_R08_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08 + */ +#define XDDR_XMPU1_CFG_R08 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU1_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Strt + */ +#define XDDR_XMPU1_CFG_R09_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09End + */ +#define XDDR_XMPU1_CFG_R09_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU1_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Mstr + */ +#define XDDR_XMPU1_CFG_R09_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09 + */ +#define XDDR_XMPU1_CFG_R09 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU1_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Strt + */ +#define XDDR_XMPU1_CFG_R10_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10End + */ +#define XDDR_XMPU1_CFG_R10_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU1_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Mstr + */ +#define XDDR_XMPU1_CFG_R10_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10 + */ +#define XDDR_XMPU1_CFG_R10 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU1_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Strt + */ +#define XDDR_XMPU1_CFG_R11_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11End + */ +#define XDDR_XMPU1_CFG_R11_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU1_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Mstr + */ +#define XDDR_XMPU1_CFG_R11_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11 + */ +#define XDDR_XMPU1_CFG_R11 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU1_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Strt + */ +#define XDDR_XMPU1_CFG_R12_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12End + */ +#define XDDR_XMPU1_CFG_R12_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU1_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Mstr + */ +#define XDDR_XMPU1_CFG_R12_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12 + */ +#define XDDR_XMPU1_CFG_R12 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU1_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Strt + */ +#define XDDR_XMPU1_CFG_R13_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13End + */ +#define XDDR_XMPU1_CFG_R13_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU1_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Mstr + */ +#define XDDR_XMPU1_CFG_R13_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13 + */ +#define XDDR_XMPU1_CFG_R13 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU1_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Strt + */ +#define XDDR_XMPU1_CFG_R14_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14End + */ +#define XDDR_XMPU1_CFG_R14_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU1_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Mstr + */ +#define XDDR_XMPU1_CFG_R14_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14 + */ +#define XDDR_XMPU1_CFG_R14 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU1_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Strt + */ +#define XDDR_XMPU1_CFG_R15_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15End + */ +#define XDDR_XMPU1_CFG_R15_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU1_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Mstr + */ +#define XDDR_XMPU1_CFG_R15_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15 + */ +#define XDDR_XMPU1_CFG_R15 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU1_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU1_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu2_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu2_cfg.h new file mode 100644 index 00000000..55ea2a7d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu2_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU2_CFG_H__ +#define __XDDR_XMPU2_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu2Cfg Base Address + */ +#define XDDR_XMPU2_CFG_BASEADDR 0xFD020000UL + +/** + * Register: XddrXmpu2CfgCtrl + */ +#define XDDR_XMPU2_CFG_CTRL ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU2_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgErrSts1 + */ +#define XDDR_XMPU2_CFG_ERR_STS1 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgErrSts2 + */ +#define XDDR_XMPU2_CFG_ERR_STS2 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgPoison + */ +#define XDDR_XMPU2_CFG_POISON ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU2_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU2_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIsr + */ +#define XDDR_XMPU2_CFG_ISR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU2_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgImr + */ +#define XDDR_XMPU2_CFG_IMR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU2_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgIen + */ +#define XDDR_XMPU2_CFG_IEN ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU2_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIds + */ +#define XDDR_XMPU2_CFG_IDS ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU2_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgLock + */ +#define XDDR_XMPU2_CFG_LOCK ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU2_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Strt + */ +#define XDDR_XMPU2_CFG_R00_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00End + */ +#define XDDR_XMPU2_CFG_R00_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU2_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Mstr + */ +#define XDDR_XMPU2_CFG_R00_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00 + */ +#define XDDR_XMPU2_CFG_R00 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU2_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Strt + */ +#define XDDR_XMPU2_CFG_R01_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01End + */ +#define XDDR_XMPU2_CFG_R01_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU2_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Mstr + */ +#define XDDR_XMPU2_CFG_R01_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01 + */ +#define XDDR_XMPU2_CFG_R01 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU2_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Strt + */ +#define XDDR_XMPU2_CFG_R02_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02End + */ +#define XDDR_XMPU2_CFG_R02_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU2_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Mstr + */ +#define XDDR_XMPU2_CFG_R02_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02 + */ +#define XDDR_XMPU2_CFG_R02 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU2_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Strt + */ +#define XDDR_XMPU2_CFG_R03_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03End + */ +#define XDDR_XMPU2_CFG_R03_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU2_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Mstr + */ +#define XDDR_XMPU2_CFG_R03_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03 + */ +#define XDDR_XMPU2_CFG_R03 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU2_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Strt + */ +#define XDDR_XMPU2_CFG_R04_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04End + */ +#define XDDR_XMPU2_CFG_R04_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU2_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Mstr + */ +#define XDDR_XMPU2_CFG_R04_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04 + */ +#define XDDR_XMPU2_CFG_R04 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU2_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Strt + */ +#define XDDR_XMPU2_CFG_R05_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05End + */ +#define XDDR_XMPU2_CFG_R05_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU2_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Mstr + */ +#define XDDR_XMPU2_CFG_R05_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05 + */ +#define XDDR_XMPU2_CFG_R05 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU2_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Strt + */ +#define XDDR_XMPU2_CFG_R06_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06End + */ +#define XDDR_XMPU2_CFG_R06_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU2_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Mstr + */ +#define XDDR_XMPU2_CFG_R06_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06 + */ +#define XDDR_XMPU2_CFG_R06 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU2_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Strt + */ +#define XDDR_XMPU2_CFG_R07_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07End + */ +#define XDDR_XMPU2_CFG_R07_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU2_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Mstr + */ +#define XDDR_XMPU2_CFG_R07_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07 + */ +#define XDDR_XMPU2_CFG_R07 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU2_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Strt + */ +#define XDDR_XMPU2_CFG_R08_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08End + */ +#define XDDR_XMPU2_CFG_R08_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU2_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Mstr + */ +#define XDDR_XMPU2_CFG_R08_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08 + */ +#define XDDR_XMPU2_CFG_R08 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU2_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Strt + */ +#define XDDR_XMPU2_CFG_R09_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09End + */ +#define XDDR_XMPU2_CFG_R09_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU2_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Mstr + */ +#define XDDR_XMPU2_CFG_R09_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09 + */ +#define XDDR_XMPU2_CFG_R09 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU2_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Strt + */ +#define XDDR_XMPU2_CFG_R10_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10End + */ +#define XDDR_XMPU2_CFG_R10_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU2_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Mstr + */ +#define XDDR_XMPU2_CFG_R10_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10 + */ +#define XDDR_XMPU2_CFG_R10 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU2_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Strt + */ +#define XDDR_XMPU2_CFG_R11_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11End + */ +#define XDDR_XMPU2_CFG_R11_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU2_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Mstr + */ +#define XDDR_XMPU2_CFG_R11_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11 + */ +#define XDDR_XMPU2_CFG_R11 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU2_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Strt + */ +#define XDDR_XMPU2_CFG_R12_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12End + */ +#define XDDR_XMPU2_CFG_R12_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU2_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Mstr + */ +#define XDDR_XMPU2_CFG_R12_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12 + */ +#define XDDR_XMPU2_CFG_R12 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU2_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Strt + */ +#define XDDR_XMPU2_CFG_R13_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13End + */ +#define XDDR_XMPU2_CFG_R13_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU2_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Mstr + */ +#define XDDR_XMPU2_CFG_R13_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13 + */ +#define XDDR_XMPU2_CFG_R13 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU2_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Strt + */ +#define XDDR_XMPU2_CFG_R14_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14End + */ +#define XDDR_XMPU2_CFG_R14_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU2_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Mstr + */ +#define XDDR_XMPU2_CFG_R14_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14 + */ +#define XDDR_XMPU2_CFG_R14 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU2_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Strt + */ +#define XDDR_XMPU2_CFG_R15_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15End + */ +#define XDDR_XMPU2_CFG_R15_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU2_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Mstr + */ +#define XDDR_XMPU2_CFG_R15_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15 + */ +#define XDDR_XMPU2_CFG_R15 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU2_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU2_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu3_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu3_cfg.h new file mode 100644 index 00000000..41631496 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu3_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU3_CFG_H__ +#define __XDDR_XMPU3_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu3Cfg Base Address + */ +#define XDDR_XMPU3_CFG_BASEADDR 0xFD030000UL + +/** + * Register: XddrXmpu3CfgCtrl + */ +#define XDDR_XMPU3_CFG_CTRL ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU3_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgErrSts1 + */ +#define XDDR_XMPU3_CFG_ERR_STS1 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgErrSts2 + */ +#define XDDR_XMPU3_CFG_ERR_STS2 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgPoison + */ +#define XDDR_XMPU3_CFG_POISON ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU3_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU3_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIsr + */ +#define XDDR_XMPU3_CFG_ISR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU3_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgImr + */ +#define XDDR_XMPU3_CFG_IMR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU3_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgIen + */ +#define XDDR_XMPU3_CFG_IEN ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU3_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIds + */ +#define XDDR_XMPU3_CFG_IDS ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU3_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgLock + */ +#define XDDR_XMPU3_CFG_LOCK ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU3_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Strt + */ +#define XDDR_XMPU3_CFG_R00_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00End + */ +#define XDDR_XMPU3_CFG_R00_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU3_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Mstr + */ +#define XDDR_XMPU3_CFG_R00_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00 + */ +#define XDDR_XMPU3_CFG_R00 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU3_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Strt + */ +#define XDDR_XMPU3_CFG_R01_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01End + */ +#define XDDR_XMPU3_CFG_R01_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU3_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Mstr + */ +#define XDDR_XMPU3_CFG_R01_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01 + */ +#define XDDR_XMPU3_CFG_R01 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU3_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Strt + */ +#define XDDR_XMPU3_CFG_R02_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02End + */ +#define XDDR_XMPU3_CFG_R02_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU3_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Mstr + */ +#define XDDR_XMPU3_CFG_R02_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02 + */ +#define XDDR_XMPU3_CFG_R02 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU3_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Strt + */ +#define XDDR_XMPU3_CFG_R03_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03End + */ +#define XDDR_XMPU3_CFG_R03_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU3_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Mstr + */ +#define XDDR_XMPU3_CFG_R03_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03 + */ +#define XDDR_XMPU3_CFG_R03 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU3_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Strt + */ +#define XDDR_XMPU3_CFG_R04_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04End + */ +#define XDDR_XMPU3_CFG_R04_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU3_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Mstr + */ +#define XDDR_XMPU3_CFG_R04_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04 + */ +#define XDDR_XMPU3_CFG_R04 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU3_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Strt + */ +#define XDDR_XMPU3_CFG_R05_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05End + */ +#define XDDR_XMPU3_CFG_R05_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU3_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Mstr + */ +#define XDDR_XMPU3_CFG_R05_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05 + */ +#define XDDR_XMPU3_CFG_R05 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU3_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Strt + */ +#define XDDR_XMPU3_CFG_R06_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06End + */ +#define XDDR_XMPU3_CFG_R06_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU3_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Mstr + */ +#define XDDR_XMPU3_CFG_R06_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06 + */ +#define XDDR_XMPU3_CFG_R06 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU3_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Strt + */ +#define XDDR_XMPU3_CFG_R07_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07End + */ +#define XDDR_XMPU3_CFG_R07_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU3_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Mstr + */ +#define XDDR_XMPU3_CFG_R07_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07 + */ +#define XDDR_XMPU3_CFG_R07 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU3_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Strt + */ +#define XDDR_XMPU3_CFG_R08_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08End + */ +#define XDDR_XMPU3_CFG_R08_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU3_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Mstr + */ +#define XDDR_XMPU3_CFG_R08_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08 + */ +#define XDDR_XMPU3_CFG_R08 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU3_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Strt + */ +#define XDDR_XMPU3_CFG_R09_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09End + */ +#define XDDR_XMPU3_CFG_R09_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU3_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Mstr + */ +#define XDDR_XMPU3_CFG_R09_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09 + */ +#define XDDR_XMPU3_CFG_R09 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU3_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Strt + */ +#define XDDR_XMPU3_CFG_R10_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10End + */ +#define XDDR_XMPU3_CFG_R10_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU3_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Mstr + */ +#define XDDR_XMPU3_CFG_R10_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10 + */ +#define XDDR_XMPU3_CFG_R10 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU3_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Strt + */ +#define XDDR_XMPU3_CFG_R11_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11End + */ +#define XDDR_XMPU3_CFG_R11_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU3_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Mstr + */ +#define XDDR_XMPU3_CFG_R11_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11 + */ +#define XDDR_XMPU3_CFG_R11 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU3_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Strt + */ +#define XDDR_XMPU3_CFG_R12_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12End + */ +#define XDDR_XMPU3_CFG_R12_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU3_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Mstr + */ +#define XDDR_XMPU3_CFG_R12_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12 + */ +#define XDDR_XMPU3_CFG_R12 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU3_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Strt + */ +#define XDDR_XMPU3_CFG_R13_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13End + */ +#define XDDR_XMPU3_CFG_R13_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU3_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Mstr + */ +#define XDDR_XMPU3_CFG_R13_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13 + */ +#define XDDR_XMPU3_CFG_R13 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU3_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Strt + */ +#define XDDR_XMPU3_CFG_R14_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14End + */ +#define XDDR_XMPU3_CFG_R14_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU3_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Mstr + */ +#define XDDR_XMPU3_CFG_R14_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14 + */ +#define XDDR_XMPU3_CFG_R14 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU3_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Strt + */ +#define XDDR_XMPU3_CFG_R15_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15End + */ +#define XDDR_XMPU3_CFG_R15_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU3_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Mstr + */ +#define XDDR_XMPU3_CFG_R15_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15 + */ +#define XDDR_XMPU3_CFG_R15 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU3_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU3_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu4_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu4_cfg.h new file mode 100644 index 00000000..2df81441 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu4_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU4_CFG_H__ +#define __XDDR_XMPU4_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu4Cfg Base Address + */ +#define XDDR_XMPU4_CFG_BASEADDR 0xFD040000UL + +/** + * Register: XddrXmpu4CfgCtrl + */ +#define XDDR_XMPU4_CFG_CTRL ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU4_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgErrSts1 + */ +#define XDDR_XMPU4_CFG_ERR_STS1 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgErrSts2 + */ +#define XDDR_XMPU4_CFG_ERR_STS2 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgPoison + */ +#define XDDR_XMPU4_CFG_POISON ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU4_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU4_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIsr + */ +#define XDDR_XMPU4_CFG_ISR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU4_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgImr + */ +#define XDDR_XMPU4_CFG_IMR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU4_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgIen + */ +#define XDDR_XMPU4_CFG_IEN ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU4_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIds + */ +#define XDDR_XMPU4_CFG_IDS ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU4_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgLock + */ +#define XDDR_XMPU4_CFG_LOCK ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU4_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Strt + */ +#define XDDR_XMPU4_CFG_R00_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00End + */ +#define XDDR_XMPU4_CFG_R00_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU4_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Mstr + */ +#define XDDR_XMPU4_CFG_R00_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00 + */ +#define XDDR_XMPU4_CFG_R00 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU4_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Strt + */ +#define XDDR_XMPU4_CFG_R01_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01End + */ +#define XDDR_XMPU4_CFG_R01_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU4_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Mstr + */ +#define XDDR_XMPU4_CFG_R01_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01 + */ +#define XDDR_XMPU4_CFG_R01 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU4_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Strt + */ +#define XDDR_XMPU4_CFG_R02_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02End + */ +#define XDDR_XMPU4_CFG_R02_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU4_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Mstr + */ +#define XDDR_XMPU4_CFG_R02_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02 + */ +#define XDDR_XMPU4_CFG_R02 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU4_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Strt + */ +#define XDDR_XMPU4_CFG_R03_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03End + */ +#define XDDR_XMPU4_CFG_R03_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU4_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Mstr + */ +#define XDDR_XMPU4_CFG_R03_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03 + */ +#define XDDR_XMPU4_CFG_R03 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU4_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Strt + */ +#define XDDR_XMPU4_CFG_R04_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04End + */ +#define XDDR_XMPU4_CFG_R04_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU4_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Mstr + */ +#define XDDR_XMPU4_CFG_R04_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04 + */ +#define XDDR_XMPU4_CFG_R04 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU4_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Strt + */ +#define XDDR_XMPU4_CFG_R05_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05End + */ +#define XDDR_XMPU4_CFG_R05_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU4_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Mstr + */ +#define XDDR_XMPU4_CFG_R05_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05 + */ +#define XDDR_XMPU4_CFG_R05 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU4_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Strt + */ +#define XDDR_XMPU4_CFG_R06_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06End + */ +#define XDDR_XMPU4_CFG_R06_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU4_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Mstr + */ +#define XDDR_XMPU4_CFG_R06_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06 + */ +#define XDDR_XMPU4_CFG_R06 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU4_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Strt + */ +#define XDDR_XMPU4_CFG_R07_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07End + */ +#define XDDR_XMPU4_CFG_R07_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU4_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Mstr + */ +#define XDDR_XMPU4_CFG_R07_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07 + */ +#define XDDR_XMPU4_CFG_R07 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU4_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Strt + */ +#define XDDR_XMPU4_CFG_R08_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08End + */ +#define XDDR_XMPU4_CFG_R08_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU4_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Mstr + */ +#define XDDR_XMPU4_CFG_R08_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08 + */ +#define XDDR_XMPU4_CFG_R08 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU4_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Strt + */ +#define XDDR_XMPU4_CFG_R09_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09End + */ +#define XDDR_XMPU4_CFG_R09_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU4_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Mstr + */ +#define XDDR_XMPU4_CFG_R09_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09 + */ +#define XDDR_XMPU4_CFG_R09 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU4_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Strt + */ +#define XDDR_XMPU4_CFG_R10_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10End + */ +#define XDDR_XMPU4_CFG_R10_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU4_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Mstr + */ +#define XDDR_XMPU4_CFG_R10_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10 + */ +#define XDDR_XMPU4_CFG_R10 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU4_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Strt + */ +#define XDDR_XMPU4_CFG_R11_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11End + */ +#define XDDR_XMPU4_CFG_R11_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU4_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Mstr + */ +#define XDDR_XMPU4_CFG_R11_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11 + */ +#define XDDR_XMPU4_CFG_R11 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU4_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Strt + */ +#define XDDR_XMPU4_CFG_R12_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12End + */ +#define XDDR_XMPU4_CFG_R12_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU4_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Mstr + */ +#define XDDR_XMPU4_CFG_R12_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12 + */ +#define XDDR_XMPU4_CFG_R12 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU4_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Strt + */ +#define XDDR_XMPU4_CFG_R13_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13End + */ +#define XDDR_XMPU4_CFG_R13_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU4_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Mstr + */ +#define XDDR_XMPU4_CFG_R13_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13 + */ +#define XDDR_XMPU4_CFG_R13 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU4_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Strt + */ +#define XDDR_XMPU4_CFG_R14_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14End + */ +#define XDDR_XMPU4_CFG_R14_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU4_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Mstr + */ +#define XDDR_XMPU4_CFG_R14_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14 + */ +#define XDDR_XMPU4_CFG_R14 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU4_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Strt + */ +#define XDDR_XMPU4_CFG_R15_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15End + */ +#define XDDR_XMPU4_CFG_R15_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU4_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Mstr + */ +#define XDDR_XMPU4_CFG_R15_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15 + */ +#define XDDR_XMPU4_CFG_R15 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU4_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU4_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xddr_xmpu5_cfg.h b/lib/bsp/standalone/src/cortexa53/xddr_xmpu5_cfg.h new file mode 100644 index 00000000..60811718 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xddr_xmpu5_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU5_CFG_H__ +#define __XDDR_XMPU5_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu5Cfg Base Address + */ +#define XDDR_XMPU5_CFG_BASEADDR 0xFD050000UL + +/** + * Register: XddrXmpu5CfgCtrl + */ +#define XDDR_XMPU5_CFG_CTRL ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU5_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgErrSts1 + */ +#define XDDR_XMPU5_CFG_ERR_STS1 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgErrSts2 + */ +#define XDDR_XMPU5_CFG_ERR_STS2 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgPoison + */ +#define XDDR_XMPU5_CFG_POISON ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU5_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU5_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIsr + */ +#define XDDR_XMPU5_CFG_ISR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU5_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgImr + */ +#define XDDR_XMPU5_CFG_IMR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU5_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgIen + */ +#define XDDR_XMPU5_CFG_IEN ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU5_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIds + */ +#define XDDR_XMPU5_CFG_IDS ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU5_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgLock + */ +#define XDDR_XMPU5_CFG_LOCK ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU5_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Strt + */ +#define XDDR_XMPU5_CFG_R00_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00End + */ +#define XDDR_XMPU5_CFG_R00_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU5_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Mstr + */ +#define XDDR_XMPU5_CFG_R00_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00 + */ +#define XDDR_XMPU5_CFG_R00 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU5_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Strt + */ +#define XDDR_XMPU5_CFG_R01_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01End + */ +#define XDDR_XMPU5_CFG_R01_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU5_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Mstr + */ +#define XDDR_XMPU5_CFG_R01_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01 + */ +#define XDDR_XMPU5_CFG_R01 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU5_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Strt + */ +#define XDDR_XMPU5_CFG_R02_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02End + */ +#define XDDR_XMPU5_CFG_R02_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU5_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Mstr + */ +#define XDDR_XMPU5_CFG_R02_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02 + */ +#define XDDR_XMPU5_CFG_R02 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU5_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Strt + */ +#define XDDR_XMPU5_CFG_R03_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03End + */ +#define XDDR_XMPU5_CFG_R03_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU5_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Mstr + */ +#define XDDR_XMPU5_CFG_R03_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03 + */ +#define XDDR_XMPU5_CFG_R03 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU5_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Strt + */ +#define XDDR_XMPU5_CFG_R04_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04End + */ +#define XDDR_XMPU5_CFG_R04_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU5_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Mstr + */ +#define XDDR_XMPU5_CFG_R04_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04 + */ +#define XDDR_XMPU5_CFG_R04 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU5_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Strt + */ +#define XDDR_XMPU5_CFG_R05_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05End + */ +#define XDDR_XMPU5_CFG_R05_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU5_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Mstr + */ +#define XDDR_XMPU5_CFG_R05_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05 + */ +#define XDDR_XMPU5_CFG_R05 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU5_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Strt + */ +#define XDDR_XMPU5_CFG_R06_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06End + */ +#define XDDR_XMPU5_CFG_R06_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU5_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Mstr + */ +#define XDDR_XMPU5_CFG_R06_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06 + */ +#define XDDR_XMPU5_CFG_R06 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU5_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Strt + */ +#define XDDR_XMPU5_CFG_R07_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07End + */ +#define XDDR_XMPU5_CFG_R07_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU5_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Mstr + */ +#define XDDR_XMPU5_CFG_R07_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07 + */ +#define XDDR_XMPU5_CFG_R07 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU5_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Strt + */ +#define XDDR_XMPU5_CFG_R08_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08End + */ +#define XDDR_XMPU5_CFG_R08_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU5_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Mstr + */ +#define XDDR_XMPU5_CFG_R08_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08 + */ +#define XDDR_XMPU5_CFG_R08 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU5_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Strt + */ +#define XDDR_XMPU5_CFG_R09_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09End + */ +#define XDDR_XMPU5_CFG_R09_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU5_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Mstr + */ +#define XDDR_XMPU5_CFG_R09_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09 + */ +#define XDDR_XMPU5_CFG_R09 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU5_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Strt + */ +#define XDDR_XMPU5_CFG_R10_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10End + */ +#define XDDR_XMPU5_CFG_R10_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU5_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Mstr + */ +#define XDDR_XMPU5_CFG_R10_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10 + */ +#define XDDR_XMPU5_CFG_R10 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU5_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Strt + */ +#define XDDR_XMPU5_CFG_R11_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11End + */ +#define XDDR_XMPU5_CFG_R11_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU5_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Mstr + */ +#define XDDR_XMPU5_CFG_R11_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11 + */ +#define XDDR_XMPU5_CFG_R11 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU5_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Strt + */ +#define XDDR_XMPU5_CFG_R12_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12End + */ +#define XDDR_XMPU5_CFG_R12_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU5_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Mstr + */ +#define XDDR_XMPU5_CFG_R12_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12 + */ +#define XDDR_XMPU5_CFG_R12 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU5_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Strt + */ +#define XDDR_XMPU5_CFG_R13_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13End + */ +#define XDDR_XMPU5_CFG_R13_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU5_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Mstr + */ +#define XDDR_XMPU5_CFG_R13_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13 + */ +#define XDDR_XMPU5_CFG_R13 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU5_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Strt + */ +#define XDDR_XMPU5_CFG_R14_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14End + */ +#define XDDR_XMPU5_CFG_R14_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU5_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Mstr + */ +#define XDDR_XMPU5_CFG_R14_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14 + */ +#define XDDR_XMPU5_CFG_R14 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU5_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Strt + */ +#define XDDR_XMPU5_CFG_R15_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15End + */ +#define XDDR_XMPU5_CFG_R15_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU5_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Mstr + */ +#define XDDR_XMPU5_CFG_R15_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15 + */ +#define XDDR_XMPU5_CFG_R15 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU5_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU5_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xfpd_slcr.h b/lib/bsp/standalone/src/cortexa53/xfpd_slcr.h new file mode 100644 index 00000000..b565b958 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xfpd_slcr.h @@ -0,0 +1,382 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_H__ +#define __XFPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcr Base Address + */ +#define XFPD_SLCR_BASEADDR 0xFD610000UL + +/** + * Register: XfpdSlcrWprot0 + */ +#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrCtrl + */ +#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIsr + */ +#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrImr + */ +#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrIer + */ +#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIdr + */ +#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrItr + */ +#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrWdtClkSel + */ +#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL ) +#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIntFpd + */ +#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL ) +#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL + +#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrGpu + */ +#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL ) +#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL + +#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL +#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL +#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL +#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL +#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL +#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL +#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL +#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL +#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL +#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrGdmaCfg + */ +#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL + +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL + +#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XfpdSlcrGdma + */ +#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL + +#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XfpdSlcrAfiFs + */ +#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL ) +#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL + +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL + +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL + +/** + * Register: XfpdSlcrErrAtbIsr + */ +#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbImr + */ +#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrErrAtbIer + */ +#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbIdr + */ +#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbCmdstore + */ +#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbRespEn + */ +#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbResptype + */ +#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbPrescale + */ +#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xfpd_slcr_secure.h b/lib/bsp/standalone/src/cortexa53/xfpd_slcr_secure.h new file mode 100644 index 00000000..6541a4f1 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xfpd_slcr_secure.h @@ -0,0 +1,277 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_SECURE_H__ +#define __XFPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcrSecure Base Address + */ +#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL + +/** + * Register: XfpdSlcrSecCtrl + */ +#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIsr + */ +#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecImr + */ +#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecIer + */ +#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIdr + */ +#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecItr + */ +#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecSata + */ +#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecPcie + */ +#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecDpdma + */ +#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL ) +#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL +#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL +#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecGdma + */ +#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL ) +#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL + +#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL +#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL +#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL + +/** + * Register: XfpdSlcrSecGic + */ +#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL ) +#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_cfg.h b/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_cfg.h new file mode 100644 index 00000000..75aef19f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_CFG_H__ +#define __XFPD_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuCfg Base Address + */ +#define XFPD_XMPU_CFG_BASEADDR 0xFD5D0000UL + +/** + * Register: XfpdXmpuCfgCtrl + */ +#define XFPD_XMPU_CFG_CTRL ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XFPD_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgErrSts1 + */ +#define XFPD_XMPU_CFG_ERR_STS1 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgErrSts2 + */ +#define XFPD_XMPU_CFG_ERR_STS2 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgPoison + */ +#define XFPD_XMPU_CFG_POISON ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XFPD_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XFPD_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XFPD_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIsr + */ +#define XFPD_XMPU_CFG_ISR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XFPD_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgImr + */ +#define XFPD_XMPU_CFG_IMR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XFPD_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgIen + */ +#define XFPD_XMPU_CFG_IEN ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XFPD_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIds + */ +#define XFPD_XMPU_CFG_IDS ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XFPD_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgLock + */ +#define XFPD_XMPU_CFG_LOCK ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XFPD_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Strt + */ +#define XFPD_XMPU_CFG_R00_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XFPD_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00End + */ +#define XFPD_XMPU_CFG_R00_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XFPD_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Mstr + */ +#define XFPD_XMPU_CFG_R00_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00 + */ +#define XFPD_XMPU_CFG_R00 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XFPD_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Strt + */ +#define XFPD_XMPU_CFG_R01_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XFPD_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01End + */ +#define XFPD_XMPU_CFG_R01_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XFPD_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Mstr + */ +#define XFPD_XMPU_CFG_R01_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01 + */ +#define XFPD_XMPU_CFG_R01 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XFPD_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Strt + */ +#define XFPD_XMPU_CFG_R02_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XFPD_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02End + */ +#define XFPD_XMPU_CFG_R02_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XFPD_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Mstr + */ +#define XFPD_XMPU_CFG_R02_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02 + */ +#define XFPD_XMPU_CFG_R02 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XFPD_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Strt + */ +#define XFPD_XMPU_CFG_R03_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XFPD_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03End + */ +#define XFPD_XMPU_CFG_R03_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XFPD_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Mstr + */ +#define XFPD_XMPU_CFG_R03_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03 + */ +#define XFPD_XMPU_CFG_R03 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XFPD_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Strt + */ +#define XFPD_XMPU_CFG_R04_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XFPD_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04End + */ +#define XFPD_XMPU_CFG_R04_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XFPD_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Mstr + */ +#define XFPD_XMPU_CFG_R04_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04 + */ +#define XFPD_XMPU_CFG_R04 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XFPD_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Strt + */ +#define XFPD_XMPU_CFG_R05_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XFPD_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05End + */ +#define XFPD_XMPU_CFG_R05_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XFPD_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Mstr + */ +#define XFPD_XMPU_CFG_R05_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05 + */ +#define XFPD_XMPU_CFG_R05 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XFPD_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Strt + */ +#define XFPD_XMPU_CFG_R06_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XFPD_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06End + */ +#define XFPD_XMPU_CFG_R06_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XFPD_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Mstr + */ +#define XFPD_XMPU_CFG_R06_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06 + */ +#define XFPD_XMPU_CFG_R06 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XFPD_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Strt + */ +#define XFPD_XMPU_CFG_R07_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XFPD_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07End + */ +#define XFPD_XMPU_CFG_R07_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XFPD_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Mstr + */ +#define XFPD_XMPU_CFG_R07_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07 + */ +#define XFPD_XMPU_CFG_R07 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XFPD_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Strt + */ +#define XFPD_XMPU_CFG_R08_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XFPD_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08End + */ +#define XFPD_XMPU_CFG_R08_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XFPD_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Mstr + */ +#define XFPD_XMPU_CFG_R08_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08 + */ +#define XFPD_XMPU_CFG_R08 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XFPD_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Strt + */ +#define XFPD_XMPU_CFG_R09_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XFPD_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09End + */ +#define XFPD_XMPU_CFG_R09_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XFPD_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Mstr + */ +#define XFPD_XMPU_CFG_R09_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09 + */ +#define XFPD_XMPU_CFG_R09 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XFPD_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Strt + */ +#define XFPD_XMPU_CFG_R10_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XFPD_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10End + */ +#define XFPD_XMPU_CFG_R10_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XFPD_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Mstr + */ +#define XFPD_XMPU_CFG_R10_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10 + */ +#define XFPD_XMPU_CFG_R10 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XFPD_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Strt + */ +#define XFPD_XMPU_CFG_R11_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XFPD_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11End + */ +#define XFPD_XMPU_CFG_R11_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XFPD_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Mstr + */ +#define XFPD_XMPU_CFG_R11_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11 + */ +#define XFPD_XMPU_CFG_R11 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XFPD_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Strt + */ +#define XFPD_XMPU_CFG_R12_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XFPD_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12End + */ +#define XFPD_XMPU_CFG_R12_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XFPD_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Mstr + */ +#define XFPD_XMPU_CFG_R12_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12 + */ +#define XFPD_XMPU_CFG_R12 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XFPD_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Strt + */ +#define XFPD_XMPU_CFG_R13_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XFPD_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13End + */ +#define XFPD_XMPU_CFG_R13_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XFPD_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Mstr + */ +#define XFPD_XMPU_CFG_R13_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13 + */ +#define XFPD_XMPU_CFG_R13 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XFPD_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Strt + */ +#define XFPD_XMPU_CFG_R14_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XFPD_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14End + */ +#define XFPD_XMPU_CFG_R14_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XFPD_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Mstr + */ +#define XFPD_XMPU_CFG_R14_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14 + */ +#define XFPD_XMPU_CFG_R14 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XFPD_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Strt + */ +#define XFPD_XMPU_CFG_R15_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XFPD_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15End + */ +#define XFPD_XMPU_CFG_R15_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XFPD_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Mstr + */ +#define XFPD_XMPU_CFG_R15_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15 + */ +#define XFPD_XMPU_CFG_R15 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XFPD_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_sink.h b/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_sink.h new file mode 100644 index 00000000..39172f1f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xfpd_xmpu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_SINK_H__ +#define __XFPD_XMPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuSink Base Address + */ +#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL + +/** + * Register: XfpdXmpuSinkErrSts + */ +#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIsr + */ +#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkImr + */ +#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuSinkIer + */ +#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIdr + */ +#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xil_cache.c b/lib/bsp/standalone/src/cortexa53/xil_cache.c new file mode 100644 index 00000000..d5450c2b --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_cache.c @@ -0,0 +1,648 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. Cache APIs are +* yet to be implemented. They are left blank to avoid any compilation error +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+*
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexa53.h" +#include "xil_exception.h" + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */ + +/**************************************************************************** +* +* Enable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_DCacheEnable(void) +{ + u32 CtrlReg; + CtrlReg = mfcp(SCTLR_EL3); + /* enable caches only if they are disabled */ + if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){ + + /* invalidate the Data cache */ + Xil_DCacheInvalidate(); + + CtrlReg |= XREG_CONTROL_DCACHE_BIT; + + /* enable the Data cache */ + mtcp(SCTLR_EL3,CtrlReg); + } +} + +/**************************************************************************** +* +* Disable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + u32 CtrlReg; + /* clean and invalidate the Data cache */ + Xil_DCacheFlush(); + CtrlReg = mfcp(SCTLR_EL3); + + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + /* disable the Data cache */ + mtcp(SCTLR_EL3,CtrlReg); +} + +/**************************************************************************** +* +* invalidate the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + register u32 CsidReg, C7Reg; + u32 LineSize, NumWays; + u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + /* Number of level of cache*/ + NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U; + + CacheLevel=0U; + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0X00000001U; + + /*Number of Set*/ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0X00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(ISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + + /* Wait for invalidate to complete */ + dsb(); + + /* Select cache level 1 and D cache in CSSR */ + CacheLevel += (0x00000001U<<1U) ; + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /* Number of Sets */ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(ISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + /* Wait for invalidate to complete */ + dsb(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are written to system memory before the line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 6 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(INTPTR adr) +{ + + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + mtcpdc(IVAC,(adr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + /* Select cache level 1 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + mtcpdc(IVAC,(adr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are written to system memory +* before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 64U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + end = tempadr + len; + tempend = end; + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempadr); + tempadr += cacheline; + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x0); + /* Invalidate Data cache line */ + mtcpdc(IVAC,(tempadr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,0x2); + /* Invalidate Data cache line */ + mtcpdc(IVAC,(tempadr & (~0x3F))); + /* Wait for invalidate to complete */ + dsb(); + tempadr += cacheline; + } + } + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 LineSize, NumWays; + u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, NumCacheLevel, CacheLevel,CacheLevelIndex; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + /* Number of level of cache*/ + NumCacheLevel = (mfcp(CLIDR_EL1)>>24U) & 0x00000007U; + + CacheLevel = 0U; + /* Select cache level 0 and D cache in CSSR */ + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /*Number of Set*/ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust = clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += (0x00000001U << WayAdjust); + } + + /* Wait for Flush to complete */ + dsb(); + + /* Select cache level 1 and D cache in CSSR */ + CacheLevel += (0x00000001U << 1U); + mtcp(CSSELR_EL1,CacheLevel); + isb(); + + CsidReg = mfcp(CCSIDR_EL1); + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + /* Number of Ways */ + NumWays = (CsidReg & 0x00001FFFU) >> 3U; + NumWays += 0x00000001U; + + /* Number of Sets */ + NumSet = (CsidReg >> 13U) & 0x00007FFFU; + NumSet += 0x00000001U; + + WayAdjust=clz(NumWays) - (u32)0x0000001FU; + + Way = 0U; + Set = 0U; + + /* Flush all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set | CacheLevel; + mtcpdc(CISW,C7Reg); + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += (0x00000001U< +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +*
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheFlushLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateLine(INTPTR adr); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa53/xil_exception.c b/lib/bsp/standalone/src/cortexa53/xil_exception.c new file mode 100644 index 00000000..e3fa6175 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_exception.c @@ -0,0 +1,214 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex A53 exception +* Handler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +static void Xil_ExceptionNullHandler(void *Data); + +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_SyncAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_SErrorAbortHandler, NULL}, + +}; +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void *)Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* +* The function is a common API used to initialize exception handlers across all +* processors supported. For ARM CortexA53, the exception handlers are being +* initialized statically and hence this function does not do anything. +* +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* +* Makes the connection between the Id of the exception source and the +* associated Handler that is to run when the exception is recognized. The +* argument provided in this call as the Data is used as the argument +* for the Handler when it is called. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. + See xil_exception_l.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* +* Removes the Handler for a specific exception Id. The stub Handler is then +* registered for this exception Id. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception_l.h for further information. + +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} +/*****************************************************************************/ +/** +* +* Default Synchronous abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_SyncAbortHandler(void *CallBackRef){ + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default SError abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_SErrorAbortHandler(void *CallBackRef){ + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexa53/xil_exception.h b/lib/bsp/standalone/src/cortexa53/xil_exception.h new file mode 100644 index 00000000..818d4430 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_exception.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ + +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ + +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); + +void Xil_SyncAbortHandler(void *CallBackRef); + +void Xil_SErrorAbortHandler(void *CallBackRef); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/lib/bsp/standalone/src/cortexa53/xil_io.c b/lib/bsp/standalone/src/cortexa53/xil_io.c new file mode 100644 index 00000000..e9dcdce3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_io.c @@ -0,0 +1,381 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. These functions encapsulate Cortex A53 architecture-specific +* I/O requirements. +* +* @note +* +* This file contains architecture-dependent code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa53.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Performs an input operation for an 8-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(INTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(INTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(INTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for an 8-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(INTPTR Addr, u8 Value) +{ + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(INTPTR Addr, u16 Value) +{ + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(INTPTR Addr, u32 Value) +{ + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 64-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out64(INTPTR Addr, u64 Value) +{ + u64 *LocalAddr = (u64 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 64-bit memory location by reading the +* specified Value to the the specified address. +* +* @param OutAddress contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +u64 Xil_In64(INTPTR Addr) +{ + return *(volatile u64 *) Addr; +} +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16BE(INTPTR Addr) +{ + u16 temp; + u16 result; + + temp = Xil_In16(Addr); + + result = Xil_EndianSwap16(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32BE(INTPTR Addr) +{ + u32 temp; + u32 result; + + temp = Xil_In32(Addr); + + result = Xil_EndianSwap32(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16BE(INTPTR Addr, u16 Value) +{ + u16 temp; + + temp = Xil_EndianSwap16(Value); + + Xil_Out16(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32BE(INTPTR Addr, u32 Value) +{ + u32 temp; + + temp = Xil_EndianSwap32(Value); + + Xil_Out32(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Perform a 16-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* Perform a 32-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +} diff --git a/lib/bsp/standalone/src/cortexa53/xil_io.h b/lib/bsp/standalone/src/cortexa53/xil_io.h new file mode 100644 index 00000000..1c89574b --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_io.h @@ -0,0 +1,240 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() + + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); +u64 Xil_In64(INTPTR Addr); + +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); +void Xil_Out64(INTPTR Addr, u64 Value); + + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/xil_mmu.c b/lib/bsp/standalone/src/cortexa53/xil_mmu.c new file mode 100644 index 00000000..ceae6edf --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_mmu.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* MMU APIs are yet to be implemented. They are left blank to avoid any +* compilation error +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mmu.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +extern INTPTR MMUTableL1; +extern INTPTR MMUTableL2; +/************************** Function Prototypes ******************************/ +/***************************************************************************** +* +* Set the memory attributes for a section, in the translation table. +* +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* +* @return None. +* +* @note The MMU and D-cache need not be disabled before changing an +* translation table attribute. +* +******************************************************************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib) +{ + INTPTR *ptr; + INTPTR section; + /* if region is less than 4GB MMUTable level 2 need to be modified */ + if(Addr<0x100000000){ + section = Addr / 0x00200000U; + ptr = &MMUTableL2 + section; + *ptr = (Addr & (~0x001FFFFFU)) | attrib; + } + /* if region is greater than 4GB MMUTable level 1 need to be modified */ + else{ + section = Addr / 0x40000000U; + ptr = &MMUTableL1 + section; + *ptr = (Addr & (~0x3FFFFFFFU)) | attrib; + } + + Xil_DCacheFlush(); + mtcptlbi(ALLE3); + + dsb(); /* ensure completion of the BP and TLB invalidation */ + isb(); /* synchronize context on this processor */ + +} diff --git a/lib/bsp/standalone/src/cortexa53/xil_mmu.h b/lib/bsp/standalone/src/cortexa53/xil_mmu.h new file mode 100644 index 00000000..d74b3d93 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_mmu.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ diff --git a/lib/bsp/standalone/src/cortexa53/xil_printf.c b/lib/bsp/standalone/src/cortexa53/xil_printf.c new file mode 100644 index 00000000..39e13e82 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_printf.c @@ -0,0 +1,329 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include +#include +#include + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; +} params_t; + +static void padding( const s32 l_flag,const params_t *par); +static void outs(const charptr lp, params_t *par); +static void outnum( const s32 n, const s32 base, params_t *par); +static s32 getnum( charptr* linep); + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const params_t *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { + outbyte( par->pad_character); + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, params_t *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; + outbyte(*LocalPtr); + LocalPtr += 1; +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, params_t *par) +{ + charptr cp; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = (n); + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); + i--; +} + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +void xil_printf( const char8 *ctrl1, ...) +{ + s32 Check; + s32 long_flag; + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { + outbyte(*ctrl); + ctrl += 1; + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; + long_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': + outbyte( '%'); + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + long_flag = 1; + Check = 0; + break; + + case 'd': + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + Check = 1; + break; + case 'x': + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': + outbyte( va_arg( argp, s32)); + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': + outbyte( ((char8)0x07)); + break; + case 'h': + outbyte( ((char8)0x08)); + break; + case 'r': + outbyte( ((char8)0x0D)); + break; + case 'n': + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); + break; + default: + outbyte( *ctrl); + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} + +/*---------------------------------------------------*/ diff --git a/lib/bsp/standalone/src/cortexa53/xil_printf.h b/lib/bsp/standalone/src/cortexa53/xil_printf.h new file mode 100644 index 00000000..2be5c573 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/xiou_secure_slcr.h b/lib/bsp/standalone/src/cortexa53/xiou_secure_slcr.h new file mode 100644 index 00000000..cb4ad490 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xiou_secure_slcr.h @@ -0,0 +1,174 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SECURE_SLCR_H__ +#define __XIOU_SECURE_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSecureSlcr Base Address + */ +#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL + +/** + * Register: XiouSecSlcrAxiWprtcn + */ +#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrAxiRprtcn + */ +#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrCtrl + */ +#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIsr + */ +#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrImr + */ +#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSecSlcrIer + */ +#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIdr + */ +#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrItr + */ +#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SECURE_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xiou_slcr.h b/lib/bsp/standalone/src/cortexa53/xiou_slcr.h new file mode 100644 index 00000000..d81d178d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xiou_slcr.h @@ -0,0 +1,4029 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SLCR_H__ +#define __XIOU_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSlcr Base Address + */ +#define XIOU_SLCR_BASEADDR 0xFF180000UL + +/** + * Register: XiouSlcrMioPin0 + */ +#define XIOU_SLCR_MIO_PIN_0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SLCR_MIO_PIN_0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin1 + */ +#define XIOU_SLCR_MIO_PIN_1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SLCR_MIO_PIN_1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin2 + */ +#define XIOU_SLCR_MIO_PIN_2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL ) +#define XIOU_SLCR_MIO_PIN_2_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin3 + */ +#define XIOU_SLCR_MIO_PIN_3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XIOU_SLCR_MIO_PIN_3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin4 + */ +#define XIOU_SLCR_MIO_PIN_4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL ) +#define XIOU_SLCR_MIO_PIN_4_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin5 + */ +#define XIOU_SLCR_MIO_PIN_5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL ) +#define XIOU_SLCR_MIO_PIN_5_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin6 + */ +#define XIOU_SLCR_MIO_PIN_6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL ) +#define XIOU_SLCR_MIO_PIN_6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin7 + */ +#define XIOU_SLCR_MIO_PIN_7 ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL ) +#define XIOU_SLCR_MIO_PIN_7_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin8 + */ +#define XIOU_SLCR_MIO_PIN_8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL ) +#define XIOU_SLCR_MIO_PIN_8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin9 + */ +#define XIOU_SLCR_MIO_PIN_9 ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL ) +#define XIOU_SLCR_MIO_PIN_9_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin10 + */ +#define XIOU_SLCR_MIO_PIN_10 ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL ) +#define XIOU_SLCR_MIO_PIN_10_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin11 + */ +#define XIOU_SLCR_MIO_PIN_11 ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL ) +#define XIOU_SLCR_MIO_PIN_11_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin12 + */ +#define XIOU_SLCR_MIO_PIN_12 ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL ) +#define XIOU_SLCR_MIO_PIN_12_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin13 + */ +#define XIOU_SLCR_MIO_PIN_13 ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL ) +#define XIOU_SLCR_MIO_PIN_13_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin14 + */ +#define XIOU_SLCR_MIO_PIN_14 ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL ) +#define XIOU_SLCR_MIO_PIN_14_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin15 + */ +#define XIOU_SLCR_MIO_PIN_15 ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL ) +#define XIOU_SLCR_MIO_PIN_15_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin16 + */ +#define XIOU_SLCR_MIO_PIN_16 ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SLCR_MIO_PIN_16_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin17 + */ +#define XIOU_SLCR_MIO_PIN_17 ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SLCR_MIO_PIN_17_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin18 + */ +#define XIOU_SLCR_MIO_PIN_18 ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SLCR_MIO_PIN_18_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin19 + */ +#define XIOU_SLCR_MIO_PIN_19 ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SLCR_MIO_PIN_19_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin20 + */ +#define XIOU_SLCR_MIO_PIN_20 ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SLCR_MIO_PIN_20_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin21 + */ +#define XIOU_SLCR_MIO_PIN_21 ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SLCR_MIO_PIN_21_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin22 + */ +#define XIOU_SLCR_MIO_PIN_22 ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL ) +#define XIOU_SLCR_MIO_PIN_22_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin23 + */ +#define XIOU_SLCR_MIO_PIN_23 ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL ) +#define XIOU_SLCR_MIO_PIN_23_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin24 + */ +#define XIOU_SLCR_MIO_PIN_24 ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL ) +#define XIOU_SLCR_MIO_PIN_24_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin25 + */ +#define XIOU_SLCR_MIO_PIN_25 ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL ) +#define XIOU_SLCR_MIO_PIN_25_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin26 + */ +#define XIOU_SLCR_MIO_PIN_26 ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL ) +#define XIOU_SLCR_MIO_PIN_26_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin27 + */ +#define XIOU_SLCR_MIO_PIN_27 ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL ) +#define XIOU_SLCR_MIO_PIN_27_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin28 + */ +#define XIOU_SLCR_MIO_PIN_28 ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL ) +#define XIOU_SLCR_MIO_PIN_28_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin29 + */ +#define XIOU_SLCR_MIO_PIN_29 ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL ) +#define XIOU_SLCR_MIO_PIN_29_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin30 + */ +#define XIOU_SLCR_MIO_PIN_30 ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL ) +#define XIOU_SLCR_MIO_PIN_30_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin31 + */ +#define XIOU_SLCR_MIO_PIN_31 ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL ) +#define XIOU_SLCR_MIO_PIN_31_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin32 + */ +#define XIOU_SLCR_MIO_PIN_32 ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL ) +#define XIOU_SLCR_MIO_PIN_32_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin33 + */ +#define XIOU_SLCR_MIO_PIN_33 ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL ) +#define XIOU_SLCR_MIO_PIN_33_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin34 + */ +#define XIOU_SLCR_MIO_PIN_34 ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL ) +#define XIOU_SLCR_MIO_PIN_34_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin35 + */ +#define XIOU_SLCR_MIO_PIN_35 ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL ) +#define XIOU_SLCR_MIO_PIN_35_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin36 + */ +#define XIOU_SLCR_MIO_PIN_36 ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL ) +#define XIOU_SLCR_MIO_PIN_36_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin37 + */ +#define XIOU_SLCR_MIO_PIN_37 ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL ) +#define XIOU_SLCR_MIO_PIN_37_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin38 + */ +#define XIOU_SLCR_MIO_PIN_38 ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL ) +#define XIOU_SLCR_MIO_PIN_38_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin39 + */ +#define XIOU_SLCR_MIO_PIN_39 ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL ) +#define XIOU_SLCR_MIO_PIN_39_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin40 + */ +#define XIOU_SLCR_MIO_PIN_40 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL ) +#define XIOU_SLCR_MIO_PIN_40_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin41 + */ +#define XIOU_SLCR_MIO_PIN_41 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL ) +#define XIOU_SLCR_MIO_PIN_41_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin42 + */ +#define XIOU_SLCR_MIO_PIN_42 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL ) +#define XIOU_SLCR_MIO_PIN_42_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin43 + */ +#define XIOU_SLCR_MIO_PIN_43 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL ) +#define XIOU_SLCR_MIO_PIN_43_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin44 + */ +#define XIOU_SLCR_MIO_PIN_44 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL ) +#define XIOU_SLCR_MIO_PIN_44_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin45 + */ +#define XIOU_SLCR_MIO_PIN_45 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL ) +#define XIOU_SLCR_MIO_PIN_45_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin46 + */ +#define XIOU_SLCR_MIO_PIN_46 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL ) +#define XIOU_SLCR_MIO_PIN_46_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin47 + */ +#define XIOU_SLCR_MIO_PIN_47 ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL ) +#define XIOU_SLCR_MIO_PIN_47_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin48 + */ +#define XIOU_SLCR_MIO_PIN_48 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL ) +#define XIOU_SLCR_MIO_PIN_48_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin49 + */ +#define XIOU_SLCR_MIO_PIN_49 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL ) +#define XIOU_SLCR_MIO_PIN_49_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin50 + */ +#define XIOU_SLCR_MIO_PIN_50 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL ) +#define XIOU_SLCR_MIO_PIN_50_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin51 + */ +#define XIOU_SLCR_MIO_PIN_51 ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL ) +#define XIOU_SLCR_MIO_PIN_51_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin52 + */ +#define XIOU_SLCR_MIO_PIN_52 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL ) +#define XIOU_SLCR_MIO_PIN_52_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin53 + */ +#define XIOU_SLCR_MIO_PIN_53 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL ) +#define XIOU_SLCR_MIO_PIN_53_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin54 + */ +#define XIOU_SLCR_MIO_PIN_54 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL ) +#define XIOU_SLCR_MIO_PIN_54_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin55 + */ +#define XIOU_SLCR_MIO_PIN_55 ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL ) +#define XIOU_SLCR_MIO_PIN_55_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin56 + */ +#define XIOU_SLCR_MIO_PIN_56 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL ) +#define XIOU_SLCR_MIO_PIN_56_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin57 + */ +#define XIOU_SLCR_MIO_PIN_57 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL ) +#define XIOU_SLCR_MIO_PIN_57_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin58 + */ +#define XIOU_SLCR_MIO_PIN_58 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL ) +#define XIOU_SLCR_MIO_PIN_58_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin59 + */ +#define XIOU_SLCR_MIO_PIN_59 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL ) +#define XIOU_SLCR_MIO_PIN_59_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin60 + */ +#define XIOU_SLCR_MIO_PIN_60 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL ) +#define XIOU_SLCR_MIO_PIN_60_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin61 + */ +#define XIOU_SLCR_MIO_PIN_61 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL ) +#define XIOU_SLCR_MIO_PIN_61_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin62 + */ +#define XIOU_SLCR_MIO_PIN_62 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL ) +#define XIOU_SLCR_MIO_PIN_62_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin63 + */ +#define XIOU_SLCR_MIO_PIN_63 ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL ) +#define XIOU_SLCR_MIO_PIN_63_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin64 + */ +#define XIOU_SLCR_MIO_PIN_64 ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL ) +#define XIOU_SLCR_MIO_PIN_64_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin65 + */ +#define XIOU_SLCR_MIO_PIN_65 ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL ) +#define XIOU_SLCR_MIO_PIN_65_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin66 + */ +#define XIOU_SLCR_MIO_PIN_66 ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL ) +#define XIOU_SLCR_MIO_PIN_66_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin67 + */ +#define XIOU_SLCR_MIO_PIN_67 ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL ) +#define XIOU_SLCR_MIO_PIN_67_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin68 + */ +#define XIOU_SLCR_MIO_PIN_68 ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL ) +#define XIOU_SLCR_MIO_PIN_68_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin69 + */ +#define XIOU_SLCR_MIO_PIN_69 ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL ) +#define XIOU_SLCR_MIO_PIN_69_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin70 + */ +#define XIOU_SLCR_MIO_PIN_70 ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL ) +#define XIOU_SLCR_MIO_PIN_70_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin71 + */ +#define XIOU_SLCR_MIO_PIN_71 ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL ) +#define XIOU_SLCR_MIO_PIN_71_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin72 + */ +#define XIOU_SLCR_MIO_PIN_72 ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL ) +#define XIOU_SLCR_MIO_PIN_72_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin73 + */ +#define XIOU_SLCR_MIO_PIN_73 ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL ) +#define XIOU_SLCR_MIO_PIN_73_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin74 + */ +#define XIOU_SLCR_MIO_PIN_74 ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL ) +#define XIOU_SLCR_MIO_PIN_74_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin75 + */ +#define XIOU_SLCR_MIO_PIN_75 ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL ) +#define XIOU_SLCR_MIO_PIN_75_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin76 + */ +#define XIOU_SLCR_MIO_PIN_76 ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL ) +#define XIOU_SLCR_MIO_PIN_76_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin77 + */ +#define XIOU_SLCR_MIO_PIN_77 ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL ) +#define XIOU_SLCR_MIO_PIN_77_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl0 + */ +#define XIOU_SLCR_BANK0_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL ) +#define XIOU_SLCR_BANK0_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl1 + */ +#define XIOU_SLCR_BANK0_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL ) +#define XIOU_SLCR_BANK0_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl3 + */ +#define XIOU_SLCR_BANK0_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL ) +#define XIOU_SLCR_BANK0_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl4 + */ +#define XIOU_SLCR_BANK0_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL ) +#define XIOU_SLCR_BANK0_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl5 + */ +#define XIOU_SLCR_BANK0_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL ) +#define XIOU_SLCR_BANK0_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl6 + */ +#define XIOU_SLCR_BANK0_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL ) +#define XIOU_SLCR_BANK0_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Sts + */ +#define XIOU_SLCR_BANK0_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL ) +#define XIOU_SLCR_BANK0_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl0 + */ +#define XIOU_SLCR_BANK1_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL ) +#define XIOU_SLCR_BANK1_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl1 + */ +#define XIOU_SLCR_BANK1_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL ) +#define XIOU_SLCR_BANK1_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl3 + */ +#define XIOU_SLCR_BANK1_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL ) +#define XIOU_SLCR_BANK1_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl4 + */ +#define XIOU_SLCR_BANK1_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL ) +#define XIOU_SLCR_BANK1_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl5 + */ +#define XIOU_SLCR_BANK1_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL ) +#define XIOU_SLCR_BANK1_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl6 + */ +#define XIOU_SLCR_BANK1_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL ) +#define XIOU_SLCR_BANK1_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Sts + */ +#define XIOU_SLCR_BANK1_STS ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL ) +#define XIOU_SLCR_BANK1_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl0 + */ +#define XIOU_SLCR_BANK2_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL ) +#define XIOU_SLCR_BANK2_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl1 + */ +#define XIOU_SLCR_BANK2_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL ) +#define XIOU_SLCR_BANK2_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl3 + */ +#define XIOU_SLCR_BANK2_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL ) +#define XIOU_SLCR_BANK2_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl4 + */ +#define XIOU_SLCR_BANK2_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL ) +#define XIOU_SLCR_BANK2_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl5 + */ +#define XIOU_SLCR_BANK2_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL ) +#define XIOU_SLCR_BANK2_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl6 + */ +#define XIOU_SLCR_BANK2_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL ) +#define XIOU_SLCR_BANK2_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Sts + */ +#define XIOU_SLCR_BANK2_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL ) +#define XIOU_SLCR_BANK2_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioLpbck + */ +#define XIOU_SLCR_MIO_LPBCK ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL ) +#define XIOU_SLCR_MIO_LPBCK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT 3UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK 0x00000008UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT 2UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK 0x00000004UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK 0x00000002UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT 0UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK 0x00000001UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioMstTri0 + */ +#define XIOU_SLCR_MIO_MST_TRI0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL ) +#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri1 + */ +#define XIOU_SLCR_MIO_MST_TRI1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL ) +#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri2 + */ +#define XIOU_SLCR_MIO_MST_TRI2 ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL ) +#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL 0x00003fffUL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrWdtClkSel + */ +#define XIOU_SLCR_WDT_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL ) +#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCanMioCtrl + */ +#define XIOU_SLCR_CAN_MIO_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL ) +#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT 23UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK 0x00800000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT 22UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK 0x00400000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT 15UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK 0x003f8000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT 8UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK 0x00000100UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK 0x00000080UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT 0UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK 0x0000007fUL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemClkCtrl + */ +#define XIOU_SLCR_GEM_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL ) +#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT 22UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK 0x00400000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT 20UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdioClkCtrl + */ +#define XIOU_SLCR_SDIO_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL ) +#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT 18UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK 0x00040000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK 0x00000004UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK 0x00000003UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCtrlRegSd + */ +#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL ) +#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 15UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 0UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdItapdly + */ +#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL ) +#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdOtapdlysel + */ +#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL ) +#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg1 + */ +#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL ) +#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg2 + */ +#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL ) +#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 25UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 24UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 9UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 8UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg3 + */ +#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL ) +#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdInitpreset + */ +#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL ) +#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +/** + * Register: XiouSlcrSdDsppreset + */ +#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL ) +#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdHspdpreset + */ +#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL ) +#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr12preset + */ +#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL ) +#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdSdr25preset + */ +#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL ) +#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr50prset + */ +#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL ) +#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdSdr104prst + */ +#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL ) +#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDdr50preset + */ +#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL ) +#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdMaxcur1p8 + */ +#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL ) +#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p0 + */ +#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL ) +#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p3 + */ +#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL ) +#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDllCtrl + */ +#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL ) +#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 18UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 2UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCdnCtrl + */ +#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL ) +#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00010000UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00000001UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemCtrl + */ +#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL ) +#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTtcApbClk + */ +#define XIOU_SLCR_TTC_APB_CLK ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL ) +#define XIOU_SLCR_TTC_APB_CLK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT 6UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK 0x000000c0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT 4UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000cUL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT 0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTapdlyBypass + */ +#define XIOU_SLCR_TAPDLY_BYPASS ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL ) +#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL 0x00000007UL + +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK 0x00000002UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT 0UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK 0x00000001UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL 0x1UL + +/** + * Register: XiouSlcrCoherentCtrl + */ +#define XIOU_SLCR_COHERENT_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL ) +#define XIOU_SLCR_COHERENT_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT 28UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK 0xf0000000UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT 24UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 20UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x00f00000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 16UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x000f0000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 12UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000f000UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 8UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x00000f00UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x000000f0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000000fUL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +/** + * Register: XiouSlcrVideoPssClkSel + */ +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL ) +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK 0x00000002UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL 0x0UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrInterconnectRoute + */ +#define XIOU_SLCR_INTERCONNECT_ROUTE ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL ) +#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL 0x00000000UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT 7UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK 0x00000080UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT 6UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 5UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000020UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 4UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000010UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 3UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000008UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 2UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000004UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000002UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 0UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000001UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan0 + */ +#define XIOU_SLCR_RAM_CAN0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL ) +#define XIOU_SLCR_RAM_CAN0_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan1 + */ +#define XIOU_SLCR_RAM_CAN1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL ) +#define XIOU_SLCR_RAM_CAN1_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamLqspi + */ +#define XIOU_SLCR_RAM_LQSPI ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL ) +#define XIOU_SLCR_RAM_LQSPI_RSTVAL 0x00002ddbUL + +#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT 13UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK 0x00002000UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT 10UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK 0x00001c00UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT 7UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK 0x00000380UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXnandps8 + */ +#define XIOU_SLCR_RAM_XNANDPS8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL ) +#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrCtrl + */ +#define XIOU_SLCR_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL ) +#define XIOU_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIsr + */ +#define XIOU_SLCR_ISR ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL ) +#define XIOU_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrImr + */ +#define XIOU_SLCR_IMR ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL ) +#define XIOU_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSlcrIer + */ +#define XIOU_SLCR_IER ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL ) +#define XIOU_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIdr + */ +#define XIOU_SLCR_IDR ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL ) +#define XIOU_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrItr + */ +#define XIOU_SLCR_ITR ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL ) +#define XIOU_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xlpd_slcr.h b/lib/bsp/standalone/src/cortexa53/xlpd_slcr.h new file mode 100644 index 00000000..cc05672e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xlpd_slcr.h @@ -0,0 +1,5667 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_H__ +#define __XLPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcr Base Address + */ +#define XLPD_SLCR_BASEADDR 0xFF410000UL + +/** + * Register: XlpdSlcrWprot0 + */ +#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XLPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCtrl + */ +#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsr + */ +#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrImr + */ +#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIer + */ +#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIdr + */ +#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrItr + */ +#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk0 + */ +#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL ) +#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk1 + */ +#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL ) +#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk2 + */ +#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL ) +#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk3 + */ +#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrXcsupmuWdtClkSel + */ +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL ) +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT 0UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH 1UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK 0x00000001UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAdmaCfg + */ +#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL ) +#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000028UL + +#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT 5UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH 2UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK 0x00000060UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XlpdSlcrAdmaRam + */ +#define XLPD_SLCR_ADMA_RAM ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL ) +#define XLPD_SLCR_ADMA_RAM_RSTVAL 0x00003b3bUL + +#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT 12UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK 0x00007000UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT 11UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK 0x00000800UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT 8UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK 0x00000700UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT 4UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK 0x00000070UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT 3UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK 0x00000008UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT 0UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK 0x00000007UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrErrAibaxiIsr + */ +#define XLPD_SLCR_ERR_AIBAXI_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiImr + */ +#define XLPD_SLCR_ERR_AIBAXI_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL ) +#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL 0x1dcf000fUL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibaxiIer + */ +#define XLPD_SLCR_ERR_AIBAXI_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiIdr + */ +#define XLPD_SLCR_ERR_AIBAXI_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL ) +#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIsr + */ +#define XLPD_SLCR_ERR_AIBAPB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL ) +#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbImr + */ +#define XLPD_SLCR_ERR_AIBAPB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL ) +#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibapbIer + */ +#define XLPD_SLCR_ERR_AIBAPB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL ) +#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIdr + */ +#define XLPD_SLCR_ERR_AIBAPB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL ) +#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiReq + */ +#define XLPD_SLCR_ISO_AIBAXI_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL ) +#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiType + */ +#define XLPD_SLCR_ISO_AIBAXI_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL ) +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL 0x19cf000fUL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibaxiAck + */ +#define XLPD_SLCR_ISO_AIBAXI_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL ) +#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbReq + */ +#define XLPD_SLCR_ISO_AIBAPB_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL ) +#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbType + */ +#define XLPD_SLCR_ISO_AIBAPB_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL ) +#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibapbAck + */ +#define XLPD_SLCR_ISO_AIBAPB_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL ) +#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIsr + */ +#define XLPD_SLCR_ERR_ATB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbImr + */ +#define XLPD_SLCR_ERR_ATB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAtbIer + */ +#define XLPD_SLCR_ERR_ATB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XLPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIdr + */ +#define XLPD_SLCR_ERR_ATB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbCmdStoreEn + */ +#define XLPD_SLCR_ATB_CMD_STORE_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbRespEn + */ +#define XLPD_SLCR_ATB_RESP_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XLPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbRespType + */ +#define XLPD_SLCR_ATB_RESP_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbPrescale + */ +#define XLPD_SLCR_ATB_PRESCALE ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XLPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XLPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + +/** + * Register: XlpdSlcrMutex0 + */ +#define XLPD_SLCR_MUTEX0 ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL ) +#define XLPD_SLCR_MUTEX0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX0_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX0_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX0_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX0_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex1 + */ +#define XLPD_SLCR_MUTEX1 ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL ) +#define XLPD_SLCR_MUTEX1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX1_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX1_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX1_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX1_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex2 + */ +#define XLPD_SLCR_MUTEX2 ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL ) +#define XLPD_SLCR_MUTEX2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX2_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX2_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX2_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX2_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex3 + */ +#define XLPD_SLCR_MUTEX3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL ) +#define XLPD_SLCR_MUTEX3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX3_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX3_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX3_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX3_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqSts + */ +#define XLPD_SLCR_GICP0_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL ) +#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqMsk + */ +#define XLPD_SLCR_GICP0_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL ) +#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp0IrqEn + */ +#define XLPD_SLCR_GICP0_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL ) +#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqDis + */ +#define XLPD_SLCR_GICP0_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL ) +#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqTrig + */ +#define XLPD_SLCR_GICP0_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL ) +#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqSts + */ +#define XLPD_SLCR_GICP1_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL ) +#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqMsk + */ +#define XLPD_SLCR_GICP1_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL ) +#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp1IrqEn + */ +#define XLPD_SLCR_GICP1_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL ) +#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqDis + */ +#define XLPD_SLCR_GICP1_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL ) +#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqTrig + */ +#define XLPD_SLCR_GICP1_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL ) +#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqSts + */ +#define XLPD_SLCR_GICP2_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL ) +#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqMsk + */ +#define XLPD_SLCR_GICP2_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL ) +#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp2IrqEn + */ +#define XLPD_SLCR_GICP2_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL ) +#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqDis + */ +#define XLPD_SLCR_GICP2_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL ) +#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqTrig + */ +#define XLPD_SLCR_GICP2_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL ) +#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqSts + */ +#define XLPD_SLCR_GICP3_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL ) +#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqMsk + */ +#define XLPD_SLCR_GICP3_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL ) +#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp3IrqEn + */ +#define XLPD_SLCR_GICP3_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL ) +#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqDis + */ +#define XLPD_SLCR_GICP3_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL ) +#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqTrig + */ +#define XLPD_SLCR_GICP3_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL ) +#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqSts + */ +#define XLPD_SLCR_GICP4_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL ) +#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqMsk + */ +#define XLPD_SLCR_GICP4_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL ) +#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp4IrqEn + */ +#define XLPD_SLCR_GICP4_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL ) +#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqDis + */ +#define XLPD_SLCR_GICP4_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL ) +#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqTrig + */ +#define XLPD_SLCR_GICP4_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL ) +#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqSts + */ +#define XLPD_SLCR_GICP_PMU_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqMsk + */ +#define XLPD_SLCR_GICP_PMU_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL 0x000000ffUL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicpPmuIrqEn + */ +#define XLPD_SLCR_GICP_PMU_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqDis + */ +#define XLPD_SLCR_GICP_PMU_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL ) +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqTrig + */ +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAfiFs + */ +#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL ) +#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL + +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL + +/** + * Register: XlpdSlcrCci + */ +#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL ) +#define XLPD_SLCR_CCI_RSTVAL 0x03801c07UL + +#define XLPD_SLCR_CCI_SPR_SHIFT 28UL +#define XLPD_SLCR_CCI_SPR_WIDTH 4UL +#define XLPD_SLCR_CCI_SPR_MASK 0xf0000000UL +#define XLPD_SLCR_CCI_SPR_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT 27UL +#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS4_MASK 0x08000000UL +#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT 26UL +#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS3_MASK 0x04000000UL +#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT 25UL +#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS2_MASK 0x02000000UL +#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT 24UL +#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS1_MASK 0x01000000UL +#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT 23UL +#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS0_MASK 0x00800000UL +#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT 18UL +#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH 5UL +#define XLPD_SLCR_CCI_QOS_OVRRD_MASK 0x007c0000UL +#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT 17UL +#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M2_MASK 0x00020000UL +#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M1_MASK 0x00010000UL +#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT 13UL +#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH 3UL +#define XLPD_SLCR_CCI_STRPG_GRAN_MASK 0x0000e000UL +#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT 12UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK 0x00001000UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT 11UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK 0x00000800UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT 10UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK 0x00000400UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT 6UL +#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH 4UL +#define XLPD_SLCR_CCI_ECOREVNUM_MASK 0x000003c0UL +#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA2_SHIFT 5UL +#define XLPD_SLCR_CCI_ASA2_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA2_MASK 0x00000020UL +#define XLPD_SLCR_CCI_ASA2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA1_SHIFT 4UL +#define XLPD_SLCR_CCI_ASA1_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA1_MASK 0x00000010UL +#define XLPD_SLCR_CCI_ASA1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA0_SHIFT 3UL +#define XLPD_SLCR_CCI_ASA0_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA0_MASK 0x00000008UL +#define XLPD_SLCR_CCI_ASA0_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_OWO2_SHIFT 2UL +#define XLPD_SLCR_CCI_OWO2_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO2_MASK 0x00000004UL +#define XLPD_SLCR_CCI_OWO2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO1_SHIFT 1UL +#define XLPD_SLCR_CCI_OWO1_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO1_MASK 0x00000002UL +#define XLPD_SLCR_CCI_OWO1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO0_SHIFT 0UL +#define XLPD_SLCR_CCI_OWO0_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO0_MASK 0x00000001UL +#define XLPD_SLCR_CCI_OWO0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCciAddrmap + */ +#define XLPD_SLCR_CCI_ADDRMAP ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL ) +#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL 0x00c000ffUL + +#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT 30UL +#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_15_MASK 0xc0000000UL +#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT 28UL +#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_14_MASK 0x30000000UL +#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT 26UL +#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_13_MASK 0x0c000000UL +#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT 24UL +#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_12_MASK 0x03000000UL +#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT 22UL +#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_11_MASK 0x00c00000UL +#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT 20UL +#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_10_MASK 0x00300000UL +#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT 18UL +#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_9_MASK 0x000c0000UL +#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT 16UL +#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_8_MASK 0x00030000UL +#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT 14UL +#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_7_MASK 0x0000c000UL +#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT 12UL +#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_6_MASK 0x00003000UL +#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT 10UL +#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_5_MASK 0x00000c00UL +#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT 8UL +#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_4_MASK 0x00000300UL +#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT 6UL +#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_3_MASK 0x000000c0UL +#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT 4UL +#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_2_MASK 0x00000030UL +#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_MASK 0x0000000cUL +#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT 0UL +#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_0_MASK 0x00000003UL +#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrCciQvnprealloc + */ +#define XLPD_SLCR_CCI_QVNPREALLOC ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL ) +#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL 0x00330330UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT 20UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK 0x00f00000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK 0x000f0000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT 8UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK 0x00000f00UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK 0x000000f0UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrSmmu + */ +#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL ) +#define XLPD_SLCR_SMMU_RSTVAL 0x0000003fUL + +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT 7UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH 1UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK 0x00000080UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_CTTW_SHIFT 6UL +#define XLPD_SLCR_SMMU_CTTW_WIDTH 1UL +#define XLPD_SLCR_SMMU_CTTW_MASK 0x00000040UL +#define XLPD_SLCR_SMMU_CTTW_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT 5UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK 0x00000020UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT 4UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK 0x00000010UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT 3UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK 0x00000008UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT 2UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK 0x00000004UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK 0x00000002UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT 0UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK 0x00000001UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrApu + */ +#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL ) +#define XLPD_SLCR_APU_RSTVAL 0x00000001UL + +#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL +#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL +#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL +#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL +#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL +#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL +#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL +#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL +#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xlpd_slcr_secure.h b/lib/bsp/standalone/src/cortexa53/xlpd_slcr_secure.h new file mode 100644 index 00000000..aff3bf2f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xlpd_slcr_secure.h @@ -0,0 +1,141 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_SECURE_H__ +#define __XLPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcrSecure Base Address + */ +#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL + +/** + * Register: XlpdSlcrSecCtrl + */ +#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIsr + */ +#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecImr + */ +#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrSecIer + */ +#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIdr + */ +#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecItr + */ +#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecRpu + */ +#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecAdma + */ +#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL ) +#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL +#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL +#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL +#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecSafetyChk + */ +#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecUsb + */ +#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL ) +#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xlpd_xppu.h b/lib/bsp/standalone/src/cortexa53/xlpd_xppu.h new file mode 100644 index 00000000..a5145eac --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xlpd_xppu.h @@ -0,0 +1,858 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_H__ +#define __XLPD_XPPU_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppu Base Address + */ +#define XLPD_XPPU_BASEADDR 0xFF980000UL + +/** + * Register: XlpdXppuCtrl + */ +#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL ) +#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL + +#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_EN_SHIFT 0UL +#define XLPD_XPPU_CTRL_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL +#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts1 + */ +#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL ) +#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts2 + */ +#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL ) +#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuPoison + */ +#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL ) +#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL + +#define XLPD_XPPU_POISON_BASE_SHIFT 0UL +#define XLPD_XPPU_POISON_BASE_WIDTH 20UL +#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL +#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIsr + */ +#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL ) +#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuImr + */ +#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL ) +#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL + +#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XlpdXppuIen + */ +#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL ) +#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIds + */ +#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL ) +#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMMstrIds + */ +#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL ) +#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL + +#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL +#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL +#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL + +/** + * Register: XlpdXppuMAperture32b + */ +#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL ) +#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL + +#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMAperture64kb + */ +#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL ) +#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL + +#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL + +/** + * Register: XlpdXppuMAperture1mb + */ +#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL ) +#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL + +#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMAperture512mb + */ +#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL ) +#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL + +#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL + +/** + * Register: XlpdXppuBase32b + */ +#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL ) +#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL + +#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL + +/** + * Register: XlpdXppuBase64kb + */ +#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL ) +#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL + +#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL + +/** + * Register: XlpdXppuBase1mb + */ +#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL ) +#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL + +#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL + +/** + * Register: XlpdXppuBase512mb + */ +#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL ) +#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL + +#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL + +/** + * Register: XlpdXppuMstrId00 + */ +#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL ) +#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL + +#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL + +#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL + +/** + * Register: XlpdXppuMstrId01 + */ +#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL ) +#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL + +#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId02 + */ +#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL ) +#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL + +#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMstrId03 + */ +#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL ) +#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL + +#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL + +#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId04 + */ +#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL ) +#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL + +#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId05 + */ +#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL ) +#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL + +#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL + +/** + * Register: XlpdXppuMstrId06 + */ +#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL ) +#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL + +#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL + +/** + * Register: XlpdXppuMstrId07 + */ +#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL ) +#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL + +#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL + +/** + * Register: XlpdXppuMstrId08 + */ +#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL ) +#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId09 + */ +#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL ) +#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId10 + */ +#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL ) +#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId11 + */ +#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL ) +#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId12 + */ +#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL ) +#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId13 + */ +#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL ) +#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId14 + */ +#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL ) +#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId15 + */ +#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL ) +#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId16 + */ +#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL ) +#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId17 + */ +#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL ) +#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId18 + */ +#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL ) +#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId19 + */ +#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL ) +#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xlpd_xppu_sink.h b/lib/bsp/standalone/src/cortexa53/xlpd_xppu_sink.h new file mode 100644 index 00000000..95f7e20a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xlpd_xppu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_SINK_H__ +#define __XLPD_XPPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppuSink Base Address + */ +#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL + +/** + * Register: XlpdXppuSinkErrSts + */ +#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIsr + */ +#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkImr + */ +#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XlpdXppuSinkIer + */ +#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIdr + */ +#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xocm_xmpu_cfg.h b/lib/bsp/standalone/src/cortexa53/xocm_xmpu_cfg.h new file mode 100644 index 00000000..5e3631f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xocm_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XOCM_XMPU_CFG_H__ +#define __XOCM_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XocmXmpuCfg Base Address + */ +#define XOCM_XMPU_CFG_BASEADDR 0xFFA70000UL + +/** + * Register: XocmXmpuCfgCtrl + */ +#define XOCM_XMPU_CFG_CTRL ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XOCM_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgErrSts1 + */ +#define XOCM_XMPU_CFG_ERR_STS1 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgErrSts2 + */ +#define XOCM_XMPU_CFG_ERR_STS2 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgPoison + */ +#define XOCM_XMPU_CFG_POISON ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XOCM_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XOCM_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XOCM_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIsr + */ +#define XOCM_XMPU_CFG_ISR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XOCM_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgImr + */ +#define XOCM_XMPU_CFG_IMR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XOCM_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgIen + */ +#define XOCM_XMPU_CFG_IEN ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XOCM_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIds + */ +#define XOCM_XMPU_CFG_IDS ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XOCM_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgLock + */ +#define XOCM_XMPU_CFG_LOCK ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XOCM_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Strt + */ +#define XOCM_XMPU_CFG_R00_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XOCM_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00End + */ +#define XOCM_XMPU_CFG_R00_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XOCM_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Mstr + */ +#define XOCM_XMPU_CFG_R00_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00 + */ +#define XOCM_XMPU_CFG_R00 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XOCM_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Strt + */ +#define XOCM_XMPU_CFG_R01_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XOCM_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01End + */ +#define XOCM_XMPU_CFG_R01_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XOCM_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Mstr + */ +#define XOCM_XMPU_CFG_R01_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01 + */ +#define XOCM_XMPU_CFG_R01 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XOCM_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Strt + */ +#define XOCM_XMPU_CFG_R02_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XOCM_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02End + */ +#define XOCM_XMPU_CFG_R02_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XOCM_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Mstr + */ +#define XOCM_XMPU_CFG_R02_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02 + */ +#define XOCM_XMPU_CFG_R02 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XOCM_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Strt + */ +#define XOCM_XMPU_CFG_R03_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XOCM_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03End + */ +#define XOCM_XMPU_CFG_R03_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XOCM_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Mstr + */ +#define XOCM_XMPU_CFG_R03_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03 + */ +#define XOCM_XMPU_CFG_R03 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XOCM_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Strt + */ +#define XOCM_XMPU_CFG_R04_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XOCM_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04End + */ +#define XOCM_XMPU_CFG_R04_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XOCM_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Mstr + */ +#define XOCM_XMPU_CFG_R04_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04 + */ +#define XOCM_XMPU_CFG_R04 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XOCM_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Strt + */ +#define XOCM_XMPU_CFG_R05_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XOCM_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05End + */ +#define XOCM_XMPU_CFG_R05_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XOCM_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Mstr + */ +#define XOCM_XMPU_CFG_R05_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05 + */ +#define XOCM_XMPU_CFG_R05 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XOCM_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Strt + */ +#define XOCM_XMPU_CFG_R06_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XOCM_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06End + */ +#define XOCM_XMPU_CFG_R06_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XOCM_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Mstr + */ +#define XOCM_XMPU_CFG_R06_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06 + */ +#define XOCM_XMPU_CFG_R06 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XOCM_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Strt + */ +#define XOCM_XMPU_CFG_R07_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XOCM_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07End + */ +#define XOCM_XMPU_CFG_R07_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XOCM_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Mstr + */ +#define XOCM_XMPU_CFG_R07_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07 + */ +#define XOCM_XMPU_CFG_R07 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XOCM_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Strt + */ +#define XOCM_XMPU_CFG_R08_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XOCM_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08End + */ +#define XOCM_XMPU_CFG_R08_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XOCM_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Mstr + */ +#define XOCM_XMPU_CFG_R08_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08 + */ +#define XOCM_XMPU_CFG_R08 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XOCM_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Strt + */ +#define XOCM_XMPU_CFG_R09_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XOCM_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09End + */ +#define XOCM_XMPU_CFG_R09_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XOCM_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Mstr + */ +#define XOCM_XMPU_CFG_R09_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09 + */ +#define XOCM_XMPU_CFG_R09 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XOCM_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Strt + */ +#define XOCM_XMPU_CFG_R10_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XOCM_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10End + */ +#define XOCM_XMPU_CFG_R10_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XOCM_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Mstr + */ +#define XOCM_XMPU_CFG_R10_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10 + */ +#define XOCM_XMPU_CFG_R10 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XOCM_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Strt + */ +#define XOCM_XMPU_CFG_R11_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XOCM_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11End + */ +#define XOCM_XMPU_CFG_R11_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XOCM_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Mstr + */ +#define XOCM_XMPU_CFG_R11_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11 + */ +#define XOCM_XMPU_CFG_R11 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XOCM_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Strt + */ +#define XOCM_XMPU_CFG_R12_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XOCM_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12End + */ +#define XOCM_XMPU_CFG_R12_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XOCM_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Mstr + */ +#define XOCM_XMPU_CFG_R12_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12 + */ +#define XOCM_XMPU_CFG_R12 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XOCM_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Strt + */ +#define XOCM_XMPU_CFG_R13_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XOCM_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13End + */ +#define XOCM_XMPU_CFG_R13_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XOCM_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Mstr + */ +#define XOCM_XMPU_CFG_R13_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13 + */ +#define XOCM_XMPU_CFG_R13 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XOCM_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Strt + */ +#define XOCM_XMPU_CFG_R14_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XOCM_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14End + */ +#define XOCM_XMPU_CFG_R14_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XOCM_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Mstr + */ +#define XOCM_XMPU_CFG_R14_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14 + */ +#define XOCM_XMPU_CFG_R14 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XOCM_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Strt + */ +#define XOCM_XMPU_CFG_R15_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XOCM_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15End + */ +#define XOCM_XMPU_CFG_R15_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XOCM_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Mstr + */ +#define XOCM_XMPU_CFG_R15_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15 + */ +#define XOCM_XMPU_CFG_R15 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XOCM_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XOCM_XMPU_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexa53/xparameters_ps.h b/lib/bsp/standalone/src/cortexa53/xparameters_ps.h new file mode 100644 index 00000000..d86e6fc5 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xparameters_ps.h @@ -0,0 +1,317 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A53 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID +#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID +#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID +#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID +#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for backwards compatibilty + */ + + +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U + + + +/* Shared Peripheral Interrupts (SPI) */ + +/* FIXME */ +/*#define XPS_FPGA0_INT_ID 100U */ +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Updated Interrupt-IDs */ +#define XPS_OCMINTR_INT_ID (10U + 32U) +#define XPS_NAND_INT_ID (14U + 32U) +#define XPS_QSPI_INT_ID (15U + 32U) +#define XPS_GPIO_INT_ID (16U + 32U) +#define XPS_I2C0_INT_ID (17U + 32U) +#define XPS_I2C1_INT_ID (18U + 32U) +#define XPS_SPI0_INT_ID (19U + 32U) +#define XPS_SPI1_INT_ID (20U + 32U) +#define XPS_UART0_INT_ID (21U + 32U) +#define XPS_UART1_INT_ID (22U + 32U) +#define XPS_CAN0_INT_ID (23U + 32U) +#define XPS_CAN1_INT_ID (24U + 32U) +#define XPS_WDT_INT_ID (52U + 32U) +#define XPS_TTC0_0_INT_ID (36U + 32U) +#define XPS_TTC0_1_INT_ID (37U + 32U) +#define XPS_TTC0_2_INT_ID (38U + 32U) +#define XPS_TTC1_0_INT_ID (39U + 32U) +#define XPS_TTC1_1_INT_ID (40U + 32U) +#define XPS_TTC1_2_INT_ID (41U + 32U) +#define XPS_TTC2_0_INT_ID (42U + 32U) +#define XPS_TTC2_1_INT_ID (43U + 32U) +#define XPS_TTC2_2_INT_ID (44U + 32U) +#define XPS_TTC3_0_INT_ID (45U + 32U) +#define XPS_TTC3_1_INT_ID (46U + 32U) +#define XPS_TTC3_2_INT_ID (47U + 32U) +#define XPS_SDIO0_INT_ID (48U + 32U) +#define XPS_SDIO1_INT_ID (49U + 32U) +#define XPS_GEM0_INT_ID (57U + 32U) +#define XPS_GEM0_WAKE_INT_ID (58U + 32U) +#define XPS_GEM1_INT_ID (59U + 32U) +#define XPS_GEM1_WAKE_INT_ID (60U + 32U) +#define XPS_GEM2_INT_ID (61U + 32U) +#define XPS_GEM2_WAKE_INT_ID (62U + 32U) +#define XPS_GEM3_INT_ID (63U + 32U) +#define XPS_GEM3_WAKE_INT_ID (64U + 32U) +#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) +#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) +#define XPS_ADMA_CH0_INT_ID (77U + 32U) +#define XPS_ADMA_CH1_INT_ID (78U + 32U) +#define XPS_ADMA_CH2_INT_ID (79U + 32U) +#define XPS_ADMA_CH3_INT_ID (80U + 32U) +#define XPS_ADMA_CH4_INT_ID (81U + 32U) +#define XPS_ADMA_CH5_INT_ID (82U + 32U) +#define XPS_ADMA_CH6_INT_ID (83U + 32U) +#define XPS_ADMA_CH7_INT_ID (84U + 32U) +#define XPS_CSU_DMA_INT_ID (86U + 32U) +#define XPS_XMPU_LPD_INT_ID (88U + 32U) +#define XPS_ZDMA_CH0_INT_ID (124U + 32U) +#define XPS_ZDMA_CH1_INT_ID (125U + 32U) +#define XPS_ZDMA_CH2_INT_ID (126U + 32U) +#define XPS_ZDMA_CH3_INT_ID (127U + 32U) +#define XPS_ZDMA_CH4_INT_ID (128U + 32U) +#define XPS_ZDMA_CH5_INT_ID (129U + 32U) +#define XPS_ZDMA_CH6_INT_ID (130U + 32U) +#define XPS_ZDMA_CH7_INT_ID (131U + 32U) +#define XPS_XMPU_FPD_INT_ID (134U + 32U) +#define XPS_FPD_CCI_INT_ID (154U + 32U) +#define XPS_FPD_SMMU_INT_ID (155U + 32U) + +/* Private Peripheral Interrupts (PPI) */ +/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */ +/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */ +/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */ +/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */ +/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */ + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID + +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h b/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h new file mode 100644 index 00000000..e5e02751 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xpseudo_asm.h @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H +#include "xreg_cortexa53.h" +#include "xpseudo_asm_gcc.h" + +#endif /* XPSEUDO_ASM_H */ diff --git a/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h b/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h new file mode 100644 index 00000000..dbc0134e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xreg_cortexa53.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa53.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +******************************************************************************/ +#ifndef XREG_CORTEXA53_H +#define XREG_CORTEXA53_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* GPRs */ +#define XREG_GPR0 x0 +#define XREG_GPR1 x1 +#define XREG_GPR2 x2 +#define XREG_GPR3 x3 +#define XREG_GPR4 x4 +#define XREG_GPR5 x5 +#define XREG_GPR6 x6 +#define XREG_GPR7 x7 +#define XREG_GPR8 x8 +#define XREG_GPR9 x9 +#define XREG_GPR10 x10 +#define XREG_GPR11 x11 +#define XREG_GPR12 x12 +#define XREG_GPR13 x13 +#define XREG_GPR14 x14 +#define XREG_GPR15 x15 +#define XREG_GPR16 x16 +#define XREG_GPR17 x17 +#define XREG_GPR18 x18 +#define XREG_GPR19 x19 +#define XREG_GPR20 x20 +#define XREG_GPR21 x21 +#define XREG_GPR22 x22 +#define XREG_GPR23 x23 +#define XREG_GPR24 x24 +#define XREG_GPR25 x25 +#define XREG_GPR26 x26 +#define XREG_GPR27 x27 +#define XREG_GPR28 x28 +#define XREG_GPR29 x29 +#define XREG_GPR30 x30 +#define XREG_CPSR cpsr + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_EL3h_MODE 0xD +#define XREG_CPSR_EL3t_MODE 0xC +#define XREG_CPSR_EL2h_MODE 0x9 +#define XREG_CPSR_EL2t_MODE 0x8 +#define XREG_CPSR_EL1h_MODE 0x5 +#define XREG_CPSR_EL1t_MODE 0x4 +#define XREG_CPSR_EL0t_MODE 0x0 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U<<23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U) +#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA53_H */ diff --git a/lib/bsp/standalone/src/cortexa53/xstatus.h b/lib/bsp/standalone/src/cortexa53/xstatus.h new file mode 100644 index 00000000..7db874c8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xstatus.h @@ -0,0 +1,430 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef int XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa53/xtime_l.c b/lib/bsp/standalone/src/cortexa53/xtime_l.c new file mode 100644 index 00000000..f0719da5 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xtime_l.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex A53 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp  05/29/14 First release
+* 
+* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Set the time in the Global Timer Counter Register. +* +* @param Value to be written to the Global Timer Counter Register. +* +* @return None. +* +* @note In multiprocessor environment reference time will reset/lost for +* all processors, when this function called by any one processor. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ +/*As the generic timer of A53 runs constantly time can not be set as desired +so the API is left unimplemented*/ +} + +/**************************************************************************** +* +* Get the time from the Global Timer Counter Register. +* +* @param Pointer to the location to be updated with the time. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + *Xtime_Global = mfcp(CNTPCT_EL0); +} diff --git a/lib/bsp/standalone/src/cortexa53/xtime_l.h b/lib/bsp/standalone/src/cortexa53/xtime_l.h new file mode 100644 index 00000000..fd75790a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa53/xtime_l.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND 0x007A1200U + +#define XIOU_SCNTRS_BASEADDR 0XFF260000U +#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U +#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U +#define XIOU_SCNTRS_FREQ 0x02FAF080U /* 50 MHz */ +#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0X00000001U + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c b/lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c new file mode 100644 index 00000000..183b4b56 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/ARM_argv_veneer.c @@ -0,0 +1 @@ +void __ARM_argv_veneer(void) {}; diff --git a/lib/bsp/standalone/src/cortexa9/armcc/Makefile b/lib/bsp/standalone/src/cortexa9/armcc/Makefile new file mode 100644 index 00000000..6646f17a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/Makefile @@ -0,0 +1,98 @@ +############################################################################### +# +# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +include config.make + +AS=armasm +COMPILER=armcc +ARCHIVER=armar +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= + +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +ECC_FLAGS += --cpu=Cortex-A9 --fpu=VFPv3_FP16 --vectorize + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include + +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h + +COBJS = $(addsuffix .o, $(basename $(wildcard *.c))) +AOBJS1 = asm_vectors.o +AOBJS2 = translation_table.o +OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) boot_post.o + +ASOURCES1 = asm_vectors.s +ASOURCES2 = translation_table.s + +# Replace boot.o with boot_post.o +OBJECTS = $(OBJS) + +libs: boot_libs banner $(LIBS) + +boot_libs: +ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S) + ${COMPILER} $(INCLUDES) -E -o boot_post.s boot.S +endif + ${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o boot_post.o boot_post.s + rm -f boot.S + +$(AOBJS1): $(ASOURCES1) + ${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o $@ $< + +$(AOBJS2): $(ASOURCES2) + ${AS} --cpu=Cortex-A9 --fpu=VFPv3 -o $@ $< + +%.o: %.c + ${COMPILER} -c $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling standalone" + +standalone_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: standalone_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c new file mode 100644 index 00000000..f78348c9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_close.c @@ -0,0 +1,6 @@ +#include "xil_types.h" +/* Stuv for close() sys-call */ +__weak s32 _sys_close(s32 fh) +{ + return -1; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c new file mode 100644 index 00000000..245e5d38 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_exit.c @@ -0,0 +1,8 @@ +#include "xil_types.h" +/* Stuv for exit() sys-call */ +__weak void _sys_exit(s32 rc) +{ + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c new file mode 100644 index 00000000..0bba57f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_iserror.c @@ -0,0 +1,10 @@ +#include "xil_types.h" +/* Stub for iserror() function */ +__weak s32 _sys_iserror(s32 status) +{ + if(status<0) { + return 1; + } + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c new file mode 100644 index 00000000..f41ad0a8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_istty.c @@ -0,0 +1,7 @@ +#include "xil_types.h" +/* Stub for istty sys-call */ +__weak s32 _sys_istty(u32* f) +{ + /* cannot read/write files */ + return 1; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c new file mode 100644 index 00000000..851798ac --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_open.c @@ -0,0 +1,6 @@ +#include "xil_types.h" +/* Stub for open sys-call */ +__weak s32 _sys_open(const char8* name, s32 openmode) +{ + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c new file mode 100644 index 00000000..6c36bb97 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_read.c @@ -0,0 +1,7 @@ +#include "xil_types.h" +/* Stub for read() sys-call */ +__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode) +{ + /* Return the number of character NOT read */ + return len; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c b/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c new file mode 100644 index 00000000..4297c0e9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/_sys_write.c @@ -0,0 +1,19 @@ +#include "xil_types.h" +#include "xparameters.h" + +__weak s32 _sys_write(u32 fh, const u8 *buf, u32 len, s32 mode) +{ +#ifdef STDOUT_BASEADDRESS + u32 volatile *uart_base = (u32 *)STDOUT_BASEADDRESS; + s32 i; + + for (i =0; i < len;i++) { + /* wait if TNFUL */ + while (*(uart_base + 11U) & (1U << 14U)) { + ; + } + *(uart_base + 12U) = buf[i]; + } +#endif + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s new file mode 100644 index 00000000..b600b125 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/asm_vectors.s @@ -0,0 +1,163 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file asm_vectors.s +; +; This file contains the initial vector table for the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver	Who     Date	  Changes
+; ----- ------- -------- ---------------------------------------------------
+; 1.00a ecm/sdm 10/20/09 Initial version
+; 3.11a asa	9/17/13	 Added support for neon.
+; 4.00  pkp	01/22/14 Modified return addresses for interrupt
+;			 handlers
+; 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+;			 abort and prefetch abort into DataAbortAddr and
+;			 PrefetchAbortAddr for further use to fix CR#854523
+;
+; +; @note +; +; None. +; +;**************************************************************************** + + EXPORT _vector_table + EXPORT IRQHandler + + IMPORT _boot + IMPORT _prestart + IMPORT IRQInterrupt + IMPORT FIQInterrupt + IMPORT SWInterrupt + IMPORT DataAbortInterrupt + IMPORT PrefetchAbortInterrupt + IMPORT DataAbortAddr + IMPORT PrefetchAbortAddr + + AREA |.vectors|, CODE + REQUIRE8 {TRUE} + PRESERVE8 {TRUE} + ENTRY ; define this as an entry point +_vector_table + B _boot + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP ; Placeholder for address exception vector + B IRQHandler + B FIQHandler + + +IRQHandler ; IRQ vector handler + + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} + bl IRQInterrupt ; IRQ vector + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + +FIQHandler ; FIQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +FIQLoop + bl FIQInterrupt ; FIQ vector + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + +Undefined ; Undefined handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + b _prestart + + movs pc, lr + + +SVCHandler ; SWI handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + tst r0, #0x20 ; check the T bit + ldrneh r0, [lr,#-2] ; Thumb mode + bicne r0, r0, #0xff00 ; Thumb mode + ldreq r0, [lr,#-4] ; ARM mode + biceq r0, r0, #0xff000000 ; ARM mode + bl SWInterrupt ; SWInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + movs pc, lr ; adjust return + +DataAbortHandler ; Data Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =DataAbortAddr + sub r1, lr,#8 + str r1, [r0] ;Address of instruction causing data abort + bl DataAbortInterrupt ;DataAbortInterrupt :call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #8 ; adjust return + +PrefetchAbortHandler ; Prefetch Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =PrefetchAbortAddr + sub r1, lr,#4 + str r1, [r0] ;Address of instruction causing prefetch abort + bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + END diff --git a/lib/bsp/standalone/src/cortexa9/armcc/boot.S b/lib/bsp/standalone/src/cortexa9/armcc/boot.S new file mode 100644 index 00000000..27c2fdc3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/boot.S @@ -0,0 +1,443 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file boot.S +; +; This file contains the initial startup code for the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver	Who	  Date	  Changes
+; ----- ------- -------- ---------------------------------------------------
+; 1.00a ecm/sdm 10/20/09 Initial version
+; 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+; 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+;			 register settings.
+; 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+;		         register settings.
+; 3.07a sgd 	07/05/12 Updated with reset and start Global Timer
+; 3.07a sgd 	10/19/12 SMC NOR and SRAM initialization with build option
+; 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+; 4.2	pkp  	08/04/14 Removed PEEP board related code which contained
+;			 initialization of uart smc nor and sram
+; 5.0	pkp	16/12/14 Modified initialization code to enable scu after
+;			 MMU is enabled and removed incorrect initialization
+;			 of TLB lockdown register to fix CR#830580
+; 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+;			 caches and TLB, enable MMU and caches, then enable SMP
+;			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+;			 is done later.
+; 
+; +; @note +; +; None. +; +;**************************************************************************** + + + +#include "xparameters.h" +#include "xil_errata.h" + +#define UART_BAUDRATE 115200 + + EXPORT _prestart + EXPORT _boot + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + IMPORT |Image$$IRQ_STACK$$ZI$$Limit| + IMPORT |Image$$SPV_STACK$$ZI$$Limit| + IMPORT |Image$$ABORT_STACK$$ZI$$Limit| + IMPORT MMUTable + IMPORT _vector_table + IMPORT __main + IMPORT Xil_ExceptionInit + IMPORT XTime_SetTime + +PSS_L2CC_BASE_ADDR EQU 0xF8F02000 +PSS_SLCR_BASE_ADDR EQU 0xF8000000 + +L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET) +L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET) +L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET) +L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET) +L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET) +L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET) +L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET) +L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET) + +SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ +SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ +SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ + +SLCRlockKey EQU 0x767B /* SLCR lock key */ +SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */ +SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */ + +CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU +CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000 + +L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable +L2CCControl EQU 0x01 ; Enable L2CC +L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM +L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM + +FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) + + AREA |.boot|, CODE + PRESERVE8 + + +; this initializes the various processor modes + +_prestart +_boot + +#if XPAR_CPU_ID==0 +; only allow cp0 through + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #0 + beq OKToRun +EndlessLoop0 + wfe + b EndlessLoop0 + +#elif XPAR_CPU_ID==1 +; only allow cp1 through + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #1 + beq OKToRun +EndlessLoop1 + wfe + b EndlessLoop1 +#endif + +OKToRun + mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ + and r5, r0, #0x00f00000 + and r6, r0, #0x0000000f + orr r6, r6, r5, lsr #20-4 + +#ifdef CONFIG_ARM_ERRATA_742230 + cmp r6, #0x22 /* only present up to r2p2 */ + mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */ + orrle r10, r10, #1 << 4 /* set bit #4 */ + mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */ +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + teq r5, #0x00200000 /* only present in r2p* */ + mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */ + orreq r10, r10, #1 << 6 /* set bit #6 */ + mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */ +#endif + + /* set VBAR to the _vector_table address in scatter file */ + ldr r0, =_vector_table + mcr p15, 0, r0, c12, c0, 0 + + ;invalidate scu + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] + + ;Invalidate caches and TLBs + mov r0,#0 ; r0 = 0 + mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 ; invalidate icache + mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array + bl invalidate_dcache ; invalidate dcache + + ; Disable MMU, if enabled + mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 + bic r0, r0, #0x1 ; clear bit 0 + mcr p15, 0, r0, c1, c0, 0 ; write value back + +#ifdef SHAREABLE_DDR + ; Mark the entire DDR memory as shareable + ldr r3, =0x3ff ; 1024 entries to cover 1G DDR + ldr r0, =TblBase ; MMU Table address in memory + ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 +shareable_loop: + str r2, [r0] ; write the entry to MMU table + add r0, r0, #0x4 ; next entry in the table + add r2, r2, #0x100000 ; next section + subs r3, r3, #1 + bge shareable_loop ; loop till 1G is covered +#endif + + ; In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable +#if USE_AMP==1 + ldr r3, =0x1ff ; 512 entries to cover 512MB DDR + ldr r0, =TblBase ; MMU Table address in memory + add r0, r0, #0x800 ; Address of entry in MMU table, for 0x20000000 + ldr r2, =0x0c02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 +mmu_loop: + str r2, [r0] ; write the entry to MMU table + add r0, r0, #0x4 ; next entry in the table + add r2, r2, #0x100000 ; next section + subs r3, r3, #1 + bge mmu_loop ; loop till 512MB is covered +#endif + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the irq stack pointer + and r2, r1, r0 + orr r2, r2, #0x12 ; IRQ mode + msr apsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the supervisor stack pointer + and r2, r1, r0 + orr r2, r2, #0x13 ; supervisor mode + msr apsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the Abort stack pointer + and r2, r1, r0 + orr r2, r2, #0x17 ; Abort mode + msr apsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the system stack pointer + and r2, r1, r0 + orr r2, r2, #0x1f ; SYS mode + msr apsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer + + ;set scu enable bit in scu + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + ; enable MMU and cache + + ldr r0,=MMUTable ; Load MMU translation table base + orr r0, r0, #0x5B ; Outer-cacheable, WB + mcr p15, 0, r0, c2, c0, 0 ; TTB0 + + mvn r0,#0 + mcr p15,0,r0,c3,c0,0 + + ; Enable mmu, icahce and dcache + ldr r0,=CRValMmuCac + + mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU + dsb ; dsb allow the MMU to start up + isb ; isb flush prefetch buffer + + ; Write to ACTLR + mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR + orr r0, r0, #(0x01 << 6) ; SMP bit + orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast + mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR + +; Invalidate L2 Cache and initialize L2 Cache +; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) +#if USE_AMP!=1 + ldr r0,=L2CCCrtl ; Load L2CC base address base + control register + mov r1, #0 ; force the disable bit + str r1, [r0] ; disable the L2 Caches + + ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register + ldr r1,[r0] ; read the register + ldr r2,=L2CCAuxControl ; set the default bits + orr r1,r1,r2 + str r1, [r0] ; store the Aux Control Register + + ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address + ldr r1,=L2CCTAGLatency ; set the latencies for the TAG + str r1, [r0] ; store the TAG Latency register Register + + ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address + ldr r1,=L2CCDataLatency ; set the latencies for the Data + str r1, [r0] ; store the Data Latency register Register + + ldr r0,=L2CCWay ; Load L2CC base address base + way register + ldr r2, =0xFFFF + str r2, [r0] ; force invalidate + + ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET + ; Load L2CC base address base + sync register + ; poll for completion +Sync + ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw ; clear pending interrupts + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register + ldr r1,=SLCRUnlockKey ;set unlock key + str r1, [r0] ;Unlock SLCR + + ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register + ldr r1,=SLCRL2cRamConfig ;set the configuration value + str r1, [r0] ;store the L2c Ram Control Register + + ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register + ldr r1,=SLCRlockKey ;set lock key + str r1, [r0] ;lock SLCR + + ldr r0,=L2CCCrtl ; Load L2CC base address base + control register + ldr r1,[r0] ; read the register + mov r2, #L2CCControl ; set the enable bit + orr r1,r1,r2 + str r1, [r0] ; enable the L2 Caches +#endif + + mov r0, r0 + mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 + orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 + mcr p15, 0, r1, c1, c0, 2 ; write back into CACR + + ; enable vfp + fmrx r1, FPEXC ; read the exception register + orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state + fmxr FPEXC, r1 ; write back the exception register + + mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable + orr r0, r0, #(0x01 << 11) ; #0x8000 + mcr p15,0,r0,c1,c0,0 + + mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register + orr r0, r0, #(0x1 << 2) ; enable Dside prefetch + orr r0, r0, #(0x1 << 1) ; enable L2 prefetch + mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register + + mrs r0, cpsr /* get the current PSR */ + bic r0, r0, #0x100 /* enable asynchronous abort exception */ + msr cpsr_xsf, r0 + +; Clear cp15 regs with unknown reset values + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 ; DFSR + mcr p15, 0, r0, c5, c0, 1 ; IFSR + mcr p15, 0, r0, c6, c0, 0 ; DFAR + mcr p15, 0, r0, c6, c0, 2 ; IFAR + mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR + mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW + mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO + +; Reset and start Cycle Counter + mov r2, #0x80000000 ; clear overflow + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd ; D, C, E + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 ; enable cycle counter + mcr p15, 0, r2, c9, c12, 1 + +; Reset and start Global Timer + mov r0, #0x0 + mov r1, #0x0 + bl XTime_SetTime + +#ifdef PROFILING /* defined in Makefile */ + /* Setup profiling stuff */ + bl _profile_init +#endif /* PROFILING */ + +; make sure argc and argv are valid + mov r0, #0 + mov r1, #0 + b __main ; jump to C startup code + and r0, r0, r0 ; no op + +Ldone b Ldone ; Paranoia: we should never get here + + +; ************************************************************************* +; * +; * invalidate_dcache - invalidate the entire d-cache by set/way +; * +; * Note: for Cortex-A9, there is no cp instruction for invalidating +; * the whole D-cache. Need to invalidate each line. +; * +; ************************************************************************* + +invalidate_dcache + mrc p15, 1, r0, c0, c0, 1 ; read CLIDR + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 ; cache level value (naturally aligned) + beq finished + mov r10, #0 ; start with level 0 +loop1 + add r2, r10, r10, lsr #1 ; work out 3xcachelevel + mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level + and r1, r1, #7 ; get those 3 bits alone + cmp r1, #2 + blt skip ; no cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + isb ; isb to sync the change to the CacheSizeID reg + mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + and r2, r1, #7 ; extract the line length field + add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) + clz r5, r4 ; r5 is the bit position of the way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) +loop2 + mov r9, r4 ; r9 working copy of the max way size (right aligned) +loop3 + orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 + orr r11, r11, r7, lsl r2 ; factor in the index number + mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way + subs r9, r9, #1 ; decrement the way number + bge loop3 + subs r7, r7, #1 ; decrement the index + bge loop2 +skip + add r10, r10, #2 ; increment the cache number + cmp r3, r10 + bgt loop1 + +finished + mov r10, #0 ; swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr + isb + + bx lr + + END diff --git a/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s new file mode 100644 index 00000000..bc20be1f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/translation_table.s @@ -0,0 +1,195 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file translation_table.s +; +; This file contains the initialization for the MMU table in RAM +; needed by the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver   Who  Date     Changes
+; ----- ---- -------- ---------------------------------------------------
+; 1.00a ecm  10/20/09 Initial version
+; 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+;		       instead of strongly-ordered.
+; 4.2	pkp  09/02/14 modified translation table entries according to address map
+; 4.2	pkp  09/11/14 modified translation table entries to resolve compilation
+;		      error for solving CR#822897
+; 
+; +; @note +; +; None. +; +;**************************************************************************** + EXPORT MMUTable + + AREA |.mmu_tbl|,CODE,ALIGN=14 + +MMUTable + ; Each table entry occupies one 32-bit word and there are + ; 4096 entries, so the entire table takes up 16KB. + ; Each entry covers a 1MB section. + + + GBLA count + GBLA sect + +; 0x00000000 - 0x3ffffff (DDR Cacheable) +count SETA 0 +sect SETA 0 + WHILE count<0x400 + DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0x40000000 - 0x7fffffff (GpAxi0) +count SETA 0 + WHILE count<0x400 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0x80000000 - 0xbfffffff (GpAxi1) +count SETA 0 + WHILE count<0x400 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1w +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xc0000000 - 0xdfffffff (undef) +count SETA 0 + WHILE count<0x200 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xe0000000 - 0xe02fffff (IOP dev) +count SETA 0 + WHILE count<0x3 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xe0300000 - 0xe0ffffff (undef/reserved) +count SETA 0 + WHILE count<0xD + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xe1000000 - 0xe1ffffff (NAND) +count SETA 0 + WHILE count<0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xe2000000 - 0xe3ffffff (NOR) +count SETA 0 + WHILE count<0x20 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + + ; 0xe4000000 - 0xe5ffffff (SRAM) +count SETA 0 + WHILE count<0x20 + DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xe6000000 - 0xf7ffffff (reserved) +count SETA 0 + WHILE count<0x120 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and +; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of +; 1MB, it is not possible to define separate regions for them + +; 0xf8000000 - 0xf8ffffff (APB device regs) +count SETA 0 + WHILE count<0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xf9000000 - 0xfbffffff (reserved) +count SETA 0 + WHILE count<0x30 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xfc000000 - 0xfdffffff (QSPI) +count SETA 0 + WHILE count<0x20 + DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xfe000000 - 0xffefffff (reserved) +count SETA 0 + WHILE count<0x1F + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + WEND + +; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of +; 1MB, it is not possible to define separate region for it + +; 0xfff00000 to 0xfffb0000 (OCM) +count SETA 0 + DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 + + END diff --git a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c new file mode 100644 index 00000000..d692ed04 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.c @@ -0,0 +1,147 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_rvct.c +* +* This header file contains functions for using assembler code. It is +* written specifically for RVCT. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  11/18/09 First Release
+* 
+* +******************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm_rvct.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* embedded assembler instructions */ +__asm void cpsiei(void) +{ + cpsie i + bx lr +} +__asm void cpsidi(void) +{ + cpsid i + bx lr +} + +__asm void cpsief(void) +{ + cpsie f + bx lr +} + +__asm void cpsidf(void) +{ + cpsid f + bx lr +} + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +__asm void isb(void) +{ + isb + bx lr +} + +/* Data Synchronization Barrier */ +__asm void dsb(void) +{ + dsb + bx lr +} + +/* Data Memory Barrier */ +__asm void dmb(void) +{ + dmb + bx lr +} + +/* Memory Operations */ +__asm u32 ldr(u32 adr) +{ + ldr r0, [r0] + bx lr +} + +__asm u32 ldrb(u32 adr) +{ + ldrb r0, [r0] + bx lr +} + +__asm void str(u32 adr, u32 val) +{ + str r1, [r0] + bx lr +} + +__asm void strb(u32 adr, u32 val) +{ + strb r1, [r0] + bx lr +} + +/* Count leading zeroes (clz) */ +__asm u32 clz(u32 arg) +{ + clz r0, r0 + bx lr +} + +__asm u32 mfcpsr(void) +{ + mrs r0, cpsr + bx lr +} diff --git a/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h new file mode 100644 index 00000000..1ac62bce --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/armcc/xpseudo_asm_rvct.h @@ -0,0 +1,130 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_rvct.h +* +* This header file contains macros for using __inline assembler code. It is +* written specifically for RVCT. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  11/18/09 First Release
+* 
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_RVCT_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_RVCT_H /* by using protection macros */ + +/***************************** Include Files ********************************/ +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + + +#define mtcpsr(v) { volatile register u32 Reg __asm("cpsr");\ + Reg = v; } + +/* general purpose register read/write */ +/*#define mfgpr(rn) ({ unsigned int val; \ + register unsigned int Reg __asm("r" stringify(rn));\ + val = Reg; \ + val;})*/ + +#define mtgpr(rn, v) { volatile register u32 Reg __asm("r" stringify(rn));\ + Reg = v; } + +/* CP15 operations */ +/*#define mfcp(rn) ({ unsigned int val; \ + val = register unsigned int Reg __asm(rn); \ + val;})*/ + +#define mtcp(rn, v) { volatile register u32 Reg __asm(rn); \ + Reg = v; } + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +__asm void cpsiei(void); + +__asm void cpsidi(void); + +__asm void cpsief(void); + +__asm void cpsidf(void); + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +__asm void isb(void); + +/* Data Synchronization Barrier */ +__asm void dsb(void); + +/* Data Memory Barrier */ +__asm void dmb(void); + +/* Memory Operations */ +__asm u32 ldr(u32 adr); + +__asm u32 ldrb(u32 adr); + +__asm void str(u32 adr, u32 val); + +__asm void strb(u32 adr, u32 val); + +/* Count leading zeroes (clz) */ +__asm u32 clz(u32 arg); +__asm u32 mfcpsr(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_RVCT_H */ diff --git a/lib/bsp/standalone/src/cortexa9/gcc/Makefile b/lib/bsp/standalone/src/cortexa9/gcc/Makefile new file mode 100644 index 00000000..62c5f544 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/Makefile @@ -0,0 +1,84 @@ +############################################################################### +# +# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +include config.make + +CC=$(COMPILER) +AR=$(ARCHIVER) +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ifeq ($(notdir $(CC))) , arm-xilinx-eabi-gcc) +ECC_FLAGS += -nostartfiles\ + -march=armv7-a \ + -mfloat-abi=soft \ + -mfpu=neon + +endif + +#The following flags are required for PEEP. We can remove them later +ECC_FLAGS += +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs + +.PHONY: include +include: standalone_includes profile_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include + +clean: + rm -rf ${OUTS} + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_exit.c b/lib/bsp/standalone/src/cortexa9/gcc/_exit.c new file mode 100644 index 00000000..53d8b14e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/_exit.c @@ -0,0 +1,44 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_open.c b/lib/bsp/standalone/src/cortexa9/gcc/_open.c new file mode 100644 index 00000000..bd6e9588 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/_open.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c new file mode 100644 index 00000000..954bcf0e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/_sbrk.c @@ -0,0 +1,70 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + heap += incr; + + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; + } + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/abort.c b/lib/bsp/standalone/src/cortexa9/gcc/abort.c new file mode 100644 index 00000000..7c073b85 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/abort.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S new file mode 100644 index 00000000..a9e801b7 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/asm_vectors.S @@ -0,0 +1,197 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A9 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+*			 abort and prefetch abort into DataAbortAddr and
+*			 PrefetchAbortAddr for further use to fix CR#854523
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +#include "xil_errata.h" + +#define __ARM_NEON__ 1 + +.org 0 +.text + +.globl _vector_table + +.section .vectors +_vector_table: + B _boot + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP /* Placeholder for address exception vector*/ + B IRQHandler + B FIQHandler + + +IRQHandler: /* IRQ vector handler */ + + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ +#ifdef __ARM_NEON__ + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +#ifdef PROFILING + ldr r2, =prof_pc + subs r3, lr, #0 + str r3, [r2] +#endif + + bl IRQInterrupt /* IRQ vector */ + +#ifdef __ARM_NEON__ + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + + subs pc, lr, #4 /* adjust return */ + + +FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +#ifdef __ARM_NEON__ + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +FIQLoop: + bl FIQInterrupt /* FIQ vector */ + +#ifdef __ARM_NEON__ + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + + +Undefined: /* Undefined handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + b _prestart + + movs pc, lr + + +SVCHandler: /* SWI handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + + tst r0, #0x20 /* check the T bit */ + ldrneh r0, [lr,#-2] /* Thumb mode */ + bicne r0, r0, #0xff00 /* Thumb mode */ + ldreq r0, [lr,#-4] /* ARM mode */ + biceq r0, r0, #0xff000000 /* ARM mode */ + + bl SWInterrupt /* SWInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + movs pc, lr /*return to the next instruction after the SWI instruction */ + + +DataAbortHandler: /* Data Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =DataAbortAddr + sub r1, lr, #8 + str r1, [r0] /* Stores instruction causing data abort */ + + bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */ + +PrefetchAbortHandler: /* Prefetch Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =PrefetchAbortAddr + sub r1, lr, #4 + str r1, [r0] /* Stores instruction causing prefetch abort */ + + bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */ + +.end diff --git a/lib/bsp/standalone/src/cortexa9/gcc/boot.S b/lib/bsp/standalone/src/cortexa9/gcc/boot.S new file mode 100644 index 00000000..8e4b8512 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/boot.S @@ -0,0 +1,443 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* This file contains the initial startup code for the Cortex A9 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+* 5.0	pkp	16/15/14 Modified initialization code to enable scu after
+*			 MMU is enabled
+* 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+*			 caches and TLB, enable MMU and caches, then enable SMP
+*			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+*			 is done later.
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_errata.h" + +.globl MMUTable +.global _prestart +.global _boot +.global __stack +.global __irq_stack +.global __supervisor_stack +.global __abort_stack +.global __fiq_stack +.global __undef_stack +.global _vector_table + +.set PSS_L2CC_BASE_ADDR, 0xF8F02000 +.set PSS_SLCR_BASE_ADDR, 0xF8000000 + +.set RESERVED, 0x0fffff00 +.set TblBase , MMUTable +.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */ +.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/ +.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/ +.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/ +.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/ +.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/ +.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/ +.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/ +.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/ + +.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ +.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ +.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ + +/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ +.if SIM_MODE == 1 +.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */ +.else +.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ +.endif + +.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */ + +.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, + Event monitor bus enable and Way Size (64 KB) */ +.set L2CCControl, 0x01 /* Enable L2CC */ +.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ +.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */ + +.set SLCRlockKey, 0x767B /* SLCR lock key */ +.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */ +.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */ + +/* Stack Pointer locations for boot code */ +.set Undef_stack, __undef_stack +.set FIQ_stack, __fiq_stack +.set Abort_stack, __abort_stack +.set SPV_stack, __supervisor_stack +.set IRQ_stack, __irq_stack +.set SYS_stack, __stack + +.set vector_base, _vector_table + +.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */ + +.section .boot,"ax" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + +#if XPAR_CPU_ID==0 +/* only allow cpu0 through */ + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #0 + beq OKToRun +EndlessLoop0: + wfe + b EndlessLoop0 + +#elif XPAR_CPU_ID==1 +/* only allow cpu1 through */ + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #1 + beq OKToRun +EndlessLoop1: + wfe + b EndlessLoop1 +#endif + +OKToRun: + mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ + and r5, r0, #0x00f00000 + and r6, r0, #0x0000000f + orr r6, r6, r5, lsr #20-4 + +#ifdef CONFIG_ARM_ERRATA_742230 + cmp r6, #0x22 /* only present up to r2p2 */ + mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */ + orrle r10, r10, #1 << 4 /* set bit #4 */ + mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */ +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + teq r5, #0x00200000 /* only present in r2p* */ + mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */ + orreq r10, r10, #1 << 6 /* set bit #6 */ + mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */ +#endif + + /* set VBAR to the _vector_table address in linker script */ + ldr r0, =vector_base + mcr p15, 0, r0, c12, c0, 0 + + /*invalidate scu*/ + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] + + /* Invalidate caches and TLBs */ + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + + /* Disable MMU, if enabled */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ + bic r0, r0, #0x1 /* clear bit 0 */ + mcr p15, 0, r0, c1, c0, 0 /* write value back */ + +#ifdef SHAREABLE_DDR + /* Mark the entire DDR memory as shareable */ + ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */ + ldr r0, =TblBase /* MMU Table address in memory */ + ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +shareable_loop: + str r2, [r0] /* write the entry to MMU table */ + add r0, r0, #0x4 /* next entry in the table */ + add r2, r2, #0x100000 /* next section */ + subs r3, r3, #1 + bge shareable_loop /* loop till 1G is covered */ +#endif + + /* In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable */ +#if USE_AMP==1 + ldr r3, =0x1ff /* 512 entries to cover 512MB DDR */ + ldr r0, =TblBase /* MMU Table address in memory */ + add r0, r0, #0x800 /* Address of entry in MMU table, for 0x20000000 */ + ldr r2, =0x0c02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +mmu_loop: + str r2, [r0] /* write the entry to MMU table */ + add r0, r0, #0x4 /* next entry in the table */ + add r2, r2, #0x100000 /* next section */ + subs r3, r3, #1 + bge mmu_loop /* loop till 512MB is covered */ +#endif + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the irq stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x12 /* IRQ mode */ + msr cpsr, r2 + ldr r13,=IRQ_stack /* IRQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the supervisor stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x13 /* supervisor mode */ + msr cpsr, r2 + ldr r13,=SPV_stack /* Supervisor stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Abort stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x17 /* Abort mode */ + msr cpsr, r2 + ldr r13,=Abort_stack /* Abort stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the FIQ stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x11 /* FIQ mode */ + msr cpsr, r2 + ldr r13,=FIQ_stack /* FIQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Undefine stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1b /* Undefine mode */ + msr cpsr, r2 + ldr r13,=Undef_stack /* Undefine stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the system stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1F /* SYS mode */ + msr cpsr, r2 + ldr r13,=SYS_stack /* SYS stack pointer */ + + /*set scu enable bit in scu*/ + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + /* enable MMU and cache */ + + ldr r0,=TblBase /* Load MMU translation table base */ + orr r0, r0, #0x5B /* Outer-cacheable, WB */ + mcr 15, 0, r0, c2, c0, 0 /* TTB0 */ + + mvn r0,#0 /* Load MMU domains -- all ones=manager */ + mcr p15,0,r0,c3,c0,0 + + /* Enable mmu, icahce and dcache */ + ldr r0,=CRValMmuCac + mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */ + dsb /* dsb allow the MMU to start up */ + isb /* isb flush prefetch buffer */ + + /* Write to ACTLR */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + orr r0, r0, #(0x01 << 6) /* set SMP bit */ + orr r0, r0, #(0x01 ) /* */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + +/* Invalidate L2 Cache and enable L2 Cache*/ +/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */ +#if USE_AMP!=1 + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + mov r1, #0 /* force the disable bit */ + str r1, [r0] /* disable the L2 Caches */ + + ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */ + ldr r1,[r0] /* read the register */ + ldr r2,=L2CCAuxControl /* set the default bits */ + orr r1,r1,r2 + str r1, [r0] /* store the Aux Control Register */ + + ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */ + ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/ + str r1, [r0] /* store the TAG Latency register Register */ + + ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */ + ldr r1,=L2CCDataLatency /* set the latencies for the Data*/ + str r1, [r0] /* store the Data Latency register Register */ + + ldr r0,=L2CCWay /* Load L2CC base address base + way register*/ + ldr r2, =0xFFFF + str r2, [r0] /* force invalidate */ + + ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */ + /* Load L2CC base address base + sync register*/ + /* poll for completion */ +Sync: ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw /* clear pending interrupts */ + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ + ldr r1,=SLCRL2cRamConfig /* set the configuration value */ + str r1, [r0] /* store the L2c Ram Control Register */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + ldr r1,[r0] /* read the register */ + mov r2, #L2CCControl /* set the enable bit */ + orr r1,r1,r2 + str r1, [r0] /* enable the L2 Caches */ +#endif + + mov r0, r0 + mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */ + orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */ + mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */ + + /* enable vfp */ + fmrx r1, FPEXC /* read the exception register */ + orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */ + fmxr FPEXC, r1 /* write back the exception register */ + + mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ + orr r0, r0, #(0x01 << 11) /* #0x8000 */ + mcr p15,0,r0,c1,c0,0 + + mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ + orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */ + orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */ + mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */ + + mrs r0, cpsr /* get the current PSR */ + bic r0, r0, #0x100 /* enable asynchronous abort exception */ + msr cpsr_xsf, r0 + + + b _start /* jump to C startup code */ + and r0, r0, r0 /* no op */ + +.Ldone: b .Ldone /* Paranoia: we should never get here */ + + +/* + ************************************************************************* + * + * invalidate_dcache - invalidate the entire d-cache by set/way + * + * Note: for Cortex-A9, there is no cp instruction for invalidating + * the whole D-cache. Need to invalidate each line. + * + ************************************************************************* + */ +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* swith back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + +.end diff --git a/lib/bsp/standalone/src/cortexa9/gcc/close.c b/lib/bsp/standalone/src/cortexa9/gcc/close.c new file mode 100644 index 00000000..ab1d34de --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/close.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _close(s32 fd); +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S b/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S new file mode 100644 index 00000000..3adad4f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/cpu_init.S @@ -0,0 +1,80 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file cpu_init.s +* +* This file contains CPU specific initialization. Invoked from main CRT +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0   pkp	12/16/14 removed incorrect initialization of TLB lockdown
+*			 register to fix CR#830580
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + .text + .global __cpu_init + .align 2 +__cpu_init: + +/* Clear cp15 regs with unknown reset values */ + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 /* DFSR */ + mcr p15, 0, r0, c5, c0, 1 /* IFSR */ + mcr p15, 0, r0, c6, c0, 0 /* DFAR */ + mcr p15, 0, r0, c6, c0, 2 /* IFAR */ + mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ + mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ + mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ + +/* Reset and start Cycle Counter */ + mov r2, #0x80000000 /* clear overflow */ + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd /* D, C, E */ + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 /* enable cycle counter */ + mcr p15, 0, r2, c9, c12, 1 + + bx lr + +.end diff --git a/lib/bsp/standalone/src/cortexa9/gcc/errno.c b/lib/bsp/standalone/src/cortexa9/gcc/errno.c new file mode 100644 index 00000000..0b259a2a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/errno.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 * __errno (void); +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c b/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c new file mode 100644 index 00000000..93449edf --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/fcntl.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/fstat.c b/lib/bsp/standalone/src/cortexa9/gcc/fstat.c new file mode 100644 index 00000000..223831ae --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/fstat.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/getpid.c b/lib/bsp/standalone/src/cortexa9/gcc/getpid.c new file mode 100644 index 00000000..420d2454 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/getpid.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _getpid(void); +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/isatty.c b/lib/bsp/standalone/src/cortexa9/gcc/isatty.c new file mode 100644 index 00000000..154625e4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/isatty.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _isatty(sint32 fd); +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/kill.c b/lib/bsp/standalone/src/cortexa9/gcc/kill.c new file mode 100644 index 00000000..dc24a99f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/kill.c @@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _kill(s32 pid, s32 sig); +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) s32 kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/lseek.c b/lib/bsp/standalone/src/cortexa9/gcc/lseek.c new file mode 100644 index 00000000..df4cbfd4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/lseek.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/open.c b/lib/bsp/standalone/src/cortexa9/gcc/open.c new file mode 100644 index 00000000..0fd19959 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/open.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/read.c b/lib/bsp/standalone/src/cortexa9/gcc/read.c new file mode 100644 index 00000000..7dcca673 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/read.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* read.c -- read bytes from a input device. + */ + +#include "xil_printf.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c b/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c new file mode 100644 index 00000000..b61c79e0 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/sbrk.c @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) char8 *sbrk (s32 nbytes); +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if(heap_ptr != NULL) { + heap_ptr += nbytes; + } + +/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ + if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S new file mode 100644 index 00000000..f340ee66 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S @@ -0,0 +1,179 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file translation_table.s +* +* This file contains the initialization for the MMU table in RAM +* needed by the Cortex A9 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2	pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*			and  0xe0000000 - 0xe1ffffff is broken down into
+*			0xe0000000 - 0xe02fffff (memory mapped devides)
+*			0xe0300000 - 0xe0ffffff (reserved) and
+*			0xe1000000 - 0xe1ffffff (NAND)
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +#include "xparameters.h" + .globl MMUTable + + .section .mmu_tbl,"a" + +MMUTable: + /* Each table entry occupies one 32-bit word and there are + * 4096 entries, so the entire table takes up 16KB. + * Each entry covers a 1MB section. + */ +.set SECT, 0 +.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR +.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 +.set UNDEF_REG, 0x3FF - DDR_REG + + /*0x00000000 - 0x00100000 (cacheable )*/ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 + +.rept DDR_REG /* (DDR Cacheable) */ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept UNDEF_REG /* (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + + +.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices) + * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */ +.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and + 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of + 1MB, it is not possible to define separate regions for them */ + +.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ + +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ +.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of + 1MB, it is not possible to define separate region for it + +/* 0xfff00000 - 0xffffffff + 256K OCM when mapped to high address space + inner-cacheable */ +.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 + +.end diff --git a/lib/bsp/standalone/src/cortexa9/gcc/unlink.c b/lib/bsp/standalone/src/cortexa9/gcc/unlink.c new file mode 100644 index 00000000..0b292832 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/unlink.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 unlink(char8 *path); +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void *)path; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/write.c b/lib/bsp/standalone/src/cortexa9/gcc/write.c new file mode 100644 index 00000000..32733722 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/write.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* write.c -- write bytes to an output device. + */ + +#include "xil_printf.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes); +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) sint32 +write (sint32 fd, char8* buf, sint32 nbytes) + +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) sint32 +_write (sint32 fd, char8* buf, sint32 nbytes) +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S new file mode 100644 index 00000000..9d06ebd6 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/xil-crt0.S @@ -0,0 +1,145 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2	pkp  08/04/14 Removed PEEP board related code which contained
+*		      initialization of uart smc nor and sram
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start + +.Lbss_end: + .long __bss_end + +.Lstack: + .long __stack + + + .globl _start +_start: + bl __cpu_init /* Initialize the CPU first (BSP provides this) */ + + mov r0, #0 + + /* clear sbss */ + ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr r2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp r1,r2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + + /* Reset and start Global Timer */ + mov r0, #0x0 + mov r1, #0x0 + bl XTime_SetTime + +#ifdef PROFILING /* defined in Makefile */ + /* Setup profiling stuff */ + bl _profile_init +#endif /* PROFILING */ + + /* run global constructors */ + bl __libc_init_array + + /* make sure argc and argv are valid */ + mov r0, #0 + mov r1, #0 + + /* Let her rip */ + bl main + + /* Cleanup global constructors */ + bl __libc_fini_array + +#ifdef PROFILING + /* Cleanup profiling stuff */ + bl _profile_clean +#endif /* PROFILING */ + + /* All done */ + bl exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _start,.Lstart-_start diff --git a/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h new file mode 100644 index 00000000..2091ab7a --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/gcc/xpseudo_asm_gcc.h @@ -0,0 +1,175 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/28/09 First release
+* 
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/Makefile b/lib/bsp/standalone/src/cortexa9/iccarm/Makefile new file mode 100644 index 00000000..61921f34 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/Makefile @@ -0,0 +1,86 @@ +############################################################################### +# +# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +include config.make + +AS=iasmarm +COMPILER=iccarm +ARCHIVER=iarchive +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= + +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +ECC_FLAGS += --cpu=Cortex-A9 --fpu=VFPv3 + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include + +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +OBJECTS += $(addsuffix .o, $(basename $(wildcard *.s))) +#OBJECTS += boot.o + +libs: banner $(LIBS) clean + +#boot.s: boot.S +# ${COMPILER} $(INCLUDES) -E -o $@ $< +# rm -f boot.S + +%.o: %.s + ${AS} --cpu Cortex-A9 --fpu VFPv3 $(INCLUDES) -o $@ $< + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling standalone" + echo "${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<" + +standalone_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: standalone_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/abort.c b/lib/bsp/standalone/src/cortexa9/iccarm/abort.c new file mode 100644 index 00000000..f1ea99bf --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/abort.c @@ -0,0 +1,40 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include + + +void abort(void) +{ + __exit(1); +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s new file mode 100644 index 00000000..15e92468 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/asm_vectors.s @@ -0,0 +1,161 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file asm_vectors.s +; +; This file contains the initial vector table for the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver	Who     Date	  Changes
+; ----- ------- -------- ---------------------------------------------------
+; 1.00a 		 Initial version
+; 4.2 	pkp 	06/27/14 Modified return addresses for interrupt
+;			 handlers
+; 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+;			 abort and prefetch abort into DataAbortAddr and
+;			 PrefetchAbortAddr for further use to fix CR#854523
+; 
+; +; @note +; +; None. +; +;**************************************************************************** + + MODULE ?asm_vectors + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +#include "xparameters.h" +;#include "xtime_l.h" + +#define UART_BAUDRATE 115200 + + IMPORT _prestart + IMPORT __iar_program_start + + + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC _vector_table + + IMPORT IRQInterrupt + IMPORT FIQInterrupt + IMPORT SWInterrupt + IMPORT DataAbortInterrupt + IMPORT PrefetchAbortInterrupt + IMPORT DataAbortAddr + IMPORT PrefetchAbortAddr + +_vector_table + ARM + + B __iar_program_start + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP ; Placeholder for address exception vector + B IRQHandler + B FIQHandler + + + SECTION .text:CODE:NOROOT(2) + REQUIRE _vector_table + + ARM +IRQHandler ; IRQ vector handler + + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + bl IRQInterrupt ; IRQ vector + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + +FIQHandler ; FIQ vector handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + +FIQLoop + bl FIQInterrupt ; FIQ vector + + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + +Undefined ; Undefined handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + b _prestart + + movs pc, lr + + +SVCHandler ; SWI handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + tst r0, #0x20 ; check the T bit + ldrneh r0, [lr,#-2] ; Thumb mode + bicne r0, r0, #0xff00 ; Thumb mode + ldreq r0, [lr,#-4] ; ARM mode + biceq r0, r0, #0xff000000 ; ARM mode + bl SWInterrupt ; SWInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + movs pc, lr ; adjust return + +DataAbortHandler ; Data Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =DataAbortAddr + sub r1, lr,#8 + str r1, [r0] ;Address of instruction causing data abort + bl DataAbortInterrupt ;DataAbortInterrupt :call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #8 ; adjust return + +PrefetchAbortHandler ; Prefetch Abort handler + stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code + ldr r0, =PrefetchAbortAddr + sub r1, lr,#4 + str r1, [r0] ;Address of instruction causing prefetch abort + bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here + ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code + subs pc, lr, #4 ; adjust return + + END diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/boot.s b/lib/bsp/standalone/src/cortexa9/iccarm/boot.s new file mode 100644 index 00000000..86123f7e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/boot.s @@ -0,0 +1,457 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file boot.s +; +; This file contains the initial vector table for the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver	Who     Date	  Changes
+; ----- ------- -------- ---------------------------------------------------
+; 1.00a 		 Initial version
+; 4.2	pkp  	08/04/14 Removed PEEP board related code which contained
+;			 initialization of uart smc nor and sram
+; 5.0	pkp	16/12/14 Modified initialization code to enable scu after
+;			 MMU is enabled and removed incorrect initialization
+;			 of TLB lockdown register to fix CR#830580
+; 5.1  pkp	05/13/15 Changed the initialization order so to first invalidate
+;			 caches and TLB, enable MMU and caches, then enable SMP
+;			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+;			 is done later.
+; 
+; +; @note +; +; None. +; +;**************************************************************************** + + MODULE ?boot + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +#include "xparameters.h" +;#include "xtime_l.h" + +#define UART_BAUDRATE 115200 + + PUBLIC _prestart + PUBLIC __iar_program_start + IMPORT _vector_table + IMPORT MMUTable + IMPORT __cmain + IMPORT Xil_ExceptionInit + IMPORT XTime_SetTime + +PSS_L2CC_BASE_ADDR EQU 0xF8F02000 +PSS_SLCR_BASE_ADDR EQU 0xF8000000 + +RESERVED EQU 0x0fffff00 +TblBase EQU MMUTable +LRemap EQU 0xFE00000F ; set the base address of the peripheral block as not shared +L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET) +L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET) +L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET) +L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET) +L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET) +L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET) +L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET) +L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET) + +SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET) +SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET) +SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) ;(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET) + +/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ +#if SIM_MODE == 1 +CRValMmuCac EQU 00000000000000b ; Disable IDC, and MMU +#else +CRValMmuCac EQU 01000000000101b ; Enable IDC, and MMU +#endif +CRValHiVectorAddr EQU 10000000000000b ; Set the Vector address to high, 0xFFFF0000 + +L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable +L2CCControl EQU 0x01 ; Enable L2CC +L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM +L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM + +SLCRlockKey EQU 0x767B ; SLCR lock key +SLCRUnlockKey EQU 0xDF0D ; SLCR unlock key +SLCRL2cRamConfig EQU 0x00020202 ; SLCR L2C ram configuration + + +vector_base EQU _vector_table + +FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30) + + SECTION .intvec:CODE:NOROOT(2) + + +; this initializes the various processor modes + +_prestart +__iar_program_start + +#if XPAR_CPU_ID==0 +; only allow cp0 through + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #0 + beq OKToRun +EndlessLoop0 + wfe + b EndlessLoop0 + +#elif XPAR_CPU_ID==1 +; only allow cp1 through + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #1 + beq OKToRun +EndlessLoop1 + wfe + b EndlessLoop1 +#endif + +OKToRun + mrc p15, 0, r0, c0, c0, 0 ; Get the revision + and r5, r0, #0x00f00000 + and r6, r0, #0x0000000f + orr r6, r6, r5, lsr #20-4 + +#ifdef CONFIG_ARM_ERRATA_742230 + cmp r6, #0x22 ; only present up to r2p2 + mrcle p15, 0, r10, c15, c0, 1 ; read diagnostic register + orrle r10, r10, #1 << 4 ; set bit #4 + mcrle p15, 0, r10, c15, c0, 1 ; write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + teq r5, #0x00200000 ; only present in r2p* + mrceq p15, 0, r10, c15, c0, 1 ; read diagnostic register + orreq r10, r10, #1 << 6 ; set bit #6 + mcreq p15, 0, r10, c15, c0, 1 ; write diagnostic register +#endif + + ; set VBAR to the _vector_table address in linker script + ldr r0, =vector_base + mcr p15, 0, r0, c12, c0, 0 + + ;invalidate scu + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] + + ;Invalidate caches and TLBs + mov r0,#0 ; r0 = 0 + mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 ; invalidate icache + mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array + bl invalidate_dcache ; invalidate dcache + + + ; Disable MMU, if enabled + mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1 + bic r0, r0, #0x1 ; clear bit 0 + mcr p15, 0, r0, c1, c0, 0 ; write value back + +#ifdef SHAREABLE_DDR + ; Mark the entire DDR memory as shareable + ldr r3, =0x3ff ; 1024 entries to cover 1G DDR + ldr r0, =TblBase ; MMU Table address in memory + ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 +shareable_loop + str r2, [r0] ; write the entry to MMU table + add r0, r0, #0x4 ; next entry in the table + add r2, r2, #0x100000 ; next section + subs r3, r3, #1 + bge shareable_loop ; loop till 1G is covered +#endif + + ; In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable +#if USE_AMP==1 + ldr r3, =0x1ff ; 512 entries to cover 512MB DDR + ldr r0, =TblBase ; MMU Table address in memory + add r0, r0, #0x800 ; Address of entry in MMU table, for 0x20000000 + ldr r2, =0x0c02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 +mmu_loop + str r2, [r0] ; write the entry to MMU table + add r0, r0, #0x4 ; next entry in the table + add r2, r2, #0x100000 ; next section + subs r3, r3, #1 + bge mmu_loop ; loop till 512MB is covered +#endif + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the irq stack pointer + and r2, r1, r0 + orr r2, r2, #0x12 ; IRQ mode + msr cpsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=SFE(IRQ_STACK) ; IRQ stack pointer + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the supervisor stack pointer + and r2, r1, r0 + orr r2, r2, #0x13 ; supervisor mode + msr cpsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=SFE(SVC_STACK) ; Supervisor stack pointer + + mrs r0, cpsr ; get the current PSR + mvn r1, #0x1f ; set up the Abort stack pointer + and r2, r1, r0 + orr r2, r2, #0x17 ; Abort mode + msr cpsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=SFE(ABT_STACK) ; Abort stack pointer + + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the FIQ stack pointer + and r2, r1, r0 + orr r2, r2, #0x11 ; FIQ mode + msr cpsr, r2 ; was cpsr + ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer + + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the Undefine stack pointer + and r2, r1, r0 + orr r2, r2, #0x1b ; Undefine mode + msr cpsr, r2 ; was cpsr + ldr r13,=SFE(UND_STACK) ; Undefine stack pointer + + mrs r0, cpsr ; was cpsr, get the current PSR + mvn r1, #0x1f ; set up the system stack pointer + and r2, r1, r0 + orr r2, r2, #0x1f ; SYS mode + msr cpsr, r2 ; was cpsr, apsr is considered synonym + ldr r13,=SFE(CSTACK) ; SYS stack pointer + + ;set scu enable bit in scu + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + ; enable MMU and cache + + ldr r0,=TblBase ; Load MMU translation table base + orr r0, r0, #0x5B ; Outer-cacheable, WB + mcr p15, 0, r0, c2, c0, 0 ; TTB0 + + mvn r0,#0 ; Load MMU domains -- all ones=manager + mcr p15,0,r0,c3,c0,0 + + ; Enable mmu, icahce and dcache + ldr r0,=CRValMmuCac + + mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU + dsb ; dsb allow the MMU to start up + isb ; isb flush prefetch buffer + + ; Write to ACTLR + mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR + orr r0, r0, #(0x01 << 6) ; SMP bit + orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast + mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR + +; Invalidate L2 Cache and initialize L2 Cache +; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) +#if USE_AMP!=1 + ldr r0,=L2CCCrtl ; Load L2CC base address base + control register + mov r1, #0 ; force the disable bit + str r1, [r0] ; disable the L2 Caches + + ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register + ldr r1,[r0] ; read the register + ldr r2,=L2CCAuxControl ; set the default bits + orr r1,r1,r2 + str r1, [r0] ; store the Aux Control Register + + ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address + ldr r1,=L2CCTAGLatency ; set the latencies for the TAG + str r1, [r0] ; store the TAG Latency register Register + + ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address + ldr r1,=L2CCDataLatency ; set the latencies for the Data + str r1, [r0] ; store the Data Latency register Register + + ldr r0,=L2CCWay ; Load L2CC base address base + way register + ldr r2, =0xFFFF + str r2, [r0] ; force invalidate + + ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET + ; Load L2CC base address base + sync register + ; poll for completion +Sync + ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw ; clear pending interrupts + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register + ldr r1,=SLCRUnlockKey ; set unlock key + str r1, [r0] ; Unlock SLCR + + ldr r0,=SLCRL2cRamReg ; Load SLCR base address base + l2c Ram Control register + str r1, [r0] ; store the L2c Ram Control Register + + ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register + ldr r1,=SLCRlockKey ; set lock key + str r1, [r0] ; lock SLCR + ldr r0,=L2CCCrtl ; Load L2CC base address base + control register + ldr r1,[r0] ; read the register + mov r2, #L2CCControl ; set the enable bit + orr r1,r1,r2 + str r1, [r0] ; enable the L2 Caches +#endif + + mov r0, r0 + mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1 + orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11 + mcr p15, 0, r1, c1, c0, 2 ; write back into CACR + + ; enable vfp + fmrx r1, FPEXC ; read the exception register + orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state + fmxr FPEXC, r1 ; write back the exception register + + mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable + orr r0, r0, #(0x01 << 11) ; #0x8000 + mcr p15,0,r0,c1,c0,0 + + mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register + orr r0, r0, #(0x1 << 2) ; enable Dside prefetch + orr r0, r0, #(0x1 << 1) ; enable L2 prefetch + mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register + + ; Initialize the vector table + ;bl Xil_ExceptionInit + +; Clear cp15 regs with unknown reset values + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 ; DFSR + mcr p15, 0, r0, c5, c0, 1 ; IFSR + mcr p15, 0, r0, c6, c0, 0 ; DFAR + mcr p15, 0, r0, c6, c0, 2 ; IFAR + mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR + mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW + mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO + +; Reset and start Cycle Counter + mov r2, #0x80000000 ; clear overflow + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd ; D, C, E + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 ; enable cycle counter + mcr p15, 0, r2, c9, c12, 1 + +; Reset and start Global Timer + mov r0, #0x0 + mov r1, #0x0 + bl XTime_SetTime + +; make sure argc and argv are valid + mov r0, #0 + mov r1, #0 + b __cmain ; jump to C startup code + + and r0, r0, r0 ; no op + +Ldone b Ldone ; Paranoia: we should never get here + + +; ************************************************************************* +; * +; * invalidate_dcache - invalidate the entire d-cache by set/way +; * +; * Note: for Cortex-A9, there is no cp instruction for invalidating +; * the whole D-cache. Need to invalidate each line. +; * +; ************************************************************************* + +invalidate_dcache + mrc p15, 1, r0, c0, c0, 1 ; read CLIDR + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 ; cache level value (naturally aligned) + beq finished + mov r10, #0 ; start with level 0 +loop1 + add r2, r10, r10, lsr #1 ; work out 3xcachelevel + mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level + and r1, r1, #7 ; get those 3 bits alone + cmp r1, #2 + blt skip ; no cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + isb ; isb to sync the change to the CacheSizeID reg + mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + and r2, r1, #7 ; extract the line length field + add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned) + clz r5, r4 ; r5 is the bit position of the way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned) +loop2 + mov r9, r4 ; r9 working copy of the max way size (right aligned) +loop3 + orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11 + orr r11, r11, r7, lsl r2 ; factor in the index number + mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way + subs r9, r9, #1 ; decrement the way number + bge loop3 + subs r7, r7, #1 ; decrement the index + bge loop2 +skip + add r10, r10, #2 ; increment the cache number + cmp r3, r10 + bgt loop1 + +finished + mov r10, #0 ; swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr + dsb + isb + + bx lr + + + END diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/clock.c b/lib/bsp/standalone/src/cortexa9/iccarm/clock.c new file mode 100644 index 00000000..20763741 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/clock.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * This is the default implementation of the "clock" function of the + * standard library. It can be replaced with a system-specific + * implementation. + * + * The "clock" function should return the processor time used by the + * program from some implementation-defined start time. The value + * should be such that if divided by the macro CLOCKS_PER_SEC the + * result should yield the time in seconds. + * + * The value "(clock_t)-1" means that the processor time is not + * available. + * + */ + +#include + + +clock_t (clock)(void) +{ + return ((clock_t) -1); +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/close.c b/lib/bsp/standalone/src/cortexa9/iccarm/close.c new file mode 100644 index 00000000..f246afb8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/close.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +sint32 __close(sint32 fd) +{ + (void)fd; + return (0); + +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/exit.c b/lib/bsp/standalone/src/cortexa9/iccarm/exit.c new file mode 100644 index 00000000..f8e1635e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/exit.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +void exit(sint32 arg) +{ + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c b/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c new file mode 100644 index 00000000..86d93be9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/low_level_init.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * This module contains the function `__low_level_init', a function + * that is called before the `main' function of the program. Normally + * low-level initializations - such as setting the prefered interrupt + * level or setting the watchdog - can be performed here. + * + * Note that this function is called before the data segments are + * initialized, this means that this function cannot rely on the + * values of global or static variables. + * + * When this function returns zero, the startup code will inhibit the + * initialization of the data segments. The result is faster startup, + * the drawback is that neither global nor static data will be + * initialized. + */ + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + + +s32 __low_level_init(void); + +s32 __low_level_init(void) +{ + /*==================================*/ + /* Initialize hardware. */ + /*==================================*/ + + /*==================================*/ + /* Choose if segment initialization */ + /* should be done or not. */ + /* Return: 0 to omit seg_init */ + /* 1 to run seg_init */ + /*==================================*/ + return 1; +} + + +#ifdef __cplusplus +} +#endif diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c b/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c new file mode 100644 index 00000000..cce6f86c --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/lseek.c @@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * + * This is a template implementation of the "__lseek" function used by + * the standard library. Replace it with a system-specific + * implementation. + * + * The "__lseek" function makes the next file operation (__read or + * __write) act on a new location. The parameter "whence" specifies + * how the "offset" parameter should be interpreted according to the + * following table: + * + * 0 (=SEEK_SET) - Goto location "offset". + * 1 (=SEEK_CUR) - Go "offset" bytes from the current location. + * 2 (=SEEK_END) - Go to "offset" bytes from the end. + * + * This function should return the current file position, or -1 on + * failure. + */ + +#include +#include +#include "xil_types.h" +LONG __lseek(sint32 handle, LONG offset, sint32 whence); + +LONG __lseek(sint32 handle, LONG offset, sint32 whence) +{ + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/open.c b/lib/bsp/standalone/src/cortexa9/iccarm/open.c new file mode 100644 index 00000000..e8348656 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/open.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * + * This is a template implementation of the "__open" function used by + * the standard library. Replace it with a system-specific + * implementation. + * + * The "__open" function opens the file named "filename" as specified + * by "mode". + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + * + */ + +#include +#include "xil_types.h" + +sint32 __open(const char8 * filename, sint32 mode); + +sint32 __open(const char8 * filename, sint32 mode) +{ +return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/read.c b/lib/bsp/standalone/src/cortexa9/iccarm/read.c new file mode 100644 index 00000000..3bb363cc --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/read.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/* + * + * + * The "__read" function reads a number of bytes, at most "size" into + * the memory area pointed to by "buffer". It returns the number of + * bytes read, 0 at the end of the file, or _LLIO_ERROR if failure + * occurs. + * + * The template implementation below should return a + * character value, or -1 on failure. + * + */ + +#include +#include "xil_types.h" + +size_t __read(sint32 handle, u8 * buffer, size_t size); + +size_t __read(sint32 handle, u8 * buffer, size_t size) +{ + +return size; +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/remove.c b/lib/bsp/standalone/src/cortexa9/iccarm/remove.c new file mode 100644 index 00000000..a2139a07 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/remove.c @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * + * The "remove" function should remove the file named "filename". It + * should return 0 on success and nonzero on failure. + * + */ + +#include +#include "xil_types.h" + +sint32 remove(const char8 * filename); + +sint32 remove(const char8 * filename) +{ + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s new file mode 100644 index 00000000..7e90fc89 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/translation_table.s @@ -0,0 +1,194 @@ +;****************************************************************************** +; +; Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), to deal +; in the Software without restriction, including without limitation the rights +; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +; copies of the Software, and to permit persons to whom the Software is +; furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included in +; all copies or substantial portions of the Software. +; +; Use of the Software is limited solely to applications: +; (a) running on a Xilinx device, or +; (b) that interact with a Xilinx device through a bus or interconnect. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +; XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +; WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +; OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +; SOFTWARE. +; +; Except as contained in this notice, the name of the Xilinx shall not be used +; in advertising or otherwise to promote the sale, use or other dealings in +; this Software without prior written authorization from Xilinx. +; +;***************************************************************************** +;**************************************************************************** +;** +; @file translation_table.s +; +; This file contains the initialization for the MMU table in RAM +; needed by the Cortex A9 processor +; +;
+; MODIFICATION HISTORY:
+;
+; Ver   Who  Date     Changes
+; ----- ---- -------- ---------------------------------------------------
+; 1.00a ecm  10/20/09 Initial version
+; 3.07a sgd  07/05/12 Configuring device address spaces as shareable device
+;		       instead of strongly-ordered.
+; 4.2	pkp  09/02/14 modified translation table entries according to address map
+; 4.2	pkp  09/11/14 modified translation table entries to resolve compilation
+;		      error for solving CR#822897
+; 
+; +; @note +; +; None. +; +;**************************************************************************** + EXPORT MMUTable + +;ARMCC AREA |.mmu_tbl|,CODE,ALIGN=14 +; RSEG mmu_tbl:CODE:ROOT (14) + SECTION .mmu_tbl:CODE:ROOT(14) + +MMUTable + ; Each table entry occupies one 32-bit word and there are + ; 4096 entries, so the entire table takes up 16KB. + ; Each entry covers a 1MB section. + + +; 0x00000000 - 0x3ffffff (DDR Cacheable) +count SETA 0 +sect SETA 0 + REPT 0x400 + DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0x40000000 - 0x7fffffff (GpAxi0) +count SETA 0 + REPT 0x400 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0x80000000 - 0xbfffffff (GpAxi1) +count SETA 0 + REPT 0x400 + DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xc0000000 - 0xdfffffff (undef) +count SETA 0 + REPT 0x200 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xe0000000 - 0xe02fffff (IOP dev) +count SETA 0 + REPT 0x3 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + + ; 0xe0300000 - 0xe0ffffff (undef/reserved) +count SETA 0 + REPT 0xD + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xe1000000 - 0xe1ffffff (NAND) +count SETA 0 + REPT 0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xe2000000 - 0xe3ffffff (NOR) +count SETA 0 + REPT 0x20 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xe4000000 - 0xe5ffffff (SRAM) +count SETA 0 + REPT 0x20 + DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xe6000000 - 0xf7ffffff (reserved) +count SETA 0 + REPT 0x0120 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and +; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of +; 1MB, it is not possible to define separate regions for them + +; 0xf8000000 - 0xf8ffffff (APB device regs) +count SETA 0 + REPT 0x10 + DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xf9000000 - 0xfbffffff (reserved) +count SETA 0 + REPT 0x30 + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfc000000 - 0xfdffffff (QSPI) +count SETA 0 + REPT 0x20 + DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfe000000 - 0xffefffff (reserved) +count SETA 0 + REPT 0x1F + DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 +sect SETA sect+0x100000 +count SETA count+1 + ENDR + +; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of +; 1MB, it is not possible to define separate region for it + +; 0xfff00000 to 0xfffb0000 (OCM) +count SETA 0 + DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 +sect SETA sect+0x100000 + + END diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/write.c b/lib/bsp/standalone/src/cortexa9/iccarm/write.c new file mode 100644 index 00000000..3d435804 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/write.c @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* + * The "__write" function should output "size" number of bytes from + * "buffer" in some application-specific way. It should return the + * number of characters written, or _LLIO_ERROR on failure. + * + * If "buffer" is zero then __write should perform flushing of + * internal buffers, if any. In this case "handle" can be -1 to + * indicate that all handles should be flushed. + * + * The template implementation below assumes that the application + * provides the function "MyLowLevelPutchar". It should return the + * character written, or -1 on failure. + * + */ + +#include +#include "xil_types.h" + + +#if 0 +/* + * If the __write implementation uses internal buffering, uncomment + * the following line to ensure that we are called with "buffer" as 0 + * (i.e. flush) when the application terminates. + */ + +size_t __write(sint32 handle, const u8 * buffer, size_t size) +{ + u32 volatile *uart_base = (u32 *)0xE0001000U; + s32 i; + + for (i =0; i < size;i++) { + /* wait if TNFUL */ + while (*(uart_base + 11U) & (1U << 14U)) ; + *(uart_base + 12U) = buffer[i]; + } + return 0; +} + +#endif + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + sint32 _write (sint32 fd, char8* buf, sint32 nbytes); +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +sint32 +write (sint32 fd, char8* buf, sint32 nbytes) + +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if (*(buf + i) == '\n') { + outbyte ('\r'); + } + outbyte (*(buf + i)); + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +size_t +__write (sint32 fd, const u8* buf, size_t nbytes) +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if (*(buf + i) == '\n') { + outbyte ('\r'); + } + outbyte (*(buf + i)); + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c new file mode 100644 index 00000000..47fc1024 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_iccarm.c +* +* This file contains functions for ARM register handling. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 3.12a asa  11/2/13 First Release
+* 
+* +******************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm_iccarm.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* embedded assembler instructions */ +s32 mfcpsr (void) +{ + s32 rval; + asm("mrs %0, cpsr" : "=r"(rval)); + return rval; +} diff --git a/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h new file mode 100644 index 00000000..924c121d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/iccarm/xpseudo_asm_iccarm.h @@ -0,0 +1,171 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_iccarm.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the IAR C/C++ compiler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/28/09 First release
+* 3.12a asa		 11/02/13  Removed the macro mfcpsr to make it a function.
+* 
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_ICCARM_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_ICCARM_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ + +#define mtcpsr(v) __asm volatile(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm volatile("cpsie i\n") +#define cpsidi() __asm volatile("cpsid i\n") + +#define cpsief() __asm volatile("cpsie f\n") +#define cpsidf() __asm volatile("cpsid f\n") + + + +#define mtgpr(rn, v) __asm volatile(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm volatile(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm volatile ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm volatile ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm volatile ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm volatile(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm volatile(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm volatile(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm volatile(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm volatile(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +/* CP15 operations */ +#define mtcp(rn, v) __asm volatile(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +/*#define mfcp(rn) ({u32 rval; \ + __asm volatile(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) */ + +#define mfcp(rn, v) __asm volatile ("mrc " rn : "=r" (v)); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ +int mfcpsr (void); +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_ICCARM_H */ diff --git a/lib/bsp/standalone/src/cortexa9/print.c b/lib/bsp/standalone/src/cortexa9/print.c new file mode 100644 index 00000000..be29280c --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/print.c @@ -0,0 +1,31 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char *ptr) +{ +#ifdef STDOUT_BASEADDRESS + while (*ptr) { + outbyte (*ptr++); + } +#else +(void)ptr; +#endif +} diff --git a/lib/bsp/standalone/src/cortexa9/putnum.c b/lib/bsp/standalone/src/cortexa9/putnum.c new file mode 100644 index 00000000..33c3a6c4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/putnum.c @@ -0,0 +1,59 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* + * putnum -- print a 32 bit number in hex + */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) +{ + char8 buf[9]; + s32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 7 ; cnt >= 0 ; cnt--) { + digit = ((num >> ((u16)cnt * 4U)) & 0xfU); + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } + print (buf); +} diff --git a/lib/bsp/standalone/src/cortexa9/sleep.c b/lib/bsp/standalone/src/cortexa9/sleep.c new file mode 100644 index 00000000..4577b564 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/sleep.c @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global Timer
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +/*****************************************************************************/ +/* +* +* This API is used to provide delays in seconds +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +****************************************************************************/ +s32 sleep(u32 seconds) +{ + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/sleep.h b/lib/bsp/standalone/src/cortexa9/sleep.h new file mode 100644 index 00000000..34eb4e49 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/sleep.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa9/smc.h b/lib/bsp/standalone/src/cortexa9/smc.h new file mode 100644 index 00000000..f5b16cf9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/smc.h @@ -0,0 +1,114 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file smc.h +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* 
+* +* @note None. +* +******************************************************************************/ + +#ifndef SMC_H /* prevent circular inclusions */ +#define SMC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory controller configuration register offset */ +#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */ + +/* Chip select configuration register offset */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */ + +/* User configuration register offset */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */ + +/* Integration test register offset */ +#define XSMCPSS_IT_OFFSET 0xE00U + +/* ID configuration register offset */ +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SMC_H */ diff --git a/lib/bsp/standalone/src/cortexa9/usleep.c b/lib/bsp/standalone/src/cortexa9/usleep.c new file mode 100644 index 00000000..cc42e59d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/usleep.c @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa9.h" + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ +s32 usleep(u32 useconds) +{ + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexa9/vectors.c b/lib/bsp/standalone/src/cortexa9/vectors.c new file mode 100644 index 00000000..b56e94a4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/vectors.c @@ -0,0 +1,168 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex A9 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/************************** Function Prototypes ******************************/ + + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} diff --git a/lib/bsp/standalone/src/cortexa9/vectors.h b/lib/bsp/standalone/src/cortexa9/vectors.h new file mode 100644 index 00000000..17a73985 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/vectors.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache.c b/lib/bsp/standalone/src/cortexa9/xil_cache.c new file mode 100644 index 00000000..e1522f76 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_cache.c @@ -0,0 +1,1611 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+*
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_cache_l.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexa9.h" +#include "xl2cc.h" +#include "xil_errata.h" +#include "xil_exception.h" + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */ + +#ifdef __GNUC__ + extern s32 _stack_end; + extern s32 __undef_stack; +#endif + +/**************************************************************************** +* +* Access L2 Debug Control Register. +* +* @param Value, value to be written to Debug Control Register. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2WriteDebugCtrl(u32 Value) +#else +static void Xil_L2WriteDebugCtrl(u32 Value) +#endif +{ +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value); +#else + (void)(Value); +#endif +} + +/**************************************************************************** +* +* Perform L2 Cache Sync Operation. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2CacheSync(void) +#else +static void Xil_L2CacheSync(void) +#endif +{ +#ifdef CONFIG_PL310_ERRATA_753970 + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U); +#else + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); +#endif +} + +/**************************************************************************** +* +* Enable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + Xil_L1DCacheEnable(); + Xil_L2CacheEnable(); +} + +/**************************************************************************** +* +* Disable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + Xil_L2CacheDisable(); + Xil_L1DCacheDisable(); +} + +/**************************************************************************** +* +* Invalidate the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L2CacheInvalidate(); + Xil_L1DCacheInvalidate(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L2CacheInvalidateLine(adr); + Xil_L1DCacheInvalidateLine(adr); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* In this function, if start address or end address is not aligned to cache-line, +* particular cache-line containing unaligned start or end address is flush first +* and then invalidated the others as invalidating the same unaligned cache line +* may result into loss of data. This issue raises few possibilities. +* +* +* If the address to be invalidated is not cache-line aligned, the +* following choices are available: +* 1) Invalidate the cache line when required and do not bother much for the +* side effects. Though it sounds good, it can result in hard-to-debug issues. +* The problem is, if some other variable are allocated in the +* same cache line and had been recently updated (in cache), the invalidation +* would result in loss of data. +* +* 2) Flush the cache line first. This will ensure that if any other variable +* present in the same cache line and updated recently are flushed out to memory. +* Then it can safely be invalidated. Again it sounds good, but this can result +* in issues. For example, when the invalidation happens +* in a typical ISR (after a DMA transfer has updated the memory), then flushing +* the cache line means, loosing data that were updated recently before the ISR +* got invoked. +* +* Linux prefers the second one. To have uniform implementation (across standalone +* and Linux), the second option is implemented. +* This being the case, follwoing needs to be taken care of: +* 1) Whenever possible, the addresses must be cache line aligned. Please nore that, +* not just start address, even the end address must be cache line aligned. If that +* is taken care of, this will always work. +* 2) Avoid situations where invalidation has to be done after the data is updated by +* peripheral/DMA directly into the memory. It is not tough to achieve (may be a bit +* risky). The common use case to do invalidation is when a DMA happens. Generally +* for such use cases, buffers can be allocated first and then start the DMA. The +* practice that needs to be followed here is, immediately after buffer allocation +* and before starting the DMA, do the invalidation. With this approach, invalidation +* need not to be done after the DMA transfer is over. +* +* This is going to always work if done carefully. +* However, the concern is, there is no guarantee that invalidate has not needed to be +* done after DMA is complete. For example, because of some reasons if the first cache +* line or last cache line (assuming the buffer in question comprises of multiple cache +* lines) are brought into cache (between the time it is invalidated and DMA completes) +* because of some speculative prefetching or reading data for a variable present +* in the same cache line, then we will have to invalidate the cache after DMA is complete. +* +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + + Xil_L1DCacheFlushLine(tempadr); + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(tempadr); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); + tempadr += cacheline; + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + + Xil_L1DCacheFlushLine(tempend); + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(tempend); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); + } + + while (tempadr < tempend) { + /* Invalidate L2 cache line */ + *L2CCOffset = tempadr; + Xil_L2CacheSync(); +#ifdef __GNUC__ + /* Invalidate L1 Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = tempadr; } +#endif + tempadr += cacheline; + } + } + + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlush(); + Xil_L2CacheFlush(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlushLine(adr); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_L2CacheFlushLine(adr); + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); + mtcpsr(currmask); +} + +/**************************************************************************** +* Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); + + while (LocalAddr < end) { +#ifdef __GNUC__ + /* Flush L1 Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + /* Flush L2 cache line */ + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); +} +/**************************************************************************** +* +* Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param Address to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheStoreLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L1DCacheStoreLine(adr); + Xil_L2CacheStoreLine(adr); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Enable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + Xil_L1ICacheEnable(); + Xil_L2CacheEnable(); +} + +/**************************************************************************** +* +* Disable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ + Xil_L2CacheDisable(); + Xil_L1ICacheDisable(); +} + +/**************************************************************************** +* +* Invalidate the entire instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L2CacheInvalidate(); + Xil_L1ICacheInvalidate(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate an instruction cache line. If the instruction specified by the +* parameter adr is cached by the instruction cache, the cacheline containing +* that instruction is invalidated. +* +* @param None. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L2CacheInvalidateLine(adr); + Xil_L1ICacheInvalidateLine(adr); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + + while (LocalAddr < end) { + /* Invalidate L2 cache line */ + *L2CCOffset = LocalAddr; + dsb(); +#ifdef __GNUC__ + /* Invalidate L1 I-cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + + LocalAddr += cacheline; + } + } + + /* Wait for L1 and L2 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Enable the level 1 Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1DCacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + return; + } + + /* clean and invalidate the Data cache */ + Xil_L1DCacheInvalidate(); + + /* enable the Data cache */ + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Disable the level 1 Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1DCacheDisable(void) +{ + register u32 CtrlReg; + + /* clean and invalidate the Data cache */ + Xil_L1DCacheFlush(); + +#ifdef __GNUC__ + /* disable the Data cache */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the level 1 Data cache. +* +* @param None. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for invalidating +* the whole D-cache. This function invalidates each line by +* set/way. +* +****************************************************************************/ +void Xil_L1DCacheInvalidate(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; + +#ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; +#endif + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + +#ifdef __GNUC__ + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /*Flush stack memory to save return address*/ + Xil_DCacheFlushRange(stack_end, stack_size); +#endif + + /* Select cache level 0 and D cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + /* Determine Cache Size */ + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; +#ifdef __GNUC__ + /* Invalidate by Set/Way */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg)); +#else + /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */ + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += 0x40000000U; + } + + /* Wait for L1 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate a level 1 Data cache line. If the byte specified by the address +* (Addr) is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/**************************************************************************** +* +* Invalidate the level 1 Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 D-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + while (LocalAddr < end) { +#ifdef __GNUC__ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + } + + /* Wait for L1 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the level 1 Data cache. +* +* @param None. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for flushing +* the whole D-cache. Need to flush each line. +* +****************************************************************************/ +void Xil_L1DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way; + u32 WayIndex, Set, SetIndex, NumSet; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + /* Select cache level 0 and D cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + + /* Determine Cache Size */ + + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + /* Flush by Set/Way */ +#ifdef __GNUC__ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += 0x40000000U; + } + + /* Wait for L1 flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush a level 1 Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheFlushLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 flush to complete */ + dsb(); +} + +/**************************************************************************** +* Flush the level 1 Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1DCacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 D-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + + while (LocalAddr < end) { +#ifdef __GNUC__ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + } + + /* Wait for L1 flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Store a level 1 Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param Address to be stored. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheStoreLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 store to complete */ + dsb(); +} + +/**************************************************************************** +* +* Enable the level 1 instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1ICacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) { + return; + } + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* enable the instruction cache */ + CtrlReg |= (XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Disable level 1 the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1ICacheDisable(void) +{ + register u32 CtrlReg; + + dsb(); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* disable the instruction cache */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the entire level 1 instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidate(void) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/**************************************************************************** +* +* Invalidate a level 1 instruction cache line. If the instruction specified by +* the parameter adr is cached by the instruction cache, the cacheline containing +* that instruction is invalidated. +* +* @param None. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/**************************************************************************** +* +* Invalidate the level 1 instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + + while (LocalAddr < end) { +#ifdef __GNUC__ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); +#elif defined (__ICCARM__) + __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + } + + /* Wait for L1 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Enable the L2 cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L2CacheEnable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + /* only enable if L2CC is currently disabled */ + if ((L2CCReg & 0x01U) == 0U) { + /* set up the way size and latencies */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_AUX_CNTRL_OFFSET); + L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK; + L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK; + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET, + L2CCReg); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET, + XPS_L2CC_TAG_RAM_DEFAULT_MASK); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET, + XPS_L2CC_DATA_RAM_DEFAULT_MASK); + + /* Clear the pending interrupts */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_ISR_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg); + + Xil_L2CacheInvalidate(); + /* Enable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg | (0x01U))); + + Xil_L2CacheSync(); + /* synchronize the processor */ + dsb(); + + } +} + +/**************************************************************************** +* +* Disable the L2 cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L2CacheDisable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + if((L2CCReg & 0x1U) != 0U) { + + /* Clean and Invalidate L2 Cache */ + Xil_L2CacheFlush(); + + /* Disable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg & (~0x01U))); + /* Wait for the cache operations to complete */ + + dsb(); + } +} + +/**************************************************************************** +* +* Invalidate the L2 cache. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheInvalidate(void) +{ + #ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /*Flush stack memory to save return address*/ + Xil_DCacheFlushRange(stack_end, stack_size); + #endif + u32 ResultDCache; + /* Invalidate the caches */ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET, + 0x0000FFFFU); + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + while(ResultDCache != (u32)0U) { + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + } + + /* Wait for the invalidate to complete */ + Xil_L2CacheSync(); + + /* synchronize the processor */ + dsb(); +} + +/**************************************************************************** +* +* Invalidate a level 2 cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheInvalidateLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr); + /* synchronize the processor */ + dsb(); +} + +/**************************************************************************** +* +* Invalidate the level 2 cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L2CacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + + /* synchronize the processor */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the L2 cache. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheFlush(void) +{ + u16 L2CCReg; + u32 ResultL2Cache; + + /* Flush the caches */ + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET, + 0x0000FFFFU); + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + + while(ResultL2Cache != (u32)0U) { + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + } + + Xil_L2CacheSync(); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + + /* synchronize the processor */ + dsb(); +} + +/**************************************************************************** +* +* Flush a level 2 cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheFlushLine(u32 adr) +{ +#ifdef CONFIG_PL310_ERRATA_588369 + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); +#else + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr); +#endif + /* synchronize the processor */ + dsb(); +} + +/**************************************************************************** +* Flush the level 2 cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_L2CacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + /* synchronize the processor */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Store a level 2 cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param Address to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheStoreLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + /* synchronize the processor */ + dsb(); +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache.h b/lib/bsp/standalone/src/cortexa9/xil_cache.h new file mode 100644 index 00000000..e79d8210 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_cache.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* Contains required functions for the ARM cache functionality +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* 
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa9/xil_cache_l.h b/lib/bsp/standalone/src/cortexa9/xil_cache_l.h new file mode 100644 index 00000000..e93641db --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_cache_l.h @@ -0,0 +1,95 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_l.h +* +* Contains L1 and L2 specific functions for the ARM cache functionality +* used by xcache.c. This functionality is being made available here for +* more sophisticated users. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* 
+* +******************************************************************************/ +#ifndef XIL_CACHE_MACH_H +#define XIL_CACHE_MACH_H + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_DCacheInvalidateLine(u32 adr); +void Xil_DCacheFlushLine(u32 adr); +void Xil_DCacheStoreLine(u32 adr); +void Xil_ICacheInvalidateLine(u32 adr); + +void Xil_L1DCacheEnable(void); +void Xil_L1DCacheDisable(void); +void Xil_L1DCacheInvalidate(void); +void Xil_L1DCacheInvalidateLine(u32 adr); +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len); +void Xil_L1DCacheFlush(void); +void Xil_L1DCacheFlushLine(u32 adr); +void Xil_L1DCacheFlushRange(u32 adr, u32 len); +void Xil_L1DCacheStoreLine(u32 adr); + +void Xil_L1ICacheEnable(void); +void Xil_L1ICacheDisable(void); +void Xil_L1ICacheInvalidate(void); +void Xil_L1ICacheInvalidateLine(u32 adr); +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len); + +void Xil_L2CacheEnable(void); +void Xil_L2CacheDisable(void); +void Xil_L2CacheInvalidate(void); +void Xil_L2CacheInvalidateLine(u32 adr); +void Xil_L2CacheInvalidateRange(u32 adr, u32 len); +void Xil_L2CacheFlush(void); +void Xil_L2CacheFlushLine(u32 adr); +void Xil_L2CacheFlushRange(u32 adr, u32 len); +void Xil_L2CacheStoreLine(u32 adr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa9/xil_errata.h b/lib/bsp/standalone/src/cortexa9/xil_errata.h new file mode 100644 index 00000000..00f2eeb6 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_errata.h @@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* This header file contains Cortex A9 and PL310 Errata definitions. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* 
+* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +#define ENABLE_ARM_ERRATA 1 + +#ifdef ENABLE_ARM_ERRATA +/* Cortex A9 ARM Errata */ + +/* + * Errata No: 742230 + * Description: DMB operation may be faulty + */ +#define CONFIG_ARM_ERRATA_742230 1 + +/* + * Errata No: 743622 + * Description: Faulty hazard checking in the Store Buffer may lead + * to data corruption. + */ +#define CONFIG_ARM_ERRATA_743622 1 + +/* + * Errata No: 775420 + * Description: A data cache maintenance operation which aborts, + * might lead to deadlock + */ +#define CONFIG_ARM_ERRATA_775420 1 + +/* + * Errata No: 794073 + * Description: Speculative instruction fetches with MMU disabled + * might not comply with architectural requirements + */ +#define CONFIG_ARM_ERRATA_794073 1 + + +/* PL310 L2 Cache Errata */ + +/* + * Errata No: 588369 + * Description: Clean & Invalidate maintenance operations do not + * invalidate clean lines + */ +#define CONFIG_PL310_ERRATA_588369 1 + +/* + * Errata No: 727915 + * Description: Background Clean and Invalidate by Way operation + * can cause data corruption + */ +#define CONFIG_PL310_ERRATA_727915 1 + +/* + * Errata No: 753970 + * Description: Cache sync operation may be faulty + */ +#define CONFIG_PL310_ERRATA_753970 1 + +#endif /* ENABLE_ARM_ERRATA */ + +#endif /* XIL_ERRATA_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_exception.c b/lib/bsp/standalone/src/cortexa9/xil_exception.c new file mode 100644 index 00000000..90b98716 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_exception.c @@ -0,0 +1,252 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex A9 exception +* Handler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/04/09 First release
+* 3.05a sdm		 02/02/12 Updated to resiter a null handler only if a handler
+*			  		      is not already registered
+* 4.2   pkp		 06/19/14 Added default exception handlers for data abort and
+*						  prefetch abort using handlers called
+*						  DataAbortHandler and PrefetchAbortHandler respectively
+*						  Both handlers are registers in vector table entries
+*						  using XExc_VectorTable
+* 5.1	pkp		 05/13/15 Added debugging message to print address of instruction
+*						  causing data abort and prefetch abort
+* 
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; + +u32 DataAbortAddr; /* Address of instruction causing data abort */ +u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void *)Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* The function is a common API used to initialize exception handlers across all +* processors supported. For ARM CortexA9, the exception handlers are being +* initialized statically and hence this function does not do anything. +* However, it is still present to avoid any compilation issues in case an +* application uses this API and also to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to initialize +* exception handlers). +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* +* Makes the connection between the Id of the exception source and the +* associated Handler that is to run when the exception is recognized. The +* argument provided in this call as the Data is used as the argument +* for the Handler when it is called. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. + See xil_exception_l.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* +* Removes the Handler for a specific exception Id. The stub Handler is then +* registered for this exception Id. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception_l.h for further information. + +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} + + +/*****************************************************************************/ +/** +* +* Default Data abort handler which prints data fault status register through +* which information about data fault can be acquired +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_DataAbortHandler(void *CallBackRef){ + u32 FaultStatus; + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr); + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default Prefetch abort handler which prints prefetch fault status register through +* which information about instruction prefetch fault can be acquired +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_PrefetchAbortHandler(void *CallBackRef){ + u32 FaultStatus; + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr); + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_exception.h b/lib/bsp/standalone/src/cortexa9/xil_exception.h new file mode 100644 index 00000000..65b2e092 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_exception.h @@ -0,0 +1,234 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A9 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/04/09 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#elif defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#elif defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Enable nested interrupts by clearing the I and F bits it CPSR +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* Disable the nested interrupts by setting the I and F bits. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_io.c b/lib/bsp/standalone/src/cortexa9/xil_io.c new file mode 100644 index 00000000..eec0b03e --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_io.c @@ -0,0 +1,344 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. These functions encapsulate Cortex A9 architecture-specific +* I/O requirements. +* +* @note +* +* This file contains architecture-dependent code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 3.06a sgd      05/15/12 Pointer volatile used for the all read functions
+* 3.07a sgd      08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
+* 3.09a sgd      02/05/13 Comments cleanup
+* 
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa9.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Performs an input operation for an 8-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(INTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(INTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(INTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for an 8-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(INTPTR Addr, u8 Value) +{ + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(INTPTR Addr, u16 Value) +{ + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(INTPTR Addr, u32 Value) +{ + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16BE(INTPTR Addr) +{ + u16 temp; + u16 result; + + temp = Xil_In16(Addr); + + result = Xil_EndianSwap16(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32BE(INTPTR Addr) +{ + u32 temp; + u32 result; + + temp = Xil_In32(Addr); + + result = Xil_EndianSwap32(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16BE(INTPTR Addr, u16 Value) +{ + u16 temp; + + temp = Xil_EndianSwap16(Value); + + Xil_Out16(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32BE(INTPTR Addr, u32 Value) +{ + u32 temp; + + temp = Xil_EndianSwap32(Value); + + Xil_Out32(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Perform a 16-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* Perform a 32-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_io.h b/lib/bsp/standalone/src/cortexa9/xil_io.h new file mode 100644 index 00000000..adc1e206 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_io.h @@ -0,0 +1,246 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+* 3.07a asa	     08/31/12 Added xil_printf.h include
+* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
+* 
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined __GNUC__ +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); + +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); + + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c new file mode 100644 index 00000000..f67ad57d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.c @@ -0,0 +1,522 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_misc_reset.c +* +* This file contains the implementation of the reset sequence for various +* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset +* sequence provided to the interfaces is based on the provision in +* slcr reset functional blcok. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 
+* +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_misc_psreset_api.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* This function contains the implementation for ddr reset. +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XDdr_ResetHw(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert and deassert the ddr softreset bit */ + RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for remapping the ocm memory region +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XOcm_Remap(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Map the ocm region to postbootrom state */ + RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; + Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for SMC reset sequence +* +* @param BaseAddress of the interface +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSmc_ResetHw(u32 BaseAddress) +{ + u32 RegVal; + + /* Clear the interuupts */ + RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); + RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK; + Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); + /* Clear the idle counter registers */ + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); + /* Update the ecc registers with reset values */ + Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, + XSMC_ECC_MEMCFG1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET, + XSMC_ECC_MEMCMD1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, + XSMC_ECC_MEMCMD2_RESET_VAL); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr mio registers +* with reset values +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_MioWriteResetValues(void) +{ + u32 i; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Update all the MIO registers with reset values */ + for (i=0U; i<=1U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + for (; i<=8U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_02_RESET_VAL); + } + for (; i<=53U ;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr pll registers +* with reset values +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_PllWriteResetValues(void) +{ + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + + /* update the pll control registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL); + /* update the pll config registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL); + /* update the clock control registers with reset values */ + Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for disabling the level shifters +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_DisableLevelShifters(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Disable the level shifters */ + RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); + Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); + +} +/*****************************************************************************/ +/** +* This function contains the implementation for OCM software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_OcmReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for Ethernet software reset from +* the slcr +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_EmacPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for USB software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_UsbPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for QSPI software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_QspiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SPI software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_SpiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for i2c software reset from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_I2cPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for UART software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_UartPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for CAN software reset from slcr +* registers +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_CanPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SMC software reset from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_SmcPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for DMA controller software reset +* from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_DmaPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for Gpio AMBA software reset from +* the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_GpioPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h new file mode 100644 index 00000000..1b37e704 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_misc_psreset_api.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register defintions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +*
+* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ +#define XIL_MISC_RESET_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) +/**< SLCR USB reset control address register */ +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ +/**< SLCR GEM reset control address register */ +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) +/**< SLCR SMC reset control address register */ +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0DU + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x00000001U +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(void); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(void); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(void); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(void); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(void); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_mmu.c b/lib/bsp/standalone/src/cortexa9/xil_mmu.c new file mode 100644 index 00000000..db7c765b --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_mmu.c @@ -0,0 +1,184 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mmu.h" +#include "xil_errata.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +extern u32 MMUTable; + +/************************** Function Prototypes ******************************/ + +/***************************************************************************** +* +* Set the memory attributes for a section, in the translation table. Each +* section covers 1MB of memory. +* +* @param Addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* +* @return None. +* +* @note The MMU and D-cache need not be disabled before changing an +* translation table attribute. +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib) +{ + u32 *ptr; + u32 section; + + section = Addr / 0x100000U; + ptr = &MMUTable; + ptr += section; + if(ptr != NULL) { + *ptr = (Addr & 0xFFF00000U) | attrib; + } + + Xil_DCacheFlush(); + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + /* Invalidate all branch predictors */ + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + + dsb(); /* ensure completion of the BP and TLB invalidation */ + isb(); /* synchronize context on this processor */ +} + +/***************************************************************************** +* +* Invalidate the caches, enable MMU and D Caches for Cortex A9 processor. +* +* @param None. +* @return None. +* +******************************************************************************/ +void Xil_EnableMMU(void) +{ + u32 Reg; + Xil_DCacheInvalidate(); + Xil_ICacheInvalidate(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg |= (u32)0x05U; + mtcp(XREG_CP15_SYS_CONTROL, Reg); + + dsb(); + isb(); +} + +/***************************************************************************** +* +* Disable MMU for Cortex A9 processors. This function invalidates the TLBs, +* Branch Predictor Array and flushed the D Caches before disabling +* the MMU and D cache. +* +* @param None. +* +* @return None. +* +******************************************************************************/ +void Xil_DisableMMU(void) +{ + u32 Reg; + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + Xil_DCacheFlush(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg &= (u32)(~0x05U); +#ifdef CONFIG_ARM_ERRATA_794073 + /* Disable Branch Prediction */ + Reg &= (u32)(~0x800U); +#endif + mtcp(XREG_CP15_SYS_CONTROL, Reg); +} diff --git a/lib/bsp/standalone/src/cortexa9/xil_mmu.h b/lib/bsp/standalone/src/cortexa9/xil_mmu.h new file mode 100644 index 00000000..839fafab --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_mmu.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMMU(void); +void Xil_DisableMMU(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xil_printf.c b/lib/bsp/standalone/src/cortexa9/xil_printf.c new file mode 100644 index 00000000..5c1b467f --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_printf.c @@ -0,0 +1,352 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include +#include +#include + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static void outnum( const s32 n, const s32 base, struct params_s *par); +static s32 getnum( charptr* linep); + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#ifdef STDOUT_BASEADDRESS + outbyte( par->pad_character); +#endif + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#ifdef STDOUT_BASEADDRESS + outbyte(*LocalPtr); + LocalPtr += 1; +#endif +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + charptr cp; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#ifdef STDOUT_BASEADDRESS + outbyte( outbuf[i] ); + i--; +#endif +} + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +void xil_printf( const char8 *ctrl1, ...) +{ + s32 Check; + s32 long_flag; + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#ifdef STDOUT_BASEADDRESS + outbyte(*ctrl); + ctrl += 1; +#endif + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; + long_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': +#ifdef STDOUT_BASEADDRESS + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + long_flag = 1; + Check = 0; + break; + + case 'd': + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + Check = 1; + break; + case 'x': + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#ifdef STDOUT_BASEADDRESS + outbyte( va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#ifdef STDOUT_BASEADDRESS + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} + +/*---------------------------------------------------*/ diff --git a/lib/bsp/standalone/src/cortexa9/xil_printf.h b/lib/bsp/standalone/src/cortexa9/xil_printf.h new file mode 100644 index 00000000..2be5c573 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc.h b/lib/bsp/standalone/src/cortexa9/xl2cc.h new file mode 100644 index 00000000..e53557d0 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xl2cc.h @@ -0,0 +1,172 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xl2cc.h +* +* This file contains the address definitions for the PL310 Level-2 Cache +* Controller. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XL2CC_H_ +#define _XL2CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* L2CC Register Offsets */ +#define XPS_L2CC_ID_OFFSET 0x0000U +#define XPS_L2CC_TYPE_OFFSET 0x0004U +#define XPS_L2CC_CNTRL_OFFSET 0x0100U +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU + +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U + +#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */ + +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */ + +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */ + +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */ + +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */ + +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */ + +/* XPS_L2CC_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */ + +/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */ + +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */ + /* Cache replacement policy, Parity enable, */ + /* Event monitor bus enable and Way Size (64 KB) */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */ + +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */ + +/* Interrupt bit masks */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */ + +/* Address filtering mask and enable bit */ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/ + +/* Debug control bits */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */ + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c new file mode 100644 index 00000000..12da65ec --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.c @@ -0,0 +1,168 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.c +* +* This file contains APIs for configuring and controlling the event counters +* in PL310 L2 cache controller. For more information about the event counters, +* see xl2cc_counter.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include +#include "xparameters_ps.h" +#include "xl2cc_counter.h" +#include "xl2cc.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XL2cc_EventCtrReset(void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* This function initializes the event counters in L2 Cache controller with a +* set of event codes specified by the user. +* +* @param Event0 is the event code for counter 0. +* @param Event1 is the event code for counter 1. +* Use the event codes defined by XL2CC_* in xl2cc_counter.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XL2cc_EventCtrInit(s32 Event0, s32 Event1) +{ + + /* Write event code into cnt1 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2); + + /* Write event code into cnt0 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2); + + /* Reset counters */ + XL2cc_EventCtrReset(); +} + +/****************************************************************************/ +/** +* +* This function starts the event counters in L2 Cache controller. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XL2cc_EventCtrStart(void) +{ + u32 *LocalPtr; + LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET); + XL2cc_EventCtrReset(); + + /* Enable counter */ + /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */ + *LocalPtr = (u32)1; +} + +/****************************************************************************/ +/** +* +* This function disables the event counters in L2 Cache controller, saves the +* counter values and resets the counters. +* +* @param EveCtr0 is an output parameter which is used to return the value +* in event counter 0. +* EveCtr1 is an output parameter which is used to return the value +* in event counter 1. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) +{ + /* Disable counter */ + *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U; + + /* Save counter values */ + *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET)); + *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET)); + + XL2cc_EventCtrReset(); +} + +/****************************************************************************/ +/** +* +* This function resets the event counters in L2 Cache controller. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XL2cc_EventCtrReset(void) +{ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U; +} diff --git a/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h new file mode 100644 index 00000000..cc484726 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xl2cc_counter.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.h +* +* This header file contains APIs for configuring and controlling the event +* counters in PL310 L2 cache controller. +* PL310 has 2 event counters which can be used to count a variety of events +* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations, +* where value configures the event counters to count a set of events. +* +* XL2cc_EventCtrInit API can be used to select a set of events and +* XL2cc_EventCtrStart configures the event counters and starts the counters. +* XL2cc_EventCtrStop diables the event counters and returns the counter values. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
+* +******************************************************************************/ + +#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ +#define L2CCCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* + * The following constants define the event codes for the event counters. + */ +#define XL2CC_CO 0x1 +#define XL2CC_DRHIT 0x2 +#define XL2CC_DRREQ 0x3 +#define XL2CC_DWHIT 0x4 +#define XL2CC_DWREQ 0x5 +#define XL2CC_DWTREQ 0x6 +#define XL2CC_IRHIT 0x7 +#define XL2CC_IRREQ 0x8 +#define XL2CC_WA 0x9 +#define XL2CC_IPFALLOC 0xa +#define XL2CC_EPFHIT 0xb +#define XL2CC_EPFALLOC 0xc +#define XL2CC_SRRCVD 0xd +#define XL2CC_SRCONF 0xe +#define XL2CC_EPFRCVD 0xf + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +void XL2cc_EventCtrInit(s32 Event0, s32 Event1); +void XL2cc_EventCtrStart(void); +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* L2CCCOUNTER_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xparameters_ps.h b/lib/bsp/standalone/src/cortexa9/xparameters_ps.h new file mode 100644 index 00000000..170ff59d --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xparameters_ps.h @@ -0,0 +1,333 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A9 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xE0000000U +#define XPS_UART1_BASEADDR 0xE0001000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U +#define XPS_I2C0_BASEADDR 0xE0004000U +#define XPS_I2C1_BASEADDR 0xE0005000U +#define XPS_SPI0_BASEADDR 0xE0006000U +#define XPS_SPI1_BASEADDR 0xE0007000U +#define XPS_CAN0_BASEADDR 0xE0008000U +#define XPS_CAN1_BASEADDR 0xE0009000U +#define XPS_GPIO_BASEADDR 0xE000A000U +#define XPS_GEM0_BASEADDR 0xE000B000U +#define XPS_GEM1_BASEADDR 0xE000C000U +#define XPS_QSPI_BASEADDR 0xE000D000U +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U +#define XPS_SDIO0_BASEADDR 0xE0100000U +#define XPS_SDIO1_BASEADDR 0xE0101000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_NAND_BASEADDR 0xE1000000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000U +#define XPS_TTC1_BASEADDR 0xF8002000U +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U +#define XPS_WDT_BASEADDR 0xF8005000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF8F00000U +#define XPS_L2CC_BASEADDR 0xF8F02000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_CORE_PARITY0_INT_ID 32U +#define XPS_CORE_PARITY1_INT_ID 33U +#define XPS_L2CC_INT_ID 34U +#define XPS_OCMINTR_INT_ID 35U +#define XPS_ECC_INT_ID 36U +#define XPS_PMU0_INT_ID 37U +#define XPS_PMU1_INT_ID 38U +#define XPS_SYSMON_INT_ID 39U +#define XPS_DVC_INT_ID 40U +#define XPS_WDT_INT_ID 41U +#define XPS_TTC0_0_INT_ID 42U +#define XPS_TTC0_1_INT_ID 43U +#define XPS_TTC0_2_INT_ID 44U +#define XPS_DMA0_ABORT_INT_ID 45U +#define XPS_DMA0_INT_ID 46U +#define XPS_DMA1_INT_ID 47U +#define XPS_DMA2_INT_ID 48U +#define XPS_DMA3_INT_ID 49U +#define XPS_SMC_INT_ID 50U +#define XPS_QSPI_INT_ID 51U +#define XPS_GPIO_INT_ID 52U +#define XPS_USB0_INT_ID 53U +#define XPS_GEM0_INT_ID 54U +#define XPS_GEM0_WAKE_INT_ID 55U +#define XPS_SDIO0_INT_ID 56U +#define XPS_I2C0_INT_ID 57U +#define XPS_SPI0_INT_ID 58U +#define XPS_UART0_INT_ID 59U +#define XPS_CAN0_INT_ID 60U +#define XPS_FPGA0_INT_ID 61U +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_TTC1_0_INT_ID 69U +#define XPS_TTC1_1_INT_ID 70U +#define XPS_TTC1_2_INT_ID 71U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_USB1_INT_ID 76U +#define XPS_GEM1_INT_ID 77U +#define XPS_GEM1_WAKE_INT_ID 78U +#define XPS_SDIO1_INT_ID 79U +#define XPS_I2C1_INT_ID 80U +#define XPS_SPI1_INT_ID 81U +#define XPS_UART1_INT_ID 82U +#define XPS_CAN1_INT_ID 83U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Private Peripheral Interrupts (PPI) */ +#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID + +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexa9/xpm_counter.c b/lib/bsp/standalone/src/cortexa9/xpm_counter.c new file mode 100644 index 00000000..e46d27ba --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xpm_counter.c @@ -0,0 +1,296 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.c +* +* This file contains APIs for configuring and controlling the Cortex-A9 +* Performance Monitor Events. For more information about the event counters, +* see xpm_counter.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 4.2	pkp	 07/21/14 Corrected reset value of event counter in function
+*					  Xpm_ResetEventCounters to fix CR#796275
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xpm_counter.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xpm_DisableEventCounters(void); +void Xpm_EnableEventCounters (void); +void Xpm_ResetEventCounters (void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* This function disables the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + /* Disable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function enables the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + /* Enable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function resets the Cortex A9 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif + Reg |= (1U << 1U); /* reset event counters */ + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); + +} + +/****************************************************************************/ +/** +* +* This function configures the Cortex A9 event counters controller, with the +* event codes, in a configuration selected by the user and enables the counters. +* +* @param PmcrCfg is configuration value based on which the event counters +* are configured. +* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + { + XPM_EVENT_DATA_READS, + XPM_EVENT_DATA_WRITE, + XPM_EVENT_EXCEPTION, + XPM_EVENT_EXCEPRETURN, + XPM_EVENT_CHANGECONTEXT, + XPM_EVENT_SW_CHANGEPC + }, + { + XPM_EVENT_IMMEDBRANCH, + XPM_EVENT_UNALIGNEDACCESS, + XPM_EVENT_BRANCHMISS, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT, + XPM_EVENT_JAVABYTECODE + }, + { + XPM_EVENT_SWJAVABYTECODE, + XPM_EVENT_JAVABACKBRANCH, + XPM_EVENT_COHERLINEMISS, + XPM_EVENT_COHERLINEHIT, + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL + }, + { + XPM_EVENT_MAINTLBSTALL, + XPM_EVENT_STREXPASS, + XPM_EVENT_STREXFAIL, + XPM_EVENT_DATAEVICT, + XPM_EVENT_NODISPATCH, + XPM_EVENT_ISSUEEMPTY + }, + { + XPM_EVENT_INSTRRENAME, + XPM_EVENT_PREDICTFUNCRET, + XPM_EVENT_MAINEXEC, + XPM_EVENT_SECEXEC, + XPM_EVENT_LDRSTR, + XPM_EVENT_FLOATRENAME + }, + { + XPM_EVENT_NEONRENAME, + XPM_EVENT_PLDSTALL, + XPM_EVENT_WRITESTALL, + XPM_EVENT_INSTRTLBSTALL, + XPM_EVENT_DATATLBSTALL, + XPM_EVENT_INSTR_uTLBSTALL + }, + { + XPM_EVENT_DATA_uTLBSTALL, + XPM_EVENT_DMB_STALL, + XPM_EVENT_INT_CLKEN, + XPM_EVENT_DE_CLKEN, + XPM_EVENT_INSTRISB, + XPM_EVENT_INSTRDSB + }, + { + XPM_EVENT_INSTRDMB, + XPM_EVENT_EXTINT, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_PLE_OVFL, + XPM_EVENT_PLE_PROG, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_DATASTALL, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + /* Selecet event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); + } + + Xpm_ResetEventCounters(); + Xpm_EnableEventCounters(); +} + +/****************************************************************************/ +/** +* +* This function disables the event counters and returns the counter values. +* +* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_GetEventCounters(u32 *PmCtrValue) +{ + u32 Counter; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); +#ifdef __GNUC__ + PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); +#else + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + PmCtrValue[Counter] = Cp15Reg; } +#endif + } +} diff --git a/lib/bsp/standalone/src/cortexa9/xpm_counter.h b/lib/bsp/standalone/src/cortexa9/xpm_counter.h new file mode 100644 index 00000000..a7a97534 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xpm_counter.h @@ -0,0 +1,571 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* This header file contains APIs for configuring and controlling the Cortex-A9 +* Performance Monitor Events. +* Cortex-A9 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-A9 TRM. This file defines +* configurations, where value configures the event counters to count a +* set of events. +* +* Xpm_SetEvents can be used to set the event counters to count a set of events +* and Xpm_GetEventCounters can be used to read the counter values. +* +* @note +* +* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is +* being used for time keeping. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 
+* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6U + +/* The following constants define the Cortex-A9 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00U + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03U + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04U + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05U + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06U + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07U + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09U + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0AU + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0BU + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0CU + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0DU + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10U + +/* + * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11U + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12U + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40U + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41U + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42U + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which also miss in all the other + * Cortex-A9 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50U + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which hit in another Cortex-A9 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-A9 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51U + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60U + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61U + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62U + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63U + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64U + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65U + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66U + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67U + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68U + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6EU + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70U + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71U + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72U + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73U + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74U + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80U + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83U + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85U + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86U + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8AU + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8BU + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90U + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91U + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92U + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93U + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0U + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1U + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2U + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3U + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4U + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5U + +/* + * The following constants define the configurations for Cortex-A9 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(s32 PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h b/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h new file mode 100644 index 00000000..420f3859 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xpseudo_asm.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* 
+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) + #include "xpseudo_asm_iccarm.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#endif /* XPSEUDO_ASM_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h b/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h new file mode 100644 index 00000000..3a31ca93 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xreg_cortexa9.h @@ -0,0 +1,591 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* 
+* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/lib/bsp/standalone/src/cortexa9/xtime_l.c b/lib/bsp/standalone/src/cortexa9/xtime_l.c new file mode 100644 index 00000000..a8c943f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xtime_l.c @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex A9 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 
+* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Set the time in the Global Timer Counter Register. +* +* @param Value to be written to the Global Timer Counter Register. +* +* @return None. +* +* @note In multiprocessor environment reference time will reset/lost for +* all processors, when this function called by any one processor. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + /* Disable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0); + + /* Updating Global Timer Counter Register */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET, + (u32)((u32)(Xtime_Global>>32U))); + + /* Enable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1); +} + +/**************************************************************************** +* +* Get the time from the Global Timer Counter Register. +* +* @param Pointer to the location to be updated with the time. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + u32 low; + u32 high; + + /* Reading Global Timer Counter Register */ + do + { + high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET); + low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET); + } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high); + + *Xtime_Global = (((XTime) high) << 32U) | (XTime) low; +} diff --git a/lib/bsp/standalone/src/cortexa9/xtime_l.h b/lib/bsp/standalone/src/cortexa9/xtime_l.h new file mode 100644 index 00000000..338d24aa --- /dev/null +++ b/lib/bsp/standalone/src/cortexa9/xtime_l.h @@ -0,0 +1,89 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/lib/bsp/standalone/src/cortexr5/gcc/Makefile b/lib/bsp/standalone/src/cortexr5/gcc/Makefile new file mode 100644 index 00000000..3a5c8c6a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/Makefile @@ -0,0 +1,78 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +include config.make +AS=arm-none-eabi-as +CC=arm-none-eabi-gcc +AR=arm-none-eabi-ar +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ifeq ($(COMPILER) , arm-eabi-gcc) + ECC_FLAGS = += -nostartfiles +endif + +#The following flags are required for PEEP. We can remove them later +ECC_FLAGS += -mcpu=cortex-r5 \ + -mfloat-abi=soft \ + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone R5" + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + +.PHONY: include +include: standalone_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OUTS} + $(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_exit.c b/lib/bsp/standalone/src/cortexr5/gcc/_exit.c new file mode 100644 index 00000000..6a914298 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_exit.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) + { + __asm__("wfi"); + } +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_open.c b/lib/bsp/standalone/src/cortexr5/gcc/_open.c new file mode 100644 index 00000000..a4b7f824 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_open.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c b/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c new file mode 100644 index 00000000..5911b058 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/_sbrk.c @@ -0,0 +1,70 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) caddr_t _sbrk ( s32 incr ); +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + heap += incr; + + if (heap > HeapEndPtr){ + Status = (caddr_t) -1; + } + else if (prev_heap != NULL) { + Status = (caddr_t) ((void *)prev_heap); + } + else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/abort.c b/lib/bsp/standalone/src/cortexr5/gcc/abort.c new file mode 100644 index 00000000..f6450940 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/abort.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S b/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S new file mode 100644 index 00000000..72ff0705 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/asm_vectors.S @@ -0,0 +1,121 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex R5 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SWInterrupt +.globl DataAbortInterrupt +.globl PrefetchAbortInterrupt + +.globl IRQHandler +.globl prof_pc + +.section .vectors, "a" +_vector_table: + ldr pc,=_boot + ldr pc,=Undefined + ldr pc,=SVCHandler + ldr pc,=PrefetchAbortHandler + ldr pc,=DataAbortHandler + NOP /* Placeholder for address exception vector*/ + ldr pc,=IRQHandler + ldr pc,=FIQHandler + +.text +IRQHandler: /* IRQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ + bl IRQInterrupt /* IRQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +FIQLoop: + bl FIQInterrupt /* FIQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +Undefined: /* Undefined handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + b _prestart + movs pc, lr + +SVCHandler: /* SWI handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + tst r0, #0x20 /* check the T bit */ + ldrneh r0, [lr,#-2] /* Thumb mode */ + bicne r0, r0, #0xff00 /* Thumb mode */ + ldreq r0, [lr,#-4] /* ARM mode */ + biceq r0, r0, #0xff000000 /* ARM mode */ + bl SWInterrupt /* SWInterrupt: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + movs pc, lr /* adjust return */ + +DataAbortHandler: /* Data Abort handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #8 /* adjust return */ + +PrefetchAbortHandler: /* Prefetch Abort handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/boot.S b/lib/bsp/standalone/src/cortexr5/gcc/boot.S new file mode 100644 index 00000000..28ef3c4d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/boot.S @@ -0,0 +1,205 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* This file contains the initial startup code for the Cortex R5 processor +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp  02/10/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xparameters.h" + + +.global _prestart +.global _boot +.global __stack +.global __irq_stack +.global __supervisor_stack +.global __abort_stack +.global __fiq_stack +.global __undef_stack +.global _vector_table + + +/* Stack Pointer locations for boot code */ +.set Undef_stack, __undef_stack +.set FIQ_stack, __fiq_stack +.set Abort_stack, __abort_stack +.set SPV_stack, __supervisor_stack +.set IRQ_stack, __irq_stack +.set SYS_stack, __stack + +.set vector_base, _vector_table + +.section .boot,"axS" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + + + +OKToRun: + +/* Initialize processor registers to 0 */ + mov r0,#0 + mov r1,#0 + mov r2,#0 + mov r3,#0 + mov r4,#0 + mov r5,#0 + mov r6,#0 + mov r7,#0 + mov r8,#0 + mov r9,#0 + mov r10,#0 + mov r11,#0 + mov r12,#0 + +/* Disable MPU and caches */ + mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ + bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */ + bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */ + dsb /* Ensure all previous loads/stores have completed */ + mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ + isb /* Ensure subsequent insts execute wrt new MPU settings */ + +/* Disable Branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */ + orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ + orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + dsb /* Complete all outstanding explicit memory operations*/ + +/* Invalidate caches */ + mov r0,#0 /* r0 = 0 */ + dsb + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ + isb + +/* Initialize stack pointer for various mode */ + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the irq stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x12 /* IRQ mode */ + msr cpsr, r2 + ldr r13,=IRQ_stack /* IRQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the supervisor stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x13 /* supervisor mode */ + msr cpsr, r2 + ldr r13,=SPV_stack /* Supervisor stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Abort stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x17 /* Abort mode */ + msr cpsr, r2 + ldr r13,=Abort_stack /* Abort stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the FIQ stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x11 /* FIQ mode */ + msr cpsr, r2 + ldr r13,=FIQ_stack /* FIQ stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Undefine stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1b /* Undefine mode */ + msr cpsr, r2 + ldr r13,=Undef_stack /* Undefine stack pointer */ + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the system stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1F /* SYS mode */ + msr cpsr, r2 + ldr r13,=SYS_stack /* SYS stack pointer */ + + bl Init_MPU /* Initialize MPU */ + +/* Enable Branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/ + bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + +/* Enable icahce and dcache */ + mrc p15,0,r1,c1,c0,0 + ldr r0, =0x1005 + orr r1,r1,r0 + dsb + mcr p15,0,r1,c1,c0,0 /* Enable cache */ + isb /* isb flush prefetch buffer */ + +/* + * Currently OpenAMP is supported only with HIVEC + * exception vectors are set to LOVEC if BSP is not built + * for OpenAMP as the default state is HIVEC + */ + +#if USEAMP != 1 +/*set exception vector to LOVEC */ + mrc p15, 0, r0, c1, c0, 0 + mvn r1, #0x2000 + and r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 +#endif + b _startup /* jump to C startup code */ + + +.Ldone: b .Ldone /* Paranoia: we should never get here */ + + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/close.c b/lib/bsp/standalone/src/cortexr5/gcc/close.c new file mode 100644 index 00000000..38bc6dca --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/close.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _close(s32 fd); +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S b/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S new file mode 100644 index 00000000..6ed4788f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/cpu_init.S @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file cpu_init.s +* +* This file contains CPU specific initialization. Invoked from main CRT +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + .text + .global __cpu_init + .align 2 +__cpu_init: + +/* Clear cp15 regs with unknown reset values */ + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 /* DFSR */ + mcr p15, 0, r0, c5, c0, 1 /* IFSR */ + mcr p15, 0, r0, c6, c0, 0 /* DFAR */ + mcr p15, 0, r0, c6, c0, 2 /* IFAR */ + mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ + mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ + mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ + + +/* Reset and start Cycle Counter */ + mov r2, #0x80000000 /* clear overflow */ + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd /* D, C, E */ + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 /* enable cycle counter */ + mcr p15, 0, r2, c9, c12, 1 + + bx lr + +.end diff --git a/lib/bsp/standalone/src/cortexr5/gcc/errno.c b/lib/bsp/standalone/src/cortexr5/gcc/errno.c new file mode 100644 index 00000000..c0b1d14f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/errno.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 * __errno (void); +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c b/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c new file mode 100644 index 00000000..63d390af --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/fcntl.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/fstat.c b/lib/bsp/standalone/src/cortexr5/gcc/fstat.c new file mode 100644 index 00000000..a1d394c9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/fstat.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/getpid.c b/lib/bsp/standalone/src/cortexr5/gcc/getpid.c new file mode 100644 index 00000000..73c7902a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/getpid.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _getpid(void); +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/isatty.c b/lib/bsp/standalone/src/cortexr5/gcc/isatty.c new file mode 100644 index 00000000..d0a8a825 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/isatty.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 _isatty(sint32 fd); +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/kill.c b/lib/bsp/standalone/src/cortexr5/gcc/kill.c new file mode 100644 index 00000000..fdbcb600 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/kill.c @@ -0,0 +1,60 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _kill(s32 pid, s32 sig); +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) s32 kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(s32 pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/lseek.c b/lib/bsp/standalone/src/cortexr5/gcc/lseek.c new file mode 100644 index 00000000..0a3a1fa8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/lseek.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/open.c b/lib/bsp/standalone/src/cortexr5/gcc/open.c new file mode 100644 index 00000000..914438f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/open.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* Use toolchain function for openamp applications*/ + +#ifndef USEAMP + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void *)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif diff --git a/lib/bsp/standalone/src/cortexr5/gcc/read.c b/lib/bsp/standalone/src/cortexr5/gcc/read.c new file mode 100644 index 00000000..398994ca --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/read.c @@ -0,0 +1,115 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/* Use toolchain function for openamp applications*/ + +#ifndef USEAMP + +/* read.c -- read bytes from a input device. + */ + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDIN_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + *LocalBuf = inbyte(); + if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { + break; + } + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + + return (i + 1); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} +#endif diff --git a/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c b/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c new file mode 100644 index 00000000..78b58091 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/sbrk.c @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) char8 *sbrk (s32 nbytes); +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if(heap_ptr != NULL) { + heap_ptr += nbytes; + } + +/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ + if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/unlink.c b/lib/bsp/standalone/src/cortexr5/gcc/unlink.c new file mode 100644 index 00000000..77cc0093 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/unlink.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) sint32 unlink(char8 *path); +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void *)path; + errno = EIO; + return (-1); +} diff --git a/lib/bsp/standalone/src/cortexr5/gcc/write.c b/lib/bsp/standalone/src/cortexr5/gcc/write.c new file mode 100644 index 00000000..55ff0d18 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/write.c @@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/* Use toolchain function for openamp applications*/ + +#ifndef USEAMP + +/* write.c -- write bytes to an output device. + */ + +#include "xparameters.h" +#include "xil_printf.h" + +#ifdef __cplusplus +extern "C" { + __attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes); +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) s32 +write (s32 fd, char8* buf, s32 nbytes) + +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_write (s32 fd, char8* buf, s32 nbytes) +{ +#ifdef STDOUT_BASEADDRESS + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} +#endif diff --git a/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S b/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S new file mode 100644 index 00000000..d296c834 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/xil-crt0.S @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/10/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start__ + +.Lbss_end: + .long __bss_end__ + +.Lstack: + .long __stack + + + .globl _startup + +_startup: + bl __cpu_init /* Initialize the CPU first (BSP provides this) */ + + mov r0, #0 + + /* clear sbss */ + ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr r2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp r1,r2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + +/* + * Uart is not initialized for OpenAMP applications + * as master processor would be controlling and using the Uart + */ +#if USEAMP != 1 + bl Init_Uart /* Initialize UART */ +#endif + bl main /* Jump to main C code */ + + bl _exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _startup,.Lstart-_startup diff --git a/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h new file mode 100644 index 00000000..5efe0126 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/gcc/xpseudo_asm_gcc.h @@ -0,0 +1,175 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/lib/bsp/standalone/src/cortexr5/mpu.c b/lib/bsp/standalone/src/cortexr5/mpu.c new file mode 100644 index 00000000..296c163d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/mpu.c @@ -0,0 +1,197 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file mpu.c +* +* This file contains initial configuration of the MPU. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xreg_cortexr5.h" +#include "xil_mpu.h" +#include "xpseudo_asm.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void Init_MPU(void); +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); +static void Xil_DisableMPURegions(void); + +/***************************************************************************** +* +* Initialize MPU for a given address map and Enabled the background Region in +* MPU with default memory attributes for rest of address range for Cortex R5 +* processor. +* +* @param None. +* +* @return None. +* +* +******************************************************************************/ + +void Init_MPU(void) +{ + u32 Addr; + u32 RegSize; + u32 Attrib; + u32 RegNum = 0; + + Xil_DisableMPURegions(); + + Addr = 0x00000000U; + RegSize = REGION_2G; + Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xC0000000U; + RegSize = REGION_512M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xF0000000U; + RegSize = REGION_128M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xF8000000U; + RegSize = REGION_64M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xFC000000U; + RegSize = REGION_32M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xFE000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xFF000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + Addr = 0xFFFC0000U; + RegSize = REGION_256K; + Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + +} + +/***************************************************************************** +* +* Set the memory attributes for a section of memory with starting address addr +* of the region size defined by reg_size having attributes attrib of region number +* reg_num +* +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. +* +* +******************************************************************************/ +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) +{ + u32 Local_reg_size = reg_size; + + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); + isb(); /* synchronize context on this processor */ +} + + +/***************************************************************************** +* +* Disable all the MPU regions if any of them is enabled +* +* @param None. +* +* @return None. +* +* +******************************************************************************/ +static void Xil_DisableMPURegions(void) +{ + u32 Temp; + u32 Index; + for (Index = 0; Index <= 15; Index++) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + } + +} \ No newline at end of file diff --git a/lib/bsp/standalone/src/cortexr5/print.c b/lib/bsp/standalone/src/cortexr5/print.c new file mode 100644 index 00000000..31d7b198 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/print.c @@ -0,0 +1,32 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + */ + +/* + * print -- do a raw print of a string + */ +#include "xil_printf.h" + +void print(const char8 *ptr) +{ +#ifdef STDOUT_BASEADDRESS + while (*ptr != (char8)0) { + outbyte (*ptr); + *ptr++; + } +#else +(void)ptr; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/putnum.c b/lib/bsp/standalone/src/cortexr5/putnum.c new file mode 100644 index 00000000..86d3a74e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/putnum.c @@ -0,0 +1,59 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +/* + * putnum -- print a 32 bit number in hex + */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Function Prototypes ******************************/ +extern void print (const char8 *ptr); +void putnum(u32 num); + +void putnum(u32 num) +{ + char8 buf[9]; + u32 cnt; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 7U ; cnt >= 0U ; cnt--) { + digit = (num >> (cnt * 4U)) & 0x0000000fU; + + if ((digit <= 9U) && (ptr != NULL)) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else if (ptr != NULL) { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } else { + /*Made for MisraC Compliance*/; + } + } + + if(ptr != NULL) { + *ptr = (char8) 0; + } + print (buf); +} diff --git a/lib/bsp/standalone/src/cortexr5/sleep.c b/lib/bsp/standalone/src/cortexr5/sleep.c new file mode 100644 index 00000000..5ea6ef6f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/sleep.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex R5 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +/*****************************************************************************/ +/* +* +* This API is used to provide delays in seconds. Maximum value of seconds +* attained with sleep routine is 10995 +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +****************************************************************************/ + +s32 sleep(u32 seconds) +{ + + XTime tEnd, tCur; + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x00000001U); + /*set prescale value*/ + Xil_Out32(TTC3_BASEADDR + 0x00000000U,0x0000000DU); + /*write interval value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000024U,0xFFFFFFFFU); + /*write match value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000030U,0xFFFFFFFFU); + /* Enable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x0000001AU); + + XTime_GetTime(&tCur); + + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + + } while (tCur < tEnd); + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU, Xil_In32(TTC3_BASEADDR + 0x0000000CU) | 0x00000001U); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/sleep.h b/lib/bsp/standalone/src/cortexr5/sleep.h new file mode 100644 index 00000000..6257e6c2 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/sleep.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_types.h" +#include "xil_io.h" + +s32 usleep(u32 useconds); +s32 sleep(u32 seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/uart.c b/lib/bsp/standalone/src/cortexr5/uart.c new file mode 100644 index 00000000..615a0694 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/uart.c @@ -0,0 +1,160 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file uart.c +* +* This file contains APIs for configuring the UART. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_types.h" +#include "xparameters.h" +#include "xil_assert.h" +#include "xil_io.h" + +/* Register offsets */ +#define UART_CR_OFFSET 0x00000000U +#define UART_MR_OFFSET 0x00000004U +#define UART_BAUDGEN_OFFSET 0x00000018U +#define UART_BAUDDIV_OFFSET 0x00000034U + +#define MAX_BAUD_ERROR_RATE 0x00000003U /* max % error allowed */ +#define UART_BAUDRATE 115200U +#define CSU_VERSION_REG 0xFFCA0044U + +void Init_Uart(void); + +void Init_Uart(void) +{ +#ifdef STDOUT_BASEADDRESS + u8 IterBAUDDIV; /* Iterator for available baud divisor values */ + u32 BRGR_Value; /* Calculated value for baud rate generator */ + u32 CalcBaudRate; /* Calculated baud rate */ + u32 BaudError; /* Diff between calculated and requested baud rate */ + u32 Best_BRGR = 0U; /* Best value for baud rate generator */ + u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */ + u32 Best_Error = 0xFFFFFFFFU; + u32 PercentError; + u32 InputClk; + u32 BaudRate = UART_BAUDRATE; + +#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) + InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ; +#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) + InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ; +#else + /* STDIO is not set or axi_uart is being used for STDIO */ + return; +#endif +InputClk = 25000000U; + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) { + + /* + * Calculate the value for BRGR register + */ + BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U)); + + /* + * Calculate the baud rate from the BRGR value + */ + CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U)); + + /* + * Avoid unsigned integer underflow + */ + if (BaudRate > CalcBaudRate) { + BaudError = BaudRate - CalcBaudRate; + } else { + BaudError = CalcBaudRate - BaudRate; + } + + /* + * Find the calculated baud rate closest to requested baud rate. + */ + if (Best_Error > BaudError) { + + Best_BRGR = BRGR_Value; + Best_BAUDDIV = IterBAUDDIV; + Best_Error = BaudError; + + } + } + + /* + * Make sure the best error is not too large. + */ + PercentError = (Best_Error * 100U) / BaudRate; + if (MAX_BAUD_ERROR_RATE < PercentError) { + return; + } + + /* set CD and BDIV */ + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV); + + /* + * Veloce specific code + */ + if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) { + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U); + Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U); + } + + /* + * 8 data, 1 stop, 0 parity bits + * sel_clk=uart_clk=APB clock + */ + Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U); + + /* enable Tx/Rx and reset Tx/Rx data path */ + Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U); + + return; +#endif +} diff --git a/lib/bsp/standalone/src/cortexr5/usleep.c b/lib/bsp/standalone/src/cortexr5/usleep.c new file mode 100644 index 00000000..934ec01b --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/usleep.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex R5 MP core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xreg_cortexr5.h" + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND 25U + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ + +s32 usleep(u32 useconds) +{ + XTime tEnd, tCur; + /*disable ttc timer*/ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1U); + /*set prescale value*/ + Xil_Out32(TTC3_BASEADDR + 0x00000000U, 0x000001U); + /*write interval value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000024U,0xFFFFFFFFU); + /*write match value to register*/ + Xil_Out32(TTC3_BASEADDR + 0x00000030U,0xFFFFFFFFU); + /* Enable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1AU); + + XTime_GetTime(&tCur); + + tEnd = tCur + (((XTime) useconds) * (COUNTS_PER_USECOND)); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); + + /* Disable ttc Timer */ + Xil_Out32(TTC3_BASEADDR + 0x0000000CU, Xil_In32(TTC3_BASEADDR + 0x0000000CU) | 0x00000001U); + + return 0; +} diff --git a/lib/bsp/standalone/src/cortexr5/vectors.c b/lib/bsp/standalone/src/cortexr5/vectors.c new file mode 100644 index 00000000..0c25b278 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/vectors.c @@ -0,0 +1,168 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex R5 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/************************** Function Prototypes ******************************/ + + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} diff --git a/lib/bsp/standalone/src/cortexr5/vectors.h b/lib/bsp/standalone/src/cortexr5/vectors.h new file mode 100644 index 00000000..cbb53ae4 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/vectors.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex R5 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef VECTORS_H_ +#define VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h new file mode 100644 index 00000000..9029bead --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU0_CFG_H__ +#define __XDDR_XMPU0_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu0Cfg Base Address + */ +#define XDDR_XMPU0_CFG_BASEADDR 0xFD000000UL + +/** + * Register: XddrXmpu0CfgCtrl + */ +#define XDDR_XMPU0_CFG_CTRL ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU0_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgErrSts1 + */ +#define XDDR_XMPU0_CFG_ERR_STS1 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgErrSts2 + */ +#define XDDR_XMPU0_CFG_ERR_STS2 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgPoison + */ +#define XDDR_XMPU0_CFG_POISON ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU0_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU0_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIsr + */ +#define XDDR_XMPU0_CFG_ISR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU0_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgImr + */ +#define XDDR_XMPU0_CFG_IMR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU0_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu0CfgIen + */ +#define XDDR_XMPU0_CFG_IEN ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU0_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgIds + */ +#define XDDR_XMPU0_CFG_IDS ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU0_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgLock + */ +#define XDDR_XMPU0_CFG_LOCK ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU0_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Strt + */ +#define XDDR_XMPU0_CFG_R00_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00End + */ +#define XDDR_XMPU0_CFG_R00_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU0_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00Mstr + */ +#define XDDR_XMPU0_CFG_R00_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR00 + */ +#define XDDR_XMPU0_CFG_R00 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU0_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Strt + */ +#define XDDR_XMPU0_CFG_R01_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01End + */ +#define XDDR_XMPU0_CFG_R01_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU0_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01Mstr + */ +#define XDDR_XMPU0_CFG_R01_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR01 + */ +#define XDDR_XMPU0_CFG_R01 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU0_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Strt + */ +#define XDDR_XMPU0_CFG_R02_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02End + */ +#define XDDR_XMPU0_CFG_R02_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU0_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02Mstr + */ +#define XDDR_XMPU0_CFG_R02_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR02 + */ +#define XDDR_XMPU0_CFG_R02 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU0_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Strt + */ +#define XDDR_XMPU0_CFG_R03_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03End + */ +#define XDDR_XMPU0_CFG_R03_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU0_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03Mstr + */ +#define XDDR_XMPU0_CFG_R03_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR03 + */ +#define XDDR_XMPU0_CFG_R03 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU0_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Strt + */ +#define XDDR_XMPU0_CFG_R04_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04End + */ +#define XDDR_XMPU0_CFG_R04_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU0_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04Mstr + */ +#define XDDR_XMPU0_CFG_R04_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR04 + */ +#define XDDR_XMPU0_CFG_R04 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU0_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Strt + */ +#define XDDR_XMPU0_CFG_R05_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05End + */ +#define XDDR_XMPU0_CFG_R05_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU0_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05Mstr + */ +#define XDDR_XMPU0_CFG_R05_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR05 + */ +#define XDDR_XMPU0_CFG_R05 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU0_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Strt + */ +#define XDDR_XMPU0_CFG_R06_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06End + */ +#define XDDR_XMPU0_CFG_R06_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU0_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06Mstr + */ +#define XDDR_XMPU0_CFG_R06_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR06 + */ +#define XDDR_XMPU0_CFG_R06 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU0_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Strt + */ +#define XDDR_XMPU0_CFG_R07_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07End + */ +#define XDDR_XMPU0_CFG_R07_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU0_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07Mstr + */ +#define XDDR_XMPU0_CFG_R07_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR07 + */ +#define XDDR_XMPU0_CFG_R07 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU0_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Strt + */ +#define XDDR_XMPU0_CFG_R08_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08End + */ +#define XDDR_XMPU0_CFG_R08_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU0_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08Mstr + */ +#define XDDR_XMPU0_CFG_R08_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR08 + */ +#define XDDR_XMPU0_CFG_R08 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU0_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Strt + */ +#define XDDR_XMPU0_CFG_R09_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09End + */ +#define XDDR_XMPU0_CFG_R09_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU0_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09Mstr + */ +#define XDDR_XMPU0_CFG_R09_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR09 + */ +#define XDDR_XMPU0_CFG_R09 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU0_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Strt + */ +#define XDDR_XMPU0_CFG_R10_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10End + */ +#define XDDR_XMPU0_CFG_R10_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU0_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10Mstr + */ +#define XDDR_XMPU0_CFG_R10_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR10 + */ +#define XDDR_XMPU0_CFG_R10 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU0_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Strt + */ +#define XDDR_XMPU0_CFG_R11_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11End + */ +#define XDDR_XMPU0_CFG_R11_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU0_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11Mstr + */ +#define XDDR_XMPU0_CFG_R11_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR11 + */ +#define XDDR_XMPU0_CFG_R11 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU0_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Strt + */ +#define XDDR_XMPU0_CFG_R12_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12End + */ +#define XDDR_XMPU0_CFG_R12_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU0_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12Mstr + */ +#define XDDR_XMPU0_CFG_R12_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR12 + */ +#define XDDR_XMPU0_CFG_R12 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU0_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Strt + */ +#define XDDR_XMPU0_CFG_R13_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13End + */ +#define XDDR_XMPU0_CFG_R13_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU0_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13Mstr + */ +#define XDDR_XMPU0_CFG_R13_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR13 + */ +#define XDDR_XMPU0_CFG_R13 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU0_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Strt + */ +#define XDDR_XMPU0_CFG_R14_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14End + */ +#define XDDR_XMPU0_CFG_R14_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU0_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14Mstr + */ +#define XDDR_XMPU0_CFG_R14_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR14 + */ +#define XDDR_XMPU0_CFG_R14 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU0_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Strt + */ +#define XDDR_XMPU0_CFG_R15_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15End + */ +#define XDDR_XMPU0_CFG_R15_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU0_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15Mstr + */ +#define XDDR_XMPU0_CFG_R15_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu0CfgR15 + */ +#define XDDR_XMPU0_CFG_R15 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU0_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU0_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU0_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU0_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU0_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU0_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h new file mode 100644 index 00000000..e2fa6d4a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU1_CFG_H__ +#define __XDDR_XMPU1_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu1Cfg Base Address + */ +#define XDDR_XMPU1_CFG_BASEADDR 0xFD010000UL + +/** + * Register: XddrXmpu1CfgCtrl + */ +#define XDDR_XMPU1_CFG_CTRL ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU1_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgErrSts1 + */ +#define XDDR_XMPU1_CFG_ERR_STS1 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgErrSts2 + */ +#define XDDR_XMPU1_CFG_ERR_STS2 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgPoison + */ +#define XDDR_XMPU1_CFG_POISON ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU1_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU1_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIsr + */ +#define XDDR_XMPU1_CFG_ISR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU1_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgImr + */ +#define XDDR_XMPU1_CFG_IMR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU1_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu1CfgIen + */ +#define XDDR_XMPU1_CFG_IEN ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU1_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgIds + */ +#define XDDR_XMPU1_CFG_IDS ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU1_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgLock + */ +#define XDDR_XMPU1_CFG_LOCK ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU1_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Strt + */ +#define XDDR_XMPU1_CFG_R00_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00End + */ +#define XDDR_XMPU1_CFG_R00_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU1_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00Mstr + */ +#define XDDR_XMPU1_CFG_R00_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR00 + */ +#define XDDR_XMPU1_CFG_R00 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU1_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Strt + */ +#define XDDR_XMPU1_CFG_R01_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01End + */ +#define XDDR_XMPU1_CFG_R01_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU1_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01Mstr + */ +#define XDDR_XMPU1_CFG_R01_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR01 + */ +#define XDDR_XMPU1_CFG_R01 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU1_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Strt + */ +#define XDDR_XMPU1_CFG_R02_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02End + */ +#define XDDR_XMPU1_CFG_R02_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU1_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02Mstr + */ +#define XDDR_XMPU1_CFG_R02_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR02 + */ +#define XDDR_XMPU1_CFG_R02 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU1_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Strt + */ +#define XDDR_XMPU1_CFG_R03_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03End + */ +#define XDDR_XMPU1_CFG_R03_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU1_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03Mstr + */ +#define XDDR_XMPU1_CFG_R03_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR03 + */ +#define XDDR_XMPU1_CFG_R03 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU1_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Strt + */ +#define XDDR_XMPU1_CFG_R04_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04End + */ +#define XDDR_XMPU1_CFG_R04_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU1_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04Mstr + */ +#define XDDR_XMPU1_CFG_R04_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR04 + */ +#define XDDR_XMPU1_CFG_R04 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU1_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Strt + */ +#define XDDR_XMPU1_CFG_R05_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05End + */ +#define XDDR_XMPU1_CFG_R05_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU1_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05Mstr + */ +#define XDDR_XMPU1_CFG_R05_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR05 + */ +#define XDDR_XMPU1_CFG_R05 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU1_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Strt + */ +#define XDDR_XMPU1_CFG_R06_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06End + */ +#define XDDR_XMPU1_CFG_R06_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU1_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06Mstr + */ +#define XDDR_XMPU1_CFG_R06_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR06 + */ +#define XDDR_XMPU1_CFG_R06 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU1_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Strt + */ +#define XDDR_XMPU1_CFG_R07_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07End + */ +#define XDDR_XMPU1_CFG_R07_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU1_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07Mstr + */ +#define XDDR_XMPU1_CFG_R07_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR07 + */ +#define XDDR_XMPU1_CFG_R07 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU1_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Strt + */ +#define XDDR_XMPU1_CFG_R08_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08End + */ +#define XDDR_XMPU1_CFG_R08_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU1_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08Mstr + */ +#define XDDR_XMPU1_CFG_R08_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR08 + */ +#define XDDR_XMPU1_CFG_R08 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU1_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Strt + */ +#define XDDR_XMPU1_CFG_R09_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09End + */ +#define XDDR_XMPU1_CFG_R09_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU1_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09Mstr + */ +#define XDDR_XMPU1_CFG_R09_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR09 + */ +#define XDDR_XMPU1_CFG_R09 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU1_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Strt + */ +#define XDDR_XMPU1_CFG_R10_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10End + */ +#define XDDR_XMPU1_CFG_R10_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU1_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10Mstr + */ +#define XDDR_XMPU1_CFG_R10_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR10 + */ +#define XDDR_XMPU1_CFG_R10 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU1_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Strt + */ +#define XDDR_XMPU1_CFG_R11_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11End + */ +#define XDDR_XMPU1_CFG_R11_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU1_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11Mstr + */ +#define XDDR_XMPU1_CFG_R11_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR11 + */ +#define XDDR_XMPU1_CFG_R11 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU1_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Strt + */ +#define XDDR_XMPU1_CFG_R12_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12End + */ +#define XDDR_XMPU1_CFG_R12_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU1_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12Mstr + */ +#define XDDR_XMPU1_CFG_R12_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR12 + */ +#define XDDR_XMPU1_CFG_R12 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU1_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Strt + */ +#define XDDR_XMPU1_CFG_R13_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13End + */ +#define XDDR_XMPU1_CFG_R13_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU1_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13Mstr + */ +#define XDDR_XMPU1_CFG_R13_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR13 + */ +#define XDDR_XMPU1_CFG_R13 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU1_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Strt + */ +#define XDDR_XMPU1_CFG_R14_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14End + */ +#define XDDR_XMPU1_CFG_R14_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU1_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14Mstr + */ +#define XDDR_XMPU1_CFG_R14_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR14 + */ +#define XDDR_XMPU1_CFG_R14 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU1_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Strt + */ +#define XDDR_XMPU1_CFG_R15_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15End + */ +#define XDDR_XMPU1_CFG_R15_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU1_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15Mstr + */ +#define XDDR_XMPU1_CFG_R15_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu1CfgR15 + */ +#define XDDR_XMPU1_CFG_R15 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU1_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU1_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU1_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU1_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU1_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU1_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h new file mode 100644 index 00000000..55ea2a7d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU2_CFG_H__ +#define __XDDR_XMPU2_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu2Cfg Base Address + */ +#define XDDR_XMPU2_CFG_BASEADDR 0xFD020000UL + +/** + * Register: XddrXmpu2CfgCtrl + */ +#define XDDR_XMPU2_CFG_CTRL ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU2_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgErrSts1 + */ +#define XDDR_XMPU2_CFG_ERR_STS1 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgErrSts2 + */ +#define XDDR_XMPU2_CFG_ERR_STS2 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgPoison + */ +#define XDDR_XMPU2_CFG_POISON ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU2_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU2_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIsr + */ +#define XDDR_XMPU2_CFG_ISR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU2_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgImr + */ +#define XDDR_XMPU2_CFG_IMR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU2_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu2CfgIen + */ +#define XDDR_XMPU2_CFG_IEN ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU2_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgIds + */ +#define XDDR_XMPU2_CFG_IDS ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU2_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgLock + */ +#define XDDR_XMPU2_CFG_LOCK ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU2_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Strt + */ +#define XDDR_XMPU2_CFG_R00_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00End + */ +#define XDDR_XMPU2_CFG_R00_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU2_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00Mstr + */ +#define XDDR_XMPU2_CFG_R00_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR00 + */ +#define XDDR_XMPU2_CFG_R00 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU2_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Strt + */ +#define XDDR_XMPU2_CFG_R01_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01End + */ +#define XDDR_XMPU2_CFG_R01_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU2_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01Mstr + */ +#define XDDR_XMPU2_CFG_R01_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR01 + */ +#define XDDR_XMPU2_CFG_R01 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU2_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Strt + */ +#define XDDR_XMPU2_CFG_R02_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02End + */ +#define XDDR_XMPU2_CFG_R02_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU2_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02Mstr + */ +#define XDDR_XMPU2_CFG_R02_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR02 + */ +#define XDDR_XMPU2_CFG_R02 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU2_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Strt + */ +#define XDDR_XMPU2_CFG_R03_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03End + */ +#define XDDR_XMPU2_CFG_R03_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU2_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03Mstr + */ +#define XDDR_XMPU2_CFG_R03_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR03 + */ +#define XDDR_XMPU2_CFG_R03 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU2_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Strt + */ +#define XDDR_XMPU2_CFG_R04_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04End + */ +#define XDDR_XMPU2_CFG_R04_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU2_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04Mstr + */ +#define XDDR_XMPU2_CFG_R04_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR04 + */ +#define XDDR_XMPU2_CFG_R04 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU2_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Strt + */ +#define XDDR_XMPU2_CFG_R05_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05End + */ +#define XDDR_XMPU2_CFG_R05_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU2_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05Mstr + */ +#define XDDR_XMPU2_CFG_R05_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR05 + */ +#define XDDR_XMPU2_CFG_R05 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU2_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Strt + */ +#define XDDR_XMPU2_CFG_R06_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06End + */ +#define XDDR_XMPU2_CFG_R06_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU2_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06Mstr + */ +#define XDDR_XMPU2_CFG_R06_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR06 + */ +#define XDDR_XMPU2_CFG_R06 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU2_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Strt + */ +#define XDDR_XMPU2_CFG_R07_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07End + */ +#define XDDR_XMPU2_CFG_R07_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU2_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07Mstr + */ +#define XDDR_XMPU2_CFG_R07_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR07 + */ +#define XDDR_XMPU2_CFG_R07 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU2_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Strt + */ +#define XDDR_XMPU2_CFG_R08_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08End + */ +#define XDDR_XMPU2_CFG_R08_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU2_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08Mstr + */ +#define XDDR_XMPU2_CFG_R08_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR08 + */ +#define XDDR_XMPU2_CFG_R08 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU2_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Strt + */ +#define XDDR_XMPU2_CFG_R09_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09End + */ +#define XDDR_XMPU2_CFG_R09_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU2_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09Mstr + */ +#define XDDR_XMPU2_CFG_R09_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR09 + */ +#define XDDR_XMPU2_CFG_R09 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU2_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Strt + */ +#define XDDR_XMPU2_CFG_R10_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10End + */ +#define XDDR_XMPU2_CFG_R10_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU2_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10Mstr + */ +#define XDDR_XMPU2_CFG_R10_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR10 + */ +#define XDDR_XMPU2_CFG_R10 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU2_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Strt + */ +#define XDDR_XMPU2_CFG_R11_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11End + */ +#define XDDR_XMPU2_CFG_R11_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU2_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11Mstr + */ +#define XDDR_XMPU2_CFG_R11_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR11 + */ +#define XDDR_XMPU2_CFG_R11 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU2_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Strt + */ +#define XDDR_XMPU2_CFG_R12_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12End + */ +#define XDDR_XMPU2_CFG_R12_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU2_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12Mstr + */ +#define XDDR_XMPU2_CFG_R12_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR12 + */ +#define XDDR_XMPU2_CFG_R12 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU2_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Strt + */ +#define XDDR_XMPU2_CFG_R13_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13End + */ +#define XDDR_XMPU2_CFG_R13_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU2_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13Mstr + */ +#define XDDR_XMPU2_CFG_R13_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR13 + */ +#define XDDR_XMPU2_CFG_R13 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU2_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Strt + */ +#define XDDR_XMPU2_CFG_R14_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14End + */ +#define XDDR_XMPU2_CFG_R14_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU2_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14Mstr + */ +#define XDDR_XMPU2_CFG_R14_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR14 + */ +#define XDDR_XMPU2_CFG_R14 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU2_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Strt + */ +#define XDDR_XMPU2_CFG_R15_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15End + */ +#define XDDR_XMPU2_CFG_R15_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU2_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15Mstr + */ +#define XDDR_XMPU2_CFG_R15_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu2CfgR15 + */ +#define XDDR_XMPU2_CFG_R15 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU2_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU2_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU2_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU2_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU2_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU2_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h new file mode 100644 index 00000000..41631496 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU3_CFG_H__ +#define __XDDR_XMPU3_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu3Cfg Base Address + */ +#define XDDR_XMPU3_CFG_BASEADDR 0xFD030000UL + +/** + * Register: XddrXmpu3CfgCtrl + */ +#define XDDR_XMPU3_CFG_CTRL ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU3_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgErrSts1 + */ +#define XDDR_XMPU3_CFG_ERR_STS1 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgErrSts2 + */ +#define XDDR_XMPU3_CFG_ERR_STS2 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgPoison + */ +#define XDDR_XMPU3_CFG_POISON ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU3_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU3_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIsr + */ +#define XDDR_XMPU3_CFG_ISR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU3_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgImr + */ +#define XDDR_XMPU3_CFG_IMR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU3_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu3CfgIen + */ +#define XDDR_XMPU3_CFG_IEN ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU3_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgIds + */ +#define XDDR_XMPU3_CFG_IDS ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU3_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgLock + */ +#define XDDR_XMPU3_CFG_LOCK ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU3_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Strt + */ +#define XDDR_XMPU3_CFG_R00_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00End + */ +#define XDDR_XMPU3_CFG_R00_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU3_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00Mstr + */ +#define XDDR_XMPU3_CFG_R00_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR00 + */ +#define XDDR_XMPU3_CFG_R00 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU3_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Strt + */ +#define XDDR_XMPU3_CFG_R01_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01End + */ +#define XDDR_XMPU3_CFG_R01_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU3_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01Mstr + */ +#define XDDR_XMPU3_CFG_R01_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR01 + */ +#define XDDR_XMPU3_CFG_R01 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU3_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Strt + */ +#define XDDR_XMPU3_CFG_R02_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02End + */ +#define XDDR_XMPU3_CFG_R02_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU3_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02Mstr + */ +#define XDDR_XMPU3_CFG_R02_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR02 + */ +#define XDDR_XMPU3_CFG_R02 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU3_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Strt + */ +#define XDDR_XMPU3_CFG_R03_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03End + */ +#define XDDR_XMPU3_CFG_R03_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU3_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03Mstr + */ +#define XDDR_XMPU3_CFG_R03_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR03 + */ +#define XDDR_XMPU3_CFG_R03 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU3_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Strt + */ +#define XDDR_XMPU3_CFG_R04_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04End + */ +#define XDDR_XMPU3_CFG_R04_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU3_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04Mstr + */ +#define XDDR_XMPU3_CFG_R04_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR04 + */ +#define XDDR_XMPU3_CFG_R04 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU3_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Strt + */ +#define XDDR_XMPU3_CFG_R05_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05End + */ +#define XDDR_XMPU3_CFG_R05_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU3_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05Mstr + */ +#define XDDR_XMPU3_CFG_R05_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR05 + */ +#define XDDR_XMPU3_CFG_R05 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU3_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Strt + */ +#define XDDR_XMPU3_CFG_R06_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06End + */ +#define XDDR_XMPU3_CFG_R06_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU3_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06Mstr + */ +#define XDDR_XMPU3_CFG_R06_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR06 + */ +#define XDDR_XMPU3_CFG_R06 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU3_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Strt + */ +#define XDDR_XMPU3_CFG_R07_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07End + */ +#define XDDR_XMPU3_CFG_R07_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU3_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07Mstr + */ +#define XDDR_XMPU3_CFG_R07_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR07 + */ +#define XDDR_XMPU3_CFG_R07 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU3_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Strt + */ +#define XDDR_XMPU3_CFG_R08_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08End + */ +#define XDDR_XMPU3_CFG_R08_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU3_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08Mstr + */ +#define XDDR_XMPU3_CFG_R08_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR08 + */ +#define XDDR_XMPU3_CFG_R08 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU3_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Strt + */ +#define XDDR_XMPU3_CFG_R09_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09End + */ +#define XDDR_XMPU3_CFG_R09_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU3_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09Mstr + */ +#define XDDR_XMPU3_CFG_R09_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR09 + */ +#define XDDR_XMPU3_CFG_R09 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU3_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Strt + */ +#define XDDR_XMPU3_CFG_R10_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10End + */ +#define XDDR_XMPU3_CFG_R10_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU3_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10Mstr + */ +#define XDDR_XMPU3_CFG_R10_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR10 + */ +#define XDDR_XMPU3_CFG_R10 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU3_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Strt + */ +#define XDDR_XMPU3_CFG_R11_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11End + */ +#define XDDR_XMPU3_CFG_R11_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU3_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11Mstr + */ +#define XDDR_XMPU3_CFG_R11_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR11 + */ +#define XDDR_XMPU3_CFG_R11 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU3_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Strt + */ +#define XDDR_XMPU3_CFG_R12_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12End + */ +#define XDDR_XMPU3_CFG_R12_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU3_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12Mstr + */ +#define XDDR_XMPU3_CFG_R12_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR12 + */ +#define XDDR_XMPU3_CFG_R12 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU3_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Strt + */ +#define XDDR_XMPU3_CFG_R13_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13End + */ +#define XDDR_XMPU3_CFG_R13_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU3_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13Mstr + */ +#define XDDR_XMPU3_CFG_R13_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR13 + */ +#define XDDR_XMPU3_CFG_R13 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU3_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Strt + */ +#define XDDR_XMPU3_CFG_R14_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14End + */ +#define XDDR_XMPU3_CFG_R14_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU3_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14Mstr + */ +#define XDDR_XMPU3_CFG_R14_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR14 + */ +#define XDDR_XMPU3_CFG_R14 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU3_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Strt + */ +#define XDDR_XMPU3_CFG_R15_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15End + */ +#define XDDR_XMPU3_CFG_R15_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU3_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15Mstr + */ +#define XDDR_XMPU3_CFG_R15_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu3CfgR15 + */ +#define XDDR_XMPU3_CFG_R15 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU3_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU3_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU3_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU3_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU3_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU3_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h new file mode 100644 index 00000000..2df81441 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU4_CFG_H__ +#define __XDDR_XMPU4_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu4Cfg Base Address + */ +#define XDDR_XMPU4_CFG_BASEADDR 0xFD040000UL + +/** + * Register: XddrXmpu4CfgCtrl + */ +#define XDDR_XMPU4_CFG_CTRL ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU4_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgErrSts1 + */ +#define XDDR_XMPU4_CFG_ERR_STS1 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgErrSts2 + */ +#define XDDR_XMPU4_CFG_ERR_STS2 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgPoison + */ +#define XDDR_XMPU4_CFG_POISON ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU4_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU4_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIsr + */ +#define XDDR_XMPU4_CFG_ISR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU4_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgImr + */ +#define XDDR_XMPU4_CFG_IMR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU4_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu4CfgIen + */ +#define XDDR_XMPU4_CFG_IEN ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU4_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgIds + */ +#define XDDR_XMPU4_CFG_IDS ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU4_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgLock + */ +#define XDDR_XMPU4_CFG_LOCK ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU4_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Strt + */ +#define XDDR_XMPU4_CFG_R00_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00End + */ +#define XDDR_XMPU4_CFG_R00_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU4_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00Mstr + */ +#define XDDR_XMPU4_CFG_R00_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR00 + */ +#define XDDR_XMPU4_CFG_R00 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU4_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Strt + */ +#define XDDR_XMPU4_CFG_R01_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01End + */ +#define XDDR_XMPU4_CFG_R01_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU4_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01Mstr + */ +#define XDDR_XMPU4_CFG_R01_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR01 + */ +#define XDDR_XMPU4_CFG_R01 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU4_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Strt + */ +#define XDDR_XMPU4_CFG_R02_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02End + */ +#define XDDR_XMPU4_CFG_R02_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU4_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02Mstr + */ +#define XDDR_XMPU4_CFG_R02_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR02 + */ +#define XDDR_XMPU4_CFG_R02 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU4_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Strt + */ +#define XDDR_XMPU4_CFG_R03_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03End + */ +#define XDDR_XMPU4_CFG_R03_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU4_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03Mstr + */ +#define XDDR_XMPU4_CFG_R03_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR03 + */ +#define XDDR_XMPU4_CFG_R03 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU4_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Strt + */ +#define XDDR_XMPU4_CFG_R04_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04End + */ +#define XDDR_XMPU4_CFG_R04_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU4_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04Mstr + */ +#define XDDR_XMPU4_CFG_R04_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR04 + */ +#define XDDR_XMPU4_CFG_R04 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU4_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Strt + */ +#define XDDR_XMPU4_CFG_R05_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05End + */ +#define XDDR_XMPU4_CFG_R05_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU4_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05Mstr + */ +#define XDDR_XMPU4_CFG_R05_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR05 + */ +#define XDDR_XMPU4_CFG_R05 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU4_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Strt + */ +#define XDDR_XMPU4_CFG_R06_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06End + */ +#define XDDR_XMPU4_CFG_R06_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU4_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06Mstr + */ +#define XDDR_XMPU4_CFG_R06_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR06 + */ +#define XDDR_XMPU4_CFG_R06 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU4_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Strt + */ +#define XDDR_XMPU4_CFG_R07_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07End + */ +#define XDDR_XMPU4_CFG_R07_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU4_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07Mstr + */ +#define XDDR_XMPU4_CFG_R07_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR07 + */ +#define XDDR_XMPU4_CFG_R07 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU4_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Strt + */ +#define XDDR_XMPU4_CFG_R08_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08End + */ +#define XDDR_XMPU4_CFG_R08_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU4_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08Mstr + */ +#define XDDR_XMPU4_CFG_R08_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR08 + */ +#define XDDR_XMPU4_CFG_R08 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU4_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Strt + */ +#define XDDR_XMPU4_CFG_R09_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09End + */ +#define XDDR_XMPU4_CFG_R09_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU4_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09Mstr + */ +#define XDDR_XMPU4_CFG_R09_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR09 + */ +#define XDDR_XMPU4_CFG_R09 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU4_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Strt + */ +#define XDDR_XMPU4_CFG_R10_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10End + */ +#define XDDR_XMPU4_CFG_R10_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU4_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10Mstr + */ +#define XDDR_XMPU4_CFG_R10_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR10 + */ +#define XDDR_XMPU4_CFG_R10 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU4_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Strt + */ +#define XDDR_XMPU4_CFG_R11_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11End + */ +#define XDDR_XMPU4_CFG_R11_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU4_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11Mstr + */ +#define XDDR_XMPU4_CFG_R11_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR11 + */ +#define XDDR_XMPU4_CFG_R11 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU4_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Strt + */ +#define XDDR_XMPU4_CFG_R12_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12End + */ +#define XDDR_XMPU4_CFG_R12_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU4_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12Mstr + */ +#define XDDR_XMPU4_CFG_R12_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR12 + */ +#define XDDR_XMPU4_CFG_R12 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU4_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Strt + */ +#define XDDR_XMPU4_CFG_R13_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13End + */ +#define XDDR_XMPU4_CFG_R13_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU4_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13Mstr + */ +#define XDDR_XMPU4_CFG_R13_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR13 + */ +#define XDDR_XMPU4_CFG_R13 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU4_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Strt + */ +#define XDDR_XMPU4_CFG_R14_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14End + */ +#define XDDR_XMPU4_CFG_R14_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU4_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14Mstr + */ +#define XDDR_XMPU4_CFG_R14_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR14 + */ +#define XDDR_XMPU4_CFG_R14 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU4_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Strt + */ +#define XDDR_XMPU4_CFG_R15_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15End + */ +#define XDDR_XMPU4_CFG_R15_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU4_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15Mstr + */ +#define XDDR_XMPU4_CFG_R15_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu4CfgR15 + */ +#define XDDR_XMPU4_CFG_R15 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU4_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU4_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU4_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU4_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU4_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU4_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h new file mode 100644 index 00000000..60811718 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XDDR_XMPU5_CFG_H__ +#define __XDDR_XMPU5_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XddrXmpu5Cfg Base Address + */ +#define XDDR_XMPU5_CFG_BASEADDR 0xFD050000UL + +/** + * Register: XddrXmpu5CfgCtrl + */ +#define XDDR_XMPU5_CFG_CTRL ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL ) +#define XDDR_XMPU5_CFG_CTRL_RSTVAL 0x00000003UL + +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgErrSts1 + */ +#define XDDR_XMPU5_CFG_ERR_STS1 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL ) +#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgErrSts2 + */ +#define XDDR_XMPU5_CFG_ERR_STS2 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL ) +#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgPoison + */ +#define XDDR_XMPU5_CFG_POISON ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL ) +#define XDDR_XMPU5_CFG_POISON_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT 20UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH 12UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT 0UL +#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH 20UL +#define XDDR_XMPU5_CFG_POISON_BASE_MASK 0x000fffffUL +#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIsr + */ +#define XDDR_XMPU5_CFG_ISR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL ) +#define XDDR_XMPU5_CFG_ISR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgImr + */ +#define XDDR_XMPU5_CFG_IMR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL ) +#define XDDR_XMPU5_CFG_IMR_RSTVAL 0x0000000fUL + +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XddrXmpu5CfgIen + */ +#define XDDR_XMPU5_CFG_IEN ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL ) +#define XDDR_XMPU5_CFG_IEN_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgIds + */ +#define XDDR_XMPU5_CFG_IDS ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL ) +#define XDDR_XMPU5_CFG_IDS_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT 0UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH 1UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgLock + */ +#define XDDR_XMPU5_CFG_LOCK ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL ) +#define XDDR_XMPU5_CFG_LOCK_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Strt + */ +#define XDDR_XMPU5_CFG_R00_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL ) +#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00End + */ +#define XDDR_XMPU5_CFG_R00_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL ) +#define XDDR_XMPU5_CFG_R00_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00Mstr + */ +#define XDDR_XMPU5_CFG_R00_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL ) +#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR00 + */ +#define XDDR_XMPU5_CFG_R00 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL ) +#define XDDR_XMPU5_CFG_R00_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R00_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R00_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R00_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Strt + */ +#define XDDR_XMPU5_CFG_R01_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL ) +#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01End + */ +#define XDDR_XMPU5_CFG_R01_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL ) +#define XDDR_XMPU5_CFG_R01_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01Mstr + */ +#define XDDR_XMPU5_CFG_R01_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL ) +#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR01 + */ +#define XDDR_XMPU5_CFG_R01 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL ) +#define XDDR_XMPU5_CFG_R01_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R01_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R01_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R01_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Strt + */ +#define XDDR_XMPU5_CFG_R02_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL ) +#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02End + */ +#define XDDR_XMPU5_CFG_R02_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL ) +#define XDDR_XMPU5_CFG_R02_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02Mstr + */ +#define XDDR_XMPU5_CFG_R02_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL ) +#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR02 + */ +#define XDDR_XMPU5_CFG_R02 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL ) +#define XDDR_XMPU5_CFG_R02_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R02_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R02_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R02_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Strt + */ +#define XDDR_XMPU5_CFG_R03_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL ) +#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03End + */ +#define XDDR_XMPU5_CFG_R03_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL ) +#define XDDR_XMPU5_CFG_R03_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03Mstr + */ +#define XDDR_XMPU5_CFG_R03_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL ) +#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR03 + */ +#define XDDR_XMPU5_CFG_R03 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL ) +#define XDDR_XMPU5_CFG_R03_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R03_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R03_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R03_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Strt + */ +#define XDDR_XMPU5_CFG_R04_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL ) +#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04End + */ +#define XDDR_XMPU5_CFG_R04_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL ) +#define XDDR_XMPU5_CFG_R04_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04Mstr + */ +#define XDDR_XMPU5_CFG_R04_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL ) +#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR04 + */ +#define XDDR_XMPU5_CFG_R04 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL ) +#define XDDR_XMPU5_CFG_R04_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R04_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R04_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R04_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Strt + */ +#define XDDR_XMPU5_CFG_R05_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL ) +#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05End + */ +#define XDDR_XMPU5_CFG_R05_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL ) +#define XDDR_XMPU5_CFG_R05_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05Mstr + */ +#define XDDR_XMPU5_CFG_R05_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL ) +#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR05 + */ +#define XDDR_XMPU5_CFG_R05 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL ) +#define XDDR_XMPU5_CFG_R05_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R05_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R05_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R05_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Strt + */ +#define XDDR_XMPU5_CFG_R06_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL ) +#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06End + */ +#define XDDR_XMPU5_CFG_R06_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL ) +#define XDDR_XMPU5_CFG_R06_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06Mstr + */ +#define XDDR_XMPU5_CFG_R06_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL ) +#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR06 + */ +#define XDDR_XMPU5_CFG_R06 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL ) +#define XDDR_XMPU5_CFG_R06_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R06_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R06_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R06_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Strt + */ +#define XDDR_XMPU5_CFG_R07_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL ) +#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07End + */ +#define XDDR_XMPU5_CFG_R07_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL ) +#define XDDR_XMPU5_CFG_R07_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07Mstr + */ +#define XDDR_XMPU5_CFG_R07_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL ) +#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR07 + */ +#define XDDR_XMPU5_CFG_R07 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL ) +#define XDDR_XMPU5_CFG_R07_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R07_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R07_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R07_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Strt + */ +#define XDDR_XMPU5_CFG_R08_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL ) +#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08End + */ +#define XDDR_XMPU5_CFG_R08_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL ) +#define XDDR_XMPU5_CFG_R08_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08Mstr + */ +#define XDDR_XMPU5_CFG_R08_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL ) +#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR08 + */ +#define XDDR_XMPU5_CFG_R08 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL ) +#define XDDR_XMPU5_CFG_R08_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R08_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R08_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R08_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Strt + */ +#define XDDR_XMPU5_CFG_R09_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL ) +#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09End + */ +#define XDDR_XMPU5_CFG_R09_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL ) +#define XDDR_XMPU5_CFG_R09_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09Mstr + */ +#define XDDR_XMPU5_CFG_R09_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL ) +#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR09 + */ +#define XDDR_XMPU5_CFG_R09 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL ) +#define XDDR_XMPU5_CFG_R09_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R09_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R09_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R09_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Strt + */ +#define XDDR_XMPU5_CFG_R10_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL ) +#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10End + */ +#define XDDR_XMPU5_CFG_R10_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL ) +#define XDDR_XMPU5_CFG_R10_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10Mstr + */ +#define XDDR_XMPU5_CFG_R10_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL ) +#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR10 + */ +#define XDDR_XMPU5_CFG_R10 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL ) +#define XDDR_XMPU5_CFG_R10_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R10_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R10_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R10_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Strt + */ +#define XDDR_XMPU5_CFG_R11_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL ) +#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11End + */ +#define XDDR_XMPU5_CFG_R11_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL ) +#define XDDR_XMPU5_CFG_R11_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11Mstr + */ +#define XDDR_XMPU5_CFG_R11_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL ) +#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR11 + */ +#define XDDR_XMPU5_CFG_R11 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL ) +#define XDDR_XMPU5_CFG_R11_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R11_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R11_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R11_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Strt + */ +#define XDDR_XMPU5_CFG_R12_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL ) +#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12End + */ +#define XDDR_XMPU5_CFG_R12_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL ) +#define XDDR_XMPU5_CFG_R12_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12Mstr + */ +#define XDDR_XMPU5_CFG_R12_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL ) +#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR12 + */ +#define XDDR_XMPU5_CFG_R12 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL ) +#define XDDR_XMPU5_CFG_R12_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R12_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R12_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R12_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Strt + */ +#define XDDR_XMPU5_CFG_R13_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL ) +#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13End + */ +#define XDDR_XMPU5_CFG_R13_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL ) +#define XDDR_XMPU5_CFG_R13_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13Mstr + */ +#define XDDR_XMPU5_CFG_R13_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL ) +#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR13 + */ +#define XDDR_XMPU5_CFG_R13 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL ) +#define XDDR_XMPU5_CFG_R13_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R13_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R13_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R13_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Strt + */ +#define XDDR_XMPU5_CFG_R14_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL ) +#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14End + */ +#define XDDR_XMPU5_CFG_R14_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL ) +#define XDDR_XMPU5_CFG_R14_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14Mstr + */ +#define XDDR_XMPU5_CFG_R14_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL ) +#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR14 + */ +#define XDDR_XMPU5_CFG_R14 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL ) +#define XDDR_XMPU5_CFG_R14_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R14_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R14_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R14_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Strt + */ +#define XDDR_XMPU5_CFG_R15_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL ) +#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15End + */ +#define XDDR_XMPU5_CFG_R15_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL ) +#define XDDR_XMPU5_CFG_R15_END_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH 28UL +#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15Mstr + */ +#define XDDR_XMPU5_CFG_R15_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL ) +#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH 16UL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XddrXmpu5CfgR15 + */ +#define XDDR_XMPU5_CFG_R15 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL ) +#define XDDR_XMPU5_CFG_R15_RSTVAL 0x00000008UL + +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT 3UL +#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_REGNNS_MASK 0x00000008UL +#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT 2UL +#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_WRALWD_MASK 0x00000004UL +#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_RDALWD_MASK 0x00000002UL +#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XDDR_XMPU5_CFG_R15_EN_SHIFT 0UL +#define XDDR_XMPU5_CFG_R15_EN_WIDTH 1UL +#define XDDR_XMPU5_CFG_R15_EN_MASK 0x00000001UL +#define XDDR_XMPU5_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XDDR_XMPU5_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h b/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h new file mode 100644 index 00000000..b565b958 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h @@ -0,0 +1,382 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_H__ +#define __XFPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcr Base Address + */ +#define XFPD_SLCR_BASEADDR 0xFD610000UL + +/** + * Register: XfpdSlcrWprot0 + */ +#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrCtrl + */ +#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIsr + */ +#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrImr + */ +#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrIer + */ +#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIdr + */ +#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrItr + */ +#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrWdtClkSel + */ +#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL ) +#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrIntFpd + */ +#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL ) +#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL + +#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL +#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrGpu + */ +#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL ) +#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL + +#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL +#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL +#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL +#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL +#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL +#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL + +#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL +#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL +#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL +#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL + +#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL +#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL +#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL +#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrGdmaCfg + */ +#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL + +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL +#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL + +#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XfpdSlcrGdma + */ +#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL + +#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL +#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL +#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL +#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL +#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL +#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL +#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XfpdSlcrAfiFs + */ +#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL ) +#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL + +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL +#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL + +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL +#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL + +/** + * Register: XfpdSlcrErrAtbIsr + */ +#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbImr + */ +#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrErrAtbIer + */ +#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrErrAtbIdr + */ +#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbCmdstore + */ +#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbRespEn + */ +#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrAtbResptype + */ +#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL +#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL + +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL +#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrAtbPrescale + */ +#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h b/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h new file mode 100644 index 00000000..6541a4f1 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h @@ -0,0 +1,277 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_SLCR_SECURE_H__ +#define __XFPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdSlcrSecure Base Address + */ +#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL + +/** + * Register: XfpdSlcrSecCtrl + */ +#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIsr + */ +#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecImr + */ +#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecIer + */ +#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecIdr + */ +#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecItr + */ +#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecSata + */ +#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL +#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL +#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL + +/** + * Register: XfpdSlcrSecPcie + */ +#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL +#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL +#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL +#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL +#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL + +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecDpdma + */ +#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL ) +#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL + +#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL +#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL +#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL + +/** + * Register: XfpdSlcrSecGdma + */ +#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL ) +#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL + +#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL +#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL +#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL +#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL + +/** + * Register: XfpdSlcrSecGic + */ +#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL ) +#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL + +#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL +#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h new file mode 100644 index 00000000..75aef19f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_CFG_H__ +#define __XFPD_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuCfg Base Address + */ +#define XFPD_XMPU_CFG_BASEADDR 0xFD5D0000UL + +/** + * Register: XfpdXmpuCfgCtrl + */ +#define XFPD_XMPU_CFG_CTRL ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XFPD_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgErrSts1 + */ +#define XFPD_XMPU_CFG_ERR_STS1 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgErrSts2 + */ +#define XFPD_XMPU_CFG_ERR_STS2 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgPoison + */ +#define XFPD_XMPU_CFG_POISON ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XFPD_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XFPD_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XFPD_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIsr + */ +#define XFPD_XMPU_CFG_ISR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XFPD_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgImr + */ +#define XFPD_XMPU_CFG_IMR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XFPD_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuCfgIen + */ +#define XFPD_XMPU_CFG_IEN ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XFPD_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgIds + */ +#define XFPD_XMPU_CFG_IDS ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XFPD_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XFPD_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgLock + */ +#define XFPD_XMPU_CFG_LOCK ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XFPD_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Strt + */ +#define XFPD_XMPU_CFG_R00_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XFPD_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00End + */ +#define XFPD_XMPU_CFG_R00_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XFPD_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00Mstr + */ +#define XFPD_XMPU_CFG_R00_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR00 + */ +#define XFPD_XMPU_CFG_R00 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XFPD_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R00_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R00_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Strt + */ +#define XFPD_XMPU_CFG_R01_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XFPD_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01End + */ +#define XFPD_XMPU_CFG_R01_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XFPD_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01Mstr + */ +#define XFPD_XMPU_CFG_R01_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR01 + */ +#define XFPD_XMPU_CFG_R01 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XFPD_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R01_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R01_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Strt + */ +#define XFPD_XMPU_CFG_R02_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XFPD_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02End + */ +#define XFPD_XMPU_CFG_R02_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XFPD_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02Mstr + */ +#define XFPD_XMPU_CFG_R02_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR02 + */ +#define XFPD_XMPU_CFG_R02 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XFPD_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R02_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R02_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Strt + */ +#define XFPD_XMPU_CFG_R03_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XFPD_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03End + */ +#define XFPD_XMPU_CFG_R03_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XFPD_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03Mstr + */ +#define XFPD_XMPU_CFG_R03_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR03 + */ +#define XFPD_XMPU_CFG_R03 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XFPD_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R03_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R03_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Strt + */ +#define XFPD_XMPU_CFG_R04_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XFPD_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04End + */ +#define XFPD_XMPU_CFG_R04_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XFPD_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04Mstr + */ +#define XFPD_XMPU_CFG_R04_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR04 + */ +#define XFPD_XMPU_CFG_R04 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XFPD_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R04_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R04_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Strt + */ +#define XFPD_XMPU_CFG_R05_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XFPD_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05End + */ +#define XFPD_XMPU_CFG_R05_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XFPD_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05Mstr + */ +#define XFPD_XMPU_CFG_R05_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR05 + */ +#define XFPD_XMPU_CFG_R05 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XFPD_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R05_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R05_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Strt + */ +#define XFPD_XMPU_CFG_R06_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XFPD_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06End + */ +#define XFPD_XMPU_CFG_R06_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XFPD_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06Mstr + */ +#define XFPD_XMPU_CFG_R06_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR06 + */ +#define XFPD_XMPU_CFG_R06 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XFPD_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R06_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R06_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Strt + */ +#define XFPD_XMPU_CFG_R07_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XFPD_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07End + */ +#define XFPD_XMPU_CFG_R07_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XFPD_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07Mstr + */ +#define XFPD_XMPU_CFG_R07_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR07 + */ +#define XFPD_XMPU_CFG_R07 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XFPD_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R07_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R07_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Strt + */ +#define XFPD_XMPU_CFG_R08_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XFPD_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08End + */ +#define XFPD_XMPU_CFG_R08_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XFPD_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08Mstr + */ +#define XFPD_XMPU_CFG_R08_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR08 + */ +#define XFPD_XMPU_CFG_R08 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XFPD_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R08_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R08_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Strt + */ +#define XFPD_XMPU_CFG_R09_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XFPD_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09End + */ +#define XFPD_XMPU_CFG_R09_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XFPD_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09Mstr + */ +#define XFPD_XMPU_CFG_R09_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR09 + */ +#define XFPD_XMPU_CFG_R09 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XFPD_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R09_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R09_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Strt + */ +#define XFPD_XMPU_CFG_R10_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XFPD_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10End + */ +#define XFPD_XMPU_CFG_R10_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XFPD_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10Mstr + */ +#define XFPD_XMPU_CFG_R10_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR10 + */ +#define XFPD_XMPU_CFG_R10 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XFPD_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R10_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R10_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Strt + */ +#define XFPD_XMPU_CFG_R11_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XFPD_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11End + */ +#define XFPD_XMPU_CFG_R11_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XFPD_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11Mstr + */ +#define XFPD_XMPU_CFG_R11_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR11 + */ +#define XFPD_XMPU_CFG_R11 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XFPD_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R11_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R11_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Strt + */ +#define XFPD_XMPU_CFG_R12_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XFPD_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12End + */ +#define XFPD_XMPU_CFG_R12_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XFPD_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12Mstr + */ +#define XFPD_XMPU_CFG_R12_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR12 + */ +#define XFPD_XMPU_CFG_R12 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XFPD_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R12_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R12_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Strt + */ +#define XFPD_XMPU_CFG_R13_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XFPD_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13End + */ +#define XFPD_XMPU_CFG_R13_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XFPD_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13Mstr + */ +#define XFPD_XMPU_CFG_R13_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR13 + */ +#define XFPD_XMPU_CFG_R13 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XFPD_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R13_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R13_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Strt + */ +#define XFPD_XMPU_CFG_R14_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XFPD_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14End + */ +#define XFPD_XMPU_CFG_R14_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XFPD_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14Mstr + */ +#define XFPD_XMPU_CFG_R14_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR14 + */ +#define XFPD_XMPU_CFG_R14 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XFPD_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R14_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R14_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Strt + */ +#define XFPD_XMPU_CFG_R15_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XFPD_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15End + */ +#define XFPD_XMPU_CFG_R15_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XFPD_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XFPD_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15Mstr + */ +#define XFPD_XMPU_CFG_R15_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuCfgR15 + */ +#define XFPD_XMPU_CFG_R15 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XFPD_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XFPD_XMPU_CFG_R15_EN_SHIFT 0UL +#define XFPD_XMPU_CFG_R15_EN_WIDTH 1UL +#define XFPD_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XFPD_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h new file mode 100644 index 00000000..39172f1f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XFPD_XMPU_SINK_H__ +#define __XFPD_XMPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XfpdXmpuSink Base Address + */ +#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL + +/** + * Register: XfpdXmpuSinkErrSts + */ +#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIsr + */ +#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkImr + */ +#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XfpdXmpuSinkIer + */ +#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XfpdXmpuSinkIdr + */ +#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XFPD_XMPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_cache.c b/lib/bsp/standalone/src/cortexr5/xil_cache.c new file mode 100644 index 00000000..2c02369f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_cache.c @@ -0,0 +1,584 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexr5.h" +#include "xil_exception.h" + + +/************************** Variable Definitions *****************************/ + +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ + + +extern s32 _stack_end; +extern s32 __undef_stack; + +/****************************************************************************/ +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Enable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) { + /* invalidate the Data cache */ + Xil_DCacheInvalidate(); + + /* enable the Data cache */ + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + } +} + +/**************************************************************************** +* +* Disable the Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + register u32 CtrlReg; + + /* clean and invalidate the Data cache */ + Xil_DCacheFlush(); + + /* disable the Data cache */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + u32 currmask; + u32 stack_start,stack_end,stack_size; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + + stack_end = (u32 )&_stack_end; + stack_start = (u32 )&__undef_stack; + stack_size = stack_start-stack_end; + + /* Flush stack memory to save return address */ + Xil_DCacheFlushRange(stack_end, stack_size); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + /*invalidate all D cache*/ + mtcp(XREG_CP15_INVAL_DC_ALL, 0); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the modified contents +* are lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for invalidate to complete */ + dsb(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + + /* Invalidate Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); + + tempadr += cacheline; + } + } + + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + /* Select cache level 0 and D cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); + + /* Determine Cache Size */ + + CacheSize = (CsidReg >> 13U) & 0x000001FFU; + CacheSize += 0x00000001U; + CacheSize *= (u32)128; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x000003ffU) >> 3U; + NumWays += 0x00000001U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x00000007U) + 0x00000004U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + /* Flush by Set/Way */ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); + + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += 0x40000000U; + } + + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param Address to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); + + while (LocalAddr < end) { + /* Flush Data cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (LocalAddr)); + + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); +} +/**************************************************************************** +* +* Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param Address to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheStoreLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for store to complete */ + dsb(); + isb(); + + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Enable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ + + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) { + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* enable the instruction cache */ + CtrlReg |= (XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + } +} + +/**************************************************************************** +* +* Disable the instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ + register u32 CtrlReg; + + dsb(); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* disable the instruction cache */ + + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + + CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/**************************************************************************** +* +* Invalidate the entire instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0); + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate an instruction cache line. If the instruction specified by the +* parameter adr is cached by the instruction cache, the cacheline containing +* that instruction is invalidated. +* +* @param None. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F))); + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/**************************************************************************** +* +* Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of range to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + + while (LocalAddr < end) { + + /* Invalidate L1 I-cache line */ + __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (LocalAddr)); + + LocalAddr += cacheline; + } + } + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_cache.h b/lib/bsp/standalone/src/cortexr5/xil_cache.h new file mode 100644 index 00000000..5114ea0d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_cache.h @@ -0,0 +1,77 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* Contains required functions for the ARM cache functionality +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlushLine(INTPTR adr); +void Xil_DCacheStoreLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateLine(INTPTR adr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/xil_exception.c b/lib/bsp/standalone/src/cortexr5/xil_exception.c new file mode 100644 index 00000000..d4bcff00 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_exception.c @@ -0,0 +1,218 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex R5 exception +* Handler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+* 
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void *)Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* The function is a common API used to initialize exception handlers across all +* processors supported. For ARM CortexR5, the exception handlers are being +* initialized statically and hence this function does not do anything. +* +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* +* Makes the connection between the Id of the exception source and the +* associated Handler that is to run when the exception is recognized. The +* argument provided in this call as the Data is used as the argument +* for the Handler when it is called. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. + See xil_exception_l.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* +* Removes the Handler for a specific exception Id. The stub Handler is then +* registered for this exception Id. +* +* @param exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception_l.h for further information. + +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} +/*****************************************************************************/ +/** +* +* Default Data abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_DataAbortHandler(void *CallBackRef){ + + xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n"); + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default Prefetch abort handler which printsa debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_PrefetchAbortHandler(void *CallBackRef){ + + xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n"); + while(1) { + ; + } +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_exception.h b/lib/bsp/standalone/src/cortexr5/xil_exception.h new file mode 100644 index 00000000..e22ebfb0 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_exception.h @@ -0,0 +1,215 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) + + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Enable nested interrupts by clearing the I and F bits it CPSR +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* Disable the nested interrupts by setting the I and F bits. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); + +extern void Xil_DataAbortHandler(void *CallBackRef); + +extern void Xil_PrefetchAbortHandler(void *CallBackRef); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_io.c b/lib/bsp/standalone/src/cortexr5/xil_io.c new file mode 100644 index 00000000..f985a733 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_io.c @@ -0,0 +1,380 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. These functions encapsulate Cortex R5 architecture-specific +* I/O requirements. +* +* @note +* +* This file contains architecture-dependent code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xpseudo_asm.h" +#include "xreg_cortexr5.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Performs an input operation for an 8-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(INTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(INTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(INTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for an 8-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(INTPTR Addr, u8 Value) +{ + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(INTPTR Addr, u16 Value) +{ + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(INTPTR Addr, u32 Value) +{ + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} +/*****************************************************************************/ +/** +* +* Performs an output operation for a 64-bit memory location by writing the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out64(INTPTR Addr, u64 Value) +{ + u64 *LocalAddr = (u64 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 64-bit memory location by reading the +* specified Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +u64 Xil_In64(INTPTR Addr) +{ + return *(volatile u64 *) Addr; +} +/*****************************************************************************/ +/** +* +* Performs an input operation for a 16-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16BE(INTPTR Addr) +{ + u16 temp; + u16 result; + + temp = Xil_In16(Addr); + + result = Xil_EndianSwap16(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the byte-swapped Value read from that +* address. +* +* @param Addr contains the address to perform the input operation +* at. +* +* @return The byte-swapped Value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32BE(INTPTR Addr) +{ + u32 temp; + u32 result; + + temp = Xil_In32(Addr); + + result = Xil_EndianSwap32(temp); + + return result; +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 16-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param OutAddress contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out16BE(INTPTR Addr, u16 Value) +{ + u16 temp; + + temp = Xil_EndianSwap16(Value); + + Xil_Out16(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Performs an output operation for a 32-bit memory location by writing the +* specified Value to the the specified address. The Value is byte-swapped +* before being written. +* +* @param OutAddress contains the address to perform the output operation +* at. +* @param Value contains the Value to be output at the specified address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_Out32BE(INTPTR Addr, u32 Value) +{ + u32 temp; + + temp = Xil_EndianSwap32(Value); + + Xil_Out32(Addr, temp); +} + +/*****************************************************************************/ +/** +* +* Perform a 16-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* Perform a 32-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << 16U) | (u32)HiWord); +} diff --git a/lib/bsp/standalone/src/cortexr5/xil_io.h b/lib/bsp/standalone/src/cortexr5/xil_io.h new file mode 100644 index 00000000..2b741bf1 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_io.h @@ -0,0 +1,244 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined __GNUC__ +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(INTPTR Addr); +u16 Xil_In16(INTPTR Addr); +u32 Xil_In32(INTPTR Addr); +u64 Xil_In64(INTPTR Addr); + +void Xil_Out8(INTPTR Addr, u8 Value); +void Xil_Out16(INTPTR Addr, u16 Value); +void Xil_Out32(INTPTR Addr, u32 Value); +void Xil_Out64(INTPTR Addr, u64 Value); + +u16 Xil_In16BE(INTPTR Addr); +u32 Xil_In32BE(INTPTR Addr); +void Xil_Out16BE(INTPTR Addr, u16 Value); +void Xil_Out32BE(INTPTR Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_mmu.h b/lib/bsp/standalone/src/cortexr5/xil_mmu.h new file mode 100644 index 00000000..8e43e822 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_mmu.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API +* defined for MPU in R5. R5 does not have mmu and for usage of similiar API +* the file has been created. +* +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.0	pkp  2/12/15 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_mpu.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_mpu.c b/lib/bsp/standalone/src/cortexr5/xil_mpu.c new file mode 100644 index 00000000..935d74f9 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_mpu.c @@ -0,0 +1,195 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mpu.c +* +* This file provides APIs for enabling/disabling MPU and setting the memory +* attributes for sections, in the MPU translation table. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mpu.h" +#include "xdebug.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/***************************************************************************** +* +* Set the memory attributes for a section of memory with starting address addr +* of the region size 1MB having attributes attrib +* +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @return None. +* +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) +{ + u32 Regionsize; + INTPTR Localaddr = addr; + u32 NextAvailableMemRegion; + + Localaddr &= (~(0xFFFFFU)); + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER); + NextAvailableMemRegion++; + if (NextAvailableMemRegion > 16) { + xdbg_printf(DEBUG, "No regions available\r\n"); + } + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); + isb(); + Regionsize = REGION_1M<<1; /* region size is hardcoded to 1MB */ + Regionsize |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,Localaddr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Regionsize); /* set the region size and enable it*/ + dsb(); + isb(); + + +} + +/***************************************************************************** +* +* Enable MPU for Cortex R5 processor. This function invalidates I cache and +* flush the D Caches before enabling the MPU. +* +* +* @param None. +* @return None. +* +******************************************************************************/ +void Xil_EnableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + Reg = mfcp(XREG_CP15_SYS_CONTROL); + Reg |= 0x00000001U; + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/***************************************************************************** +* +* Disable MPU for Cortex R5 processors. This function invalidates I cache and +* flush the D Caches before disabling the MPU. +* +* @param None. +* +* @return None. +* +******************************************************************************/ +void Xil_DisableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); + Reg = mfcp(XREG_CP15_SYS_CONTROL); + Reg &= ~(0x00000001U); + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} \ No newline at end of file diff --git a/lib/bsp/standalone/src/cortexr5/xil_mpu.h b/lib/bsp/standalone/src/cortexr5/xil_mpu.h new file mode 100644 index 00000000..eccbc25e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_mpu.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MPU_H +#define XIL_MPU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "xil_types.h" +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMPU(void); +void Xil_DisableMPU(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MPU_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xil_printf.c b/lib/bsp/standalone/src/cortexr5/xil_printf.c new file mode 100644 index 00000000..5c1b467f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_printf.c @@ -0,0 +1,352 @@ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include +#include +#include + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static void outnum( const s32 n, const s32 base, struct params_s *par); +static s32 getnum( charptr* linep); + +typedef struct params_s { + s32 len; + s32 num1; + s32 num2; + char8 pad_character; + s32 do_padding; + s32 left_flag; +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +/* */ +/* This routine puts pad characters into the output */ +/* buffer. */ +/* */ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#ifdef STDOUT_BASEADDRESS + outbyte( par->pad_character); +#endif + } + } +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a string to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + } + padding( !(par->left_flag), par); + + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#ifdef STDOUT_BASEADDRESS + outbyte(*LocalPtr); + LocalPtr += 1; +#endif +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + /* par->len = strlen( lp) */ + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine moves a number to the output buffer */ +/* as directed by the padding and positioning flags. */ +/* */ + +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + charptr cp; + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#ifdef STDOUT_BASEADDRESS + outbyte( outbuf[i] ); + i--; +#endif +} + padding( par->left_flag, par); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine gets a number from the format */ +/* string. */ +/* */ +static s32 getnum( charptr* linep) +{ + s32 n; + s32 ResultIsDigit = 0; + charptr cptr; + n = 0; + cptr = *linep; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + while (ResultIsDigit != 0) { + if(cptr != NULL){ + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + if(cptr != NULL){ + ResultIsDigit = isdigit(((s32)*cptr)); + } + } + ResultIsDigit = isdigit(((s32)*cptr)); + } + *linep = ((charptr )(cptr)); + return(n); +} + +/*---------------------------------------------------*/ +/* */ +/* This routine operates just like a printf/sprintf */ +/* routine. It outputs a set of data under the */ +/* control of a formatting string. Not all of the */ +/* standard C format control are supported. The ones */ +/* provided are primarily those needed for embedded */ +/* systems work. Primarily the floating point */ +/* routines are omitted. Other formats could be */ +/* added easily by following the examples shown for */ +/* the supported formats. */ +/* */ + +/* void esp_printf( const func_ptr f_ptr, + const charptr ctrl1, ...) */ +void xil_printf( const char8 *ctrl1, ...) +{ + s32 Check; + s32 long_flag; + s32 dot_flag; + + params_t par; + + char8 ch; + va_list argp; + char8 *ctrl = (char8 *)ctrl1; + + va_start( argp, ctrl1); + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#ifdef STDOUT_BASEADDRESS + outbyte(*ctrl); + ctrl += 1; +#endif + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; + long_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = *ctrl; + } + else { + ch = *ctrl; + } + + if (isdigit((s32)ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == '0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower((s32)ch)) { + case '%': +#ifdef STDOUT_BASEADDRESS + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + long_flag = 1; + Check = 0; + break; + + case 'd': + if ((long_flag != 0) || (ch == 'D')) { + outnum( va_arg(argp, s32), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + Check = 1; + break; + case 'x': + outnum((s32)va_arg(argp, s32), 16L, &par); + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#ifdef STDOUT_BASEADDRESS + outbyte( va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#ifdef STDOUT_BASEADDRESS + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#ifdef STDOUT_BASEADDRESS + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } + va_end( argp); +} + +/*---------------------------------------------------*/ diff --git a/lib/bsp/standalone/src/cortexr5/xil_printf.h b/lib/bsp/standalone/src/cortexr5/xil_printf.h new file mode 100644 index 00000000..2be5c573 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h b/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h new file mode 100644 index 00000000..cb4ad490 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h @@ -0,0 +1,174 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SECURE_SLCR_H__ +#define __XIOU_SECURE_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSecureSlcr Base Address + */ +#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL + +/** + * Register: XiouSecSlcrAxiWprtcn + */ +#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrAxiRprtcn + */ +#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL +#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrCtrl + */ +#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIsr + */ +#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrImr + */ +#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSecSlcrIer + */ +#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrIdr + */ +#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSecSlcrItr + */ +#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SECURE_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xiou_slcr.h b/lib/bsp/standalone/src/cortexr5/xiou_slcr.h new file mode 100644 index 00000000..d81d178d --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xiou_slcr.h @@ -0,0 +1,4029 @@ +/* ### HEADER ### */ + +#ifndef __XIOU_SLCR_H__ +#define __XIOU_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XiouSlcr Base Address + */ +#define XIOU_SLCR_BASEADDR 0xFF180000UL + +/** + * Register: XiouSlcrMioPin0 + */ +#define XIOU_SLCR_MIO_PIN_0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL ) +#define XIOU_SLCR_MIO_PIN_0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin1 + */ +#define XIOU_SLCR_MIO_PIN_1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL ) +#define XIOU_SLCR_MIO_PIN_1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin2 + */ +#define XIOU_SLCR_MIO_PIN_2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL ) +#define XIOU_SLCR_MIO_PIN_2_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin3 + */ +#define XIOU_SLCR_MIO_PIN_3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XIOU_SLCR_MIO_PIN_3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin4 + */ +#define XIOU_SLCR_MIO_PIN_4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL ) +#define XIOU_SLCR_MIO_PIN_4_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin5 + */ +#define XIOU_SLCR_MIO_PIN_5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL ) +#define XIOU_SLCR_MIO_PIN_5_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin6 + */ +#define XIOU_SLCR_MIO_PIN_6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL ) +#define XIOU_SLCR_MIO_PIN_6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin7 + */ +#define XIOU_SLCR_MIO_PIN_7 ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL ) +#define XIOU_SLCR_MIO_PIN_7_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin8 + */ +#define XIOU_SLCR_MIO_PIN_8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL ) +#define XIOU_SLCR_MIO_PIN_8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin9 + */ +#define XIOU_SLCR_MIO_PIN_9 ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL ) +#define XIOU_SLCR_MIO_PIN_9_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin10 + */ +#define XIOU_SLCR_MIO_PIN_10 ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL ) +#define XIOU_SLCR_MIO_PIN_10_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin11 + */ +#define XIOU_SLCR_MIO_PIN_11 ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL ) +#define XIOU_SLCR_MIO_PIN_11_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin12 + */ +#define XIOU_SLCR_MIO_PIN_12 ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL ) +#define XIOU_SLCR_MIO_PIN_12_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin13 + */ +#define XIOU_SLCR_MIO_PIN_13 ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL ) +#define XIOU_SLCR_MIO_PIN_13_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin14 + */ +#define XIOU_SLCR_MIO_PIN_14 ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL ) +#define XIOU_SLCR_MIO_PIN_14_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin15 + */ +#define XIOU_SLCR_MIO_PIN_15 ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL ) +#define XIOU_SLCR_MIO_PIN_15_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin16 + */ +#define XIOU_SLCR_MIO_PIN_16 ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL ) +#define XIOU_SLCR_MIO_PIN_16_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin17 + */ +#define XIOU_SLCR_MIO_PIN_17 ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL ) +#define XIOU_SLCR_MIO_PIN_17_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin18 + */ +#define XIOU_SLCR_MIO_PIN_18 ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL ) +#define XIOU_SLCR_MIO_PIN_18_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin19 + */ +#define XIOU_SLCR_MIO_PIN_19 ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XIOU_SLCR_MIO_PIN_19_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin20 + */ +#define XIOU_SLCR_MIO_PIN_20 ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL ) +#define XIOU_SLCR_MIO_PIN_20_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin21 + */ +#define XIOU_SLCR_MIO_PIN_21 ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL ) +#define XIOU_SLCR_MIO_PIN_21_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin22 + */ +#define XIOU_SLCR_MIO_PIN_22 ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL ) +#define XIOU_SLCR_MIO_PIN_22_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin23 + */ +#define XIOU_SLCR_MIO_PIN_23 ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL ) +#define XIOU_SLCR_MIO_PIN_23_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin24 + */ +#define XIOU_SLCR_MIO_PIN_24 ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL ) +#define XIOU_SLCR_MIO_PIN_24_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin25 + */ +#define XIOU_SLCR_MIO_PIN_25 ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL ) +#define XIOU_SLCR_MIO_PIN_25_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin26 + */ +#define XIOU_SLCR_MIO_PIN_26 ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL ) +#define XIOU_SLCR_MIO_PIN_26_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin27 + */ +#define XIOU_SLCR_MIO_PIN_27 ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL ) +#define XIOU_SLCR_MIO_PIN_27_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin28 + */ +#define XIOU_SLCR_MIO_PIN_28 ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL ) +#define XIOU_SLCR_MIO_PIN_28_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin29 + */ +#define XIOU_SLCR_MIO_PIN_29 ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL ) +#define XIOU_SLCR_MIO_PIN_29_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin30 + */ +#define XIOU_SLCR_MIO_PIN_30 ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL ) +#define XIOU_SLCR_MIO_PIN_30_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin31 + */ +#define XIOU_SLCR_MIO_PIN_31 ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL ) +#define XIOU_SLCR_MIO_PIN_31_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin32 + */ +#define XIOU_SLCR_MIO_PIN_32 ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL ) +#define XIOU_SLCR_MIO_PIN_32_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin33 + */ +#define XIOU_SLCR_MIO_PIN_33 ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL ) +#define XIOU_SLCR_MIO_PIN_33_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin34 + */ +#define XIOU_SLCR_MIO_PIN_34 ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL ) +#define XIOU_SLCR_MIO_PIN_34_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin35 + */ +#define XIOU_SLCR_MIO_PIN_35 ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL ) +#define XIOU_SLCR_MIO_PIN_35_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin36 + */ +#define XIOU_SLCR_MIO_PIN_36 ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL ) +#define XIOU_SLCR_MIO_PIN_36_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin37 + */ +#define XIOU_SLCR_MIO_PIN_37 ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL ) +#define XIOU_SLCR_MIO_PIN_37_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin38 + */ +#define XIOU_SLCR_MIO_PIN_38 ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL ) +#define XIOU_SLCR_MIO_PIN_38_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin39 + */ +#define XIOU_SLCR_MIO_PIN_39 ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL ) +#define XIOU_SLCR_MIO_PIN_39_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin40 + */ +#define XIOU_SLCR_MIO_PIN_40 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL ) +#define XIOU_SLCR_MIO_PIN_40_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin41 + */ +#define XIOU_SLCR_MIO_PIN_41 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL ) +#define XIOU_SLCR_MIO_PIN_41_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin42 + */ +#define XIOU_SLCR_MIO_PIN_42 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL ) +#define XIOU_SLCR_MIO_PIN_42_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin43 + */ +#define XIOU_SLCR_MIO_PIN_43 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL ) +#define XIOU_SLCR_MIO_PIN_43_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin44 + */ +#define XIOU_SLCR_MIO_PIN_44 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL ) +#define XIOU_SLCR_MIO_PIN_44_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin45 + */ +#define XIOU_SLCR_MIO_PIN_45 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL ) +#define XIOU_SLCR_MIO_PIN_45_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin46 + */ +#define XIOU_SLCR_MIO_PIN_46 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL ) +#define XIOU_SLCR_MIO_PIN_46_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin47 + */ +#define XIOU_SLCR_MIO_PIN_47 ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL ) +#define XIOU_SLCR_MIO_PIN_47_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin48 + */ +#define XIOU_SLCR_MIO_PIN_48 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL ) +#define XIOU_SLCR_MIO_PIN_48_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin49 + */ +#define XIOU_SLCR_MIO_PIN_49 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL ) +#define XIOU_SLCR_MIO_PIN_49_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin50 + */ +#define XIOU_SLCR_MIO_PIN_50 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL ) +#define XIOU_SLCR_MIO_PIN_50_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin51 + */ +#define XIOU_SLCR_MIO_PIN_51 ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL ) +#define XIOU_SLCR_MIO_PIN_51_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin52 + */ +#define XIOU_SLCR_MIO_PIN_52 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL ) +#define XIOU_SLCR_MIO_PIN_52_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin53 + */ +#define XIOU_SLCR_MIO_PIN_53 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL ) +#define XIOU_SLCR_MIO_PIN_53_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin54 + */ +#define XIOU_SLCR_MIO_PIN_54 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL ) +#define XIOU_SLCR_MIO_PIN_54_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin55 + */ +#define XIOU_SLCR_MIO_PIN_55 ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL ) +#define XIOU_SLCR_MIO_PIN_55_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin56 + */ +#define XIOU_SLCR_MIO_PIN_56 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL ) +#define XIOU_SLCR_MIO_PIN_56_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin57 + */ +#define XIOU_SLCR_MIO_PIN_57 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL ) +#define XIOU_SLCR_MIO_PIN_57_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin58 + */ +#define XIOU_SLCR_MIO_PIN_58 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL ) +#define XIOU_SLCR_MIO_PIN_58_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin59 + */ +#define XIOU_SLCR_MIO_PIN_59 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL ) +#define XIOU_SLCR_MIO_PIN_59_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin60 + */ +#define XIOU_SLCR_MIO_PIN_60 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL ) +#define XIOU_SLCR_MIO_PIN_60_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin61 + */ +#define XIOU_SLCR_MIO_PIN_61 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL ) +#define XIOU_SLCR_MIO_PIN_61_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin62 + */ +#define XIOU_SLCR_MIO_PIN_62 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL ) +#define XIOU_SLCR_MIO_PIN_62_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin63 + */ +#define XIOU_SLCR_MIO_PIN_63 ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL ) +#define XIOU_SLCR_MIO_PIN_63_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin64 + */ +#define XIOU_SLCR_MIO_PIN_64 ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL ) +#define XIOU_SLCR_MIO_PIN_64_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin65 + */ +#define XIOU_SLCR_MIO_PIN_65 ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL ) +#define XIOU_SLCR_MIO_PIN_65_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin66 + */ +#define XIOU_SLCR_MIO_PIN_66 ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL ) +#define XIOU_SLCR_MIO_PIN_66_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin67 + */ +#define XIOU_SLCR_MIO_PIN_67 ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL ) +#define XIOU_SLCR_MIO_PIN_67_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin68 + */ +#define XIOU_SLCR_MIO_PIN_68 ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL ) +#define XIOU_SLCR_MIO_PIN_68_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin69 + */ +#define XIOU_SLCR_MIO_PIN_69 ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL ) +#define XIOU_SLCR_MIO_PIN_69_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin70 + */ +#define XIOU_SLCR_MIO_PIN_70 ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL ) +#define XIOU_SLCR_MIO_PIN_70_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin71 + */ +#define XIOU_SLCR_MIO_PIN_71 ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL ) +#define XIOU_SLCR_MIO_PIN_71_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin72 + */ +#define XIOU_SLCR_MIO_PIN_72 ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL ) +#define XIOU_SLCR_MIO_PIN_72_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin73 + */ +#define XIOU_SLCR_MIO_PIN_73 ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL ) +#define XIOU_SLCR_MIO_PIN_73_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin74 + */ +#define XIOU_SLCR_MIO_PIN_74 ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL ) +#define XIOU_SLCR_MIO_PIN_74_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin75 + */ +#define XIOU_SLCR_MIO_PIN_75 ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL ) +#define XIOU_SLCR_MIO_PIN_75_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin76 + */ +#define XIOU_SLCR_MIO_PIN_76 ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL ) +#define XIOU_SLCR_MIO_PIN_76_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioPin77 + */ +#define XIOU_SLCR_MIO_PIN_77 ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL ) +#define XIOU_SLCR_MIO_PIN_77_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH 3UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000e0UL +#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH 2UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018UL +#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004UL +#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH 1UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002UL +#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl0 + */ +#define XIOU_SLCR_BANK0_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL ) +#define XIOU_SLCR_BANK0_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl1 + */ +#define XIOU_SLCR_BANK0_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL ) +#define XIOU_SLCR_BANK0_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl3 + */ +#define XIOU_SLCR_BANK0_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL ) +#define XIOU_SLCR_BANK0_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Ctrl4 + */ +#define XIOU_SLCR_BANK0_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL ) +#define XIOU_SLCR_BANK0_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl5 + */ +#define XIOU_SLCR_BANK0_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL ) +#define XIOU_SLCR_BANK0_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank0Ctrl6 + */ +#define XIOU_SLCR_BANK0_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL ) +#define XIOU_SLCR_BANK0_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank0Sts + */ +#define XIOU_SLCR_BANK0_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL ) +#define XIOU_SLCR_BANK0_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl0 + */ +#define XIOU_SLCR_BANK1_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL ) +#define XIOU_SLCR_BANK1_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl1 + */ +#define XIOU_SLCR_BANK1_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL ) +#define XIOU_SLCR_BANK1_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl3 + */ +#define XIOU_SLCR_BANK1_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL ) +#define XIOU_SLCR_BANK1_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Ctrl4 + */ +#define XIOU_SLCR_BANK1_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL ) +#define XIOU_SLCR_BANK1_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl5 + */ +#define XIOU_SLCR_BANK1_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL ) +#define XIOU_SLCR_BANK1_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank1Ctrl6 + */ +#define XIOU_SLCR_BANK1_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL ) +#define XIOU_SLCR_BANK1_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank1Sts + */ +#define XIOU_SLCR_BANK1_STS ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL ) +#define XIOU_SLCR_BANK1_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl0 + */ +#define XIOU_SLCR_BANK2_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL ) +#define XIOU_SLCR_BANK2_CTRL0_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl1 + */ +#define XIOU_SLCR_BANK2_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL ) +#define XIOU_SLCR_BANK2_CTRL1_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl3 + */ +#define XIOU_SLCR_BANK2_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL ) +#define XIOU_SLCR_BANK2_CTRL3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Ctrl4 + */ +#define XIOU_SLCR_BANK2_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL ) +#define XIOU_SLCR_BANK2_CTRL4_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl5 + */ +#define XIOU_SLCR_BANK2_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL ) +#define XIOU_SLCR_BANK2_CTRL5_RSTVAL 0x03ffffffUL + +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL + +/** + * Register: XiouSlcrBank2Ctrl6 + */ +#define XIOU_SLCR_BANK2_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL ) +#define XIOU_SLCR_BANK2_CTRL6_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL +#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL + +/** + * Register: XiouSlcrBank2Sts + */ +#define XIOU_SLCR_BANK2_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL ) +#define XIOU_SLCR_BANK2_STS_RSTVAL 0x00000000UL + +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT 0UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH 1UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK 0x00000001UL +#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioLpbck + */ +#define XIOU_SLCR_MIO_LPBCK ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL ) +#define XIOU_SLCR_MIO_LPBCK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT 3UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK 0x00000008UL +#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT 2UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK 0x00000004UL +#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK 0x00000002UL +#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL 0x0UL + +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT 0UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH 1UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK 0x00000001UL +#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL 0x0UL + +/** + * Register: XiouSlcrMioMstTri0 + */ +#define XIOU_SLCR_MIO_MST_TRI0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL ) +#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri1 + */ +#define XIOU_SLCR_MIO_MST_TRI1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL ) +#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL 0xffffffffUL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrMioMstTri2 + */ +#define XIOU_SLCR_MIO_MST_TRI2 ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL ) +#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL 0x00003fffUL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x1UL + +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH 1UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001UL +#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x1UL + +/** + * Register: XiouSlcrWdtClkSel + */ +#define XIOU_SLCR_WDT_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL ) +#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_WDT_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_WDT_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_WDT_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCanMioCtrl + */ +#define XIOU_SLCR_CAN_MIO_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL ) +#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT 23UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK 0x00800000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT 22UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK 0x00400000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT 15UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK 0x003f8000UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT 8UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK 0x00000100UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH 1UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK 0x00000080UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT 0UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH 7UL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK 0x0000007fUL +#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemClkCtrl + */ +#define XIOU_SLCR_GEM_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL ) +#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT 22UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK 0x00400000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT 20UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL +#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdioClkCtrl + */ +#define XIOU_SLCR_SDIO_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL ) +#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT 18UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK 0x00040000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH 1UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK 0x00000004UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT 0UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH 2UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK 0x00000003UL +#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrCtrlRegSd + */ +#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL ) +#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 15UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00008000UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 0UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdItapdly + */ +#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL ) +#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL +#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdOtapdlysel + */ +#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL ) +#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL +#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg1 + */ +#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL ) +#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL + +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg2 + */ +#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL ) +#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 25UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 24UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 23UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 9UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 8UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 7UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL +#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCfgReg3 + */ +#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL ) +#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 18UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 17UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 16UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 2UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 0UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL +#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdInitpreset + */ +#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL ) +#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL + +/** + * Register: XiouSlcrSdDsppreset + */ +#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL ) +#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdHspdpreset + */ +#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL ) +#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr12preset + */ +#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL ) +#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL + +/** + * Register: XiouSlcrSdSdr25preset + */ +#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL ) +#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdSdr50prset + */ +#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL ) +#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL + +/** + * Register: XiouSlcrSdSdr104prst + */ +#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL ) +#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL +#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDdr50preset + */ +#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL ) +#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x1fff0000UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x00001fffUL +#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL + +/** + * Register: XiouSlcrSdMaxcur1p8 + */ +#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL ) +#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p0 + */ +#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL ) +#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdMaxcur3p3 + */ +#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL ) +#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x000000ffUL +#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdDllCtrl + */ +#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL ) +#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 18UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 2UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL +#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL + +/** + * Register: XiouSlcrSdCdnCtrl + */ +#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL ) +#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 16UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00010000UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 0UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00000001UL +#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrGemCtrl + */ +#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL ) +#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL +#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTtcApbClk + */ +#define XIOU_SLCR_TTC_APB_CLK ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL ) +#define XIOU_SLCR_TTC_APB_CLK_RSTVAL 0x00000000UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT 6UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK 0x000000c0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT 4UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030UL +#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000cUL +#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x0UL + +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT 0UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH 2UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003UL +#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrTapdlyBypass + */ +#define XIOU_SLCR_TAPDLY_BYPASS ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL ) +#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL 0x00000007UL + +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004UL +#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK 0x00000002UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL 0x1UL + +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT 0UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH 1UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK 0x00000001UL +#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL 0x1UL + +/** + * Register: XiouSlcrCoherentCtrl + */ +#define XIOU_SLCR_COHERENT_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL ) +#define XIOU_SLCR_COHERENT_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT 28UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK 0xf0000000UL +#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT 24UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL +#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 20UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x00f00000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 16UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x000f0000UL +#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 12UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000f000UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 8UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x00000f00UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x000000f0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 0UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000000fUL +#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL + +/** + * Register: XiouSlcrVideoPssClkSel + */ +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL ) +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK 0x00000002UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL 0x0UL + +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT 0UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH 1UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK 0x00000001UL +#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XiouSlcrInterconnectRoute + */ +#define XIOU_SLCR_INTERCONNECT_ROUTE ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL ) +#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL 0x00000000UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT 7UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK 0x00000080UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT 6UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 5UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000020UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 4UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000010UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 3UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000008UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 2UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000004UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000002UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 0UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000001UL +#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXemacps + */ +#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL ) +#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXsdps + */ +#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL ) +#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan0 + */ +#define XIOU_SLCR_RAM_CAN0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL ) +#define XIOU_SLCR_RAM_CAN0_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamCan1 + */ +#define XIOU_SLCR_RAM_CAN1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL ) +#define XIOU_SLCR_RAM_CAN1_RSTVAL 0x005b5b5bUL + +#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT 22UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK 0x00400000UL +#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT 19UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK 0x00380000UL +#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT 16UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK 0x00070000UL +#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT 14UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK 0x00004000UL +#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT 11UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK 0x00003800UL +#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT 8UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK 0x00000700UL +#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamLqspi + */ +#define XIOU_SLCR_RAM_LQSPI ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL ) +#define XIOU_SLCR_RAM_LQSPI_RSTVAL 0x00002ddbUL + +#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT 13UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK 0x00002000UL +#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT 10UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK 0x00001c00UL +#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT 7UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK 0x00000380UL +#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrRamXnandps8 + */ +#define XIOU_SLCR_RAM_XNANDPS8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL ) +#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL 0x0000005bUL + +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT 6UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH 1UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK 0x00000040UL +#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL 0x1UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK 0x00000038UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL 0x3UL + +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT 0UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH 3UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK 0x00000007UL +#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL 0x3UL + +/** + * Register: XiouSlcrCtrl + */ +#define XIOU_SLCR_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL ) +#define XIOU_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XIOU_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIsr + */ +#define XIOU_SLCR_ISR ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL ) +#define XIOU_SLCR_ISR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrImr + */ +#define XIOU_SLCR_IMR ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL ) +#define XIOU_SLCR_IMR_RSTVAL 0x00000001UL + +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XiouSlcrIer + */ +#define XIOU_SLCR_IER ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL ) +#define XIOU_SLCR_IER_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrIdr + */ +#define XIOU_SLCR_IDR ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL ) +#define XIOU_SLCR_IDR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XiouSlcrItr + */ +#define XIOU_SLCR_ITR ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL ) +#define XIOU_SLCR_ITR_RSTVAL 0x00000000UL + +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XIOU_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h b/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h new file mode 100644 index 00000000..cc05672e --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h @@ -0,0 +1,5667 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_H__ +#define __XLPD_SLCR_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcr Base Address + */ +#define XLPD_SLCR_BASEADDR 0xFF410000UL + +/** + * Register: XlpdSlcrWprot0 + */ +#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL ) +#define XLPD_SLCR_WPROT0_RSTVAL 0x00000001UL + +#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL +#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL +#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL +#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCtrl + */ +#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsr + */ +#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrImr + */ +#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIer + */ +#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIdr + */ +#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrItr + */ +#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk0 + */ +#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL ) +#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk1 + */ +#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL ) +#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk2 + */ +#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL ) +#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSafetyChk3 + */ +#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL ) +#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT 0UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH 32UL +#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrXcsupmuWdtClkSel + */ +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL ) +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT 0UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH 1UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK 0x00000001UL +#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAdmaCfg + */ +#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL ) +#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000028UL + +#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT 5UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH 2UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK 0x00000060UL +#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL +#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL + +/** + * Register: XlpdSlcrAdmaRam + */ +#define XLPD_SLCR_ADMA_RAM ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL ) +#define XLPD_SLCR_ADMA_RAM_RSTVAL 0x00003b3bUL + +#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT 12UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK 0x00007000UL +#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT 11UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK 0x00000800UL +#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT 8UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK 0x00000700UL +#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT 4UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK 0x00000070UL +#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL 0x3UL + +#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT 3UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH 1UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK 0x00000008UL +#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL 0x1UL + +#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT 0UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH 3UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK 0x00000007UL +#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrErrAibaxiIsr + */ +#define XLPD_SLCR_ERR_AIBAXI_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL ) +#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiImr + */ +#define XLPD_SLCR_ERR_AIBAXI_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL ) +#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL 0x1dcf000fUL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibaxiIer + */ +#define XLPD_SLCR_ERR_AIBAXI_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL ) +#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibaxiIdr + */ +#define XLPD_SLCR_ERR_AIBAXI_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL ) +#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT 27UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIsr + */ +#define XLPD_SLCR_ERR_AIBAPB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL ) +#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbImr + */ +#define XLPD_SLCR_ERR_AIBAPB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL ) +#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAibapbIer + */ +#define XLPD_SLCR_ERR_AIBAPB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL ) +#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAibapbIdr + */ +#define XLPD_SLCR_ERR_AIBAPB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL ) +#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiReq + */ +#define XLPD_SLCR_ISO_AIBAXI_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL ) +#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibaxiType + */ +#define XLPD_SLCR_ISO_AIBAXI_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL ) +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL 0x19cf000fUL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL 0x1UL + +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibaxiAck + */ +#define XLPD_SLCR_ISO_AIBAXI_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL ) +#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK 0x10000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT 27UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK 0x08000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK 0x04000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK 0x01000000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK 0x00800000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK 0x00400000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK 0x00080000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK 0x00040000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK 0x00020000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK 0x00010000UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK 0x00000008UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK 0x00000004UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK 0x00000002UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL 0x0UL + +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbReq + */ +#define XLPD_SLCR_ISO_AIBAPB_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL ) +#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrIsoAibapbType + */ +#define XLPD_SLCR_ISO_AIBAPB_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL ) +#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL 0x00000001UL + +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrIsoAibapbAck + */ +#define XLPD_SLCR_ISO_AIBAPB_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL ) +#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK 0x00000001UL +#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIsr + */ +#define XLPD_SLCR_ERR_ATB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL ) +#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbImr + */ +#define XLPD_SLCR_ERR_ATB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL ) +#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrErrAtbIer + */ +#define XLPD_SLCR_ERR_ATB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL ) +#define XLPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrErrAtbIdr + */ +#define XLPD_SLCR_ERR_ATB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL ) +#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbCmdStoreEn + */ +#define XLPD_SLCR_ATB_CMD_STORE_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL ) +#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbRespEn + */ +#define XLPD_SLCR_ATB_RESP_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL ) +#define XLPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAtbRespType + */ +#define XLPD_SLCR_ATB_RESP_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL ) +#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL 0x00000003UL + +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK 0x00000002UL +#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL 0x1UL + +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK 0x00000001UL +#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrAtbPrescale + */ +#define XLPD_SLCR_ATB_PRESCALE ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL ) +#define XLPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL + +#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL +#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL +#define XLPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL +#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL + +#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL +#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL +#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL + +/** + * Register: XlpdSlcrMutex0 + */ +#define XLPD_SLCR_MUTEX0 ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL ) +#define XLPD_SLCR_MUTEX0_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX0_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX0_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX0_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX0_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex1 + */ +#define XLPD_SLCR_MUTEX1 ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL ) +#define XLPD_SLCR_MUTEX1_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX1_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX1_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX1_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX1_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex2 + */ +#define XLPD_SLCR_MUTEX2 ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL ) +#define XLPD_SLCR_MUTEX2_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX2_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX2_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX2_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX2_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrMutex3 + */ +#define XLPD_SLCR_MUTEX3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL ) +#define XLPD_SLCR_MUTEX3_RSTVAL 0x00000000UL + +#define XLPD_SLCR_MUTEX3_ID_SHIFT 0UL +#define XLPD_SLCR_MUTEX3_ID_WIDTH 32UL +#define XLPD_SLCR_MUTEX3_ID_MASK 0xffffffffUL +#define XLPD_SLCR_MUTEX3_ID_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqSts + */ +#define XLPD_SLCR_GICP0_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL ) +#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqMsk + */ +#define XLPD_SLCR_GICP0_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL ) +#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp0IrqEn + */ +#define XLPD_SLCR_GICP0_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL ) +#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqDis + */ +#define XLPD_SLCR_GICP0_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL ) +#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp0IrqTrig + */ +#define XLPD_SLCR_GICP0_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL ) +#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqSts + */ +#define XLPD_SLCR_GICP1_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL ) +#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqMsk + */ +#define XLPD_SLCR_GICP1_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL ) +#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp1IrqEn + */ +#define XLPD_SLCR_GICP1_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL ) +#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqDis + */ +#define XLPD_SLCR_GICP1_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL ) +#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp1IrqTrig + */ +#define XLPD_SLCR_GICP1_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL ) +#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqSts + */ +#define XLPD_SLCR_GICP2_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL ) +#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqMsk + */ +#define XLPD_SLCR_GICP2_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL ) +#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp2IrqEn + */ +#define XLPD_SLCR_GICP2_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL ) +#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqDis + */ +#define XLPD_SLCR_GICP2_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL ) +#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp2IrqTrig + */ +#define XLPD_SLCR_GICP2_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL ) +#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqSts + */ +#define XLPD_SLCR_GICP3_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL ) +#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqMsk + */ +#define XLPD_SLCR_GICP3_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL ) +#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp3IrqEn + */ +#define XLPD_SLCR_GICP3_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL ) +#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqDis + */ +#define XLPD_SLCR_GICP3_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL ) +#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp3IrqTrig + */ +#define XLPD_SLCR_GICP3_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL ) +#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqSts + */ +#define XLPD_SLCR_GICP4_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL ) +#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqMsk + */ +#define XLPD_SLCR_GICP4_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL ) +#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL 0xffffffffUL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicp4IrqEn + */ +#define XLPD_SLCR_GICP4_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL ) +#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqDis + */ +#define XLPD_SLCR_GICP4_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL ) +#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicp4IrqTrig + */ +#define XLPD_SLCR_GICP4_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL ) +#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT 31UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK 0x80000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT 30UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK 0x40000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT 29UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK 0x20000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT 28UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK 0x10000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT 27UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK 0x08000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT 26UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK 0x04000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT 25UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK 0x02000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT 24UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK 0x01000000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT 23UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK 0x00800000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT 22UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK 0x00400000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT 21UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK 0x00200000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT 20UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK 0x00100000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT 19UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK 0x00080000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT 18UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK 0x00040000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT 17UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK 0x00020000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT 16UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK 0x00010000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT 15UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK 0x00008000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT 14UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK 0x00004000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT 13UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK 0x00002000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT 12UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK 0x00001000UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT 11UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK 0x00000800UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT 10UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK 0x00000400UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT 9UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK 0x00000200UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT 8UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK 0x00000100UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqSts + */ +#define XLPD_SLCR_GICP_PMU_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqMsk + */ +#define XLPD_SLCR_GICP_PMU_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL 0x000000ffUL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL 0x1UL + +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrGicpPmuIrqEn + */ +#define XLPD_SLCR_GICP_PMU_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqDis + */ +#define XLPD_SLCR_GICP_PMU_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL ) +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrGicpPmuIrqTrig + */ +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL ) +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL 0x00000000UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT 7UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK 0x00000080UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT 6UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK 0x00000040UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT 5UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK 0x00000020UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT 4UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK 0x00000010UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT 3UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK 0x00000008UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT 2UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK 0x00000004UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK 0x00000002UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL 0x0UL + +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT 0UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH 1UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK 0x00000001UL +#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrAfiFs + */ +#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL ) +#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL + +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL +#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL + +/** + * Register: XlpdSlcrCci + */ +#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL ) +#define XLPD_SLCR_CCI_RSTVAL 0x03801c07UL + +#define XLPD_SLCR_CCI_SPR_SHIFT 28UL +#define XLPD_SLCR_CCI_SPR_WIDTH 4UL +#define XLPD_SLCR_CCI_SPR_MASK 0xf0000000UL +#define XLPD_SLCR_CCI_SPR_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT 27UL +#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS4_MASK 0x08000000UL +#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT 26UL +#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS3_MASK 0x04000000UL +#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT 25UL +#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS2_MASK 0x02000000UL +#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT 24UL +#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS1_MASK 0x01000000UL +#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT 23UL +#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH 1UL +#define XLPD_SLCR_CCI_QVNVNETS0_MASK 0x00800000UL +#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT 18UL +#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH 5UL +#define XLPD_SLCR_CCI_QOS_OVRRD_MASK 0x007c0000UL +#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT 17UL +#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M2_MASK 0x00020000UL +#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH 1UL +#define XLPD_SLCR_CCI_QVN_EN_M1_MASK 0x00010000UL +#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT 13UL +#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH 3UL +#define XLPD_SLCR_CCI_STRPG_GRAN_MASK 0x0000e000UL +#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT 12UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK 0x00001000UL +#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT 11UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK 0x00000800UL +#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT 10UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH 1UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK 0x00000400UL +#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT 6UL +#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH 4UL +#define XLPD_SLCR_CCI_ECOREVNUM_MASK 0x000003c0UL +#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA2_SHIFT 5UL +#define XLPD_SLCR_CCI_ASA2_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA2_MASK 0x00000020UL +#define XLPD_SLCR_CCI_ASA2_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA1_SHIFT 4UL +#define XLPD_SLCR_CCI_ASA1_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA1_MASK 0x00000010UL +#define XLPD_SLCR_CCI_ASA1_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ASA0_SHIFT 3UL +#define XLPD_SLCR_CCI_ASA0_WIDTH 1UL +#define XLPD_SLCR_CCI_ASA0_MASK 0x00000008UL +#define XLPD_SLCR_CCI_ASA0_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_OWO2_SHIFT 2UL +#define XLPD_SLCR_CCI_OWO2_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO2_MASK 0x00000004UL +#define XLPD_SLCR_CCI_OWO2_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO1_SHIFT 1UL +#define XLPD_SLCR_CCI_OWO1_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO1_MASK 0x00000002UL +#define XLPD_SLCR_CCI_OWO1_DEFVAL 0x1UL + +#define XLPD_SLCR_CCI_OWO0_SHIFT 0UL +#define XLPD_SLCR_CCI_OWO0_WIDTH 1UL +#define XLPD_SLCR_CCI_OWO0_MASK 0x00000001UL +#define XLPD_SLCR_CCI_OWO0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrCciAddrmap + */ +#define XLPD_SLCR_CCI_ADDRMAP ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL ) +#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL 0x00c000ffUL + +#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT 30UL +#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_15_MASK 0xc0000000UL +#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT 28UL +#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_14_MASK 0x30000000UL +#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT 26UL +#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_13_MASK 0x0c000000UL +#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT 24UL +#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_12_MASK 0x03000000UL +#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT 22UL +#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_11_MASK 0x00c00000UL +#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT 20UL +#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_10_MASK 0x00300000UL +#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT 18UL +#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_9_MASK 0x000c0000UL +#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT 16UL +#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_8_MASK 0x00030000UL +#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT 14UL +#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_7_MASK 0x0000c000UL +#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT 12UL +#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_6_MASK 0x00003000UL +#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT 10UL +#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_5_MASK 0x00000c00UL +#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT 8UL +#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_4_MASK 0x00000300UL +#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL 0x0UL + +#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT 6UL +#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_3_MASK 0x000000c0UL +#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT 4UL +#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_2_MASK 0x00000030UL +#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_1_MASK 0x0000000cUL +#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT 0UL +#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH 2UL +#define XLPD_SLCR_CCI_ADDRMAP_0_MASK 0x00000003UL +#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrCciQvnprealloc + */ +#define XLPD_SLCR_CCI_QVNPREALLOC ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL ) +#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL 0x00330330UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT 20UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK 0x00f00000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT 16UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK 0x000f0000UL +#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT 8UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK 0x00000f00UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL 0x3UL + +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH 4UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK 0x000000f0UL +#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL 0x3UL + +/** + * Register: XlpdSlcrSmmu + */ +#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL ) +#define XLPD_SLCR_SMMU_RSTVAL 0x0000003fUL + +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT 7UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH 1UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK 0x00000080UL +#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_CTTW_SHIFT 6UL +#define XLPD_SLCR_SMMU_CTTW_WIDTH 1UL +#define XLPD_SLCR_SMMU_CTTW_MASK 0x00000040UL +#define XLPD_SLCR_SMMU_CTTW_DEFVAL 0x0UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT 5UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK 0x00000020UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT 4UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK 0x00000010UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT 3UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK 0x00000008UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT 2UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK 0x00000004UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK 0x00000002UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL 0x1UL + +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT 0UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH 1UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK 0x00000001UL +#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrApu + */ +#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL ) +#define XLPD_SLCR_APU_RSTVAL 0x00000001UL + +#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL +#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL +#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL +#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL +#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL +#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL +#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL + +#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL +#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL +#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL +#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h b/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h new file mode 100644 index 00000000..aff3bf2f --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h @@ -0,0 +1,141 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_SLCR_SECURE_H__ +#define __XLPD_SLCR_SECURE_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdSlcrSecure Base Address + */ +#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL + +/** + * Register: XlpdSlcrSecCtrl + */ +#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) +#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL +#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIsr + */ +#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) +#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecImr + */ +#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) +#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL + +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL + +/** + * Register: XlpdSlcrSecIer + */ +#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) +#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecIdr + */ +#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) +#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecItr + */ +#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) +#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL +#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecRpu + */ +#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) +#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL + +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecAdma + */ +#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL ) +#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL +#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL +#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL +#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecSafetyChk + */ +#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) +#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL + +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL +#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL + +/** + * Register: XlpdSlcrSecUsb + */ +#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL ) +#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL + +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL +#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h b/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h new file mode 100644 index 00000000..a5145eac --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h @@ -0,0 +1,858 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_H__ +#define __XLPD_XPPU_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppu Base Address + */ +#define XLPD_XPPU_BASEADDR 0xFF980000UL + +/** + * Register: XlpdXppuCtrl + */ +#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL ) +#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL + +#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL +#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL +#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL + +#define XLPD_XPPU_CTRL_EN_SHIFT 0UL +#define XLPD_XPPU_CTRL_EN_WIDTH 1UL +#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL +#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts1 + */ +#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL ) +#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuErrSts2 + */ +#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL ) +#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL +#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuPoison + */ +#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL ) +#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL + +#define XLPD_XPPU_POISON_BASE_SHIFT 0UL +#define XLPD_XPPU_POISON_BASE_WIDTH 20UL +#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL +#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIsr + */ +#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL ) +#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuImr + */ +#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL ) +#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL + +#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL + +#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XlpdXppuIen + */ +#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL ) +#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuIds + */ +#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL ) +#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL +#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL +#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL +#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL +#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL +#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL +#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL +#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL +#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL +#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL +#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL +#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL +#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL +#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL +#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL + +#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL +#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL +#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL +#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMMstrIds + */ +#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL ) +#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL + +#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL +#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL +#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL + +/** + * Register: XlpdXppuMAperture32b + */ +#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL ) +#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL + +#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMAperture64kb + */ +#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL ) +#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL + +#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL + +/** + * Register: XlpdXppuMAperture1mb + */ +#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL ) +#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL + +#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMAperture512mb + */ +#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL ) +#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL + +#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL +#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL +#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL + +/** + * Register: XlpdXppuBase32b + */ +#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL ) +#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL + +#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL + +/** + * Register: XlpdXppuBase64kb + */ +#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL ) +#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL + +#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL + +/** + * Register: XlpdXppuBase1mb + */ +#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL ) +#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL + +#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL + +/** + * Register: XlpdXppuBase512mb + */ +#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL ) +#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL + +#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL +#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL +#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL +#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL + +/** + * Register: XlpdXppuMstrId00 + */ +#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL ) +#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL + +#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL + +#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL + +/** + * Register: XlpdXppuMstrId01 + */ +#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL ) +#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL + +#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId02 + */ +#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL ) +#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL + +#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL + +#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL + +/** + * Register: XlpdXppuMstrId03 + */ +#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL ) +#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL + +#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL + +#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId04 + */ +#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL ) +#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL + +#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL + +/** + * Register: XlpdXppuMstrId05 + */ +#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL ) +#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL + +#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL + +/** + * Register: XlpdXppuMstrId06 + */ +#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL ) +#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL + +#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL + +/** + * Register: XlpdXppuMstrId07 + */ +#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL ) +#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL + +#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL + +#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL + +#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL + +/** + * Register: XlpdXppuMstrId08 + */ +#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL ) +#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId09 + */ +#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL ) +#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId10 + */ +#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL ) +#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId11 + */ +#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL ) +#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId12 + */ +#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL ) +#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId13 + */ +#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL ) +#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId14 + */ +#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL ) +#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId15 + */ +#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL ) +#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId16 + */ +#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL ) +#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId17 + */ +#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL ) +#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId18 + */ +#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL ) +#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL + +/** + * Register: XlpdXppuMstrId19 + */ +#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL ) +#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL + +#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL +#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL +#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL +#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL +#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL +#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL +#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL +#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL + +#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL +#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL +#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL +#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h b/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h new file mode 100644 index 00000000..95f7e20a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h @@ -0,0 +1,81 @@ +/* ### HEADER ### */ + +#ifndef __XLPD_XPPU_SINK_H__ +#define __XLPD_XPPU_SINK_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XlpdXppuSink Base Address + */ +#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL + +/** + * Register: XlpdXppuSinkErrSts + */ +#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL ) +#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL +#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL + +#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL +#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIsr + */ +#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL ) +#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkImr + */ +#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL ) +#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL + +#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL + +/** + * Register: XlpdXppuSinkIer + */ +#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL ) +#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL + +/** + * Register: XlpdXppuSinkIdr + */ +#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL ) +#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL + +#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL +#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XLPD_XPPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h b/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h new file mode 100644 index 00000000..5e3631f3 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h @@ -0,0 +1,1304 @@ +/* ### HEADER ### */ + +#ifndef __XOCM_XMPU_CFG_H__ +#define __XOCM_XMPU_CFG_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * XocmXmpuCfg Base Address + */ +#define XOCM_XMPU_CFG_BASEADDR 0xFFA70000UL + +/** + * Register: XocmXmpuCfgCtrl + */ +#define XOCM_XMPU_CFG_CTRL ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL ) +#define XOCM_XMPU_CFG_CTRL_RSTVAL 0x00000003UL + +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL +#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL +#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL +#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgErrSts1 + */ +#define XOCM_XMPU_CFG_ERR_STS1 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL ) +#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL +#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgErrSts2 + */ +#define XOCM_XMPU_CFG_ERR_STS2 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL ) +#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgPoison + */ +#define XOCM_XMPU_CFG_POISON ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) +#define XOCM_XMPU_CFG_POISON_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL +#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_POISON_BASE_SHIFT 0UL +#define XOCM_XMPU_CFG_POISON_BASE_WIDTH 20UL +#define XOCM_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL +#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIsr + */ +#define XOCM_XMPU_CFG_ISR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL ) +#define XOCM_XMPU_CFG_ISR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgImr + */ +#define XOCM_XMPU_CFG_IMR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL ) +#define XOCM_XMPU_CFG_IMR_RSTVAL 0x0000000fUL + +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL + +/** + * Register: XocmXmpuCfgIen + */ +#define XOCM_XMPU_CFG_IEN ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL ) +#define XOCM_XMPU_CFG_IEN_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgIds + */ +#define XOCM_XMPU_CFG_IDS ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) +#define XOCM_XMPU_CFG_IDS_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL +#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL +#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL +#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT 0UL +#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH 1UL +#define XOCM_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL +#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgLock + */ +#define XOCM_XMPU_CFG_LOCK ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL ) +#define XOCM_XMPU_CFG_LOCK_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL +#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Strt + */ +#define XOCM_XMPU_CFG_R00_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL ) +#define XOCM_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00End + */ +#define XOCM_XMPU_CFG_R00_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL ) +#define XOCM_XMPU_CFG_R00_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00Mstr + */ +#define XOCM_XMPU_CFG_R00_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL ) +#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR00 + */ +#define XOCM_XMPU_CFG_R00 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) +#define XOCM_XMPU_CFG_R00_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R00_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R00_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R00_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R00_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Strt + */ +#define XOCM_XMPU_CFG_R01_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL ) +#define XOCM_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01End + */ +#define XOCM_XMPU_CFG_R01_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL ) +#define XOCM_XMPU_CFG_R01_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01Mstr + */ +#define XOCM_XMPU_CFG_R01_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL ) +#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR01 + */ +#define XOCM_XMPU_CFG_R01 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) +#define XOCM_XMPU_CFG_R01_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R01_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R01_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R01_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R01_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Strt + */ +#define XOCM_XMPU_CFG_R02_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL ) +#define XOCM_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02End + */ +#define XOCM_XMPU_CFG_R02_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL ) +#define XOCM_XMPU_CFG_R02_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02Mstr + */ +#define XOCM_XMPU_CFG_R02_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL ) +#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR02 + */ +#define XOCM_XMPU_CFG_R02 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) +#define XOCM_XMPU_CFG_R02_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R02_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R02_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R02_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R02_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Strt + */ +#define XOCM_XMPU_CFG_R03_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL ) +#define XOCM_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03End + */ +#define XOCM_XMPU_CFG_R03_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL ) +#define XOCM_XMPU_CFG_R03_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03Mstr + */ +#define XOCM_XMPU_CFG_R03_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL ) +#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR03 + */ +#define XOCM_XMPU_CFG_R03 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) +#define XOCM_XMPU_CFG_R03_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R03_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R03_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R03_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R03_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Strt + */ +#define XOCM_XMPU_CFG_R04_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL ) +#define XOCM_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04End + */ +#define XOCM_XMPU_CFG_R04_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL ) +#define XOCM_XMPU_CFG_R04_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04Mstr + */ +#define XOCM_XMPU_CFG_R04_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL ) +#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR04 + */ +#define XOCM_XMPU_CFG_R04 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) +#define XOCM_XMPU_CFG_R04_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R04_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R04_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R04_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R04_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Strt + */ +#define XOCM_XMPU_CFG_R05_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL ) +#define XOCM_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05End + */ +#define XOCM_XMPU_CFG_R05_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL ) +#define XOCM_XMPU_CFG_R05_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05Mstr + */ +#define XOCM_XMPU_CFG_R05_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL ) +#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR05 + */ +#define XOCM_XMPU_CFG_R05 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) +#define XOCM_XMPU_CFG_R05_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R05_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R05_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R05_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R05_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Strt + */ +#define XOCM_XMPU_CFG_R06_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL ) +#define XOCM_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06End + */ +#define XOCM_XMPU_CFG_R06_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL ) +#define XOCM_XMPU_CFG_R06_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06Mstr + */ +#define XOCM_XMPU_CFG_R06_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL ) +#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR06 + */ +#define XOCM_XMPU_CFG_R06 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) +#define XOCM_XMPU_CFG_R06_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R06_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R06_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R06_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R06_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Strt + */ +#define XOCM_XMPU_CFG_R07_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL ) +#define XOCM_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07End + */ +#define XOCM_XMPU_CFG_R07_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL ) +#define XOCM_XMPU_CFG_R07_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07Mstr + */ +#define XOCM_XMPU_CFG_R07_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL ) +#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR07 + */ +#define XOCM_XMPU_CFG_R07 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) +#define XOCM_XMPU_CFG_R07_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R07_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R07_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R07_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R07_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Strt + */ +#define XOCM_XMPU_CFG_R08_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL ) +#define XOCM_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08End + */ +#define XOCM_XMPU_CFG_R08_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL ) +#define XOCM_XMPU_CFG_R08_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08Mstr + */ +#define XOCM_XMPU_CFG_R08_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL ) +#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR08 + */ +#define XOCM_XMPU_CFG_R08 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) +#define XOCM_XMPU_CFG_R08_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R08_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R08_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R08_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R08_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Strt + */ +#define XOCM_XMPU_CFG_R09_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL ) +#define XOCM_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09End + */ +#define XOCM_XMPU_CFG_R09_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL ) +#define XOCM_XMPU_CFG_R09_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09Mstr + */ +#define XOCM_XMPU_CFG_R09_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL ) +#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR09 + */ +#define XOCM_XMPU_CFG_R09 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) +#define XOCM_XMPU_CFG_R09_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R09_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R09_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R09_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R09_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Strt + */ +#define XOCM_XMPU_CFG_R10_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) +#define XOCM_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10End + */ +#define XOCM_XMPU_CFG_R10_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) +#define XOCM_XMPU_CFG_R10_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10Mstr + */ +#define XOCM_XMPU_CFG_R10_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) +#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR10 + */ +#define XOCM_XMPU_CFG_R10 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) +#define XOCM_XMPU_CFG_R10_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R10_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R10_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R10_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R10_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Strt + */ +#define XOCM_XMPU_CFG_R11_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) +#define XOCM_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11End + */ +#define XOCM_XMPU_CFG_R11_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) +#define XOCM_XMPU_CFG_R11_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11Mstr + */ +#define XOCM_XMPU_CFG_R11_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) +#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR11 + */ +#define XOCM_XMPU_CFG_R11 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) +#define XOCM_XMPU_CFG_R11_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R11_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R11_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R11_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R11_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Strt + */ +#define XOCM_XMPU_CFG_R12_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) +#define XOCM_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12End + */ +#define XOCM_XMPU_CFG_R12_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) +#define XOCM_XMPU_CFG_R12_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12Mstr + */ +#define XOCM_XMPU_CFG_R12_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) +#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR12 + */ +#define XOCM_XMPU_CFG_R12 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) +#define XOCM_XMPU_CFG_R12_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R12_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R12_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R12_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R12_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Strt + */ +#define XOCM_XMPU_CFG_R13_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) +#define XOCM_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13End + */ +#define XOCM_XMPU_CFG_R13_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) +#define XOCM_XMPU_CFG_R13_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13Mstr + */ +#define XOCM_XMPU_CFG_R13_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) +#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR13 + */ +#define XOCM_XMPU_CFG_R13 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) +#define XOCM_XMPU_CFG_R13_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R13_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R13_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R13_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R13_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Strt + */ +#define XOCM_XMPU_CFG_R14_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) +#define XOCM_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14End + */ +#define XOCM_XMPU_CFG_R14_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) +#define XOCM_XMPU_CFG_R14_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14Mstr + */ +#define XOCM_XMPU_CFG_R14_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) +#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR14 + */ +#define XOCM_XMPU_CFG_R14 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) +#define XOCM_XMPU_CFG_R14_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R14_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R14_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R14_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R14_EN_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Strt + */ +#define XOCM_XMPU_CFG_R15_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) +#define XOCM_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15End + */ +#define XOCM_XMPU_CFG_R15_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) +#define XOCM_XMPU_CFG_R15_END_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH 28UL +#define XOCM_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL +#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15Mstr + */ +#define XOCM_XMPU_CFG_R15_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) +#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL + +#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL +#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL +#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL +#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL + +/** + * Register: XocmXmpuCfgR15 + */ +#define XOCM_XMPU_CFG_R15 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) +#define XOCM_XMPU_CFG_R15_RSTVAL 0x00000008UL + +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL +#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT 3UL +#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL +#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL + +#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT 2UL +#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL +#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL +#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL + +#define XOCM_XMPU_CFG_R15_EN_SHIFT 0UL +#define XOCM_XMPU_CFG_R15_EN_WIDTH 1UL +#define XOCM_XMPU_CFG_R15_EN_MASK 0x00000001UL +#define XOCM_XMPU_CFG_R15_EN_DEFVAL 0x0UL + + +#ifdef __cplusplus +} +#endif + +#endif /* __XOCM_XMPU_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xparameters_ps.h b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h new file mode 100644 index 00000000..3a164ca0 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h @@ -0,0 +1,315 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex R5 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp  	02/29/14 Initial version
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XPARAMETERS_PS_H_ +#define XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID +#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID +#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID +#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID +#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U + + +/* Shared Peripheral Interrupts (SPI) */ + +/* FIXME */ +/*#define XPS_FPGA0_INT_ID 100U */ +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Updated Interrupt-IDs */ +#define XPS_OCMINTR_INT_ID (10U + 32U) +#define XPS_NAND_INT_ID (14U + 32U) +#define XPS_QSPI_INT_ID (15U + 32U) +#define XPS_GPIO_INT_ID (16U + 32U) +#define XPS_I2C0_INT_ID (17U + 32U) +#define XPS_I2C1_INT_ID (18U + 32U) +#define XPS_SPI0_INT_ID (19U + 32U) +#define XPS_SPI1_INT_ID (20U + 32U) +#define XPS_UART0_INT_ID (21U + 32U) +#define XPS_UART1_INT_ID (22U + 32U) +#define XPS_CAN0_INT_ID (23U + 32U) +#define XPS_CAN1_INT_ID (24U + 32U) +#define XPS_WDT_INT_ID (52U + 32U) +#define XPS_TTC0_0_INT_ID (36U + 32U) +#define XPS_TTC0_1_INT_ID (37U + 32U) +#define XPS_TTC0_2_INT_ID (38U + 32U) +#define XPS_TTC1_0_INT_ID (39U + 32U) +#define XPS_TTC1_1_INT_ID (40U + 32U) +#define XPS_TTC1_2_INT_ID (41U + 32U) +#define XPS_TTC2_0_INT_ID (42U + 32U) +#define XPS_TTC2_1_INT_ID (43U + 32U) +#define XPS_TTC2_2_INT_ID (44U + 32U) +#define XPS_TTC3_0_INT_ID (45U + 32U) +#define XPS_TTC3_1_INT_ID (46U + 32U) +#define XPS_TTC3_2_INT_ID (47U + 32U) +#define XPS_SDIO0_INT_ID (48U + 32U) +#define XPS_SDIO1_INT_ID (49U + 32U) +#define XPS_GEM0_INT_ID (57U + 32U) +#define XPS_GEM0_WAKE_INT_ID (58U + 32U) +#define XPS_GEM1_INT_ID (59U + 32U) +#define XPS_GEM1_WAKE_INT_ID (60U + 32U) +#define XPS_GEM2_INT_ID (61U + 32U) +#define XPS_GEM2_WAKE_INT_ID (62U + 32U) +#define XPS_GEM3_INT_ID (63U + 32U) +#define XPS_GEM3_WAKE_INT_ID (64U + 32U) +#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) +#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) +#define XPS_ADMA_CH0_INT_ID (77U + 32U) +#define XPS_ADMA_CH1_INT_ID (78U + 32U) +#define XPS_ADMA_CH2_INT_ID (79U + 32U) +#define XPS_ADMA_CH3_INT_ID (80U + 32U) +#define XPS_ADMA_CH4_INT_ID (81U + 32U) +#define XPS_ADMA_CH5_INT_ID (82U + 32U) +#define XPS_ADMA_CH6_INT_ID (83U + 32U) +#define XPS_ADMA_CH7_INT_ID (84U + 32U) +#define XPS_CSU_DMA_INT_ID (86U + 32U) +#define XPS_XMPU_LPD_INT_ID (88U + 32U) +#define XPS_ZDMA_CH0_INT_ID (124U + 32U) +#define XPS_ZDMA_CH1_INT_ID (125U + 32U) +#define XPS_ZDMA_CH2_INT_ID (126U + 32U) +#define XPS_ZDMA_CH3_INT_ID (127U + 32U) +#define XPS_ZDMA_CH4_INT_ID (128U + 32U) +#define XPS_ZDMA_CH5_INT_ID (129U + 32U) +#define XPS_ZDMA_CH6_INT_ID (130U + 32U) +#define XPS_ZDMA_CH7_INT_ID (131U + 32U) +#define XPS_XMPU_FPD_INT_ID (134U + 32U) +#define XPS_FPD_CCI_INT_ID (154U + 32U) +#define XPS_FPD_SMMU_INT_ID (155U + 32U) + +/* Private Peripheral Interrupts (PPI) */ +/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */ +/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */ +/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */ +/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */ +/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */ + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID + +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xpm_counter.c b/lib/bsp/standalone/src/cortexr5/xpm_counter.c new file mode 100644 index 00000000..53d1e501 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpm_counter.c @@ -0,0 +1,292 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.c +* +* This file contains APIs for configuring and controlling the Cortex-R5 +* Performance Monitor Events. For more information about the event counters, +* see xpm_counter.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xpm_counter.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + + + +/************************** Function Prototypes ******************************/ + +void Xpm_DisableEventCounters(void); +void Xpm_EnableEventCounters (void); +void Xpm_ResetEventCounters (void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* This function disables the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + /* Disable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function enables the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + /* Enable the event counters */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); +} + +/****************************************************************************/ +/** +* +* This function resets the Cortex R5 event counters. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif + Reg |= (1U << 2U); /* reset event counters */ + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +} + +/****************************************************************************/ +/** +* +* This function configures the Cortex R5 event counters controller, with the +* event codes, in a configuration selected by the user and enables the counters. +* +* @param PmcrCfg is configuration value based on which the event counters +* are configured. +* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + { + XPM_EVENT_DATA_READS, + XPM_EVENT_DATA_WRITE, + XPM_EVENT_EXCEPTION, + XPM_EVENT_EXCEPRETURN, + XPM_EVENT_CHANGECONTEXT, + XPM_EVENT_SW_CHANGEPC + }, + { + XPM_EVENT_IMMEDBRANCH, + XPM_EVENT_UNALIGNEDACCESS, + XPM_EVENT_BRANCHMISS, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT, + XPM_EVENT_JAVABYTECODE + }, + { + XPM_EVENT_SWJAVABYTECODE, + XPM_EVENT_JAVABACKBRANCH, + XPM_EVENT_COHERLINEMISS, + XPM_EVENT_COHERLINEHIT, + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL + }, + { + XPM_EVENT_MAINTLBSTALL, + XPM_EVENT_STREXPASS, + XPM_EVENT_STREXFAIL, + XPM_EVENT_DATAEVICT, + XPM_EVENT_NODISPATCH, + XPM_EVENT_ISSUEEMPTY + }, + { + XPM_EVENT_INSTRRENAME, + XPM_EVENT_PREDICTFUNCRET, + XPM_EVENT_MAINEXEC, + XPM_EVENT_SECEXEC, + XPM_EVENT_LDRSTR, + XPM_EVENT_FLOATRENAME + }, + { + XPM_EVENT_NEONRENAME, + XPM_EVENT_PLDSTALL, + XPM_EVENT_WRITESTALL, + XPM_EVENT_INSTRTLBSTALL, + XPM_EVENT_DATATLBSTALL, + XPM_EVENT_INSTR_uTLBSTALL + }, + { + XPM_EVENT_DATA_uTLBSTALL, + XPM_EVENT_DMB_STALL, + XPM_EVENT_INT_CLKEN, + XPM_EVENT_DE_CLKEN, + XPM_EVENT_INSTRISB, + XPM_EVENT_INSTRDSB + }, + { + XPM_EVENT_INSTRDMB, + XPM_EVENT_EXTINT, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_PLE_OVFL, + XPM_EVENT_PLE_PROG, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_DATASTALL, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + /* Selecet event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); + } + + Xpm_ResetEventCounters(); + Xpm_EnableEventCounters(); +} + +/****************************************************************************/ +/** +* +* This function disables the event counters and returns the counter values. +* +* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xpm_GetEventCounters(u32 *PmCtrValue) +{ + u32 Counter; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); +#ifdef __GNUC__ + PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#else + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + PmCtrValue[Counter] = Cp15Reg; } +#endif + } +} diff --git a/lib/bsp/standalone/src/cortexr5/xpm_counter.h b/lib/bsp/standalone/src/cortexr5/xpm_counter.h new file mode 100644 index 00000000..355aab1a --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpm_counter.h @@ -0,0 +1,571 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* This header file contains APIs for configuring and controlling the Cortex-R5 +* Performance Monitor Events. +* Cortex-R5 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-R5 TRM. This file defines +* configurations, where value configures the event counters to count a +* set of events. +* +* Xpm_SetEvents can be used to set the event counters to count a set of events +* and Xpm_GetEventCounters can be used to read the counter values. +* +* @note +* +* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is +* being used for time keeping. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6U + +/* The following constants define the Cortex-R5 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00U + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03U + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04U + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05U + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06U + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07U + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09U + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0AU + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0BU + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0CU + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0DU + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10U + +/* + * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11U + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12U + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40U + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41U + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42U + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-R5 processor which also miss in all the other + * Cortex-R5 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50U + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-R5 processor which hit in another Cortex-R5 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-R5 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51U + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60U + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61U + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62U + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63U + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64U + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65U + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66U + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67U + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68U + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6EU + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70U + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71U + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72U + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73U + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74U + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80U + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83U + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85U + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86U + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8AU + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8BU + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90U + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91U + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92U + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93U + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0U + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1U + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2U + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3U + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4U + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5U + +/* + * The following constants define the configurations for Cortex-R5 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(s32 PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h b/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h new file mode 100644 index 00000000..571e85f6 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xpseudo_asm.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_H /* by using protection macros */ + +#include "xreg_cortexr5.h" +#include "xpseudo_asm_gcc.h" + +#endif /* XPSEUDO_ASM_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h b/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h new file mode 100644 index 00000000..81383100 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xreg_cortexr5.h @@ -0,0 +1,445 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexr5.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, IAR, ARMCC compiler. +* +* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 
+* +******************************************************************************/ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U + +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/*MPU region definitions*/ +#define REGION_32B 0x00000004U +#define REGION_64B 0x00000005U +#define REGION_128B 0x00000006U +#define REGION_256B 0x00000007U +#define REGION_512B 0x00000008U +#define REGION_1K 0x00000009U +#define REGION_2K 0x0000000AU +#define REGION_4K 0x0000000BU +#define REGION_8K 0x0000000CU +#define REGION_16K 0x0000000DU +#define REGION_32K 0x0000000EU +#define REGION_64K 0x0000000FU +#define REGION_128K 0x00000010U +#define REGION_256K 0x00000011U +#define REGION_512K 0x00000012U +#define REGION_1M 0x00000013U +#define REGION_2M 0x00000014U +#define REGION_4M 0x00000015U +#define REGION_8M 0x00000016U +#define REGION_16M 0x00000017U +#define REGION_32M 0x00000018U +#define REGION_64M 0x00000019U +#define REGION_128M 0x0000001AU +#define REGION_256M 0x0000001BU +#define REGION_512M 0x0000001CU +#define REGION_1G 0x0000001DU +#define REGION_2G 0x0000001EU +#define REGION_4G 0x0000001FU + +#define REGION_EN 0x00000001U + + + +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ + +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ + +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ + +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ + +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ + +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ + +/* inner and outer cache policies can be combined for different combinations */ + +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ + +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ + +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ + +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ + + +/* CP15 defines */ + +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U +/* C2 Register Defines */ +/* Not Used */ + +/* C3 Register Defines */ +/* Not Used */ + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" + +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex R5. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex R5. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +/* Not Used */ + + +/* C9 Register Defines */ + +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" + +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +/* Not used */ + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +/* Not used */ + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" + + + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXR5_H */ diff --git a/lib/bsp/standalone/src/cortexr5/xstatus.h b/lib/bsp/standalone/src/cortexr5/xstatus.h new file mode 100644 index 00000000..7db874c8 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xstatus.h @@ -0,0 +1,430 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef int XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/cortexr5/xtime_l.c b/lib/bsp/standalone/src/cortexr5/xtime_l.c new file mode 100644 index 00000000..a9727371 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xtime_l.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex R5 core. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp  08/29/14 First release
+* 
+* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/**************************************************************************** +* +* Set the time in the Global Timer Counter Register. +* +* @param Value to be written to the Global Timer Counter Register. +* +* @return None. +* +* @note In multiprocessor environment reference time will reset/lost for +* all processors, when this function called by any one processor. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + + +} + +/**************************************************************************** +* +* Get the time from the Global Timer Counter Register. +* +* @param Pointer to the location to be updated with the time. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + *Xtime_Global = Xil_In32(TTC3_BASEADDR+0x00000018U); +} diff --git a/lib/bsp/standalone/src/cortexr5/xtime_l.h b/lib/bsp/standalone/src/cortexr5/xtime_l.h new file mode 100644 index 00000000..b7525168 --- /dev/null +++ b/lib/bsp/standalone/src/cortexr5/xtime_l.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xparameters.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Constant Definitions *****************************/ + +#define COUNTS_PER_SECOND 0x0005F5E1U + +#define TTC3_BASEADDR 0xFF140000U +/**************************** Type Definitions *******************************/ + +typedef u32 XTime; + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/lib/bsp/standalone/src/microblaze/Makefile b/lib/bsp/standalone/src/microblaze/Makefile new file mode 100644 index 00000000..40c3c82d --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/Makefile @@ -0,0 +1,77 @@ +############################################################################### +# +# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### + +# The following are defined in config.make +# LIBSOURCES - Based on if MicroBlaze support Exceptions +# LIBS - Do Build Profile Libraries +include config.make + +AS=mb-as +CC=mb-gcc +AR=mb-ar +CP=cp +COMPILER_FLAGS=-O2 -c +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS)) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(LIBSOURCES) + echo "Compiling standalone"; + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs + +include: standalone_includes profile_includes + +standalone_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include + +clean: + rm -rf ${OUTS} + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean diff --git a/lib/bsp/standalone/src/microblaze/_exit.c b/lib/bsp/standalone/src/microblaze/_exit.c new file mode 100644 index 00000000..3fb2ec63 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/_exit.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include +#include "xil_types.h" +void _exit (sint32 status); + +/* _exit - Simple implementation. Does not return. +*/ +void _exit (sint32 status) +{ + (void) status; + while (1) + { + ; + } +} diff --git a/lib/bsp/standalone/src/microblaze/errno.c b/lib/bsp/standalone/src/microblaze/errno.c new file mode 100644 index 00000000..3d6fb202 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/errno.c @@ -0,0 +1,14 @@ +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" +sint32 * __errno (void); + +sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/lib/bsp/standalone/src/microblaze/fcntl.c b/lib/bsp/standalone/src/microblaze/fcntl.c new file mode 100644 index 00000000..257cee56 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/fcntl.c @@ -0,0 +1,15 @@ +#include +#include "xil_types.h" +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg); + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg) +{ + (void) fd; + (void) cmd; + (void) arg; + return 0; +} diff --git a/lib/bsp/standalone/src/microblaze/fsl.h b/lib/bsp/standalone/src/microblaze/fsl.h new file mode 100644 index 00000000..29906d95 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/fsl.h @@ -0,0 +1,47 @@ +#ifndef FSL_H +#define FSL_H + +#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Extended FSL macros. These now replace all of the previous FSL macros */ +#define FSL_DEFAULT +#define FSL_NONBLOCKING n +#define FSL_EXCEPTION e +#define FSL_CONTROL c +#define FSL_ATOMIC a + +#define FSL_NONBLOCKING_EXCEPTION ne +#define FSL_NONBLOCKING_CONTROL nc +#define FSL_NONBLOCKING_ATOMIC na +#define FSL_EXCEPTION_CONTROL ec +#define FSL_EXCEPTION_ATOMIC ea +#define FSL_CONTROL_ATOMIC ca + +#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec +#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea +#define FSL_NONBLOCKING_CONTROL_ATOMIC nca +#define FSL_EXCEPTION_CONTROL_ATOMIC eca + +#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca + +#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val)) +#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val)) + +#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val)) +#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id)) + +#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var)) +#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var)) + +#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var)) +#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var)) + + +#ifdef __cplusplus +} +#endif +#endif /* FSL_H */ diff --git a/lib/bsp/standalone/src/microblaze/hw_exception_handler.S b/lib/bsp/standalone/src/microblaze/hw_exception_handler.S new file mode 100644 index 00000000..7db0afd6 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/hw_exception_handler.S @@ -0,0 +1,659 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** + * Microblaze HW Exception Handler + * - Non self-modifying exception handler for the following exception conditions + * - Unalignment + * - Instruction bus error + * - Data bus error + * - Illegal instruction opcode + * - Divide-by-zero + * - Stack protection violation + *******************************************************************************/ + +#include "microblaze_exceptions_g.h" +#include "xparameters.h" + +/* Helpful Macros */ +#define EX_HANDLER_STACK_SIZ (4*21) +#define RMSR_OFFSET (20 * 4) +#define R17_OFFSET (0) +#define REG_OFFSET(regnum) (4 * (regnum + 1)) +#define NUM_TO_REG(num) r ## num + +#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum) +#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum) + +#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) +#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum) + +/* Uses r5 */ +#define PUSH_MSR \ + mfs r5, rmsr; \ + swi r5, r1, RMSR_OFFSET; + +#define PUSH_MSR_AND_ENABLE_EXC \ + mfs r5, rmsr; \ + swi r5, r1, RMSR_OFFSET; \ + ori r5, r5, 0x100; /* Turn ON the EE bit*/ \ + mts rmsr, r5; + +/* Uses r5 */ +#define POP_MSR \ + lwi r5, r1, RMSR_OFFSET; \ + mts rmsr, r5; + +/* Push r17 */ +#define PUSH_R17 swi r17, r1, R17_OFFSET +/* Pop r17 */ +#define POP_R17 lwi r17, r1, R17_OFFSET + +#define LWREG_NOP \ + bri ex_handler_unhandled; \ + nop; + +#define SWREG_NOP \ + bri ex_handler_unhandled; \ + nop; + +/* r3 is the source */ +#define R3_TO_LWREG_V(regnum) \ + R3_TO_STACK (regnum); \ + bri ex_handler_done; + +/* r3 is the source */ +#define R3_TO_LWREG(regnum) \ + or NUM_TO_REG (regnum), r0, r3; \ + bri ex_handler_done; + +/* r3 is the target */ +#define SWREG_TO_R3_V(regnum) \ + R3_FROM_STACK (regnum); \ + bri ex_sw_tail; + +/* r3 is the target */ +#define SWREG_TO_R3(regnum) \ + or r3, r0, NUM_TO_REG (regnum); \ + bri ex_sw_tail; + +/* regnum is the source */ +#define FP_EX_OPB_SAVE(regnum) \ + swi NUM_TO_REG (regnum), r0, mb_fpex_op_b; \ + nop; \ + bri handle_fp_ex_opa; + +/* regnum is the source */ +#define FP_EX_OPB_SAVE_V(regnum) \ + R3_FROM_STACK (regnum); \ + swi r3, r0, mb_fpex_op_b; \ + bri handle_fp_ex_opa; + +/* regnum is the source */ +#define FP_EX_OPA_SAVE(regnum) \ + swi NUM_TO_REG (regnum), r0, mb_fpex_op_a; \ + nop; \ + bri handle_fp_ex_done; + +/* regnum is the source */ +#define FP_EX_OPA_SAVE_V(regnum) \ + R3_FROM_STACK (regnum); \ + swi r3, r0, mb_fpex_op_a; \ + bri handle_fp_ex_done; + +#define FP_EX_UNHANDLED \ + bri fp_ex_unhandled; \ + nop; \ + nop; + +/* ESR masks */ +#define ESR_EXC_MASK 0x0000001F +#define ESR_REG_MASK 0x000003E0 +#define ESR_LW_SW_MASK 0x00000400 +#define ESR_WORD_MASK 0x00000800 +#define ESR_DS_MASK 0x00001000 + +/* Extern declarations */ +.extern XNullHandler + + +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */ + +/* + * hw_exception_handler - Handler for unaligned exceptions + * Exception handler notes: + * - Does not handle exceptions other than unaligned exceptions + * - Does not handle exceptions during load into r17, r1, r0. + * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case) + * + * Relevant register structures + * + * EAR - |----|----|----|----|----|----|----|----| + * - < ## 32 bit faulting address ## > + * + * ESR - |----|----|----|----|----| - | - |-----|-----| + * - W S REG EXC + * + * + * STACK FRAME STRUCTURE + * --------------------- + * + * +-------------+ + 0 + * | r17 | + * +-------------+ + 4 + * | Args for | + * | next func | + * +-------------+ + 8 + * | r1 | + * | . | + * | . | + * | . | + * | . | + * | r18 | + * +-------------+ + 80 + * | MSR | + * +-------------+ + 84 + * | . | + * | . | + */ + + +.global _hw_exception_handler +.section .text +.align 2 +.ent _hw_exception_handler +.type _hw_exception_handler, @function +_hw_exception_handler: + +#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) + /* Immediately halt for stack protection violation exception without using any stack */ + swi r3, r0, mb_sp_save_r3; /* Save temporary register */ + mfs r3, resr; /* Extract ESR[DS] */ + andi r3, r3, ESR_EXC_MASK; + xori r3, r3, 0x7; /* Check for stack protection violation */ + bnei r3, ex_handler_not_sp_violation; +ex_handler_sp_violation: + bri 0; /* Halt here if stack protection violation */ +ex_handler_not_sp_violation: + lwi r3, r0, mb_sp_save_r3; /* Restore temporary register */ +#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */ + + addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ + PUSH_REG(3); + PUSH_REG(4); + PUSH_REG(5); + PUSH_REG(6); +#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS + mfs r6, resr; + andi r6, r6, ESR_DS_MASK; + beqi r6, ex_handler_no_ds; + mfs r17, rbtr; +ex_handler_no_ds: +#endif + PUSH_R17; + PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */ + + mfs r3, resr; + andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */ +#ifndef NO_UNALIGNED_EXCEPTIONS + xori r6, r5, 1; /* 00001 = Unaligned Exception */ + bnei r6, handle_ex_regular; + + la r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */ + lwi r4, r4, 8; + la r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */ + xor r6, r4, r6; /* the default exception handler */ + beqi r6, handle_unaligned_ex ; + +handle_ex_regular: +#endif /* ! NO_UNALIGNED_EXCEPTIONS */ + +#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) + xori r6, r5, 6; /* 00110 = FPU exception */ + beqi r6, handle_fp_ex; /* Go and decode the FP exception */ +#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ + +handle_other_ex: /* Handle Other exceptions here */ + ori r6, r0, 20; + cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */ + blei r6, ex_handler_unhandled; + + ori r6, r0, 7; + cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */ + bgti r6, handle_other_ex_tail; + ori r5, r0, 0x7; + +handle_other_ex_tail: + PUSH_REG(7); /* Save other volatiles before we make procedure calls below */ + PUSH_REG(8); + PUSH_REG(9); + PUSH_REG(10); + PUSH_REG(11); + PUSH_REG(12); + PUSH_REG(15); + PUSH_REG(18); + + la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */ + addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */ + addk r7, r7, r7; + addk r7, r7, r7; + addk r7, r7, r4; /* Get pointer to exception vector */ + lwi r5, r7, 4; /* Load argument to exception handler from table */ + lw r7, r7, r0; /* Load vector itself here */ + + brald r15, r7; /* Branch to handler */ + nop; + + POP_REG(7); /* Restore other volatiles */ + POP_REG(8); + POP_REG(9); + POP_REG(10); + POP_REG(11); + POP_REG(12); + POP_REG(15); + POP_REG(18); + + bri ex_handler_done; /* Complete exception handling */ + +#ifndef NO_UNALIGNED_EXCEPTIONS +handle_unaligned_ex: + andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */ + srl r6, r6; /* r6 >> 5 */ + srl r6, r6; + srl r6, r6; + srl r6, r6; + srl r6, r6; + sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */ + mfs r4, rear; + andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */ + bnei r6, ex_sw; +ex_lw: + andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */ + beqi r6, ex_lhw; + lbui r5, r4, 0; /* Exception address in r4 */ + sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */ + lbui r5, r4, 1; + sbi r5, r0, ex_tmp_data_loc_1; + lbui r5, r4, 2; + sbi r5, r0, ex_tmp_data_loc_2; + lbui r5, r4, 3; + sbi r5, r0, ex_tmp_data_loc_3; + lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ + bri ex_lw_tail; +ex_lhw: + lbui r5, r4, 0; /* Exception address in r4 */ + sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */ + lbui r5, r4, 1; + sbi r5, r0, ex_tmp_data_loc_1; + lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */ +ex_lw_tail: + lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ + la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */ + addk r5, r5, r5; + addk r5, r5, r5; + addk r5, r5, r5; + addk r5, r5, r6; + bra r5; +ex_lw_end: /* Exception handling of load word, ends */ +ex_sw: + lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */ + la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */ + add r5, r5, r5; + add r5, r5, r5; + add r5, r5, r5; + add r5, r5, r6; + bra r5; +ex_sw_tail: + mfs r6, resr; + andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */ + beqi r6, ex_shw; + swi r3, r0, ex_tmp_data_loc_0; + lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */ + sbi r3, r4, 0; + lbui r3, r0, ex_tmp_data_loc_1; + sbi r3, r4, 1; + lbui r3, r0, ex_tmp_data_loc_2; + sbi r3, r4, 2; + lbui r3, r0, ex_tmp_data_loc_3; + sbi r3, r4, 3; + bri ex_handler_done; +ex_shw: + swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */ + +#ifdef __LITTLE_ENDIAN__ + lbui r3, r0, ex_tmp_data_loc_0; +#else + lbui r3, r0, ex_tmp_data_loc_2; +#endif + sbi r3, r4, 0; +#ifdef __LITTLE_ENDIAN__ + lbui r3, r0, ex_tmp_data_loc_1; +#else + lbui r3, r0, ex_tmp_data_loc_3; +#endif + sbi r3, r4, 1; +ex_sw_end: /* Exception handling of store word, ends. */ + bri ex_handler_done; +#endif /* !NO_UNALIGNED_EXCEPTIONS */ + +#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) +handle_fp_ex: + addik r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */ + lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */ + +handle_fp_ex_opb: + la r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */ + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + andi r3, r4, 0x1F; + add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ + add r3, r3, r3; + add r5, r3, r3; + add r5, r5, r3; + add r5, r5, r6; + bra r5; + +handle_fp_ex_opa: + la r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */ + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + srl r4, r4; + andi r3, r4, 0x1F; + add r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */ + add r3, r3, r3; + add r5, r3, r3; + add r5, r5, r3; + add r5, r5, r6; + bra r5; + +handle_fp_ex_done: + ori r5, r0, 6; /* Set exception number back to 6 */ + bri handle_other_ex_tail; + +fp_ex_unhandled: + bri 0; +#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ + +ex_handler_done: + POP_R17; + POP_MSR; + POP_REG(3); + POP_REG(4); + POP_REG(5); + POP_REG(6); + + rted r17, 0 + addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */ +ex_handler_unhandled: + bri 0 /* UNHANDLED. TRAP HERE */ +.end _hw_exception_handler + +#ifndef NO_UNALIGNED_EXCEPTIONS + +/* + * hw_exception_handler Jump Table + * - Contains code snippets for each register that caused the unaligned exception. + * - Hence exception handler is NOT self-modifying + * - Separate table for load exceptions and store exceptions. + * - Each table is of size: (8 * 32) = 256 bytes + */ + +.section .text +.align 4 +lw_table: +lw_r0: R3_TO_LWREG (0); +lw_r1: LWREG_NOP; +lw_r2: R3_TO_LWREG (2); +lw_r3: R3_TO_LWREG_V (3); +lw_r4: R3_TO_LWREG_V (4); +lw_r5: R3_TO_LWREG_V (5); +lw_r6: R3_TO_LWREG_V (6); +lw_r7: R3_TO_LWREG (7); +lw_r8: R3_TO_LWREG (8); +lw_r9: R3_TO_LWREG (9); +lw_r10: R3_TO_LWREG (10); +lw_r11: R3_TO_LWREG (11); +lw_r12: R3_TO_LWREG (12); +lw_r13: R3_TO_LWREG (13); +lw_r14: R3_TO_LWREG (14); +lw_r15: R3_TO_LWREG (15); +lw_r16: R3_TO_LWREG (16); +lw_r17: LWREG_NOP; +lw_r18: R3_TO_LWREG (18); +lw_r19: R3_TO_LWREG (19); +lw_r20: R3_TO_LWREG (20); +lw_r21: R3_TO_LWREG (21); +lw_r22: R3_TO_LWREG (22); +lw_r23: R3_TO_LWREG (23); +lw_r24: R3_TO_LWREG (24); +lw_r25: R3_TO_LWREG (25); +lw_r26: R3_TO_LWREG (26); +lw_r27: R3_TO_LWREG (27); +lw_r28: R3_TO_LWREG (28); +lw_r29: R3_TO_LWREG (29); +lw_r30: R3_TO_LWREG (30); +lw_r31: R3_TO_LWREG (31); + +sw_table: +sw_r0: SWREG_TO_R3 (0); +sw_r1: SWREG_NOP; +sw_r2: SWREG_TO_R3 (2); +sw_r3: SWREG_TO_R3_V (3); +sw_r4: SWREG_TO_R3_V (4); +sw_r5: SWREG_TO_R3_V (5); +sw_r6: SWREG_TO_R3_V (6); +sw_r7: SWREG_TO_R3 (7); +sw_r8: SWREG_TO_R3 (8); +sw_r9: SWREG_TO_R3 (9); +sw_r10: SWREG_TO_R3 (10); +sw_r11: SWREG_TO_R3 (11); +sw_r12: SWREG_TO_R3 (12); +sw_r13: SWREG_TO_R3 (13); +sw_r14: SWREG_TO_R3 (14); +sw_r15: SWREG_TO_R3 (15); +sw_r16: SWREG_TO_R3 (16); +sw_r17: SWREG_NOP; +sw_r18: SWREG_TO_R3 (18); +sw_r19: SWREG_TO_R3 (19); +sw_r20: SWREG_TO_R3 (20); +sw_r21: SWREG_TO_R3 (21); +sw_r22: SWREG_TO_R3 (22); +sw_r23: SWREG_TO_R3 (23); +sw_r24: SWREG_TO_R3 (24); +sw_r25: SWREG_TO_R3 (25); +sw_r26: SWREG_TO_R3 (26); +sw_r27: SWREG_TO_R3 (27); +sw_r28: SWREG_TO_R3 (28); +sw_r29: SWREG_TO_R3 (29); +sw_r30: SWREG_TO_R3 (30); +sw_r31: SWREG_TO_R3 (31); + +/* Temporary data structures used in the handler */ +.section .data +.align 2 +ex_tmp_data_loc_0: + .byte 0 +ex_tmp_data_loc_1: + .byte 0 +ex_tmp_data_loc_2: + .byte 0 +ex_tmp_data_loc_3: + .byte 0 +ex_reg_op: + .byte 0 + +#endif /* ! NO_UNALIGNED_EXCEPTIONS */ + +#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) +/* + * FP exception decode jump table. + * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction + * - Hence exception handler is NOT self-modifying + * - Separate table for opA and opB + * - Each table is of size: (12 * 32) = 384 bytes + */ + +.section .text +.align 4 +fp_table_opa: +opa_r0: FP_EX_OPA_SAVE (0); +opa_r1: FP_EX_UNHANDLED; +opa_r2: FP_EX_OPA_SAVE (2); +opa_r3: FP_EX_OPA_SAVE_V (3); +opa_r4: FP_EX_OPA_SAVE_V (4); +opa_r5: FP_EX_OPA_SAVE_V (5); +opa_r6: FP_EX_OPA_SAVE_V (6); +opa_r7: FP_EX_OPA_SAVE (7); +opa_r8: FP_EX_OPA_SAVE (8); +opa_r9: FP_EX_OPA_SAVE (9); +opa_r10: FP_EX_OPA_SAVE (10); +opa_r11: FP_EX_OPA_SAVE (11); +opa_r12: FP_EX_OPA_SAVE (12); +opa_r13: FP_EX_OPA_SAVE (13); +opa_r14: FP_EX_UNHANDLED; +opa_r15: FP_EX_UNHANDLED; +opa_r16: FP_EX_UNHANDLED; +opa_r17: FP_EX_UNHANDLED; +opa_r18: FP_EX_OPA_SAVE (18); +opa_r19: FP_EX_OPA_SAVE (19); +opa_r20: FP_EX_OPA_SAVE (20); +opa_r21: FP_EX_OPA_SAVE (21); +opa_r22: FP_EX_OPA_SAVE (22); +opa_r23: FP_EX_OPA_SAVE (23); +opa_r24: FP_EX_OPA_SAVE (24); +opa_r25: FP_EX_OPA_SAVE (25); +opa_r26: FP_EX_OPA_SAVE (26); +opa_r27: FP_EX_OPA_SAVE (27); +opa_r28: FP_EX_OPA_SAVE (28); +opa_r29: FP_EX_OPA_SAVE (29); +opa_r30: FP_EX_OPA_SAVE (30); +opa_r31: FP_EX_OPA_SAVE (31); + +fp_table_opb: +opb_r0: FP_EX_OPB_SAVE (0); +opb_r1: FP_EX_UNHANDLED; +opb_r2: FP_EX_OPB_SAVE (2); +opb_r3: FP_EX_OPB_SAVE_V (3); +opb_r4: FP_EX_OPB_SAVE_V (4); +opb_r5: FP_EX_OPB_SAVE_V (5); +opb_r6: FP_EX_OPB_SAVE_V (6); +opb_r7: FP_EX_OPB_SAVE (7); +opb_r8: FP_EX_OPB_SAVE (8); +opb_r9: FP_EX_OPB_SAVE (9); +opb_r10: FP_EX_OPB_SAVE (10); +opb_r11: FP_EX_OPB_SAVE (11); +opb_r12: FP_EX_OPB_SAVE (12); +opb_r13: FP_EX_OPB_SAVE (13); +opb_r14: FP_EX_UNHANDLED; +opb_r15: FP_EX_UNHANDLED; +opb_r16: FP_EX_UNHANDLED; +opb_r17: FP_EX_UNHANDLED; +opb_r18: FP_EX_OPB_SAVE (18); +opb_r19: FP_EX_OPB_SAVE (19); +opb_r20: FP_EX_OPB_SAVE (20); +opb_r21: FP_EX_OPB_SAVE (21); +opb_r22: FP_EX_OPB_SAVE (22); +opb_r23: FP_EX_OPB_SAVE (23); +opb_r24: FP_EX_OPB_SAVE (24); +opb_r25: FP_EX_OPB_SAVE (25); +opb_r26: FP_EX_OPB_SAVE (26); +opb_r27: FP_EX_OPB_SAVE (27); +opb_r28: FP_EX_OPB_SAVE (28); +opb_r29: FP_EX_OPB_SAVE (29); +opb_r30: FP_EX_OPB_SAVE (30); +opb_r31: FP_EX_OPB_SAVE (31); + +#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ + +#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE) +/* This is where we store the opA and opB of the last excepting FP instruction */ +.section .data +.align 2 +.global mb_fpex_op_a +.global mb_fpex_op_b +mb_fpex_op_a: + .long 0 +mb_fpex_op_b: + .long 0 +#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */ + +#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) +/* This is where we store the register used to check which exception occurred */ + .section .data + .align 2 +mb_sp_save_r3: + .long 0 +#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */ + +/* The exception vector table */ +.section .data +.align 2 +.global MB_ExceptionVectorTable +MB_ExceptionVectorTable: + .long XNullHandler + .long 0 /* -- FSL Exception -- */ + .long XNullHandler + .long 1 /* -- Unaligned Access Exception -- */ + .long XNullHandler + .long 2 /* -- Illegal Opcode Exception -- */ + .long XNullHandler + .long 3 /* -- Instruction Bus Exception -- */ + .long XNullHandler + .long 4 /* -- Data Bus Exception -- */ + .long XNullHandler + .long 5 /* -- Div-by-0 Exception -- */ + .long XNullHandler + .long 6 /* -- FPU Exception -- */ + .long XNullHandler + .long 7 /* -- MMU Exceptions -- */ + +#else /* Dummy exception handler, in case exceptions are not present in the processor */ + +.global _hw_exception_handler +.section .text +.align 2 +.ent _hw_exception_handler +_hw_exception_handler: + bri 0; +.end _hw_exception_handler + +#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ diff --git a/lib/bsp/standalone/src/microblaze/mb_interface.h b/lib/bsp/standalone/src/microblaze/mb_interface.h new file mode 100644 index 00000000..ab9b0c0d --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/mb_interface.h @@ -0,0 +1,378 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _MICROBLAZE_INTERFACE_H_ +#define _MICROBLAZE_INTERFACE_H_ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" + +#ifdef __cplusplus +extern "C" { +#endif +extern void microblaze_enable_interrupts(void); /* Enable Interrupts */ +extern void microblaze_disable_interrupts(void); /* Disable Interrupts */ +extern void microblaze_enable_icache(void); /* Enable Instruction Cache */ +extern void microblaze_disable_icache(void); /* Disable Instruction Cache */ +extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */ +extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */ +extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */ +extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */ +extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */ +extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */ + +extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */ +extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */ +extern void microblaze_flush_dcache(void); /* Flush the whole dcache */ +extern void microblaze_invalidate_icache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the icache */ +extern void microblaze_invalidate_dcache_range(u32 cacheaddr, u32 len); /* Invalidate a part of the dcache */ +extern void microblaze_flush_dcache_range(u32 cacheaddr, u32 len); /* Flush a part of the dcache */ +extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */ +extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */ +extern void microblaze_flush_cache_ext(void); /* Flush cache ext */ +extern void microblaze_flush_cache_ext_range(u32 cacheaddr, + u32 len); /* Flush cache ext range */ +extern void microblaze_invalidate_cache_ext_range(u32 cacheaddr, + u32 len); /* Invalidate cache ext range */ + +/* Deprecated */ +extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated)); +extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated)); + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* FSL Access Macros */ + +/* Blocking Data Read and Write to FSL no. id */ +#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val)) +#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val)) + +/* Non-blocking Data Read and Write to FSL no. id */ +#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val)) +#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val)) + +/* Blocking Control Read and Write to FSL no. id */ +#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val)) +#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val)) + +/* Non-blocking Control Read and Write to FSL no. id */ +#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val)) +#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val)) + +/* Polling versions of FSL access macros. This makes the FSL access interruptible */ +#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \ + "addic\tr18,r0,0\n\t" \ + "bnei\tr18,1b\n" \ + : "=d" (val) :: "r18") + +#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \ + "addic\tr18,r0,0\n\t" \ + "bnei\tr18,1b\n" \ + :: "d" (val) : "r18") + +#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \ + "addic\tr18,r0,0\n\t" \ + "bnei\tr18,1b\n" \ + : "=d" (val) :: "r18") + +#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \ + "addic\tr18,r0,0\n\t" \ + "bnei\tr18,1b\n" \ + :: "d" (val) : "r18") +/* FSL valid and error check macros. */ +#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result)) +#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \ + "andi\t%0,%0,0x10" : "=d" (error)) + +/* Pseudo assembler instructions */ +#define clz(v) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \ + ); \ + _rval; \ + }) + +#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); }) +#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); }) + +#define mb_swapb(v) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \ + ); \ + _rval; \ + }) + +#define mb_swaph(v) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \ + ); \ + _rval; \ + }) + +#define mfgpr(rn) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfmsr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rmsr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfear() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rear\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfesr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,resr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mffsr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rfsr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfpvr(rn) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfbtr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rbtr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfedr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,redr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfpid() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rpid\n" : "=d"(_rval)\ + ); \ + _rval; \ + }) + +#define mfzpr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rzpr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mftlbx() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rtlbx\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mftlblo() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rtlblo\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mftlbhi() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rtlbhi\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfslr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rslr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mfshr() ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "mfs\t%0,rshr\n" : "=d"(_rval) \ + ); \ + _rval; \ + }) + +#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \ + "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \ + ); \ + }) + +#define mtmsr(v) ({ __asm__ __volatile__ ( \ + "mts\trmsr,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + + +#define mtfsr(v) ({ __asm__ __volatile__ ( \ + "mts\trfsr,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mtpid(v) ({ __asm__ __volatile__ ( \ + "mts\trpid,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mtzpr(v) ({ __asm__ __volatile__ ( \ + "mts\trzpr,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mttlbx(v) ({ __asm__ __volatile__ ( \ + "mts\trtlbx,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mttlblo(v) ({ __asm__ __volatile__ ( \ + "mts\trtlblo,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mttlbhi(v) ({ __asm__ __volatile__ ( \ + "mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mttlbsx(v) ({ __asm__ __volatile__ ( \ + "mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mtslr(v) ({ __asm__ __volatile__ ( \ + "mts\trslr,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define mtshr(v) ({ __asm__ __volatile__ ( \ + "mts\trshr,%0\n\tnop\n" :: "d" (v) \ + ); \ + }) + +#define lwx(address) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ + ); \ + _rval; \ + }) + +#define lwr(address) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ + ); \ + _rval; \ + }) + +#define lhur(address) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ + ); \ + _rval; \ + }) + +#define lbur(address) ({ u32 _rval; \ + __asm__ __volatile__ ( \ + "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \ + ); \ + _rval; \ + }) + +#define swx(address, data) ({ __asm__ __volatile__ ( \ + "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \ + ); \ + }) + +#define swr(address, data) ({ __asm__ __volatile__ ( \ + "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \ + ); \ + }) + +#define shr(address, data) ({ __asm__ __volatile__ ( \ + "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \ + ); \ + }) + +#define sbr(address, data) ({ __asm__ __volatile__ ( \ + "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \ + ); \ + }) + +#define microblaze_getfpex_operand_a() ({ \ + extern u32 mb_fpex_op_a; \ + mb_fpex_op_a; \ + }) + +#define microblaze_getfpex_operand_b() ({ \ + extern u32 mb_fpex_op_b; \ + mb_fpex_op_b; \ + }) + +/* Deprecated MicroBlaze FSL macros */ +#define microblaze_bread_datafsl(val, id) getfsl(val,id) +#define microblaze_bwrite_datafsl(val, id) putfsl(val,id) +#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id) +#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id) +#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id) +#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id) +#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id) +#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id) + +#ifdef __cplusplus +} +#endif +#endif // _MICROBLAZE_INTERFACE_H_ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S new file mode 100644 index 00000000..af9d41bd --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_dcache.S @@ -0,0 +1,84 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* File : microblaze_disable_dcache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable the L1 dcache on the microblaze. +* +*******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_disable_dcache + .ent microblaze_disable_dcache + .align 2 +microblaze_disable_dcache: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + addik r1, r1, -4 + swi r15, r1, 0 + brlid r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/ + nop + lwi r15, r1, 0 + addi r1, r1, 4 +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + rtsd r15, 8 + msrclr r0, 0x80 + +#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */ + + addik r1, r1, -4 + +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + swi r15, r1, 0 + brlid r15, microblaze_flush_dcache + nop +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + mfs r11, rmsr + andi r11, r11, ~(0x80) + mts rmsr, r11 + +#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 + lwi r15, r1, 0 +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */ + + rtsd r15, 8 + addi r1, r1, 4 + +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_disable_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S new file mode 100644 index 00000000..60efc72b --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_exceptions.S @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* Disable exceptions on microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_disable_exceptions + .ent microblaze_disable_exceptions + .align 2 +microblaze_disable_exceptions: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrclr r0, 0x100 +#else + mfs r4, rmsr; + andi r4, r4, ~(0x100); /* Turn OFF the EE bit */ + mts rmsr, r4; + rtsd r15, 8; + nop; +#endif +.end microblaze_disable_exceptions diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S new file mode 100644 index 00000000..da946fc7 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_icache.S @@ -0,0 +1,66 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_disable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable L1 icache on the microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_disable_icache + .ent microblaze_disable_icache + .align 2 +microblaze_disable_icache: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrclr r0, 0x20 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + #Read the MSR register + mfs r8, rmsr + #Clear the icache enable bit + andi r8, r8, ~(0x20) + #Save the MSR register + mts rmsr, r8 + #Return + rtsd r15, 8 + nop +#endif + .end microblaze_disable_icache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S b/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S new file mode 100644 index 00000000..08f6ecaf --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_disable_interrupts.S @@ -0,0 +1,66 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_disable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Disable interrupts on the microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_disable_interrupts + .ent microblaze_disable_interrupts + .align 2 +microblaze_disable_interrupts: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrclr r0, 0x2 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + #Read the MSR register + mfs r12, rmsr + #Clear the interrupt enable bit + andi r12, r12, ~(0x2) + #Save the MSR register + mts rmsr, r12 + #Return + rtsd r15, 8 + nop +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_disable_interrupts diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S new file mode 100644 index 00000000..cf0991e6 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_dcache.S @@ -0,0 +1,67 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_dcache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable L1 dcache on the microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_enable_dcache + .ent microblaze_enable_dcache + .align 2 +microblaze_enable_dcache: + +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrset r0, 0x80 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + #Read the MSR register + mfs r8, rmsr + #Set the interrupt enable bit + ori r8, r8, 0x80 + #Save the MSR register + mts rmsr, r8 + #Return + rtsd r15, 8 + nop +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_enable_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S new file mode 100644 index 00000000..8e1ea080 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_exceptions.S @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* Enable exceptions on microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_enable_exceptions + .ent microblaze_enable_exceptions + .align 2 +microblaze_enable_exceptions: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8; + msrset r0, 0x100 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + mfs r4, rmsr; + ori r4, r4, 0x100; /* Turn ON the EE bit */ + mts rmsr, r4; + rtsd r15, 8; + nop; +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ +.end microblaze_enable_exceptions diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S new file mode 100644 index 00000000..a398f1fd --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_icache.S @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_icache.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable icache on the microblaze. +* +* +******************************************************************************/ +#include "xparameters.h" + + .text + .globl microblaze_enable_icache + .ent microblaze_enable_icache + .align 2 +microblaze_enable_icache: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrset r0, 0x20 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + #Read the MSR register + mfs r8, rmsr + #Set the interrupt enable bit + ori r8, r8, 0x20 + #Save the MSR register + mts rmsr, r8 + #Return + rtsd r15, 8 + nop +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_enable_icache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S b/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S new file mode 100644 index 00000000..11c8c667 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_enable_interrupts.S @@ -0,0 +1,66 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_enable_interrupts.s +* Date : 2002, March 20. +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Enable interrupts on the microblaze. +* +* +******************************************************************************/ + +#include "xparameters.h" + + .text + .globl microblaze_enable_interrupts + .ent microblaze_enable_interrupts + .align 2 +microblaze_enable_interrupts: +#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1 + rtsd r15, 8 + msrset r0, 0x2 +#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + #Read the MSR register + mfs r12, rmsr + #Set the interrupt enable bit + ori r12, r12, 0x2 + #Save the MSR register + mts rmsr, r12 + #Return + rtsd r15, 8 + nop +#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/ + .end microblaze_enable_interrupts diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c b/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c new file mode 100644 index 00000000..a504f272 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_exception_handler.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file microblaze_exception_handler.c +* +* This file contains exception handler registration routines for +* the MicroBlaze processor. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 06/24/04 First release
+* 
+* +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "microblaze_exceptions_i.h" +#include "microblaze_exceptions_g.h" + +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */ +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[]; +/****************************************************************************/ + +/*****************************************************************************/ +/** +* +* Registers an exception handler for the MicroBlaze. The +* argument provided in this call as the DataPtr is used as the argument +* for the handler when it is called. +* +* @param ExceptionId is the id of the exception to register this handler +* for. +* @param Top level handler. +* @param DataPtr is a reference to data that will be passed to the handler +* when it gets called. +* @return None. +* +* @note +* +* None. +* +****************************************************************************/ +void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr) +{ + MB_ExceptionVectorTable[ExceptionId].Handler = Handler; + MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr; +} + +#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h new file mode 100644 index 00000000..c155a98a --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_g.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_exceptions_g.h +* +* This file contains the exception handling information for the MicroBlaze +* processor. This file is usually generated by LibGen. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00a 06/24/04 First release
+* 
+* +******************************************************************************/ +#ifndef MICROBLAZE_EXCEPTIONS_G_H /* prevent circular inclusions */ +#define MICROBLAZE_EXCEPTIONS_G_H /* by using protection macros */ + +#define MICROBLAZE_EXCEPTIONS_ENABLED 1 + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h new file mode 100644 index 00000000..b7e0d963 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_exceptions_i.h @@ -0,0 +1,87 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_exceptions_i.h +* +* This header file contains defines for structures used by the microblaze +* hardware exception handler. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00a 06/24/04 First release
+* 
+* +******************************************************************************/ + +#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */ +#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + Xil_ExceptionHandler Handler; + void *CallBackRef; +} MB_ExceptionVectorTableEntry; + +/* Exception IDs */ +#define XEXC_ID_FSL 0U +#define XEXC_ID_UNALIGNED_ACCESS 1U +#define XEXC_ID_ILLEGAL_OPCODE 2U +#define XEXC_ID_M_AXI_I_EXCEPTION 3U +#define XEXC_ID_IPLB_EXCEPTION 3U +#define XEXC_ID_M_AXI_D_EXCEPTION 4U +#define XEXC_ID_DPLB_EXCEPTION 4U +#define XEXC_ID_DIV_BY_ZERO 5U +#define XEXC_ID_FPU 6U +#define XEXC_ID_STACK_VIOLATION 7U +#define XEXC_ID_MMU 7U + +void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S new file mode 100644 index 00000000..a2257688 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext.S @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_flush_cache_ext() +* +* Flush the entire L2 Cache +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16 + + .text + .globl microblaze_flush_cache_ext + .ent microblaze_flush_cache_ext + .align 2 + +microblaze_flush_cache_ext: + +#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) + + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + +Loop_start: + wdc.ext.flush r5, r6 + bgtid r6,Loop_start + addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) +#endif + rtsd r15, 8 + nop + .end microblaze_flush_cache_ext diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S new file mode 100644 index 00000000..9251db20 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_cache_ext_range.S @@ -0,0 +1,74 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len) +* +*Flush a L2 Cache range +* +*Parameters: +* 'cacheaddr' - address in the L2 cache where the flush begins +* 'len ' - length (in bytes) worth of L2 cache to be flushed +* +*******************************************************************************/ + +#include "xparameters.h" + +#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16 + + .text + .globl microblaze_flush_cache_ext_range + .ent microblaze_flush_cache_ext_range + .align 2 + +microblaze_flush_cache_ext_range: +#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) + beqi r6, Loop_done + + addik r6, r6, -1 + add r6, r5, r6 + + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + + rsubk r6, r5, r6 +Loop_start: + wdc.ext.flush r5, r6 + bneid r6, Loop_start + addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + +Loop_done: +#endif + rtsd r15, 8 + nop + + .end microblaze_flush_cache_ext_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S new file mode 100644 index 00000000..1f18cce7 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache.S @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_flush_dcache() +* +* Flush the L1 DCache +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + + .text + .globl microblaze_flush_dcache + .ent microblaze_flush_dcache + .align 2 + +microblaze_flush_dcache: + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + +L_start: + wdc.flush r5, r0 /* Flush the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ + nop + .end microblaze_flush_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S new file mode 100644 index 00000000..0bb81cd3 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_flush_dcache_range.S @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_flush_dcache_range (unsigned int cacheaddr, unsigned int len) +* +* Flush a L1 DCache range +* +* Parameters: +* 'cacheaddr' - address in the Dcache where the flush begins +* 'len ' - length (in bytes) worth of Dcache to be flushed +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#define MB_HAS_WRITEBACK_SET 0 +#else +#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#endif + + .text + .globl microblaze_flush_dcache_range + .ent microblaze_flush_dcache_range + .align 2 + +microblaze_flush_dcache_range: + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + + beqi r6, L_done /* Skip loop if size is zero */ + + add r6, r5, r6 /* Compute end address */ + addik r6, r6, -1 + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ + +#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ + +L_start: + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + + wdc r5, r0 /* Invalidate the cache line */ + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ +#else + rsubk r6, r5, r6 + /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ +L_start: + wdc.flush r5, r6 /* Flush the cache line */ + bneid r6, L_start + addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) + +#endif + +L_done: + rtsd r15, 8 +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + .end microblaze_flush_dcache_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S new file mode 100644 index 00000000..925a387f --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_init_dcache_range.S @@ -0,0 +1,82 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len) +* +* Invalidate dcache on the microblaze +* +* Parameters: +* 'cache_start' - address in the Dcache where invalidation begins +* 'cache_len' - length (in bytes) worth of Dcache to be invalidated +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + + .text + .globl microblaze_init_dcache_range + .ent microblaze_init_dcache_range + .align 2 + +microblaze_init_dcache_range: + + mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */ + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 + + andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ + + add r6, r5, r6 /* Compute end */ + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */ + +L_start: + wdc r5, r0 /* Invalidate the Cache (delay slot) */ + + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ + mts rmsr, r9 + .end microblaze_init_dcache_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S new file mode 100644 index 00000000..15563f87 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_init_icache_range.S @@ -0,0 +1,83 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len) +* +* Invalidate icache on the microblaze +* +* Parameters: +* 'cache_start' - address in the Icache where invalidation begins +* 'cache_len' - length (in bytes) worth of Icache to be invalidated +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN +#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 +#endif + + .text + .globl microblaze_init_icache_range + .ent microblaze_init_icache_range + .align 2 + +microblaze_init_icache_range: + + mfs r9, rmsr /* Disable Icache and interrupts before invalidating */ + andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 + + andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ + + add r6, r5, r6 /* Compute end */ + andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */ + +L_start: + wic r5, r0 /* Invalidate the Cache (delay slot) */ + + cmpu r18, r5, r6 /* Are we at the end ? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ + mts rmsr, r9 + .end microblaze_init_icache_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c b/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c new file mode 100644 index 00000000..a8a8e7b8 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupt_handler.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_interrupt_handler.c +* +* This file contains the standard interrupt handler for the MicroBlaze processor. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* 
+* +******************************************************************************/ + + +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "microblaze_interrupts_i.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void __interrupt_handler (void) __attribute__ ((interrupt_handler)); +void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); + +/************************** Variable Definitions *****************************/ + +extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; +/*****************************************************************************/ +/** +* +* This function is the standard interrupt handler used by the MicroBlaze processor. +* It saves all volatile registers, calls the users top level interrupt handler. +* When this returns, it restores all registers, and returns using a rtid instruction. +* +* @param +* +* None +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void __interrupt_handler(void) +{ + /* The compiler saves all volatiles and the MSR */ + (void)MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef); + /* The compiler restores all volatiles and MSR, and returns from interrupt */ +} + +/****************************************************************************/ +/*****************************************************************************/ +/** +* +* Registers a top-level interrupt handler for the MicroBlaze. The +* argument provided in this call as the DataPtr is used as the argument +* for the handler when it is called. +* +* @param Top level handler. +* @param DataPtr is a reference to data that will be passed to the handler +* when it gets called. + +* @return None. +* +* @note +* +* None. +* +****************************************************************************/ +void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr) +{ + MB_InterruptVectorTable.Handler = Handler; + MB_InterruptVectorTable.CallBackRef = DataPtr; +} diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c new file mode 100644 index 00000000..5bd9dbd1 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_g.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_interrupts_g.c +* +* This file contains the interrupt handler table for the MicroBlaze processor. +* This file is usually generated by LibGen. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* 
+* +******************************************************************************/ + +#include "microblaze_interrupts_i.h" +#include "xparameters.h" + + +/* extern void XNullHandler (void *NullParameter) */ + +/* +* The interrupt handler table for microblaze processor +*/ + +MB_InterruptVectorTableEntry MB_InterruptVectorTable[] = +{ + {XNullHandler, + (void)XNULL} +}; diff --git a/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h new file mode 100644 index 00000000..d0fecdbc --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_interrupts_i.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_interrupts_i.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* High-level driver functions are defined in xintc.h. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* 
+* +******************************************************************************/ + +#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */ +#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + XInterruptHandler Handler; + void *CallBackRef; +} MB_InterruptVectorTableEntry; + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S new file mode 100644 index 00000000..d806519a --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext.S @@ -0,0 +1,66 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_invalidate_cache_ext() +* +*Invalidate the entire L2 Cache +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16 + + .text + .globl microblaze_invalidate_cache_ext + .ent microblaze_invalidate_cache_ext + .align 2 + +microblaze_invalidate_cache_ext: + +#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)) + + addik r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + +Loop_start: + wdc.ext.clear r5, r6 + bgtid r6,Loop_start + addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) +#endif + rtsd r15, 8 + nop + + .end microblaze_invalidate_cache_ext diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S new file mode 100644 index 00000000..13ce65e1 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len) +* +*Invalidate an L2 cache range +* +*Parameters: +* 'cacheaddr' - address in the L2 cache where invalidation begins +* 'len ' - length (in bytes) worth of Dcache to be invalidated +* +*******************************************************************************/ + +#include "xparameters.h" + +#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16 + + .text + .globl microblaze_invalidate_cache_ext_range + .ent microblaze_invalidate_cache_ext_range + .align 2 + +microblaze_invalidate_cache_ext_range: +#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) + beqi r6, Loop_done + + add r6, r5, r6 + addik r6, r6, -1 + + andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + + rsubk r6, r5, r6 + +Loop_start: + wdc.ext.clear r5, r6 + bneid r6, Loop_start + addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) + +Loop_done: +#endif + rtsd r15, 8 + nop + + .end microblaze_invalidate_cache_ext_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S new file mode 100644 index 00000000..6a51217f --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache.S @@ -0,0 +1,86 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_invalidate_dcache() +* +* Invalidate the entire L1 DCache +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#endif + + .text + .globl microblaze_invalidate_dcache + .ent microblaze_invalidate_dcache + .align 2 + +microblaze_invalidate_dcache: + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + addik r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) + addik r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */ + +L_start: + wdc r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + + .end microblaze_invalidate_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S new file mode 100644 index 00000000..7c455c65 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_dcache_range.S @@ -0,0 +1,112 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len) +* +* Invalidate a Dcache range +* +* Parameters: +* 'cacheaddr' - address in the Dcache where invalidation begins +* 'len ' - length (in bytes) worth of Dcache to be invalidated +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#define MB_HAS_WRITEBACK_SET 0 +#else +#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#endif + + .text + .globl microblaze_invalidate_dcache_range + .ent microblaze_invalidate_dcache_range + .align 2 + +microblaze_invalidate_dcache_range: + + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + + beqi r6, L_done /* Skip loop if size is zero */ + + add r6, r5, r6 /* Compute end address */ + addik r6, r6, -1 + + andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */ + andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */ + +#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ + +L_start: + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + + wdc r5, r0 + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ +#else + + rsubk r6, r5, r6 + /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */ +L_start: + wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */ + bneid r6, L_start + addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) + +#endif + +L_done: + rtsd r15, 8 +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + .end microblaze_invalidate_dcache_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S new file mode 100644 index 00000000..d244e667 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache.S @@ -0,0 +1,86 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_invalidate_icache() +* +* Invalidate the entire ICache +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN +#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#endif + + .text + .globl microblaze_invalidate_icache + .ent microblaze_invalidate_icache + .align 2 + +microblaze_invalidate_icache: + +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + addik r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */ +L_start: + wic r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ + +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + .end microblaze_invalidate_icache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S new file mode 100644 index 00000000..5a82d261 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_invalidate_icache_range.S @@ -0,0 +1,96 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len) +* +* Invalidate an ICache range +* +* Parameters: +* 'cacheaddr' - address in the Icache where invalidation begins +* 'len' - length (in bytes) worth of Icache to be invalidated +* +* +*******************************************************************************/ + +#include "xparameters.h" + +#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN +#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#endif + + .text + .globl microblaze_invalidate_icache_range + .ent microblaze_invalidate_icache_range + .align 2 + +microblaze_invalidate_icache_range: + +#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + + beqi r6, L_done /* Skip loop if size is zero */ + + add r6, r5, r6 /* Compute end address */ + addik r6, r6, -1 + + andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */ + andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */ + +L_start: + cmpu r18, r5, r6 /* Are we at the end? */ + blti r18, L_done + + wic r5, r0 /* Invalidate the cache line */ + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the addrees by 4 (delay slot) */ + +L_done: + rtsd r15, 8 /* Return */ +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + .end microblaze_invalidate_icache_range diff --git a/lib/bsp/standalone/src/microblaze/microblaze_scrub.S b/lib/bsp/standalone/src/microblaze/microblaze_scrub.S new file mode 100644 index 00000000..6c1512ab --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_scrub.S @@ -0,0 +1,211 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* microblaze_scrub () +* +* Scrub LMB memory and all internal BRAMs (data cache, instruction cache, +* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility +* of an uncorrectable error when fault tolerance support is enabled. +* +* This routine assumes that the processor is in privileged mode when it is +* called, if the MMU is enabled. +* +* Call this routine regularly from a timer interrupt. +* +* Parameters: +* None +* +* +*******************************************************************************/ + +#include "xparameters.h" + +/* Define if fault tolerance is used */ +#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT + #if XPAR_MICROBLAZE_FAULT_TOLERANT > 0 + #define FAULT_TOLERANT + #endif +#endif + +/* Define if LMB is used and can be scrubbed */ +#if defined(XPAR_MICROBLAZE_D_LMB) && \ + defined(XPAR_DLMB_CNTLR_BASEADDR) && \ + defined(XPAR_DLMB_CNTLR_HIGHADDR) + #if XPAR_MICROBLAZE_D_LMB == 1 + #define HAS_SCRUBBABLE_LMB + #define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR) + #endif +#endif + +/* Set default cache line lengths */ +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN + #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4 +#endif + +#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN + #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4 +#endif + +/* Define if internal Data Cache BRAMs are used */ +#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE) + #if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024 + #define HAS_BRAM_DCACHE + #define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) + #define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1) + #endif +#endif + +/* Define if internal Instruction Cache BRAMs are used */ +#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE) + #if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024 + #define HAS_BRAM_ICACHE + #define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) + #define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1) + #endif +#endif + +/* Define if internal MMU UTLB BRAM is used */ +#ifdef XPAR_MICROBLAZE_USE_MMU + #if XPAR_MICROBLAZE_USE_MMU > 1 + #define HAS_BRAM_MMU_UTLB + #endif +#endif + +/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */ +#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \ + defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE) + #if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1 + #if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \ + XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4 + #define HAS_BRAM_BRANCH_TARGET_CACHE + #ifdef HAS_BRAM_DCACHE + #define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1) + #else + #define BTC_MASK_D 256 + #endif + #ifdef HAS_BRAM_ICACHE + #define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1) + #else + #define BTC_MASK_I 256 + #endif + #if BTC_MASK_D > BTC_MASK_I + #define BTC_MASK BTC_MASK_D + #else + #define BTC_MASK BTC_MASK_I + #endif + #endif + #endif +#endif + +/* Define index offsets to persistent data used by this routine */ +#define DLMB_INDEX_OFFSET 0 +#define DCACHE_INDEX_OFFSET 4 +#define ICACHE_INDEX_OFFSET 8 +#define MMU_INDEX_OFFSET 12 +#define BTC_CALL_COUNT_OFFSET 16 + + .text + .globl microblaze_scrub + .ent microblaze_scrub + .align 2 + +microblaze_scrub: +#ifdef FAULT_TOLERANT + la r6, r0, L_persistent_data /* Get pointer to data */ + +#ifdef HAS_SCRUBBABLE_LMB +L_dlmb: + lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */ + lw r7, r5, r0 /* Load and store */ + sw r7, r5, r0 + addik r5, r5, 4 /* Increment and save dlmb index */ + andi r5, r5, DLMB_MASK + swi r5, r6, DLMB_INDEX_OFFSET +#endif /* HAS_SCRUBBABLE_LMB */ + +#ifdef HAS_BRAM_DCACHE +L_dcache: + lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */ + wdc r5, r0 /* Invalidate data cache line */ + addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */ + andi r5, r5, DCACHE_MASK + swi r5, r6, DCACHE_INDEX_OFFSET +#endif /* HAS_BRAM_DCACHE */ + +#ifdef HAS_BRAM_ICACHE +L_icache: + lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */ + wic r5, r0 /* Invalidate data cache line */ + addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */ + andi r5, r5, ICACHE_MASK + swi r5, r6, ICACHE_INDEX_OFFSET +#endif /* HAS_BRAM_ICACHE */ + +#ifdef HAS_BRAM_MMU_UTLB +L_mmu: + lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */ + mts rtlbx, r5 /* Access next entry in UTLB */ + mts rtlbhi, r0 /* Clear the UTLB entry */ + + addik r5, r5, 1 /* Increment and save entry index */ + andi r5, r5, 0x3F + swi r5, r6, MMU_INDEX_OFFSET +#endif /* HAS_BRAM_MMU_UTLB */ + +#ifdef HAS_BRAM_BRANCH_TARGET_CACHE +L_btc: + lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */ + addik r5, r5, 1 /* Increment and save call count */ + andi r5, r5, BTC_MASK + swi r5, r6, BTC_CALL_COUNT_OFFSET + + bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */ + bri 4 /* Clear branch target cache */ +L_skip_btc_scrub: +#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */ + +#endif /* FAULT_TOLERANT */ +L_done: + rtsd r15, 8 /* Return */ + nop + .end microblaze_scrub + + /* Persistent data used by this routine */ + .data + .align 2 +L_persistent_data: + .long 0 /* dlmb index */ + .long 0 /* dcache index */ + .long 0 /* icache index */ + .long 0 /* mmu entry index */ + .long 0 /* btc call count */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_sleep.c b/lib/bsp/standalone/src/microblaze/microblaze_sleep.c new file mode 100644 index 00000000..0e34cc62 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_sleep.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_sleep.c +* +* Contains implementation of microblaze sleep function. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.1   hk   04/18/14 Add sleep function.
+*
+* 
+* +* @note +* +* This file may contain architecture-dependent code. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "microblaze_sleep.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + + +/*****************************************************************************/ +/** +* +* Provides delay for requested duration. +* +* @param Delay time in milliseconds. +* +* @return None. +* +* @note Instruction cache should be enabled for this to work. +* +******************************************************************************/ +void MB_Sleep(u32 MilliSeconds) +{ + if (((mfmsr() & 0x20U) == 0U)) { + /* + * Instruction cache not enabled. + * Delay will be much higher than expected. + */ + } + + asm volatile ("\n" + "1: \n\t" + "addik r7, r0, %0 \n\t" + "2: \n\t" + "addik r7, r7, -1 \n\t" + "bneid r7, 2b \n\t" + "or r0, r0, r0 \n\t" + "bneid %1, 1b \n\t" + "addik %1, %1, -1 \n\t" + :: "i"(ITERS_PER_MSEC), "d" (MilliSeconds)); + +} diff --git a/lib/bsp/standalone/src/microblaze/microblaze_sleep.h b/lib/bsp/standalone/src/microblaze/microblaze_sleep.h new file mode 100644 index 00000000..ab4e8f44 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_sleep.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file microblaze_sleep.h +* +* Contains microblaze sleep function API. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.1   asa  04/18/14 Add sleep function - first release.
+*
+* 
+* +* @note +* +* This file may contain architecture-dependent items. +* +******************************************************************************/ + +#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */ +#define MICROBLAZE_SLEEP_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "mb_interface.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define ITERS_PER_MSEC ((XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000) / 6) + +/************************** Function Prototypes ******************************/ + +void MB_Sleep(u32 MilliSeconds); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S b/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S new file mode 100644 index 00000000..0d497e74 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_update_dcache.S @@ -0,0 +1,106 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* +* File : microblaze_update_dcache.s +* Date : 2003, September 24 +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Update dcache on the microblaze. +* Takes in three parameters +* r5 : Cache Tag Line +* r6 : Cache Data +* r7 : Lock/Valid information +* Bit 30 is Lock [ 1 indicates locked ] +* Bit 31 is Valid [ 1 indicates valid ] +* +* -------------------------------------------------------------- +* | Lock | Valid | Effect +* -------------------------------------------------------------- +* | 0 | 0 | Invalidate Cache +* | 0 | 1 | Valid, but unlocked cacheline +* | 1 | 0 | Invalidate Cache, No effect of lock +* | 1 | 1 | Valid cache. Locked to a +* | | | particular addrees +* -------------------------------------------------------------- +* +* +**********************************************************************************/ +#include "xparameters.h" + +#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN +#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1 +#endif + + .text + .globl microblaze_update_dcache + .ent microblaze_update_dcache + .align 2 +microblaze_update_dcache: + +#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 + +/* Read the MSR register into a temp register */ + mfs r18, rmsr + +/* Clear the dcache enable bit to disable the cache + Register r10,r18 are volatile registers and hence do not need to be saved before use */ + andi r10, r18, ~128 + mts rmsr, r10 + +/* Update the lock and valid info */ + andi r5, r5, 0xfffffffc + or r5, r5, r7 + +/* Update dcache */ + wdc r5, r6 + +/* Return */ + rtsd r15, 8 + mts rmsr, r18 + +#else + + /* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line + So call microblaze_init_dcache_range appropriately to do the job */ + + brid microblaze_init_dcache_range + addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) + + /* We don't have a return instruction here. This is tail call optimization :) */ + +#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */ + + .end microblaze_update_dcache diff --git a/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S b/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S new file mode 100644 index 00000000..789f6bb8 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/microblaze_update_icache.S @@ -0,0 +1,105 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************** +* +* File : microblaze_update_icache.s +* Date : 2003, September 24 +* Company: Xilinx +* Group : Emerging Software Technologies +* +* Summary: +* Update icache on the microblaze. +* Takes in three parameters +* r5 : Cache Tag Line +* r6 : Cache Data +* r7 : Lock/Valid information +* Bit 30 is Lock [ 1 indicates locked ] +* Bit 31 is Valid [ 1 indicates valid ] +* +* -------------------------------------------------------------- +* | Lock | Valid | Effect +* -------------------------------------------------------------- +* | 0 | 0 | Invalidate Cache +* | 0 | 1 | Valid, but unlocked cacheline +* | 1 | 0 | Invalidate Cache, No effect of lock +* | 1 | 1 | Valid cache. Locked to a +* | | | particular addrees +* -------------------------------------------------------------- +* +* +**********************************************************************************/ +#include "xparameters.h" + +#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN +#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1 +#endif + + .text + .globl microblaze_update_icache + .ent microblaze_update_icache + .align 2 +microblaze_update_icache: + +#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 + +/* Read the MSR register into a temp register */ + mfs r18, rmsr + +/* Clear the icache enable bit to disable the cache + Register r10,r18 are volatile registers and hence do not need to be saved before use */ + andi r10, r18, ~32 + mts rmsr, r10 + +/* Update the lock and valid info */ + andi r5, r5, 0xfffffffc + or r5, r5, r7 + +/* Update icache */ + wic r5, r6 + +/* Return */ + rtsd r15, 8 + mts rmsr, r18 + +#else + + /* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line + So call microblaze_init_icache_range appropriately to do the job */ + + brid microblaze_init_icache_range + addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) + + /* We don't have a return instruction here. This is tail call optimization :) */ + +#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */ + + .end microblaze_update_icache diff --git a/lib/bsp/standalone/src/microblaze/pvr.c b/lib/bsp/standalone/src/microblaze/pvr.c new file mode 100644 index 00000000..ca09703a --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/pvr.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pvr.c +* +* This header file contains defines for structures used by the microblaze +* PVR routines +* +******************************************************************************/ +#include "xparameters.h" +#include "pvr.h" +#include + +/* Definitions */ +int microblaze_get_pvr (pvr_t *pvr) +{ + if (!pvr) + return -1; + + bzero ((void*)pvr, sizeof (pvr_t)); + +#ifdef MICROBLAZE_PVR_NONE + return -1; +#else + getpvr (0, pvr->pvr[0]); +#endif /* MICROBLAZE_PVR_NONE */ + +#ifdef MICROBLAZE_PVR_FULL + getpvr (1, pvr->pvr[1]); + getpvr (2, pvr->pvr[2]); + getpvr (3, pvr->pvr[3]); + + getpvr (4, pvr->pvr[4]); + getpvr (5, pvr->pvr[5]); + getpvr (6, pvr->pvr[6]); + getpvr (7, pvr->pvr[7]); + + getpvr (8, pvr->pvr[8]); + getpvr (9, pvr->pvr[9]); + getpvr (10, pvr->pvr[10]); + getpvr (11, pvr->pvr[11]); + +/* getpvr (12, pvr->pvr[12]); */ +/* getpvr (13, pvr->pvr[13]); */ +/* getpvr (14, pvr->pvr[14]); */ +/* getpvr (15, pvr->pvr[15]); */ + +#endif /* MICROBLAZE_PVR_FULL */ + + return 0; +} diff --git a/lib/bsp/standalone/src/microblaze/pvr.h b/lib/bsp/standalone/src/microblaze/pvr.h new file mode 100644 index 00000000..5e8dc897 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/pvr.h @@ -0,0 +1,276 @@ +/****************************************************************************** +* +* Copyright (C) 2006 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pvr.h +* +* This header file contains defines for structures used by the microblaze +* PVR routines +* +******************************************************************************/ + +#ifndef _PVR_H +#define _PVR_H + +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "mb_interface.h" +#include "bspconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Defs */ +typedef struct pvr_s { +#ifdef MICROBLAZE_PVR_FULL + unsigned int pvr[16]; +#else + unsigned int pvr[1]; +#endif +} pvr_t; + + +#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val)) + +/* Basic PVR mask */ +#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000 +#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000 +#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000 +#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000 +#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000 +#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000 +#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000 +#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000 +#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000 +#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000 +#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000 +#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000 +#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000 +#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00 +#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF + +/* User 2 PVR mask */ +#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF + +/* Configuration PVR masks */ +#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000 +#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000 +#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000 +#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000 +#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000 +#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000 +#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 +#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 +#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000 +#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000 +#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000 +#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000 +#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000 +#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000 +#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000 +#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000 +#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000 +#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800 +#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200 +#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400 +#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040 +#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020 +#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010 +#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008 +#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004 +#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100 +#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080 +#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002 +#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001 +#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000 + +/* Debug and exception PVR masks */ +#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000 +#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 +#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 +#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 +#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380 +#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007 + +/* ICache config PVR masks */ +#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000 +#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 +#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 +#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 +#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 +#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000 +#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000 +#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00 +#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300 +#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080 +#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040 + +/* DCache config PVR masks */ +#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000 +#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 +#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 +#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 +#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 +#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000 +#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000 +#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000 +#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00 +#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080 +#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040 + +/* ICache base address PVR mask */ +#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF + +/* ICache high address PVR mask */ +#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF + +/* DCache base address PVR mask */ +#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF + +/* DCache high address PVR mask */ +#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF + +/* Target family PVR mask */ +#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000 + +/* MSR Reset value PVR mask */ +#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF + +/* MMU value PVR mask */ +#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000 +#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000 +#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000 +#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000 +#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000 +#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000 + +/* PVR access macros */ +#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK) +#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK) +#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK) +#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK) +#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK) +#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK) +#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK) +#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK) +#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK) +#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK) +#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK) +#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK) +#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8) +#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK) + +#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK) + +#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK) +#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK) +#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK) +#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK) +#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK) +#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK) +#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK) +#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK) +#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK) +#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK) +#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK) +#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK) +#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK) +#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK) +#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK) +#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK) +#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK) +#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK) +#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK) +#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK) +#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK) +#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK) +#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK) +#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK) +#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK) + +#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK) +#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) +#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) +#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) +#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7) +#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK) + +#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) +#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK) +#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21)) +#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) +#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK) +#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK) +#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10) +#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8) +#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK) +#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK) + +#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) +#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK) +#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21)) +#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) +#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK) +#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK) +#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK) +#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10) +#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK) +#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK) + +#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK) +#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK) + +#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK) +#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK) + +#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24) + +#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK) + +#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30) +#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27) +#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24) +#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22) +#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17) +#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16) + +/* Protos */ +int microblaze_get_pvr (pvr_t *pvr); + +#ifdef __cplusplus +} +#endif +#endif /* _PVR_H */ diff --git a/lib/bsp/standalone/src/microblaze/xil_cache.c b/lib/bsp/standalone/src/microblaze/xil_cache.c new file mode 100644 index 00000000..8024b7fd --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_cache.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* This contains implementation of cache related driver functions. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+* 3.10  asa  05/04/13 This version of MicroBlaze BSP adds support for system
+*					  cache/L2 cache. Existing APIs in this file are modified
+*					  to add support for L2 cache.
+*					  These changes are done for implementing PR #697214.
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_cache.h" + + +/****************************************************************************/ +/** +* +* Disable the data cache. +* +* @param None +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ + Xil_DCacheFlush(); + Xil_DCacheInvalidate(); + Xil_L1DCacheDisable(); +} + +/****************************************************************************/ +/** +* +* Disable the instruction cache. +* +* @param None +* +* @return None. +* +* @note +* +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ + Xil_ICacheInvalidate(); + Xil_L1ICacheDisable(); +} diff --git a/lib/bsp/standalone/src/microblaze/xil_cache.h b/lib/bsp/standalone/src/microblaze/xil_cache.h new file mode 100644 index 00000000..aa4f7965 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_cache.h @@ -0,0 +1,447 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* This header file contains cache related driver functions (or macros) +* that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The functions in this header file can be used across all Xilinx supported +* processors. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+* 3.02a sdm  10/24/11 Updated the file to include xparameters.h so that
+*                     the correct cache flush routines are used based on
+*                     whether the write-back or write-through caches are
+*                     used (cr #630532).
+* 3.10a asa  05/04/13 This version of MicroBlaze BSP adds support for system
+*					  cache/L2 cache. The existing/old APIs/macros in this
+*					  file are renamed to imply that they deal with L1 cache.
+*					  New macros/APIs are added to address similar features for
+*					  L2 cache. Users can include this file in their application
+*					  to use the various cache related APIs. These changes are
+*					  done for implementing PR #697214.
+*
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#if defined XENV_VXWORKS +/* VxWorks environment */ +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#else +/* standalone environment */ + +#include "mb_interface.h" +#include "xil_types.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/** +* +* Invalidate the entire L1 data cache. If the cacheline is modified (dirty), +* the modified contents are lost. +* +* @param None. +* +* @return None. +* +* @note +* +* Processor must be in real mode. +****************************************************************************/ +#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache() + +/****************************************************************************/ +/** +* +* Invalidate the entire L2 data cache. If the cacheline is modified (dirty), +* the modified contents are lost. +* +* @param None. +* +* @return None. +* +* @note +* +* Processor must be in real mode. +****************************************************************************/ +#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext() + +/****************************************************************************/ +/** +* +* Invalidate the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the L1 data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost. +* +* @param Addr is address of ragne to be invalidated. +* @param Len is the length in bytes to be invalidated. +* +* @return None. +* +* @note +* +* Processor must be in real mode. +****************************************************************************/ +#define Xil_L1DCacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_dcache_range((Addr), (Len)) + +/****************************************************************************/ +/** +* +* Invalidate the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the L1 data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost. +* +* @param Addr is address of ragne to be invalidated. +* @param Len is the length in bytes to be invalidated. +* +* @return None. +* +* @note +* +* Processor must be in real mode. +****************************************************************************/ +#define Xil_L2CacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_cache_ext_range((Addr), (Len)) + +/****************************************************************************/ +/** +* Flush the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the data cache, +* and is modified (dirty), the cacheline will be written to system memory. +* The cacheline will also be invalidated. +* +* @param Addr is the starting address of the range to be flushed. +* @param Len is the length in byte to be flushed. +* +* @return None. +* +****************************************************************************/ +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define Xil_L1DCacheFlushRange(Addr, Len) \ + microblaze_flush_dcache_range((Addr), (Len)) +#else +# define Xil_L1DCacheFlushRange(Addr, Len) \ + microblaze_invalidate_dcache_range((Addr), (Len)) +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ + +/****************************************************************************/ +/** +* Flush the L2 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the data cache, +* and is modified (dirty), the cacheline will be written to system memory. +* The cacheline will also be invalidated. +* +* @param Addr is the starting address of the range to be flushed. +* @param Len is the length in byte to be flushed. +* +* @return None. +* +****************************************************************************/ +#define Xil_L2CacheFlushRange(Addr, Len) \ + microblaze_flush_cache_ext_range((Addr), (Len)) + +/****************************************************************************/ +/** +* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be +* written to system memory. The entire data cache will be invalidated. +* +* @return None. +* +* @note +* +****************************************************************************/ +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define Xil_L1DCacheFlush() microblaze_flush_dcache() +#else +# define Xil_L1DCacheFlush() microblaze_invalidate_dcache() +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ + +/****************************************************************************/ +/** +* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be +* written to system memory. The entire data cache will be invalidated. +* +* @return None. +* +* @note +* +****************************************************************************/ +#define Xil_L2CacheFlush() microblaze_flush_cache_ext() + +/****************************************************************************/ +/** +* +* Invalidate the instruction cache for the given address range. +* +* @param Addr is address of ragne to be invalidated. +* @param Len is the length in bytes to be invalidated. +* +* @return None. +* +****************************************************************************/ +#define Xil_L1ICacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_icache_range((Addr), (Len)) + +/****************************************************************************/ +/** +* +* Invalidate the entire instruction cache. +* +* @param None +* +* @return None. +* +****************************************************************************/ +#define Xil_L1ICacheInvalidate() \ + microblaze_invalidate_icache() + + +/****************************************************************************/ +/** +* +* Enable the L1 data cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1DCacheEnable() \ + microblaze_enable_dcache() + +/****************************************************************************/ +/** +* +* Disable the L1 data cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1DCacheDisable() \ + microblaze_disable_dcache() + +/****************************************************************************/ +/** +* +* Enable the instruction cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1ICacheEnable() \ + microblaze_enable_icache() + +/****************************************************************************/ +/** +* +* Disable the L1 Instruction cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1ICacheDisable() \ + microblaze_disable_icache() + +/****************************************************************************/ +/** +* +* Enable the data cache. +* +* @param None +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheEnable() Xil_L1DCacheEnable() + +/****************************************************************************/ +/** +* +* Enable the instruction cache. +* +* @param None +* +* @return None. +* +* @note +* +* +****************************************************************************/ +#define Xil_ICacheEnable() Xil_L1ICacheEnable() + +/**************************************************************************** +* +* Invalidate the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_DCacheInvalidate() \ + Xil_L2CacheInvalidate(); \ + Xil_L1DCacheInvalidate(); + + +/**************************************************************************** +* +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of ragne to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_DCacheInvalidateRange(Addr, Len) \ + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1DCacheInvalidateRange((Addr), (Len)); + + +/**************************************************************************** +* +* Flush the entire Data cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_DCacheFlush() \ + Xil_L2CacheFlush(); \ + Xil_L1DCacheFlush(); + +/**************************************************************************** +* Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the written to system memory first before the +* before the line is invalidated. +* +* @param Start address of range to be flushed. +* @param Length of range to be flushed in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_DCacheFlushRange(Addr, Len) \ + Xil_L2CacheFlushRange((Addr), (Len)); \ + Xil_L1DCacheFlushRange((Addr), (Len)); + + +/**************************************************************************** +* +* Invalidate the entire instruction cache. +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_ICacheInvalidate() \ + Xil_L2CacheInvalidate(); \ + Xil_L1ICacheInvalidate(); + + +/**************************************************************************** +* +* Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the Data cache, +* the cacheline containing that byte is invalidated. If the cacheline +* is modified (dirty), the modified contents are lost and are NOT +* written to system memory before the line is invalidated. +* +* @param Start address of ragne to be invalidated. +* @param Length of range to be invalidated in bytes. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +#define Xil_ICacheInvalidateRange(Addr, Len) \ + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1ICacheInvalidateRange((Addr), (Len)); + +void Xil_DCacheDisable(void); +void Xil_ICacheDisable(void); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/lib/bsp/standalone/src/microblaze/xil_exception.c b/lib/bsp/standalone/src/microblaze/xil_exception.c new file mode 100644 index 00000000..2c1c4734 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_exception.c @@ -0,0 +1,244 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains implementation of exception related driver functions. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+*
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_types.h" +#include "xil_exception.h" + +#include "microblaze_exceptions_g.h" +#include "microblaze_interrupts_i.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern void microblaze_enable_exceptions(void); +extern void microblaze_disable_exceptions(void); +extern void microblaze_enable_interrupts(void); +extern void microblaze_disable_interrupts(void); + +/** +* Currently HAL is an augmented part of standalone BSP, so the old definition +* of MB_ExceptionVectorTableEntry is used here. +*/ + +typedef struct { + Xil_ExceptionHandler Handler; + void *CallBackRef; +} MB_ExceptionVectorTableEntry; + +/*typedef struct { + Xil_ExceptionHandler Handler, + void *CallBackRef, +} MB_InterruptVectorTableEntry, */ + +#ifdef __cplusplus +} +#endif + + +/************************** Variable Definitions *****************************/ +extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT]; +extern MB_InterruptVectorTableEntry MB_InterruptVectorTable; + +/** + * + * This function is a stub handler that is the default handler that gets called + * if the application has not setup a handler for a specific exception. The + * function interface has to match the interface specified for a handler even + * though none of the arguments are used. + * + * @param Data is unused by this function. + * + * @return + * + * None. + * + * @note + * + * None. + * + *****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void *) Data; +} + +/****************************************************************************/ +/** +* +* Initialize exception handling for the processor. The exception vector table +* is setup with the stub handler for all exceptions. +* +* @param None. +* +* @return None. +* +* @note +* +* None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + /* + * there is no need to setup the exception table here + */ + +} + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_ExceptionEnable(void) +{ +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED + microblaze_enable_exceptions(); +#endif + microblaze_enable_interrupts(); +} + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void Xil_ExceptionDisable(void) +{ +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED + microblaze_disable_exceptions(); +#endif + microblaze_disable_interrupts(); +} + +/*****************************************************************************/ +/** +* +* Makes the connection between the Id of the exception source and the +* associated handler that is to run when the exception is recognized. The +* argument provided in this call as the DataPtr is used as the argument +* for the handler when it is called. +* +* @param Id contains the ID of the exception source and should +* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST. +* See xil_mach_exception.h for further information. +* @param Handler to the handler for that exception. +* @param Data is a reference to data that will be passed to the handler +* when it gets called. +* +* @return None. +* +* @note +* +* None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler, + void *Data) +{ + if (Id == XIL_EXCEPTION_ID_INT) { + MB_InterruptVectorTable.Handler = Handler; + MB_InterruptVectorTable.CallBackRef = Data; + } + else { +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED + MB_ExceptionVectorTable[Id].Handler = Handler; + MB_ExceptionVectorTable[Id].CallBackRef = Data; +#endif + } +} + + +/*****************************************************************************/ +/** +* +* Removes the handler for a specific exception Id. The stub handler is then +* registered for this exception Id. +* +* @param Id contains the ID of the exception source and should +* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST. +* See xexception_l.h for further information. +* +* @return None. +* +* @note +* +* None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Id) +{ + if (Id == XIL_EXCEPTION_ID_INT) { + MB_InterruptVectorTable.Handler = Xil_ExceptionNullHandler; + MB_InterruptVectorTable.CallBackRef = NULL; + } + else { + +#ifdef MICROBLAZE_EXCEPTIONS_ENABLED + MB_ExceptionVectorTable[Id].Handler = + Xil_ExceptionNullHandler; + MB_ExceptionVectorTable[Id].CallBackRef = NULL; +#endif + } +} diff --git a/lib/bsp/standalone/src/microblaze/xil_exception.h b/lib/bsp/standalone/src/microblaze/xil_exception.h new file mode 100644 index 00000000..79418dd0 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_exception.h @@ -0,0 +1,124 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains exception related driver functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+*
+* 
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * These constants are specific to Microblaze processor. + */ + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_FSL 0U +#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U +#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U +#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U +#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U +#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U +#define XIL_EXCEPTION_ID_FPU 6U +#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U +#define XIL_EXCEPTION_ID_MMU 7U +#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU + +/* + * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value. + */ +#define XIL_EXCEPTION_ID_INT 16U /** + * exception ID for interrupt + */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *Data); + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Id); + +extern void Xil_ExceptionInit(void); +extern void Xil_ExceptionEnable(void); +extern void Xil_ExceptionDisable(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/microblaze/xil_io.c b/lib/bsp/standalone/src/microblaze/xil_io.c new file mode 100644 index 00000000..4da60764 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_io.c @@ -0,0 +1,358 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped architectures. These functions +* encapsulate generic CPU I/O requirements. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a hbm  07/28/09 Initial release
+* 3.00a hbm  07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
+*
+* 
+* +* @note +* +* This file may contain architecture-dependent code. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/***************** Macros (Inline Functions) and Functions Definitions *******/ + +/*****************************************************************************/ +/** +* +* Perform an input operation for an 8-bit memory location by reading from the +* specified address and returning the value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u8 Xil_In8(u32 Addr) { + return *(volatile u8 *)Addr; +} + +/*****************************************************************************/ +/** +* +* Perform an input operation for a 16-bit memory location by reading from the +* specified address and returning the value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u16 Xil_In16(u32 Addr) { + return *(volatile u16 *)Addr; +} + +/*****************************************************************************/ +/** +* +* Performs an input operation for a 32-bit memory location by reading from the +* specified address and returning the Value read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address. +* +* @note None. +* +******************************************************************************/ +u32 Xil_In32(u32 Addr) { + return *(volatile u32 *)Addr; +} + + +/*****************************************************************************/ +/** +* +* Perform an output operation for an 8-bit memory location by writing the +* specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out8(u32 Addr, u8 Value) { + u8 *LocalAddr = (u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Perform an output operation for a 16-bit memory location by writing the +* specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out16(u32 Addr, u16 Value) { + u16 *LocalAddr = (u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Perform an output operation for a 32-bit memory location by writing the +* specified value to the specified address. +* +* @param addr contains the address to perform the output operation at. +* @param value contains the value to be output at the specified address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void Xil_Out32(u32 Addr, u32 Value) { + u32 *LocalAddr = (u32 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* Perform a 16-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* Perform a 32-bit endian converion. +* +* @param Data contains the value to be converted. +* +* @return converted value. +* +* @note None. +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +} + +/*****************************************************************************/ +/** +* +* Perform a little-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the byte-swapped value +* read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address with the +* proper endianness. The return value has the same endianness +* as that of the processor, i.e. if the processor is big-engian, +* the return value is the byte-swapped value read from the +* address. +* +* +* @note None. +* +******************************************************************************/ +#ifndef __LITTLE_ENDIAN__ +u16 Xil_In16LE(u32 Addr) +#else +u16 Xil_In16BE(u32 Addr) +#endif +{ + u16 Value; + + /* get the data then swap it */ + Value = Xil_In16(Addr); + + return Xil_EndianSwap16(Value); +} + +/*****************************************************************************/ +/** +* +* Perform a little-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the byte-swapped value +* read from that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address with the +* proper endianness. The return value has the same endianness +* as that of the processor, i.e. if the processor is big-engian, +* the return value is the byte-swapped value read from the +* address. +* +* @note None. +* +******************************************************************************/ +#ifndef __LITTLE_ENDIAN__ +u32 Xil_In32LE(u32 Addr) +#else +u32 Xil_In32BE(u32 Addr) +#endif +{ + u32 InValue; + + /* get the data then swap it */ + InValue = Xil_In32(Addr); + return Xil_EndianSwap32(InValue); +} + +/*****************************************************************************/ +/** +* +* Perform a little-endian output operation for a 16-bit memory location by +* writing the specified value to the the specified address. The value is +* byte-swapped before being written. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the value to be output at the specified address. +* The value has the same endianness as that of the processor. +* If the processor is big-endian, the byte-swapped value is +* written to the address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#ifndef __LITTLE_ENDIAN__ +void Xil_Out16LE(u32 Addr, u16 Value) +#else +void Xil_Out16BE(u32 Addr, u16 Value) +#endif +{ + u16 OutValue; + + /* swap the data then output it */ + OutValue = Xil_EndianSwap16(Value); + + Xil_Out16(Addr, OutValue); +} + +/*****************************************************************************/ +/** +* +* Perform a little-endian output operation for a 32-bit memory location +* by writing the specified value to the the specified address. The value is +* byte-swapped before being written. +* +* @param Addr contains the address at which the output operation at. +* @param Value contains the value to be output at the specified address. +* The value has the same endianness as that of the processor. +* If the processor is big-endian, the byte-swapped value is +* written to the address. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#ifndef __LITTLE_ENDIAN__ +void Xil_Out32LE(u32 Addr, u32 Value) +#else +void Xil_Out32BE(u32 Addr, u32 Value) +#endif +{ + u32 OutValue; + + /* swap the data then output it */ + OutValue = Xil_EndianSwap32(Value); + Xil_Out32(Addr, OutValue); +} diff --git a/lib/bsp/standalone/src/microblaze/xil_io.h b/lib/bsp/standalone/src/microblaze/xil_io.h new file mode 100644 index 00000000..74e6049c --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_io.h @@ -0,0 +1,269 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a hbm  07/28/09 Initial release
+* 3.00a hbm  07/21/10 Added Xil_EndianSwap32/16, Xil_Htonl/s, Xil_Ntohl/s
+* 3.03a sdm  08/18/11 Added INST_SYNC and DATA_SYNC macros.
+* 3.07a asa  08/31/12 Added xil_printf.h include
+*
+* 
+* +* @note +* +* This file may contain architecture-dependent items. +* +******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "mb_interface.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Function Prototypes ****************************/ + +u8 Xil_In8(u32 Addr); +u16 Xil_In16(u32 Addr); +u32 Xil_In32(u32 Addr); + +void Xil_Out8(u32 Addr, u8 Value); +void Xil_Out16(u32 Addr, u16 Value); +void Xil_Out32(u32 Addr, u32 Value); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined __GNUC__ +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +#else +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/* + * The following macros allow optimized I/O operations for memory mapped I/O. + * It should be noted that macros cannot be used if synchronization of the I/O + * operation is needed as it will likely break some code. + */ + + + +extern u16 Xil_EndianSwap16(u16 Data); +extern u32 Xil_EndianSwap32(u32 Data); + +#ifndef __LITTLE_ENDIAN__ +extern u16 Xil_In16LE(u32 Addr); +extern u32 Xil_In32LE(u32 Addr); +extern void Xil_Out16LE(u32 Addr, u16 Value); +extern void Xil_Out32LE(u32 Addr, u32 Value); + +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the value read from +* that address. +* +* @param addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address with the +* proper endianness. The return value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return value is the byte-swapped value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16BE(Addr) Xil_In16((Addr)) + +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The value read from the specified input address with the +* proper endianness. The return value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return value is the byte-swapped value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32BE(Addr) Xil_In32((Addr)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the value to be output at the specified address. +* The value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16BE(Addr, Value) Xil_Out16((Addr), (Value)) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the value to be output at the specified address. +* The value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32BE(Addr, Value) Xil_Out32((Addr), (Value)) + +#define Xil_Htonl(Data) (Data) +#define Xil_Htons(Data) (Data) +#define Xil_Ntohl(Data) (Data) +#define Xil_Ntohs(Data) (Data) + +#else + +extern u16 Xil_In16BE(u32 Addr); +extern u32 Xil_In32BE(u32 Addr); +extern void Xil_Out16BE(u32 Addr, u16 Value); +extern void Xil_Out32BE(u32 Addr, u32 Value); + +#define Xil_In16LE(Addr) Xil_In16((Addr)) +#define Xil_In32LE(Addr) Xil_In32((Addr)) +#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) +#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) + + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Value the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Value the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c new file mode 100644 index 00000000..13aef959 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.c @@ -0,0 +1,522 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_misc_reset.c +* +* This file contains the implementation of the reset sequence for various +* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset +* sequence provided to the interfaces is based on the provision in +* slcr reset functional blcok. +* +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 
+* +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_misc_psreset_api.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* This function contains the implementation for ddr reset. +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XDdr_ResetHw(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert and deassert the ddr softreset bit */ + RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + RegVal |= XDDRPS_CTRL_RESET_MASK; + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for remapping the ocm memory region +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XOcm_Remap(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Map the ocm region to postbootrom state */ + RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; + Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for SMC reset sequence +* +* @param BaseAddress of the interface +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSmc_ResetHw(u32 BaseAddress) +{ + u32 RegVal; + + /* Clear the interuupts */ + RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); + RegVal |= XSMC_MEMC_CLR_CONFIG_MASK; + Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); + /* Clear the idle counter registers */ + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); + /* Update the ecc registers with reset values */ + Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, + XSMC_ECC_MEMCFG1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET, + XSMC_ECC_MEMCMD1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, + XSMC_ECC_MEMCMD2_RESET_VAL); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr mio registers +* with reset values +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_MioWriteResetValues(void) +{ + u32 i; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Update all the MIO registers with reset values */ + for (i=0U; i<=1U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + for (; i<=8U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_02_RESET_VAL); + } + for (; i<=53U ;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr pll registers +* with reset values +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_PllWriteResetValues(void) +{ + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + + /* update the pll control registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL); + /* update the pll config registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL); + /* update the clock control registers with reset values */ + Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for disabling the level shifters +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_DisableLevelShifters(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Disable the level shifters */ + RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); + Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); + +} +/*****************************************************************************/ +/** +* This function contains the implementation for OCM software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_OcmReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal |= XSLCR_OCM_RST_CTRL_VAL; + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for Ethernet software reset from +* the slcr +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_EmacPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal |= XSLCR_GEM_RST_CTRL_VAL; + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for USB software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_UsbPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal |= XSLCR_USB_RST_CTRL_VAL; + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for QSPI software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_QspiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal |= XSLCR_QSPI_RST_CTRL_VAL; + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SPI software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_SpiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal |= XSLCR_SPI_RST_CTRL_VAL; + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for i2c software reset from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_I2cPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal |= XSLCR_I2C_RST_CTRL_VAL; + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for UART software reset from the +* slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_UartPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal |= XSLCR_UART_RST_CTRL_VAL; + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for CAN software reset from slcr +* registers +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_CanPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal |= XSLCR_CAN_RST_CTRL_VAL; + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SMC software reset from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_SmcPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal |= XSLCR_SMC_RST_CTRL_VAL; + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for DMA controller software reset +* from the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_DmaPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal |= XSLCR_DMAC_RST_CTRL_VAL; + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for Gpio AMBA software reset from +* the slcr +* +* @param N/A. +* +* @return N/A. +* +* @note None. +* +******************************************************************************/ +void XSlcr_GpioPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal |= XSLCR_GPIO_RST_CTRL_VAL; + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); +} diff --git a/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h new file mode 100644 index 00000000..234d9beb --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_misc_psreset_api.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register defintions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +* +* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ +#define XIL_MISC_RESET_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) +/**< SLCR USB reset control address register */ +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ +/**< SLCR GEM reset control address register */ +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) +/**< SLCR SMC reset control address register */ +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0DU + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x00000001U +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(void); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(void); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(void); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(void); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(void); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/lib/bsp/standalone/src/microblaze/xil_printf.h b/lib/bsp/standalone/src/microblaze/xil_printf.h new file mode 100644 index 00000000..a1675924 --- /dev/null +++ b/lib/bsp/standalone/src/microblaze/xil_printf.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef XIL_PRINTF_H +#define XIL_PRINTF_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void xil_printf(const char8 *ctrl1, ...); +void print(char *ptr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/bsp/standalone/src/profile/Makefile b/lib/bsp/standalone/src/profile/Makefile new file mode 100644 index 00000000..891fdf64 --- /dev/null +++ b/lib/bsp/standalone/src/profile/Makefile @@ -0,0 +1,78 @@ +############################################################################### +# +# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +# +# Makefile for profiler +# +####################################################################### + +# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here +include ../config.make + +AS=mb-as +COMPILER = mb-gcc +ARCHIVER = mb-ar +CP = cp +COMPILER_FLAGS=-O2 +EXTRA_COMPILER_FLAGS= +LIB = libxil.a +DUMMYLIB = libxilprofile.a + +CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS)) + +RELEASEDIR = ../../../../lib +INCLUDEDIR = ../../../../include +INCLUDES = -I./. -I${INCLUDEDIR} + +OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o +DUMMYOBJ = dummy.o +INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h + +libs : reallibs dummylibs + +reallibs : $(OBJS) $(PROFILE_ARCH_OBJS) + $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS) + +dummylibs : $(DUMMYOBJ) + $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ) + +%.o:%.c + $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) + +%.o:%.S + $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) + +include: + $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB) diff --git a/lib/bsp/standalone/src/profile/_profile_clean.c b/lib/bsp/standalone/src/profile/_profile_clean.c new file mode 100644 index 00000000..1d8aada0 --- /dev/null +++ b/lib/bsp/standalone/src/profile/_profile_clean.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "profile.h" +#include "_profile_timer_hw.h" +#include "xil_exception.h" + +void _profile_clean( void ); + +/* + * This function is the exit routine and is called by the crtinit, when the + * program terminates. The name needs to be changed later.. + */ +void _profile_clean( void ) +{ + Xil_ExceptionDisable(); + disable_timer(); +} diff --git a/lib/bsp/standalone/src/profile/_profile_init.c b/lib/bsp/standalone/src/profile/_profile_init.c new file mode 100644 index 00000000..0ac51b17 --- /dev/null +++ b/lib/bsp/standalone/src/profile/_profile_init.c @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_init.c: +* Initialize the Profiling Structures. +* +******************************************************************************/ + +#include "profile.h" + +/* XMD Initializes the following Global Variables Value during Program + * Download with appropriate values. */ + +#ifdef PROC_MICROBLAZE + +extern s32 microblaze_init(void); + +#elif defined PROC_PPC + +extern s32 powerpc405_init(void); + +#else + +extern s32 cortexa9_init(void); + +#endif + +s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */ + +u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */ +u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */ +u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */ +u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */ + +/* Structure for Storing the Profiling Data */ +struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU); +s32 n_gmon_sections = 1; + +/* This is the initialization code, which is called from the crtinit. */ + +void _profile_init( void ) +{ +/* print("Gmon Init called....\r\n") */ +/* putnum(n_gmon_sections) , print("\r\n") */ +/* if( _gmonparam == 0xffffffff ) */ +/* printf("Gmonparam is NULL !!\r\n") */ +/* for( i = 0, i < n_gmon_sections, i++ )[ */ +/* putnum( _gmonparam[i].lowpc) , print("\t") */ +/* putnum( _gmonparam[i].highpc) , print("\r\n") */ +/* putnum( _gmonparam[i].textsize ), print("\r\n") */ +/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */ +/* ] */ + +#ifdef PROC_MICROBLAZE + (void)microblaze_init(); +#elif defined PROC_PPC + powerpc405_init(); +#else + (void)cortexa9_init(); +#endif +} diff --git a/lib/bsp/standalone/src/profile/_profile_timer_hw.c b/lib/bsp/standalone/src/profile/_profile_timer_hw.c new file mode 100644 index 00000000..e85fb5c2 --- /dev/null +++ b/lib/bsp/standalone/src/profile/_profile_timer_hw.c @@ -0,0 +1,387 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_timer_hw.c: +* Timer related functions +* +******************************************************************************/ + +#include "profile.h" +#include "_profile_timer_hw.h" + +#include "xil_exception.h" + +#ifdef PROC_PPC +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +/* #ifndef PPC_PIT_INTERRUPT */ +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +/* extern u32 timer_clk_ticks, */ + +#ifdef PROC_PPC405 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_pit_init( void ); +#endif +s32 powerpc405_init() +#endif /* PROC_CORTEXA9 */ + +#ifdef PROC_PPC440 +#ifdef PPC_PIT_INTERRUPT +s32 ppc_dec_init( void ); +#endif +s32 powerpc405_init(void); +#endif /* PROC_PPC440 */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +s32 opb_timer_init( void ); +#endif + +#ifdef PROC_MICROBLAZE +s32 microblaze_init(void); +#endif /* PROC_MICROBLAZE */ + +#ifdef PROC_CORTEXA9 +s32 scu_timer_init( void ); +s32 cortexa9_init(void); +#endif /* PROC_CORTEXA9 */ + + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC405 + + +/*-------------------------------------------------------------------- +* PowerPC PIT Timer Init. +* Defined only if PIT Timer is used for Profiling +* +*-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +int ppc_pit_init( void ) +{ + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set PIT Timer Interrupt and Enable it. */ + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + XTime_PITSetInterval( timer_clk_ticks ) ; + XTime_PITEnableAutoReload() ; + return 0; +} +#endif + + +/* -------------------------------------------------------------------- +* PowerPC Timer Initialization functions. +* For PowerPC, PIT and opb_timer can be used for Profiling. This +* is selected by the user in standalone BSP +* +*-------------------------------------------------------------------- */ +s32 powerpc405_init() +{ + Xil_ExceptionInit() ; + Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; + + /* Initialize the Timer. + * 1. If PowerPC PIT Timer has to be used, initialize PIT timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ +#ifdef PPC_PIT_INTERRUPT + ppc_pit_init(); +#else +#ifdef TIMER_CONNECT_INTC + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); +#endif + /* Initialize the timer with Timer Ticks */ + opb_timer_init() ; +#endif + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef PPC_PIT_INTERRUPT + XTime_PITEnableInterrupt() ; +#elif TIMER_CONNECT_INTC + XIntc_MasterEnable( INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); +#endif + Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ; +#endif + return 0; +} + +#endif /* PROC_PPC */ + + + +/*-------------------------------------------------------------------- + * PowerPC440 Target - Timer related functions + * -------------------------------------------------------------------- */ +#ifdef PROC_PPC440 + + +/*-------------------------------------------------------------------- + * PowerPC DEC Timer Init. + * Defined only if DEC Timer is used for Profiling + * + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +s32 ppc_dec_init( void ) +{ + /* 1. Register Profile_intr_handler as Interrupt handler */ + /* 2. Set DEC Timer Interrupt and Enable it. */ + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + XTime_DECSetInterval( timer_clk_ticks ) ; + XTime_DECEnableAutoReload() ; + return 0; +} +#endif + + +/*-------------------------------------------------------------------- + * PowerPC Timer Initialization functions. + * For PowerPC, DEC and opb_timer can be used for Profiling. This + * is selected by the user in standalone BSP + * + *-------------------------------------------------------------------- */ +s32 powerpc405_init(void) +{ + Xil_ExceptionInit(); + Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; + + /* Initialize the Timer. + * 1. If PowerPC DEC Timer has to be used, initialize DEC timer. + * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */ +#ifdef PPC_PIT_INTERRUPT + ppc_dec_init(); +#else +#ifdef TIMER_CONNECT_INTC + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); + + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); + Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, + (Xil_ExceptionHandler)profile_intr_handler,NULL); +#endif + /* Initialize the timer with Timer Ticks */ + opb_timer_init() ; +#endif + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef PPC_PIT_INTERRUPT + XTime_DECEnableInterrupt() ; +#elif TIMER_CONNECT_INTC + XIntc_MasterEnable( INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); +#endif + Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ; +#endif + return 0; +} + +#endif /* PROC_PPC440 */ + +/* -------------------------------------------------------------------- + * opb_timer Initialization for PowerPC and MicroBlaze. This function + * is not needed if DEC timer is used in PowerPC + * + *-------------------------------------------------------------------- */ +/* #ifndef PPC_PIT_INTERRUPT */ +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +s32 opb_timer_init( void ) +{ + /* set the number of cycles the timer counts before interrupting */ + XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks); + + /* reset the timers, and clear interrupts */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, + (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK ); + + /* start the timers */ + XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK + | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK); + return 0; +} +#endif + + +/*-------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for MicroBlaze Target. + * For MicroBlaze, opb_timer is used. The opb_timer can be directly + * connected to MicroBlaze or connected through Interrupt Controller. + * + *-------------------------------------------------------------------- */ +s32 microblaze_init(void) +{ + /* Register profile_intr_handler + * 1. If timer is connected to Interrupt Controller, register the handler + * to Interrupt Controllers vector table. + * 2. If timer is directly connected to MicroBlaze, register the handler + * as Interrupt handler */ + Xil_ExceptionInit(); + +#ifdef TIMER_CONNECT_INTC + XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, + (XInterruptHandler)profile_intr_handler,NULL); +#else + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)profile_intr_handler, + NULL) ; +#endif + + /* Initialize the timer with Timer Ticks */ + (void)opb_timer_init() ; + + /* Enable Interrupts in the System, if Profile Timer is the only Interrupt + * in the System. */ +#ifdef ENABLE_SYS_INTR +#ifdef TIMER_CONNECT_INTC + XIntc_MasterEnable((u32)INTC_BASEADDR ); + XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); + XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL); +#endif + +#endif + + Xil_ExceptionEnable(); + + return 0; + +} + +#endif /* PROC_MICROBLAZE */ + + + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Initialize the Profile Timer for Cortex A9 Target. + * The scu private timer is connected to the Scu GIC controller. + * + *-------------------------------------------------------------------- */ +s32 scu_timer_init( void ) +{ + /* set the number of cycles the timer counts before interrupting + * scu timer runs at half the cpu clock */ + XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U); + + /* clear any pending interrupts */ + XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U); + + /* enable interrupts, auto-reload mode and start the timer */ + XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK | + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK); + + return 0; +} + +s32 cortexa9_init(void) +{ + + Xil_ExceptionInit(); + + XScuGic_DeviceInitialize(0); + + /* + * Connect the interrupt controller interrupt handler to the hardware + * interrupt handling logic in the processor. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler, + NULL); + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR, + PROFILE_TIMER_INTR_ID, + (Xil_ExceptionHandler)profile_intr_handler, + NULL); + + /* + * Enable the interrupt for scu timer. + */ + XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID); + + /* + * Enable interrupts in the Processor. + */ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); + + /* + * Initialize the timer with Timer Ticks + */ + (void)scu_timer_init() ; + + Xil_ExceptionEnable(); + + return 0; +} + +#endif /* PROC_CORTEXA9 */ diff --git a/lib/bsp/standalone/src/profile/_profile_timer_hw.h b/lib/bsp/standalone/src/profile/_profile_timer_hw.h new file mode 100644 index 00000000..2cee66b0 --- /dev/null +++ b/lib/bsp/standalone/src/profile/_profile_timer_hw.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_timer_hw.h: +* Timer related functions +* +******************************************************************************/ + +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H + +#include "profile.h" + +#ifdef PROC_PPC +#if defined __GNUC__ +# define SYNCHRONIZE_IO __asm__ volatile ("eieio") +#elif defined __DCC__ +# define SYNCHRONIZE_IO __asm volatile(" eieio") +#else +# define SYNCHRONIZE_IO +#endif +#endif + +#ifdef PROC_PPC +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } +#else +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } +#endif + +#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) + +#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) + +#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ + ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ + (RegisterValue)) + +#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PROC_PPC +#include "xexception_l.h" +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +#ifdef PROC_CORTEXA9 +#include "xscutimer_hw.h" +#include "xscugic.h" +#endif + +extern u32 timer_clk_ticks ; + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC + +#ifdef PPC_PIT_INTERRUPT +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ +#endif + +#ifdef PROC_PPC440 +#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE +#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS +#define XREG_SPR_PIT XREG_SPR_DEC +#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT +#endif + +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ + +#ifdef PPC_PIT_INTERRUPT +#define disable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ + timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ + mtspr(XREG_SPR_PIT, 0); \ + } +#else +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define enable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ + mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ + } +#else +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define timer_ack() \ + { \ + u32 val; \ + mtspr(XREG_SPR_PIT, timer_clk_ticks); \ + mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ + } +#else +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } +#endif + +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ + + + + +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ + } + +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/profile/dummy.S b/lib/bsp/standalone/src/profile/dummy.S new file mode 100644 index 00000000..d28646d6 --- /dev/null +++ b/lib/bsp/standalone/src/profile/dummy.S @@ -0,0 +1,64 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + .globl dummy_f + +#ifdef PROC_MICROBLAZE + .text + .align 2 + .ent dummy_f + +dummy_f: + nop + + .end dummy_f +#endif + +#ifdef PROC_PPC + .section .text + .align 2 + .type dummy_f@function + +dummy_f: + b dummy_f + +#endif + +#ifdef PROC_CORTEXA9 + .section .text + .align 2 + .type dummy_f, %function + +dummy_f: + b dummy_f + +#endif diff --git a/lib/bsp/standalone/src/profile/mblaze_nt_types.h b/lib/bsp/standalone/src/profile/mblaze_nt_types.h new file mode 100644 index 00000000..7096a92d --- /dev/null +++ b/lib/bsp/standalone/src/profile/mblaze_nt_types.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef _MBLAZE_NT_TYPES_H +#define _MBLAZE_NT_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef char byte; +typedef short half; +typedef int word; +typedef unsigned char ubyte; +typedef unsigned short uhalf; +typedef unsigned int uword; +typedef ubyte boolean; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/bsp/standalone/src/profile/profile.h b/lib/bsp/standalone/src/profile/profile.h new file mode 100644 index 00000000..4cb07a7d --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef PROFILE_H +#define PROFILE_H 1 + +#include +#include "xil_types.h" +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(u32 frompc, u32 selfpc); +void profile_intr_handler( void ) ; +void _profile_init( void ); + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER u16 + +struct tostruct { + u32 selfpc; + s32 count; + s16 link; + u16 pad; +}; + +struct fromstruct { + u32 frompc ; + s16 link ; + u16 pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + s32 state; + + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ + + /* Call-graph Information */ + struct fromstruct *froms; + u32 fromssize; + struct tostruct *tos; + u32 tossize; + + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ +}; +extern struct gmonparam *_gmonparam; +extern s32 n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* PROFILE_H */ diff --git a/lib/bsp/standalone/src/profile/profile_cg.c b/lib/bsp/standalone/src/profile/profile_cg.c new file mode 100644 index 00000000..2539ce61 --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_cg.c @@ -0,0 +1,171 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "profile.h" +#include "_profile_timer_hw.h" +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +/* + * The mcount fucntion is excluded from the library, if the user defines + * PROFILE_NO_GRAPH. + */ +#ifndef PROFILE_NO_GRAPH + +#include +#include +#include + +#ifdef PROFILE_NO_FUNCPTR +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ); +#else +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ); +#endif + +/*extern struct gmonparam *_gmonparam, */ + +#ifdef PROFILE_NO_FUNCPTR +s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc ) +{ + s32 index = 0 ; + + while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){ + index++ ; + } + if( index == cgtable_size ) { + return -1 ; + } else { + return index ; + } +} +#else +s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc ) +{ + s32 index = 0 ; + s32 Status; + + while( (index < fromssize) && (froms[index].frompc != frompc) ){ + index++ ; + } + if( index == fromssize ) { + Status = -1 ; + } else { + Status = index ; + } + return Status; +} +#endif /* PROFILE_NO_FUNCPTR */ + + +void mcount( u32 frompc, u32 selfpc ) +{ + register struct gmonparam *p = NULL; + register s32 toindex, fromindex; + s32 j; + + disable_timer(); + + /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") , + * check that frompcindex is a reasonable pc value. + * for example: signal catchers get called from the stack, + * not from text space. too bad. + */ + for(j = 0; j < n_gmon_sections; j++ ){ + if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) { + p = &_gmonparam[j]; + break; + } + } + if( j == n_gmon_sections ) { + goto done; + } + +#ifdef PROFILE_NO_FUNCPTR + fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ; + if( fromindex == -1 ) { + fromindex = p->cgtable_size ; + p->cgtable_size++ ; + p->cgtable[fromindex].frompc = frompc ; + p->cgtable[fromindex].selfpc = selfpc ; + p->cgtable[fromindex].count = 1 ; + goto done ; + } + p->cgtable[fromindex].count++ ; +#else + fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ; + if( fromindex == -1 ) { + fromindex = (s32)p->fromssize ; + p->fromssize++ ; + /*if( fromindex >= N_FROMS ) { + * print("Error : From PC table overflow\r\n") + * goto overflow + *}*/ + p->froms[fromindex].frompc = frompc ; + p->froms[fromindex].link = -1 ; + }else { + toindex = ((s32)(p->froms[fromindex].link)); + while(toindex != -1) { + toindex = (((s32)p->tossize) - toindex)-1 ; + if( p->tos[toindex].selfpc == selfpc ) { + p->tos[toindex].count++ ; + goto done ; + } + toindex = ((s32)(p->tos[toindex].link)) ; + } + } + + /*if( toindex == -1 ) { */ + p->tos-- ; + p->tossize++ ; + /* if( toindex >= N_TOS ) { + * print("Error : To PC table overflow\r\n") + * goto overflow + *} */ + p->tos[0].selfpc = selfpc ; + p->tos[0].count = 1 ; + p->tos[0].link = p->froms[fromindex].link ; + p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1); +#endif + + done: + p->state = GMON_PROF_ON; + goto enable_timer_label ; + /* overflow: */ + /*p->state = GMON_PROF_ERROR */ + enable_timer_label: + enable_timer(); + return ; +} + + +#endif /* PROFILE_NO_GRAPH */ diff --git a/lib/bsp/standalone/src/profile/profile_config.h b/lib/bsp/standalone/src/profile/profile_config.h new file mode 100644 index 00000000..550c60b4 --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_config.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef _PROFILE_CONFIG_H +#define _PROFILE_CONFIG_H + +#define BINSIZE 4U +#define SAMPLE_FREQ_HZ 100000U +#define TIMER_CLK_TICKS 1000U + +#define PROFILE_NO_FUNCPTR_FLAG 0 + +#define PROFILE_TIMER_BASEADDR 0x00608000U +#define PROFILE_TIMER_INTR_ID 0U + +#define TIMER_CONNECT_INTC + +#endif diff --git a/lib/bsp/standalone/src/profile/profile_hist.c b/lib/bsp/standalone/src/profile/profile_hist.c new file mode 100644 index 00000000..c8ee9cef --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_hist.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "profile.h" +#include "_profile_timer_hw.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef PROC_PPC +#include "xpseudo_asm.h" +#define SPR_SRR0 0x01A +#endif + +#include "xil_types.h" + +extern u32 binsize ; +u32 prof_pc ; + +void profile_intr_handler( void ) +{ + + s32 j; + +#ifdef PROC_MICROBLAZE + asm( "swi r14, r0, prof_pc" ) ; +#elif defined PROC_PPC + prof_pc = mfspr(SPR_SRR0); +#else + /* for cortexa9, lr is saved in asm interrupt handler */ +#endif + /* print("PC: "), putnum(prof_pc), print("\r\n"), */ + for(j = 0; j < n_gmon_sections; j++ ){ + if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) { + _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++; + break; + } + } + /* Ack the Timer Interrupt */ + timer_ack(); +} diff --git a/lib/bsp/standalone/src/profile/profile_mcount_arm.S b/lib/bsp/standalone/src/profile/profile_mcount_arm.S new file mode 100644 index 00000000..e62cec0b --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_mcount_arm.S @@ -0,0 +1,45 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI + +.globl __gnu_mcount_nc +.type __gnu_mcount_nc, %function + +__gnu_mcount_nc: + push {r0, r1, r2, r3, lr} + subs r1, lr, #0 /* callee - current lr */ + ldr r0, [sp, #20] /* caller - at the top of the stack */ + bl mcount /* when __gnu_mcount_nc is called */ + pop {r0, r1, r2, r3, ip, lr} + bx ip + + .end __gnu_mcount_nc diff --git a/lib/bsp/standalone/src/profile/profile_mcount_mb.S b/lib/bsp/standalone/src/profile/profile_mcount_mb.S new file mode 100644 index 00000000..bea2726b --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_mcount_mb.S @@ -0,0 +1,69 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + .globl _mcount + .text + .align 2 + .ent _mcount + + #ifndef PROFILE_NO_GRAPH + +_mcount: + addi r1, r1, -48 + swi r11, r1, 44 + swi r12, r1, 40 + swi r5, r1, 36 + swi r6, r1, 32 + swi r7, r1, 28 + swi r8, r1, 24 + swi r9, r1, 20 + swi r10, r1, 16 + swi r15, r1, 12 + add r5, r0, r15 + brlid r15, mcount + add r6, r0, r16 + + lwi r11, r1, 44 + lwi r12, r1, 40 + lwi r5, r1, 36 + lwi r6, r1, 32 + lwi r7, r1, 28 + lwi r8, r1, 24 + lwi r9, r1, 20 + lwi r10, r1, 16 + lwi r15, r1, 12 + rtsd r15, 4 + addi r1, r1, 48 + + #endif /* PROFILE_NO_GRAPH */ + + .end _mcount diff --git a/lib/bsp/standalone/src/profile/profile_mcount_ppc.S b/lib/bsp/standalone/src/profile/profile_mcount_ppc.S new file mode 100644 index 00000000..39bb92f7 --- /dev/null +++ b/lib/bsp/standalone/src/profile/profile_mcount_ppc.S @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + .globl _mcount + + #define _MCOUNT_STACK_FRAME 48 + .section .text + .align 2 + .type _mcount@function + + +_mcount: + stwu 1, -_MCOUNT_STACK_FRAME(1) + stw 3, 8(1) + stw 4, 12(1) + stw 5, 16(1) + stw 6, 20(1) + stw 7, 24(1) + stw 8, 28(1) + stw 9, 32(1) + stw 10, 36(1) + stw 11, 40(1) + stw 12, 44(1) + mflr 4 + stw 4, (_MCOUNT_STACK_FRAME+4)(1) + lwz 3, (_MCOUNT_STACK_FRAME)(1) + lwz 3, 4(3) + bl mcount + lwz 4, (_MCOUNT_STACK_FRAME+4)(1) + mtlr 4 + lwz 12, 44(1) + lwz 11, 40(1) + lwz 10, 36(1) + lwz 9, 32(1) + lwz 8, 28(1) + lwz 7, 24(1) + lwz 6, 20(1) + lwz 5, 16(1) + lwz 4, 12(1) + lwz 3, 8(1) + addi 1,1, _MCOUNT_STACK_FRAME + blr