diff --git a/lib/sw_services/xilskey/src/changelog.txt b/lib/sw_services/xilskey/src/changelog.txt index fde09c1c..0f5ece2c 100644 --- a/lib/sw_services/xilskey/src/changelog.txt +++ b/lib/sw_services/xilskey/src/changelog.txt @@ -61,5 +61,10 @@ * Modified Zynq efuse PL jtagwrite API by adding clock after * RTI state and one more clock at the end of 11us. * (CR #885421). + * vns 10/20/15 Added cplusplus boundary blocks. (CR #911062) + * Modified XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits API + * when reading from efuse memory to return both bits + * of secure control feature for RSA enable, PPK hash + * bits invalid bits. (CR #911063) * ********************************************************************************/ diff --git a/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h b/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h index df47fba5..9811a1ab 100644 --- a/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h +++ b/lib/sw_services/xilskey/src/include/xilskey_eps_zynqmp.h @@ -43,6 +43,7 @@ * Ver Who Date Changes * ----- ---- -------- -------------------------------------------------------- * 4.0 vns 10/01/15 First release +* vns 10/20/15 Modified secure control bits readback bits. * * *****************************************************************************/ @@ -121,6 +122,12 @@ extern "C" { #define XilSKey_ZynqMp_EfusePs_TsuHCs(RefClk) \ XilSKey_Ceil(((float)30 * RefClk) / (float)1000000000) +#define BOTH_BITS_SET 0x3 + /**< If both bits are set */ +#define XSK_ZYNQMP_EFUSEPS_SECTRL_BIT_SHIFT 0x1 + /**< Shift macro for SEC_CTRL + * if it has 2 bits */ + /** @name efuse types * @{ */ @@ -146,11 +153,14 @@ typedef enum { XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE1, XSK_ZYNQMP_EFUSEPS_SEC_DIS_PROG_GATE2, XSK_ZYNQMP_EFUSEPS_SEC_LOCK, - XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN = 24, - XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK = 26, - XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD = 27, - XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK = 29, - XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT1 = 24, + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT2, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1, + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1, + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2 }XskEfusePS_SecCtrlBits; /*@}*/ diff --git a/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c index 72055b2a..2a897ec3 100644 --- a/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c +++ b/lib/sw_services/xilskey/src/xilskey_eps_zynqmp.c @@ -43,6 +43,10 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------ * 4.0 vns 10/01/15 First release +* vns 10/20/15 Modified XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits API +* when reading from efuse memory to return both bits +* of secure control feature for RSA enable, PPK hash +* bits invalid bits. * * *****************************************************************************/ @@ -373,15 +377,21 @@ u32 XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits( ReadBackSecCtrlBits->SecureLock = DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_LOCK]; ReadBackSecCtrlBits->RSAEnable = - DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN]; + (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT2] << + XSK_ZYNQMP_EFUSEPS_SECTRL_BIT_SHIFT) | + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT1]; ReadBackSecCtrlBits->PPK0WrLock = DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_WRLK]; ReadBackSecCtrlBits->PPK0Revoke = - DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD]; + (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2] << + XSK_ZYNQMP_EFUSEPS_SECTRL_BIT_SHIFT) | + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1]; ReadBackSecCtrlBits->PPK1WrLock = DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_WRLK]; ReadBackSecCtrlBits->PPK1Revoke = - DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD]; + (DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2] << + XSK_ZYNQMP_EFUSEPS_SECTRL_BIT_SHIFT) | + DataInBits[XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1]; Status = XilSKey_ZynqMp_EfusePs_ReadRow( XSK_ZYNQMP_EFUSEPS_XILINX_SPECIFIC_CTRL_BITS_ROW, @@ -1238,12 +1248,12 @@ static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits( if ((InstancePtr->PrgrmgSecCtrlBits.RSAEnable != 0x00) && (InstancePtr->ReadBackSecCtrlBits.RSAEnable == 0x00)) { Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN, EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT1, EfuseType); if (Status != XST_SUCCESS) { return Status; } Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - (XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN + 1), EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_RSA_EN_BIT2, EfuseType); if (Status != XST_SUCCESS) { return Status; } @@ -1259,12 +1269,12 @@ static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits( if ((InstancePtr->PrgrmgSecCtrlBits.PPK0Revoke != 0x00) && (InstancePtr->ReadBackSecCtrlBits.PPK0Revoke == 0x00)) { Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD, EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT1, EfuseType); if (Status != XST_SUCCESS) { return Status; } Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - (XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD + 1), EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_PPK0_INVLD_BIT2, EfuseType); if (Status != XST_SUCCESS) { return Status; } @@ -1280,12 +1290,12 @@ static inline u32 XilSKey_ZynqMp_EfusePs_Write_SecCtrlBits( if ((InstancePtr->PrgrmgSecCtrlBits.PPK1Revoke != 0x00) && (InstancePtr->ReadBackSecCtrlBits.PPK1Revoke == 0x00)) { Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD, EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT1, EfuseType); if (Status != XST_SUCCESS) { return Status; } Status = XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit(Row, - XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD + 1, EfuseType); + XSK_ZYNQMP_EFUSEPS_SEC_PPK1_INVLD_BIT2, EfuseType); if (Status != XST_SUCCESS) { return Status; }