From 56ea0274dfb422e8a5672d083dcdaeef059a64b4 Mon Sep 17 00:00:00 2001 From: P L Sai Krishna Date: Tue, 20 Oct 2015 18:08:27 +0530 Subject: [PATCH] sdps: Polled for transfer complete for cmd6. This patch does following things: Added polling for transfer complete for cmd6 in case of eMMC and MMC card. Added 2.0 controller version check in case of eMMC to switch for High speed mode in Zynq. Added check for eMMC card, since HS200 mode switching will only support by eMMC. Signed-off-by: P L Sai Krishna Acked-by: Harini Katakam --- XilinxProcessorIPLib/drivers/sdps/src/xsdps.c | 5 +- .../drivers/sdps/src/xsdps_options.c | 49 +++++++++++++++++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c index 2d3d87a3..d1bed796 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps.c @@ -628,7 +628,8 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } - } else if (InstancePtr->CardType == XSDPS_CARD_MMC) { + } else if ((InstancePtr->CardType == XSDPS_CARD_MMC) && + (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) { Status = XSdPs_Change_BusWidth(InstancePtr); if (Status != XST_SUCCESS) { @@ -666,7 +667,7 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } } - } else { + } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){ /* Change bus width to 8-bit */ Status = XSdPs_Change_BusWidth(InstancePtr); if (Status != XST_SUCCESS) { diff --git a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c index 80b33f19..d7a10b0a 100644 --- a/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c +++ b/XilinxProcessorIPLib/drivers/sdps/src/xsdps_options.c @@ -507,6 +507,31 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) Status = XST_FAILURE; goto RETURN_PATH; } + + /* + * Check for transfer complete + */ + do { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET); + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + /* + * Write to clear error bits + */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + Status = XST_FAILURE; + goto RETURN_PATH; + } + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); + + /* + * Write to clear bit + */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + /* Change the clock frequency to 52 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); @@ -523,6 +548,30 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) goto RETURN_PATH; } + /* + * Check for transfer complete + */ + do { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET); + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + /* + * Write to clear error bits + */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + Status = XST_FAILURE; + goto RETURN_PATH; + } + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); + + /* + * Write to clear bit + */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + /* Change the clock frequency to 200 MHz */ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;