| XCresample | |
| XCresample_Config | |
| XHorizontal_Coeffs | |
| XVertical_Coeffs |
-MODIFICATION HISTORY:
-Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 1.00a gaborz 08/04/11 Updated for CRESAMPLE V1.0 2.00a vyc 04/24/12 Updated for CRESAMPLE V2.00.a 2.00a vyc 07/25/12 Switched from Xuint32 to u32 2.00a vyc 10/16/12 Switch order of functions to remove compile warning -
-#include "cresample.h"
-#include "xenv.h"
-
| cresample.c | |||||
| xcresample.c | |
| xcresample.h | |
| xcresample_g.c | |
| xcresample_hw.h | |
| xcresample_intr.c | |
| xcresample_selftest.c | |
| xcresample_sinit.c |
+Here is a list of all class members with links to the classes they belong to: +
+
+ +
+
+Here is a list of all file members with links to the files they belong to: +
+
+Here is a list of all file members with links to the files they belong to: +
+
+ +
+
+ +
+
+
+
+
+
-This header file contains identifiers and register-level driver functions (or macros) that can be used to access the Xilinx Chroma Resampler core instance.
-MODIFICATION HISTORY:
-Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 2.00a vy 04/24/12 Updated for version 2.00.a Converted from xio.h to xil_io.h, translating basic type, MB cache functions, exceptions and assertion to xil_io format. 1.00a vy 10/22/10 Initial version 3.0 adk 19/12/13 Updated as per the New Tcl API's Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +This header file contains identifiers and register-level driver functions (or macros), that can be used to access the Xilinx Chroma Resampler (Cresample) core instance.
+The Chroma Resampler core converts between chroma sub-sampling formats of 4:4:4, 4:2:2,and 4:2:0. There are a total of six conversions available for the three supported sub-sampling formats. Conversion is achieved using a FIR filter approach. Some conversions require filtering in only the horizontal dimension, only the vertical dimension, or both. Interpolation operations are implemented using a two-phase polyphase FIR filter. Decimation operations are implemented using a low-pass FIR filter to suppress chroma aliasing.
+Features of Chroma Resampler core are
+Initialization & Configuration
+The device driver enables higher layer software (e.g., an application) to communicate to the Cresample core.
+XCresample_CfgInitialize() API is used to initialize the Cresample core. The user needs to first call the XCresample_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XCresample_CfgInitialize() API.
+ Interrupts
+The driver provides an interrupt handler XCresample_IntrHandler for handling the interrupt from the Cresample core. The users of this driver have to register this handler with the interrupt system and provide the callback functions by using XCresample_SetCallBack API.
+ Virtual Memory
+This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.
+ Threads
+This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.
+ Asserts
+Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.
+ Building the driver
+The Cresample driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.*
+
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------- -------- ------------------------------------------------------- + 2.00a vy 04/24/12 Updated for version 2.00.a + Converted from xio.h to xil_io.h, translating + basic type, MB cache functions, exceptions and + assertion to xil_io format. + 1.00a vy 10/22/10 Initial version + 3.0 adk 19/12/13 Updated as per the New Tcl API's. + 4.0 adk 03/12/14 Changed the file name cresample.h to xcresample.h. + Macros of register offsets, bit definitions, + ReadReg and WriteReg macros which are the part of + xcresample_hw.h.were moved to xcresample_hw.h. + Removed file inclusion of Xil_io.h.
+
Removed the following functional macros: + CRESAMPLE_Enable, CRESAMPLE_Disable, + CRESAMPLE_RegUpdateEnable, CRESAMPLE_RegUpdateDisable, + CRESAMPLE_Reset, CRESAMPLE_ClearReset, + CRESAMPLe_AutoSyncReset. + Defined the following functional macros: + XCresample_Enable, XCresample_Disable, + XCresample_RegUpdateEnable,XCresample_RegUpdateDisable + XCresample_Reset, XCresample_ClearReset, + XCresample_SyncReset, XCresample_IntrDisable, + XCresample_IntrEnable, XCresample_StatusGetPending + XCresample_IntrGetPending, XCresample_IntrClear. + Declared following structures: + XCresample_Config and XCresample of Chroma Resampler.
+
Defined the following range macros: + XCRE_VSIZE_FIRST, XCRE_VSIZE_LAST, XCRE_HSIZE_FIRST, + XCRE_HSIZE_FIRST, XCRE_HSIZE_LAST, XCRE_PARITY_ODD, + XCRE_PARITY_EVEN, XCRE_COEF_FIRST, XCRE_COEF_LAST, + XCRE_OFFSET_DIFF, XCRE_NUM_OF_PHASES, XCRE_NUM_HCOEFS, + and XCRE_NUM_VCOEFS.
+
Modifications in the file xcresample_hw.h are: + Added the register offsets and bit masks for the + registers and added backward compatibility for macros.
+
Modifications in the file xcresample.c are: + Changed the filename cresample.c to xcresample.c. + The Following functions are removed: + clear_coef_values, configure_444_to_422, + configure_422_to_444, configure_422_to_420, + configure_420_to_422, configure_444_to_420 and + configure_420_to_444. + Implemented the following functions : + StubCallBack, StubErrorCallBack, + XCresample_CfgInitialize, + XCresample_GetVersion, XCresample_EnableDbgByPass, + XCresample_IsDbgByPassEnabled, + XCresample_DisableDbgByPass, + XCresample_SetDbgTestPattern, + XCresample_IsDbgTestPatternEnabled, + XCresample_DisableDbgTestPattern + XCresample_GetDbgFrameCount, + XCresample_GetDbgLineCount, + XCresample_GetDbgPixelCount, + XCresample_SetActiveSize, XCresample_GetActiveSize, + XCresample_SetFieldParity, XCresample_GetFieldParity, + XCresample_SetChromaParity, + XCresample_GetChromaParity + XCresample_SetHCoefs, XCresample_GetHCoefs, + XCresample_SetVCoefs, XCresample_GetVCoefs, + XCresample_Clear_HCoef_Values, and + XCresample_Clear_VCoef_Values.
+
Modifications in the file xcresample_intr.c are: + Implemented XCresample_IntrHandler and + XCresample_SetCallBack functions.
+
Modifications in the file xcresample_selftest.c are: + Implemented XCresample_SelfTest function.
+
Modifications in the file xcresample_sinit.c are: + Implemented XCresample_LookupConfig function.
+
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/struct_x_coeffs-members.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/struct_x_coeffs-members.html new file mode 100644 index 00000000..8fabac02 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/struct_x_coeffs-members.html @@ -0,0 +1,27 @@ + + + +
| HCoeff | XCoeffs | |
| VCoeff | XCoeffs |
#include <xcresample.h>
++
Public Attributes | |
| float | HCoeff [2][24] |
| float | VCoeff [2][8] |
| float XCoeffs::HCoeff[2][24] | +
+ +
| float XCoeffs::VCoeff[2][8] | +
+ +
+
#include <xcresample.h>
++
Public Attributes | |
| XCresample_Config | Config |
| u32 | IsReady |
| u16 | HSize |
| u16 | VSize |
| XCresample_CallBack | ProcStartCallBack |
| void * | ProcStartRef |
| XCresample_CallBack | FrameDoneCallBack |
| void * | FrameDoneRef |
| XCresample_ErrorCallBack | ErrCallBack |
| void * | ErrRef |
| u32 | CoefH [XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS] |
| u32 | CoefV [XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS] |
| u32 XCresample::CoefH[XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS] | +
+Horizontal filter coefficients +
| u32 XCresample::CoefV[XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS] | +
+Vertical filter coefficients +
| XCresample_Config XCresample::Config | +
+Hardware configuration +
| XCresample_ErrorCallBack XCresample::ErrCallBack | +
+Call back for error interrupt +
| void* XCresample::ErrRef | +
+To be passed to the error interrupt callback +
| XCresample_CallBack XCresample::FrameDoneCallBack | +
+Call back for frame done interrupt +
| void* XCresample::FrameDoneRef | +
+To be passed to the frame done interrupt callback +
| u16 XCresample::HSize | +
+Active video horizontal size +
| u32 XCresample::IsReady | +
+Device and the driver instance are initialized +
| XCresample_CallBack XCresample::ProcStartCallBack | +
+Call back for processing start interrupt +
| void* XCresample::ProcStartRef | +
+To be passed to the process start interrupt callback +
| u16 XCresample::VSize | +
+Active video vertical size +
+
#include <xcresample.h>
++
Public Attributes | |
| u16 | DeviceId |
| u32 | BaseAddress |
| u32 | SlaveAxisVideoFormat |
| u32 | MasterAxisVideoFormat |
| u32 | SlaveAxiClkFreqHz |
| u16 | HasIntcIf |
| u16 | HasDebug |
| u32 | MaxColumns |
| u32 | ActiveRows |
| u32 | ActiveColumns |
| u8 | ChromaParity |
| u8 | FieldParity |
| u32 | Interlaced |
| u32 | NumHTaps |
| u32 | NumVTaps |
| u32 | ConvertType |
| u32 | CoefWidth |
| u32 XCresample_Config::ActiveColumns | +
+Active columns +
| u32 XCresample_Config::ActiveRows | +
+Active rows +
| u32 XCresample_Config::BaseAddress | +
+BaseAddress is the physical base address of the device's registers +
| u8 XCresample_Config::ChromaParity | +
+Chroma parity +
| u32 XCresample_Config::CoefWidth | +
+Coefficient width +
| u32 XCresample_Config::ConvertType | +
+Convert type +
| u16 XCresample_Config::DeviceId | +
+DeviceId is the unique ID of the device +
| u8 XCresample_Config::FieldParity | +
+Chroma parity +
| u16 XCresample_Config::HasDebug | +
+Has debug GUI specified +
| u16 XCresample_Config::HasIntcIf | +
+Has interrupt control +
| u32 XCresample_Config::Interlaced | +
+Interlaced value +
| u32 XCresample_Config::MasterAxisVideoFormat | +
+Master axis video format +
| u32 XCresample_Config::MaxColumns | +
+Maximum columns +
| u32 XCresample_Config::NumHTaps | +
+Horizontal taps +
| u32 XCresample_Config::NumVTaps | +
+Vertical taps +
| u32 XCresample_Config::SlaveAxiClkFreqHz | +
+Slave clock frequency +
| u32 XCresample_Config::SlaveAxisVideoFormat | +
+Slave axis video format +
+
| HCoeff | XHorizontal_Coeffs |
#include <xcresample.h>
++
Public Attributes | |
| float | HCoeff [XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS] |
| float XHorizontal_Coeffs::HCoeff[XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS] | +
+Matrix for Horizontal Coefficients +
+
| VCoeff | XVertical_Coeffs |
#include <xcresample.h>
++
Public Attributes | |
| float | VCoeff [XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS] |
| float XVertical_Coeffs::VCoeff[XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS] | +
+Matrix for Vertical Coefficients +
+
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------ -------- ---------------------------------------------------- + 1.00a gaborz 08/04/11 Updated for CRESAMPLE V1.0 + 2.00a vyc 04/24/12 Updated for CRESAMPLE V2.00.a + 2.00a vyc 07/25/12 Switched from Xuu3232 to u32 + 2.00a vyc 10/16/12 Switch order of functions to remove compile warning + 4.0 adk 03/12/14 Changed the filename cresample.c to xcresample.c. + The Following functions are removed: + clear_coef_values, configure_444_to_422, + configure_422_to_444, configure_422_to_420, + configure_420_to_422, configure_444_to_420 and + configure_420_to_444. + Implemented the following functions : + StubCallBack, StubErrorCallBack, + XCresample_CfgInitialize, + XCresample_GetVersion, XCresample_EnableDbgByPass, + XCresample_IsDbgByPassEnabled, + XCresample_DisableDbgByPass, + XCresample_SetDbgTestPattern, + XCresample_IsDbgTestPatternEnabled, + XCresample_DisableDbgTestPattern + XCresample_GetDbgFrameCount, + XCresample_GetDbgLineCount, + XCresample_GetDbgPixelCount, + XCresample_SetActiveSize, XCresample_GetActiveSize, + XCresample_SetFieldParity, XCresample_GetFieldParity, + XCresample_SetChromaParity, + XCresample_GetChromaParity + XCresample_SetHCoefs, XCresample_GetHCoefs, + XCresample_SetVCoefs, XCresample_GetVCoefs, + XCresample_Clear_HCoef_Values, and + XCresample_Clear_VCoef_Values.
+
+
+#include "xcresample.h"
+
| int XCresample_CfgInitialize | +( | +XCresample * | +InstancePtr, | +|
| + | + | XCresample_Config * | +CfgPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function initializes the Cresample core. This function must be called prior to using the Cresample core. Initialization of the Cresample includes setting up the instance data and ensuring the hardware is in a quiescent state.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| CfgPtr | is a reference to a structure containing information about a specific Chroma Resampler driver. | |
| EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead. |
| void XCresample_Clear_HCoef_Values | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function clears all horizontal coefficients of the Chroma Resampler core which are previously set.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_Clear_VCoef_Values | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function clears all vertical coefficients of a the Chroma Resampler which are previously set.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_DisableDbgBypass | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function disables bypass mode of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_DisableDbgTestPattern | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function disables debug test pattern mode in Control register of the Chroma Resampler core, if Debug feature is enabled.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_EnableDbgByPass | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function enables the bypass mode by setting bypass bit of the Control register to switch the core to bypass mode if debug feature is enabled in the core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_EnableDbgTestPattern | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function enables the test-pattern mode if debug feature is enabled by setting test-pattern bit of the Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_GetActiveSize | +( | +XCresample * | +InstancePtr, | +|
| + | + | u16 * | +HSize, | +|
| + | + | u16 * | +VSize | + |
| + | ) | ++ |
+This function gets the number of Active Pixels per Scan line and number of Active Lines per Frame from the Active Size register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| HSize | is a pointer to 16-bit variable in which the number of Active Pixels per Scan Line is returned (Range is 32 to 7680). | |
| VSize | is a pointer to 16-bit variable in which the number of Active Lines per Frame is returned (Range is 32 to 7680). |
| u8 XCresample_GetChromaParity | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the value of chroma parity of the Chroma Resampler core from Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgFrameCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of frames processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgLineCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of lines processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgPixelCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of pixels processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u8 XCresample_GetFieldParity | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the field parity value of the Chroma Resampler core from Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_GetHCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XHorizontal_Coeffs * | +Coeff | + |
| + | ) | ++ |
+This function gets the coefficient values from all the Horizontal Coefficient registers of phase0 and phase1 of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has horizontal coefficients of both phases.(Phase 0 and Phase 1) in which coefficients are updated. Range of coefficient values is [-2, 2). |
| void XCresample_GetVCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XVertical_Coeffs * | +Coeff | + |
| + | ) | ++ |
+This function gets the vertical coefficient values of the Chroma Resampler core from all Vertical Coefficient registers of phase0 and phase1.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XVertical_Coeffs which has vertical coefficients of both phases.(Phase 0 and Phase 1) in which coefficients are updated. Range of coefficient values is [-2, 2). |
| u32 XCresample_GetVersion | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the version of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance. |
| int XCresample_IsDbgByPassEnabled | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the current bypass mode settings from Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| int XCresample_IsDbgTestPatternEnabled | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the test-pattern mode (enabled or not) from Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_SetActiveSize | +( | +XCresample * | +InstancePtr, | +|
| + | + | u16 | +HSize, | +|
| + | + | u16 | +VSize | + |
| + | ) | ++ |
+This function sets the active H/V sizes in the Active Size register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| HSize | specifies the number of Active Pixels per Scan Line that needs to be set (Range is 32 to 7680). | |
| VSize | specifies the number of Active Lines per Frame that needs to be set (Range is 32 to 7680). |
| void XCresample_SetChromaParity | +( | +XCresample * | +InstancePtr, | +|
| + | + | u8 | +ChromaParity | + |
| + | ) | ++ |
+This functions sets the Chroma parity value of the Chroma Resampler core in the Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| ChromaParity | specifies the parity value which needs to be set.(0 or 1).
|
| void XCresample_SetFieldParity | +( | +XCresample * | +InstancePtr, | +|
| + | + | u8 | +FieldParity | + |
| + | ) | ++ |
+This functions sets the field parity value of the Chroma Resampler core in the Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| FieldParity | specifies the parity value which needs to be set.(0 or 1).
|
| void XCresample_SetHCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XHorizontal_Coeffs * | +Coeff, | +|
| + | + | u32 | +Phases | + |
| + | ) | ++ |
+This function sets the horizontal coefficient values of the Chroma Resampler core for phase 0 or phase 1 or both phases.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has horizontal coefficients of both phases (Phase 0 and Phase 1) which needs to be set. Range of coefficient values is [-2, 2). | |
| Phases | specifies number of phases needs to be set.
|
| void XCresample_SetVCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XVertical_Coeffs * | +Coeff, | +|
| + | + | u32 | +Phases | + |
| + | ) | ++ |
+This function sets the vertical coefficient values of the Chroma Resampler for phase 0 or for phase 1 or for both phases.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has vertical coefficients of both phases (Phase 0 and Phase 1) which needs to be set. | |
| Phases | specifies number of phases needs to be set.
|
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample_8h.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample_8h.html new file mode 100644 index 00000000..82803717 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample_8h.html @@ -0,0 +1,1738 @@ + +
+ +
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xcresample_hw.h"
+
Classes | |
| struct | XCresample_Config |
| struct | XCresample |
| struct | XHorizontal_Coeffs |
| struct | XVertical_Coeffs |
Active size ranges | |
| #define | XCRE_ACT_SIZE_FIRST 32 |
| #define | XCRE_ACT_SIZE_LAST 7680 |
Parity valid values | |
| #define | XCRE_PARITY_ODD 1 |
| #define | XCRE_PARITY_EVEN 0 |
Coefficient ranges | |
| #define | XCRE_COEF_FIRST -2.0 |
| #define | XCRE_COEF_LAST 2.0 |
| #define | XCRE_OFFSET_DIFF 4 |
Number of phases | |
| #define | XCRE_NUM_OF_PHASES 2 |
Number of coefficients | |
| #define | XCRE_NUM_HCOEFS 24 |
| #define | XCRE_NUM_VCOEFS 8 |
Interrupt types for setting up callbacks | |
| enum | { XCRE_HANDLER_PROCSTART = 1, +XCRE_HANDLER_FRAMEDONE, +XCRE_HANDLER_ERROR + } |
Defines | |
| #define | XCRESAMPLE_H_ |
| #define | XCresample_Enable(InstancePtr) |
| #define | XCresample_Disable(InstancePtr) |
| #define | XCresample_Start XCresample_Enable |
| #define | XCresample_Stop XCresample_Disable |
| #define | XCresample_RegUpdateEnable(InstancePtr) |
| #define | XCresample_RegUpdateDisable(InstancePtr) |
| #define | XCresample_SyncReset(InstancePtr) |
| #define | XCresample_Reset(InstancePtr) |
| #define | XCresample_IntrEnable(InstancePtr, IntrType) |
| #define | XCresample_IntrDisable(InstancePtr, IntrType) |
| #define | XCresample_StatusGetPending(InstancePtr) |
| #define | XCresample_IntrGetPending(InstancePtr) |
| #define | XCresample_IntrClear(InstancePtr, IntrType) |
Typedefs | |
| typedef void(*) | XCresample_CallBack (void *CallBackRef) |
| typedef void(*) | XCresample_ErrorCallBack (void *CallBackRef, u32 ErrorMask) |
Functions | |
| int | XCresample_CfgInitialize (XCresample *InstancePtr, XCresample_Config *CfgPtr, u32 EffectiveAddr) |
| u32 | XCresample_GetVersion (XCresample *InstancePtr) |
| void | XCresample_EnableDbgByPass (XCresample *InstancePtr) |
| int | XCresample_IsDbgByPassEnabled (XCresample *InstancePtr) |
| void | XCresample_DisableDbgBypass (XCresample *InstancePtr) |
| void | XCresample_EnableDbgTestPattern (XCresample *InstancePtr) |
| int | XCresample_IsDbgTestPatternEnabled (XCresample *InstancePtr) |
| void | XCresample_DisableDbgTestPattern (XCresample *InstancePtr) |
| u32 | XCresample_GetDbgFrameCount (XCresample *InstancePtr) |
| u32 | XCresample_GetDbgLineCount (XCresample *InstancePtr) |
| u32 | XCresample_GetDbgPixelCount (XCresample *InstancePtr) |
| void | XCresample_SetActiveSize (XCresample *InstancePtr, u16 HSize, u16 VSize) |
| void | XCresample_GetActiveSize (XCresample *InstancePtr, u16 *HSize, u16 *VSize) |
| void | XCresample_SetFieldParity (XCresample *InstancePtr, u8 FieldParity) |
| void | XCresample_SetChromaParity (XCresample *InstancePtr, u8 ChromaParity) |
| u8 | XCresample_GetFieldParity (XCresample *InstancePtr) |
| u8 | XCresample_GetChromaParity (XCresample *InstancePtr) |
| void | XCresample_SetHCoefs (XCresample *InstancePtr, XHorizontal_Coeffs *Coeff, u32 Phases) |
| void | XCresample_SetVCoefs (XCresample *InstancePtr, XVertical_Coeffs *Coeff, u32 Phases) |
| void | XCresample_GetHCoefs (XCresample *InstancePtr, XHorizontal_Coeffs *Coeff) |
| void | XCresample_GetVCoefs (XCresample *InstancePtr, XVertical_Coeffs *Coeff) |
| XCresample_Config * | XCresample_LookupConfig (u16 DeviceId) |
| int | XCresample_SelfTest (XCresample *InstancePtr) |
| int | XCresample_SetCallBack (XCresample *InstancePtr, u32 HandlerType, void *CallBackFunc, void *CallBackRef) |
| void | XCresample_IntrHandler (void *InstancePtr) |
| void | XCresample_Clear_HCoef_Values (XCresample *InstancePtr) |
| void | XCresample_Clear_VCoef_Values (XCresample *InstancePtr) |
| #define XCRE_ACT_SIZE_FIRST 32 | +
+Active Size starting value +
| #define XCRE_ACT_SIZE_LAST 7680 | +
+Active Size ending value +
| #define XCRE_COEF_FIRST -2.0 | +
+Coefficient start value +
| #define XCRE_COEF_LAST 2.0 | +
+Coefficient end value +
| #define XCRE_NUM_HCOEFS 24 | +
+Number of horizontal coefficients +
| #define XCRE_NUM_OF_PHASES 2 | +
+Number of phases +
| #define XCRE_NUM_VCOEFS 8 | +
+Number of vertical coefficients +
| #define XCRE_OFFSET_DIFF 4 | +
+Coefficient offset difference +
| #define XCRE_PARITY_EVEN 0 | +
+For even (or bottom) field it is 0 +
| #define XCRE_PARITY_ODD 1 | +
+For odd (or top) field it is 1 +
| #define XCresample_Disable | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) & (~(XCRE_CTL_SW_EN_MASK)))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_Enable | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_SW_EN_MASK))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCRESAMPLE_H_ | +
+Prevent circular inclusions by using protection macros +
| #define XCresample_IntrClear | +( | +InstancePtr, | |||
| + | + | IntrType | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS_OFFSET), \ + ((IntrType) & ((u32)(XCRE_IXR_ALLINTR_MASK)))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. | |
| IntrType | is the pending interrupts to clear/acknowledge. Use OR'ing of XCRE_IXR_*_MASK constants defined in xcresample_hw.h to create this parameter value. |
| #define XCresample_IntrDisable | +( | +InstancePtr, | |||
| + | + | IntrType | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET))) \ + & ((~(IntrType)) & (XCRE_IXR_ALLINTR_MASK)))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. | |
| IntrType | is the type of the interrupts to disable. Use OR'ing of XCRE_IXR_*_MASK constants defined in xcresample_hw.h to create this parameter value. |
| #define XCresample_IntrEnable | +( | +InstancePtr, | |||
| + | + | IntrType | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET), \ + (((IntrType) & (XCRE_IXR_ALLINTR_MASK)) | \ + (XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET))))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. | |
| IntrType | is the type of the interrupts to enable. Use OR'ing of XCRE_IXR_*_MASK constants defined in xcresample_hw.h to create this parameter value. |
| #define XCresample_IntrGetPending | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET)) & \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS_OFFSET))) & ((u32)(XCRE_IXR_ALLINTR_MASK))) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_RegUpdateDisable | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) & (u32)(~(XCRE_CTL_RUE_MASK)))) +
+This macro only works when the Chroma Resampler core is enabled.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_RegUpdateEnable | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_RUE_MASK))) +
+This macro only works when the Chroma Resampler core is enabled.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_Reset | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), (XCRE_CTL_RESET_MASK)) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_Start XCresample_Enable | +
+This macro enables/starts the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_StatusGetPending | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS)) & (XCRE_IXR_ALLINTR_MASK) +
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_Stop XCresample_Disable | +
+This macro disables/stops the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| #define XCresample_SyncReset | +( | +InstancePtr | ++ | ) | ++ |
+Value:
XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), (XCRE_CTL_AUTORESET_MASK)) +
+On the next raising edge of SOF following a call to XCresample_SyncReset(), all of the core's configuration registers and outputs will be reset, then the reset flag will be immediately released, allowing the core to immediately resume default operation.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
+
| typedef void(*) XCresample_CallBack(void *CallBackRef) | +
+Callback type for all interrupts except error interrupt.
+
| CallBackRef | is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. |
| typedef void(*) XCresample_ErrorCallBack(void *CallBackRef, u32 ErrorMask) | +
+Callback type for Error interrupt.
+
| CallBackRef | is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. | |
| ErrorMask | is a bit mask indicating the cause of the error. Its value equals 'OR'ing one or more XCRE_IXR_* values defined in xcresample_hw.h |
+
| anonymous enum | +
+These constants specify different types of handler and used to differentiate interrupt requests from core.
+ ++
| int XCresample_CfgInitialize | +( | +XCresample * | +InstancePtr, | +|
| + | + | XCresample_Config * | +CfgPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function initializes the Cresample core. This function must be called prior to using the Cresample core. Initialization of the Cresample includes setting up the instance data and ensuring the hardware is in a quiescent state.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| CfgPtr | is a reference to a structure containing information about a specific Chroma Resampler driver. | |
| EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead. |
| void XCresample_Clear_HCoef_Values | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function clears all horizontal coefficients of the Chroma Resampler core which are previously set.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_Clear_VCoef_Values | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function clears all vertical coefficients of a the Chroma Resampler which are previously set.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_DisableDbgBypass | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function disables bypass mode of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_DisableDbgTestPattern | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function disables debug test pattern mode in Control register of the Chroma Resampler core, if Debug feature is enabled.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_EnableDbgByPass | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function enables the bypass mode by setting bypass bit of the Control register to switch the core to bypass mode if debug feature is enabled in the core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_EnableDbgTestPattern | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function enables the test-pattern mode if debug feature is enabled by setting test-pattern bit of the Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| void XCresample_GetActiveSize | +( | +XCresample * | +InstancePtr, | +|
| + | + | u16 * | +HSize, | +|
| + | + | u16 * | +VSize | + |
| + | ) | ++ |
+This function gets the number of Active Pixels per Scan line and number of Active Lines per Frame from the Active Size register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| HSize | is a pointer to 16-bit variable in which the number of Active Pixels per Scan Line is returned (Range is 32 to 7680). | |
| VSize | is a pointer to 16-bit variable in which the number of Active Lines per Frame is returned (Range is 32 to 7680). |
| u8 XCresample_GetChromaParity | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the value of chroma parity of the Chroma Resampler core from Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgFrameCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of frames processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgLineCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of lines processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u32 XCresample_GetDbgPixelCount | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the number of pixels processed since power-up or last time the core is reset.
+
| InstancePtr | is a pointer to the XCresample instance. |
| u8 XCresample_GetFieldParity | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the field parity value of the Chroma Resampler core from Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_GetHCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XHorizontal_Coeffs * | +Coeff | + |
| + | ) | ++ |
+This function gets the coefficient values from all the Horizontal Coefficient registers of phase0 and phase1 of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has horizontal coefficients of both phases.(Phase 0 and Phase 1) in which coefficients are updated. Range of coefficient values is [-2, 2). |
| void XCresample_GetVCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XVertical_Coeffs * | +Coeff | + |
| + | ) | ++ |
+This function gets the vertical coefficient values of the Chroma Resampler core from all Vertical Coefficient registers of phase0 and phase1.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XVertical_Coeffs which has vertical coefficients of both phases.(Phase 0 and Phase 1) in which coefficients are updated. Range of coefficient values is [-2, 2). |
| u32 XCresample_GetVersion | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the version of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_IntrHandler | +( | +void * | +InstancePtr | +) | ++ |
+This function is the interrupt handler for the Chroma Resampler driver.
+This handler reads the pending interrupt from the STATUS register, determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in IRQ_ENABLE register, and finally clears the interrupts.
+The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using Xcresample_SetCallBack() during initialization phase.
+
| InstancePtr | is a pointer to the XCresample instance that just interrupted. |
| int XCresample_IsDbgByPassEnabled | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the current bypass mode settings from Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| int XCresample_IsDbgTestPatternEnabled | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function returns the test-pattern mode (enabled or not) from Control register of the Chroma Resampler core.
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. |
| XCresample_Config* XCresample_LookupConfig | +( | +u16 | +DeviceId | +) | ++ |
+This function returns a reference to an XCresample_Config structure based on the unique device id, DeviceId. The return value will refer to an entry in the device configuration table defined in the xcresample_g.c file.
+
| DeviceId | is the unique device ID of the device for the lookup operation. |
| int XCresample_SelfTest | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function reads version register of Chroma Resampler core and compares with zero as part of self test.
+
| InstancePtr | is a pointer to the XCresample instance. |
| void XCresample_SetActiveSize | +( | +XCresample * | +InstancePtr, | +|
| + | + | u16 | +HSize, | +|
| + | + | u16 | +VSize | + |
| + | ) | ++ |
+This function sets the active H/V sizes in the Active Size register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| HSize | specifies the number of Active Pixels per Scan Line that needs to be set (Range is 32 to 7680). | |
| VSize | specifies the number of Active Lines per Frame that needs to be set (Range is 32 to 7680). |
| int XCresample_SetCallBack | +( | +XCresample * | +InstancePtr, | +|
| + | + | u32 | +HandlerType, | +|
| + | + | void * | +CallBackFunc, | +|
| + | + | void * | +CallBackRef | + |
| + | ) | ++ |
+This routine installs an asynchronous callback function for the given HandlerType:
+
+ HandlerType Callback Function Type + ----------------------- -------------------------------------------------- + XCRE_HANDLER_FRAMEDONE FrameDoneCallBack + XCRE_HANDLER_PROCSTART ProcStartCallBack + XCRE_HANDLER_ERROR ErrCallBack
+
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. | |
| HandlerType | specifies which callback is to be attached. | |
| CallBackFunc | is the address of the callback function. | |
| CallBackRef | is a user data item that will be passed to the callback function when it is invoked. |
| void XCresample_SetChromaParity | +( | +XCresample * | +InstancePtr, | +|
| + | + | u8 | +ChromaParity | + |
| + | ) | ++ |
+This functions sets the Chroma parity value of the Chroma Resampler core in the Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| ChromaParity | specifies the parity value which needs to be set.(0 or 1).
|
| void XCresample_SetFieldParity | +( | +XCresample * | +InstancePtr, | +|
| + | + | u8 | +FieldParity | + |
| + | ) | ++ |
+This functions sets the field parity value of the Chroma Resampler core in the Encoding register.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| FieldParity | specifies the parity value which needs to be set.(0 or 1).
|
| void XCresample_SetHCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XHorizontal_Coeffs * | +Coeff, | +|
| + | + | u32 | +Phases | + |
| + | ) | ++ |
+This function sets the horizontal coefficient values of the Chroma Resampler core for phase 0 or phase 1 or both phases.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has horizontal coefficients of both phases (Phase 0 and Phase 1) which needs to be set. Range of coefficient values is [-2, 2). | |
| Phases | specifies number of phases needs to be set.
|
| void XCresample_SetVCoefs | +( | +XCresample * | +InstancePtr, | +|
| + | + | XVertical_Coeffs * | +Coeff, | +|
| + | + | u32 | +Phases | + |
| + | ) | ++ |
+This function sets the vertical coefficient values of the Chroma Resampler for phase 0 or for phase 1 or for both phases.
+
| InstancePtr | is a pointer to the XCresample instance. | |
| Coeff | is a pointer to the structure XHorizontal_Coeffs which has vertical coefficients of both phases (Phase 0 and Phase 1) which needs to be set. | |
| Phases | specifies number of phases needs to be set.
|
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__g_8c.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__g_8c.html new file mode 100644 index 00000000..1ba2e909 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__g_8c.html @@ -0,0 +1,50 @@ + +
+ +
+#include "xparameters.h"
+#include "xcresample.h"
+
Variables | |
| XCresample_Config | XCresample_ConfigTable [] |
| XCresample_Config XCresample_ConfigTable[] | +
+ +
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__hw_8h.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__hw_8h.html new file mode 100644 index 00000000..2d452734 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__hw_8h.html @@ -0,0 +1,3526 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------- -------- ------------------------------------------------------- + 4.0 adk 03/12/14 First release + Added the register offsets and bit masks for the + registers and added backward compatibility for macros.
+
+
+#include "xil_io.h"
+
register offsets | |
| #define | XCRE_CONTROL_OFFSET 0x0000 |
| #define | XCRE_STATUS_OFFSET 0x0004 |
| #define | XCRE_ERROR_OFFSET 0x0008 |
| #define | XCRE_IRQ_EN_OFFSET 0x000C |
| #define | XCRE_VERSION_OFFSET 0x0010 |
| #define | XCRE_SYSDEBUG0_OFFSET 0x0014 |
| #define | XCRE_SYSDEBUG1_OFFSET 0x0018 |
| #define | XCRE_SYSDEBUG2_OFFSET 0x001C |
Control register bit masks | |
| #define | XCRE_CTL_SW_EN_MASK 0x00000001 |
| #define | XCRE_CTL_RUE_MASK 0x00000002 |
| #define | XCRE_CTL_BPE_MASK 0x00000010 |
| #define | XCRE_CTL_TPE_MASK 0x00000020 |
| #define | XCRE_CTL_AUTORESET_MASK 0x40000000 |
| #define | XCRE_CTL_RESET_MASK 0x80000000 |
Interrupt register bit masks. It is applicable for | |
| Status and IRQ_ENABLE Registers | |
| #define | XCRE_IXR_PROCS_STARTED_MASK 0x00000001 |
| #define | XCRE_IXR_EOF_MASK 0x00000002 |
| #define | XCRE_IXR_SE_MASK 0x00010000 |
| #define | XCRE_IXR_ALLINTR_MASK 0x00010003U |
Error register bit masks | |
| #define | XCRE_ERR_EOL_EARLY_MASK 0x00000001 |
| #define | XCRE_ERR_EOL_LATE_MASK 0x00000002 |
| #define | XCRE_ERR_SOF_EARLY_MASK 0x00000004 |
| #define | XCRE_ERR_SOF_LATE_MASK 0x00000008 |
Version register bit masks and shifts | |
| #define | XCRE_VER_REV_NUM_MASK 0x000000FF |
| #define | XCRE_VER_PID_MASK 0x00000F00 |
| #define | XCRE_VER_REV_MASK 0x0000F000 |
| #define | XCRE_VER_MINOR_MASK 0x00FF0000 |
| #define | XCRE_VER_MAJOR_MASK 0xFF000000 |
| #define | XCRE_VER_INTERNAL_SHIFT 0x00000008 |
| #define | XCRE_VER_REV_SHIFT 0x0000000C |
| #define | XCRE_VER_MINOR_SHIFT 0x00000010 |
| #define | XCRE_VER_MAJOR_SHIFT 0x00000018 |
Active size register bit masks and shifts | |
| #define | XCRE_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF |
| #define | XCRE_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 |
| #define | XCRE_ACTSIZE_NUM_LINE_SHIFT 16 |
Encoding register bit masks and shifts | |
| #define | XCRE_ENCODING_FIELD_MASK 0x00000080 |
| #define | XCRE_ENCODING_CHROMA_MASK 0x00000100 |
| #define | XCRE_ENCODING_FIELD_SHIFT 7 |
| #define | XCRE_ENCODING_CHROMA_SHIFT 8 |
Coefficient bit mask and shift | |
| #define | XCRE_COEFF_FRAC_MASK 0x00003FFF |
| #define | XCRE_COEF_DECI_MASK 0x00004000 |
| #define | XCRE_COEF_SIGN_MASK 0x00008000 |
| #define | XCRE_COEFF_MASK 0x0000FFFF |
| #define | XCRE_COEFF_SHIFT 14 |
| #define | XCRE_COEFF_SIGN_SHIFT 16 |
General purpose macros | |
| #define | XCRE_SIGN_MUL -1 |
| #define | XCRE_SIGNBIT_MASK 0x10000000 |
| #define | XCRE_MAX_VALUE 0xFFFFFFFF |
backward compatibility macros | |
| To support backward compatibility following macro definition are re-defined. | |
| #define | CRESAMPLE_CONTROL XCRE_CONTROL_OFFSET |
| #define | CRESAMPLE_STATUS XCRE_STATUS_OFFSET |
| #define | CRESAMPLE_ERROR XCRE_ERROR_OFFSET |
| #define | CRESAMPLE_IRQ_ENABLE XCRE_IRQ_EN_OFFSET |
| #define | CRESAMPLE_VERSION XCRE_VERSION_OFFSET |
| #define | CRESAMPLE_SYSDEBUG0 XCRE_SYSDEBUG0_OFFSET |
| #define | CRESAMPLE_SYSDEBUG1 XCRE_SYSDEBUG1_OFFSET |
| #define | CRESAMPLE_SYSDEBUG2 XCRE_SYSDEBUG2_OFFSET |
| #define | CRESAMPLE_ACTIVE_SIZE XCRE_ACTIVE_SIZE_OFFSET |
| #define | CRESAMPLE_ENCODING XCRE_ENCODING_OFFSET |
| #define | CRESAMPLE_COEF00_HPHASE0 XCRE_COEF00_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF01_HPHASE0 XCRE_COEF01_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF02_HPHASE0 XCRE_COEF02_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF03_HPHASE0 XCRE_COEF03_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF04_HPHASE0 XCRE_COEF04_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF05_HPHASE0 XCRE_COEF05_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF06_HPHASE0 XCRE_COEF06_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF07_HPHASE0 XCRE_COEF07_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF08_HPHASE0 XCRE_COEF08_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF09_HPHASE0 XCRE_COEF09_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF10_HPHASE0 XCRE_COEF10_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF11_HPHASE0 XCRE_COEF11_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF12_HPHASE0 XCRE_COEF12_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF13_HPHASE0 XCRE_COEF13_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF14_HPHASE0 XCRE_COEF14_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF15_HPHASE0 XCRE_COEF15_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF16_HPHASE0 XCRE_COEF16_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF17_HPHASE0 XCRE_COEF17_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF18_HPHASE0 XCRE_COEF18_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF19_HPHASE0 XCRE_COEF19_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF20_HPHASE0 XCRE_COEF20_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF21_HPHASE0 XCRE_COEF21_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF22_HPHASE0 XCRE_COEF22_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF23_HPHASE0 XCRE_COEF23_HPHASE0_OFFSET |
| #define | CRESAMPLE_COEF00_HPHASE1 XCRE_COEF00_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF01_HPHASE1 XCRE_COEF01_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF02_HPHASE1 XCRE_COEF02_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF03_HPHASE1 XCRE_COEF03_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF04_HPHASE1 XCRE_COEF04_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF05_HPHASE1 XCRE_COEF05_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF06_HPHASE1 XCRE_COEF06_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF07_HPHASE1 XCRE_COEF07_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF08_HPHASE1 XCRE_COEF08_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF09_HPHASE1 XCRE_COEF09_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF10_HPHASE1 XCRE_COEF10_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF11_HPHASE1 XCRE_COEF11_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF12_HPHASE1 XCRE_COEF12_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF13_HPHASE1 XCRE_COEF13_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF14_HPHASE1 XCRE_COEF14_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF15_HPHASE1 XCRE_COEF15_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF16_HPHASE1 XCRE_COEF16_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF17_HPHASE1 XCRE_COEF17_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF18_HPHASE1 XCRE_COEF18_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF19_HPHASE1 XCRE_COEF19_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF20_HPHASE1 XCRE_COEF20_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF21_HPHASE1 XCRE_COEF21_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF22_HPHASE1 XCRE_COEF22_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF23_HPHASE1 XCRE_COEF23_HPHASE1_OFFSET |
| #define | CRESAMPLE_COEF00_VPHASE0 XCRE_COEF00_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF01_VPHASE0 XCRE_COEF01_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF02_VPHASE0 XCRE_COEF02_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF03_VPHASE0 XCRE_COEF03_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF04_VPHASE0 XCRE_COEF04_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF05_VPHASE0 XCRE_COEF05_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF06_VPHASE0 XCRE_COEF06_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF07_VPHASE0 XCRE_COEF07_VPHASE0_OFFSET |
| #define | CRESAMPLE_COEF00_VPHASE1 XCRE_COEF00_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF01_VPHASE1 XCRE_COEF01_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF02_VPHASE1 XCRE_COEF02_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF03_VPHASE1 XCRE_COEF03_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF04_VPHASE1 XCRE_COEF04_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF05_VPHASE1 XCRE_COEF05_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF06_VPHASE1 XCRE_COEF06_VPHASE1_OFFSET |
| #define | CRESAMPLE_COEF07_VPHASE1 XCRE_COEF07_VPHASE1_OFFSET |
| #define | CRESAMPLE_CTL_EN_MASK XCRE_CTL_SW_EN_MASK |
| #define | CRESAMPLE_CTL_RU_MASK XCRE_CTL_RUE_MASK |
| #define | CRESAMPLE_CTL_AUTORESET XCRE_CTL_AUTORESET_MASK |
| #define | CRESAMPLE_CTL_RESET XCRE_CTL_RESET_MASK |
| #define | CRESAMPLE_In32 XCresample_In32 |
| #define | CRESAMPLE_Out32 XCresample_Out32 |
| #define | CRESAMPLE_ReadReg XCresample_ReadReg |
| #define | CRESAMPLE_WriteReg XCresample_WriteReg |
Interrupt registers | |
| #define | XCRE_ISR_OFFSET XCRE_STATUS_OFFSET |
| #define | XCRE_IER_OFFSET XCRE_IRQ_EN_OFFSET |
Defines | |
| #define | XCRESAMPLE_HW_H_ |
| #define | XCRE_ACTIVE_SIZE_OFFSET 0x0020 |
| #define | XCRE_ENCODING_OFFSET 0x0028 |
| #define | XCRE_COEF00_HPHASE0_OFFSET 0x0100 |
| #define | XCRE_COEF01_HPHASE0_OFFSET 0x0104 |
| #define | XCRE_COEF02_HPHASE0_OFFSET 0x0108 |
| #define | XCRE_COEF03_HPHASE0_OFFSET 0x010C |
| #define | XCRE_COEF04_HPHASE0_OFFSET 0x0110 |
| #define | XCRE_COEF05_HPHASE0_OFFSET 0x0114 |
| #define | XCRE_COEF06_HPHASE0_OFFSET 0x0118 |
| #define | XCRE_COEF07_HPHASE0_OFFSET 0x011C |
| #define | XCRE_COEF08_HPHASE0_OFFSET 0x0120 |
| #define | XCRE_COEF09_HPHASE0_OFFSET 0x0124 |
| #define | XCRE_COEF10_HPHASE0_OFFSET 0x0128 |
| #define | XCRE_COEF11_HPHASE0_OFFSET 0x012C |
| #define | XCRE_COEF12_HPHASE0_OFFSET 0x0130 |
| #define | XCRE_COEF13_HPHASE0_OFFSET 0x0134 |
| #define | XCRE_COEF14_HPHASE0_OFFSET 0x0138 |
| #define | XCRE_COEF15_HPHASE0_OFFSET 0x013C |
| #define | XCRE_COEF16_HPHASE0_OFFSET 0x0140 |
| #define | XCRE_COEF17_HPHASE0_OFFSET 0x0144 |
| #define | XCRE_COEF18_HPHASE0_OFFSET 0x0148 |
| #define | XCRE_COEF19_HPHASE0_OFFSET 0x014C |
| #define | XCRE_COEF20_HPHASE0_OFFSET 0x0150 |
| #define | XCRE_COEF21_HPHASE0_OFFSET 0x0154 |
| #define | XCRE_COEF22_HPHASE0_OFFSET 0x0158 |
| #define | XCRE_COEF23_HPHASE0_OFFSET 0x015C |
| #define | XCRE_COEF00_HPHASE1_OFFSET 0x0160 |
| #define | XCRE_COEF01_HPHASE1_OFFSET 0x0164 |
| #define | XCRE_COEF02_HPHASE1_OFFSET 0x0168 |
| #define | XCRE_COEF03_HPHASE1_OFFSET 0x016C |
| #define | XCRE_COEF04_HPHASE1_OFFSET 0x0170 |
| #define | XCRE_COEF05_HPHASE1_OFFSET 0x0174 |
| #define | XCRE_COEF06_HPHASE1_OFFSET 0x0178 |
| #define | XCRE_COEF07_HPHASE1_OFFSET 0x017C |
| #define | XCRE_COEF08_HPHASE1_OFFSET 0x0180 |
| #define | XCRE_COEF09_HPHASE1_OFFSET 0x0184 |
| #define | XCRE_COEF10_HPHASE1_OFFSET 0x0188 |
| #define | XCRE_COEF11_HPHASE1_OFFSET 0x018C |
| #define | XCRE_COEF12_HPHASE1_OFFSET 0x0190 |
| #define | XCRE_COEF13_HPHASE1_OFFSET 0x0194 |
| #define | XCRE_COEF14_HPHASE1_OFFSET 0x0198 |
| #define | XCRE_COEF15_HPHASE1_OFFSET 0x019C |
| #define | XCRE_COEF16_HPHASE1_OFFSET 0x01A0 |
| #define | XCRE_COEF17_HPHASE1_OFFSET 0x01A4 |
| #define | XCRE_COEF18_HPHASE1_OFFSET 0x01A8 |
| #define | XCRE_COEF19_HPHASE1_OFFSET 0x01AC |
| #define | XCRE_COEF20_HPHASE1_OFFSET 0x01B0 |
| #define | XCRE_COEF21_HPHASE1_OFFSET 0x01B4 |
| #define | XCRE_COEF22_HPHASE1_OFFSET 0x01B8 |
| #define | XCRE_COEF23_HPHASE1_OFFSET 0x01BC |
| #define | XCRE_COEF00_VPHASE0_OFFSET 0x01C0 |
| #define | XCRE_COEF01_VPHASE0_OFFSET 0x01C4 |
| #define | XCRE_COEF02_VPHASE0_OFFSET 0x01C8 |
| #define | XCRE_COEF03_VPHASE0_OFFSET 0x01CC |
| #define | XCRE_COEF04_VPHASE0_OFFSET 0x01D0 |
| #define | XCRE_COEF05_VPHASE0_OFFSET 0x01D4 |
| #define | XCRE_COEF06_VPHASE0_OFFSET 0x01D8 |
| #define | XCRE_COEF07_VPHASE0_OFFSET 0x01DC |
| #define | XCRE_COEF00_VPHASE1_OFFSET 0x01E0 |
| #define | XCRE_COEF01_VPHASE1_OFFSET 0x01E4 |
| #define | XCRE_COEF02_VPHASE1_OFFSET 0x01E8 |
| #define | XCRE_COEF03_VPHASE1_OFFSET 0x01EC |
| #define | XCRE_COEF04_VPHASE1_OFFSET 0x01F0 |
| #define | XCRE_COEF05_VPHASE1_OFFSET 0x01F4 |
| #define | XCRE_COEF06_VPHASE1_OFFSET 0x01F8 |
| #define | XCRE_COEF07_VPHASE1_OFFSET 0x01FC |
| #define | XCresample_In32 Xil_In32 |
| #define | XCresample_Out32 Xil_Out32 |
| #define | XCresample_ReadReg(BaseAddress, RegOffset) XCresample_In32((BaseAddress) + (u32)(RegOffset)) |
| #define | XCresample_WriteReg(BaseAddress, RegOffset, Data) XCresample_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) |
| #define CRESAMPLE_ACTIVE_SIZE XCRE_ACTIVE_SIZE_OFFSET | +
+ +
| #define CRESAMPLE_COEF00_HPHASE0 XCRE_COEF00_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF00_HPHASE1 XCRE_COEF00_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF00_VPHASE0 XCRE_COEF00_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF00_VPHASE1 XCRE_COEF00_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF01_HPHASE0 XCRE_COEF01_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF01_HPHASE1 XCRE_COEF01_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF01_VPHASE0 XCRE_COEF01_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF01_VPHASE1 XCRE_COEF01_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF02_HPHASE0 XCRE_COEF02_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF02_HPHASE1 XCRE_COEF02_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF02_VPHASE0 XCRE_COEF02_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF02_VPHASE1 XCRE_COEF02_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF03_HPHASE0 XCRE_COEF03_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF03_HPHASE1 XCRE_COEF03_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF03_VPHASE0 XCRE_COEF03_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF03_VPHASE1 XCRE_COEF03_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF04_HPHASE0 XCRE_COEF04_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF04_HPHASE1 XCRE_COEF04_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF04_VPHASE0 XCRE_COEF04_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF04_VPHASE1 XCRE_COEF04_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF05_HPHASE0 XCRE_COEF05_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF05_HPHASE1 XCRE_COEF05_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF05_VPHASE0 XCRE_COEF05_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF05_VPHASE1 XCRE_COEF05_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF06_HPHASE0 XCRE_COEF06_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF06_HPHASE1 XCRE_COEF06_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF06_VPHASE0 XCRE_COEF06_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF06_VPHASE1 XCRE_COEF06_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF07_HPHASE0 XCRE_COEF07_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF07_HPHASE1 XCRE_COEF07_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF07_VPHASE0 XCRE_COEF07_VPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF07_VPHASE1 XCRE_COEF07_VPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF08_HPHASE0 XCRE_COEF08_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF08_HPHASE1 XCRE_COEF08_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF09_HPHASE0 XCRE_COEF09_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF09_HPHASE1 XCRE_COEF09_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF10_HPHASE0 XCRE_COEF10_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF10_HPHASE1 XCRE_COEF10_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF11_HPHASE0 XCRE_COEF11_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF11_HPHASE1 XCRE_COEF11_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF12_HPHASE0 XCRE_COEF12_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF12_HPHASE1 XCRE_COEF12_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF13_HPHASE0 XCRE_COEF13_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF13_HPHASE1 XCRE_COEF13_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF14_HPHASE0 XCRE_COEF14_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF14_HPHASE1 XCRE_COEF14_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF15_HPHASE0 XCRE_COEF15_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF15_HPHASE1 XCRE_COEF15_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF16_HPHASE0 XCRE_COEF16_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF16_HPHASE1 XCRE_COEF16_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF17_HPHASE0 XCRE_COEF17_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF17_HPHASE1 XCRE_COEF17_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF18_HPHASE0 XCRE_COEF18_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF18_HPHASE1 XCRE_COEF18_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF19_HPHASE0 XCRE_COEF19_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF19_HPHASE1 XCRE_COEF19_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF20_HPHASE0 XCRE_COEF20_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF20_HPHASE1 XCRE_COEF20_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF21_HPHASE0 XCRE_COEF21_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF21_HPHASE1 XCRE_COEF21_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF22_HPHASE0 XCRE_COEF22_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF22_HPHASE1 XCRE_COEF22_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_COEF23_HPHASE0 XCRE_COEF23_HPHASE0_OFFSET | +
+ +
| #define CRESAMPLE_COEF23_HPHASE1 XCRE_COEF23_HPHASE1_OFFSET | +
+ +
| #define CRESAMPLE_CONTROL XCRE_CONTROL_OFFSET | +
+ +
| #define CRESAMPLE_CTL_AUTORESET XCRE_CTL_AUTORESET_MASK | +
+ +
| #define CRESAMPLE_CTL_EN_MASK XCRE_CTL_SW_EN_MASK | +
+ +
| #define CRESAMPLE_CTL_RESET XCRE_CTL_RESET_MASK | +
+ +
| #define CRESAMPLE_CTL_RU_MASK XCRE_CTL_RUE_MASK | +
+ +
| #define CRESAMPLE_ENCODING XCRE_ENCODING_OFFSET | +
+ +
| #define CRESAMPLE_ERROR XCRE_ERROR_OFFSET | +
+ +
| #define CRESAMPLE_In32 XCresample_In32 | +
+ +
| #define CRESAMPLE_IRQ_ENABLE XCRE_IRQ_EN_OFFSET | +
+ +
| #define CRESAMPLE_Out32 XCresample_Out32 | +
+ +
| #define CRESAMPLE_ReadReg XCresample_ReadReg | +
+ +
| #define CRESAMPLE_STATUS XCRE_STATUS_OFFSET | +
+ +
| #define CRESAMPLE_SYSDEBUG0 XCRE_SYSDEBUG0_OFFSET | +
+ +
| #define CRESAMPLE_SYSDEBUG1 XCRE_SYSDEBUG1_OFFSET | +
+ +
| #define CRESAMPLE_SYSDEBUG2 XCRE_SYSDEBUG2_OFFSET | +
+ +
| #define CRESAMPLE_VERSION XCRE_VERSION_OFFSET | +
+ +
| #define CRESAMPLE_WriteReg XCresample_WriteReg | +
+ +
| #define XCRE_ACTIVE_SIZE_OFFSET 0x0020 | +
+Horizontal and vertical active frame size +
| #define XCRE_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 | +
+Number of Active lines per frame (Vertical) mask +
| #define XCRE_ACTSIZE_NUM_LINE_SHIFT 16 | +
+Shift for number of lines +
| #define XCRE_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF | +
+Number of Active pixels per scan line (horizontal) mask +
| #define XCRE_COEF00_HPHASE0_OFFSET 0x0100 | +
+Coefficient 00 of horizontal phase 0 filter +
| #define XCRE_COEF00_HPHASE1_OFFSET 0x0160 | +
+Coefficient 00 of horizontal phase 1 filter +
| #define XCRE_COEF00_VPHASE0_OFFSET 0x01C0 | +
+Coefficient 00 of vertical phase 0 filter +
| #define XCRE_COEF00_VPHASE1_OFFSET 0x01E0 | +
+Coefficient 00 of vertical phase 1 filter +
| #define XCRE_COEF01_HPHASE0_OFFSET 0x0104 | +
+Coefficient 01 of horizontal phase 0 filter +
| #define XCRE_COEF01_HPHASE1_OFFSET 0x0164 | +
+Coefficient 01 of horizontal phase 1 filter +
| #define XCRE_COEF01_VPHASE0_OFFSET 0x01C4 | +
+Coefficient 01 of vertical phase 0 filter +
| #define XCRE_COEF01_VPHASE1_OFFSET 0x01E4 | +
+Coefficient 01 of vertical phase 1 filter +
| #define XCRE_COEF02_HPHASE0_OFFSET 0x0108 | +
+Coefficient 02 of horizontal phase 0 filter +
| #define XCRE_COEF02_HPHASE1_OFFSET 0x0168 | +
+Coefficient 02 of horizontal phase 1 filter +
| #define XCRE_COEF02_VPHASE0_OFFSET 0x01C8 | +
+Coefficient 02 of vertical phase 0 filter +
| #define XCRE_COEF02_VPHASE1_OFFSET 0x01E8 | +
+Coefficient 02 of vertical phase 1 filter +
| #define XCRE_COEF03_HPHASE0_OFFSET 0x010C | +
+Coefficient 03 of horizontal phase 0 filter +
| #define XCRE_COEF03_HPHASE1_OFFSET 0x016C | +
+Coefficient 03 of horizontal phase 1 filter +
| #define XCRE_COEF03_VPHASE0_OFFSET 0x01CC | +
+Coefficient 03 of vertical phase 0 filter +
| #define XCRE_COEF03_VPHASE1_OFFSET 0x01EC | +
+Coefficient 03 of vertical phase 1 filter +
| #define XCRE_COEF04_HPHASE0_OFFSET 0x0110 | +
+Coefficient 04 of horizontal phase 0 filter +
| #define XCRE_COEF04_HPHASE1_OFFSET 0x0170 | +
+Coefficient 04 of horizontal phase 1 filter +
| #define XCRE_COEF04_VPHASE0_OFFSET 0x01D0 | +
+Coefficient 04 of vertical phase 0 filter +
| #define XCRE_COEF04_VPHASE1_OFFSET 0x01F0 | +
+Coefficient 04 of vertical phase 1 filter +
| #define XCRE_COEF05_HPHASE0_OFFSET 0x0114 | +
+Coefficient 05 of horizontal phase 0 filter +
| #define XCRE_COEF05_HPHASE1_OFFSET 0x0174 | +
+Coefficient 05 of horizontal phase 1 filter +
| #define XCRE_COEF05_VPHASE0_OFFSET 0x01D4 | +
+Coefficient 05 of vertical phase 0 filter +
| #define XCRE_COEF05_VPHASE1_OFFSET 0x01F4 | +
+Coefficient 05 of vertical phase 1 filter +
| #define XCRE_COEF06_HPHASE0_OFFSET 0x0118 | +
+Coefficient 06 of horizontal phase 0 filter +
| #define XCRE_COEF06_HPHASE1_OFFSET 0x0178 | +
+Coefficient 06 of horizontal phase 1 filter +
| #define XCRE_COEF06_VPHASE0_OFFSET 0x01D8 | +
+Coefficient 06 of vertical phase 0 filter +
| #define XCRE_COEF06_VPHASE1_OFFSET 0x01F8 | +
+Coefficient 06 of vertical phase 1 filter +
| #define XCRE_COEF07_HPHASE0_OFFSET 0x011C | +
+Coefficient 07 of horizontal phase 0 filter +
| #define XCRE_COEF07_HPHASE1_OFFSET 0x017C | +
+Coefficient 07 of horizontal phase 1 filter +
| #define XCRE_COEF07_VPHASE0_OFFSET 0x01DC | +
+Coefficient 07 of vertical phase 0 filter +
| #define XCRE_COEF07_VPHASE1_OFFSET 0x01FC | +
+Coefficient 07 of vertical phase 1 filter +
| #define XCRE_COEF08_HPHASE0_OFFSET 0x0120 | +
+Coefficient 08 of horizontal phase 0 filter +
| #define XCRE_COEF08_HPHASE1_OFFSET 0x0180 | +
+Coefficient 08 of horizontal phase 1 filter +
| #define XCRE_COEF09_HPHASE0_OFFSET 0x0124 | +
+Coefficient 09 of horizontal phase 0 filter +
| #define XCRE_COEF09_HPHASE1_OFFSET 0x0184 | +
+Coefficient 09 of horizontal phase 1 filter +
| #define XCRE_COEF10_HPHASE0_OFFSET 0x0128 | +
+Coefficient 10 of horizontal phase 0 filter +
| #define XCRE_COEF10_HPHASE1_OFFSET 0x0188 | +
+Coefficient 10 of horizontal phase 1 filter +
| #define XCRE_COEF11_HPHASE0_OFFSET 0x012C | +
+Coefficient 11 of horizontal phase 0 filter +
| #define XCRE_COEF11_HPHASE1_OFFSET 0x018C | +
+Coefficient 11 of horizontal phase 1 filter +
| #define XCRE_COEF12_HPHASE0_OFFSET 0x0130 | +
+Coefficient 12 of horizontal phase 0 filter +
| #define XCRE_COEF12_HPHASE1_OFFSET 0x0190 | +
+Coefficient 12 of horizontal phase 1 filter +
| #define XCRE_COEF13_HPHASE0_OFFSET 0x0134 | +
+Coefficient 13 of horizontal phase 0 filter +
| #define XCRE_COEF13_HPHASE1_OFFSET 0x0194 | +
+Coefficient 13 of horizontal phase 1 filter +
| #define XCRE_COEF14_HPHASE0_OFFSET 0x0138 | +
+Coefficient 14 of horizontal phase 0 filter +
| #define XCRE_COEF14_HPHASE1_OFFSET 0x0198 | +
+Coefficient 14 of horizontal phase 1 filter +
| #define XCRE_COEF15_HPHASE0_OFFSET 0x013C | +
+Coefficient 15 of horizontal phase 0 filter +
| #define XCRE_COEF15_HPHASE1_OFFSET 0x019C | +
+Coefficient 15 of horizontal phase 1 filter +
| #define XCRE_COEF16_HPHASE0_OFFSET 0x0140 | +
+Coefficient 16 of horizontal phase 0 filter +
| #define XCRE_COEF16_HPHASE1_OFFSET 0x01A0 | +
+Coefficient 16 of horizontal phase 1 filter +
| #define XCRE_COEF17_HPHASE0_OFFSET 0x0144 | +
+Coefficient 17 of horizontal phase 0 filter +
| #define XCRE_COEF17_HPHASE1_OFFSET 0x01A4 | +
+Coefficient 17 of horizontal phase 1 filter +
| #define XCRE_COEF18_HPHASE0_OFFSET 0x0148 | +
+Coefficient 18 of horizontal phase 0 filter +
| #define XCRE_COEF18_HPHASE1_OFFSET 0x01A8 | +
+Coefficient 18 of horizontal phase 1 filter +
| #define XCRE_COEF19_HPHASE0_OFFSET 0x014C | +
+Coefficient 19 of horizontal phase 0 filter +
| #define XCRE_COEF19_HPHASE1_OFFSET 0x01AC | +
+Coefficient 19 of horizontal phase 1 filter +
| #define XCRE_COEF20_HPHASE0_OFFSET 0x0150 | +
+Coefficient 20 of horizontal phase 0 filter +
| #define XCRE_COEF20_HPHASE1_OFFSET 0x01B0 | +
+Coefficient 20 of horizontal phase 1 filter +
| #define XCRE_COEF21_HPHASE0_OFFSET 0x0154 | +
+Coefficient 21 of horizontal phase 0 filter +
| #define XCRE_COEF21_HPHASE1_OFFSET 0x01B4 | +
+Coefficient 21 of horizontal phase 1 filter +
| #define XCRE_COEF22_HPHASE0_OFFSET 0x0158 | +
+Coefficient 22 of horizontal phase 0 filter +
| #define XCRE_COEF22_HPHASE1_OFFSET 0x01B8 | +
+Coefficient 22 of horizontal phase 1 filter +
| #define XCRE_COEF23_HPHASE0_OFFSET 0x015C | +
+Coefficient 23 of horizontal phase 0 filter +
| #define XCRE_COEF23_HPHASE1_OFFSET 0x01BC | +
+Coefficient 23 of horizontal phase 1 filter +
| #define XCRE_COEF_DECI_MASK 0x00004000 | +
+Mask of Decimal part +
| #define XCRE_COEF_SIGN_MASK 0x00008000 | +
+Mask for Coefficient sign bit +
| #define XCRE_COEFF_FRAC_MASK 0x00003FFF | +
+Mask of Fractional part +
| #define XCRE_COEFF_MASK 0x0000FFFF | +
+Coefficient mask +
| #define XCRE_COEFF_SHIFT 14 | +
+Shift for decimal value +
| #define XCRE_COEFF_SIGN_SHIFT 16 | +
+Coefficient shift +
| #define XCRE_CONTROL_OFFSET 0x0000 | +
+Control +
| #define XCRE_CTL_AUTORESET_MASK 0x40000000 | +
+Software reset - Auto-synchronize to SOF mask +
| #define XCRE_CTL_BPE_MASK 0x00000010 | +
+Bypass mask +
| #define XCRE_CTL_RESET_MASK 0x80000000 | +
+Software reset - instantaneous mask +
| #define XCRE_CTL_RUE_MASK 0x00000002 | +
+Register update mask +
| #define XCRE_CTL_SW_EN_MASK 0x00000001 | +
+Enable mask +
| #define XCRE_CTL_TPE_MASK 0x00000020 | +
+Test pattern mask +
| #define XCRE_ENCODING_CHROMA_MASK 0x00000100 | +
+Chroma parity mask +
| #define XCRE_ENCODING_CHROMA_SHIFT 8 | +
+Chroma parity shift +
| #define XCRE_ENCODING_FIELD_MASK 0x00000080 | +
+Field parity mask +
| #define XCRE_ENCODING_FIELD_SHIFT 7 | +
+Field parity shift +
| #define XCRE_ENCODING_OFFSET 0x0028 | +
+Frame encoding +
| #define XCRE_ERR_EOL_EARLY_MASK 0x00000001 | +
+Error: End of Line Early mask +
| #define XCRE_ERR_EOL_LATE_MASK 0x00000002 | +
+Error: End of Line Late mask +
| #define XCRE_ERR_SOF_EARLY_MASK 0x00000004 | +
+Error: Start of Frame Early mask +
| #define XCRE_ERR_SOF_LATE_MASK 0x00000008 | +
+Error: Start of Frame Late mask +
| #define XCRE_ERROR_OFFSET 0x0008 | +
+Error +
| #define XCRE_IER_OFFSET XCRE_IRQ_EN_OFFSET | +
+Interrupt enable .*..register corresponds to status bits +
| #define XCRE_IRQ_EN_OFFSET 0x000C | +
+IRQ enable +
| #define XCRE_ISR_OFFSET XCRE_STATUS_OFFSET | +
+Interrupt status register +
| #define XCRE_IXR_ALLINTR_MASK 0x00010003U | +
+OR of all mask +
| #define XCRE_IXR_EOF_MASK 0x00000002 | +
+End-Of-Frame mask +
| #define XCRE_IXR_PROCS_STARTED_MASK 0x00000001 | +
+Proc started mask +
| #define XCRE_IXR_SE_MASK 0x00010000 | +
+Slave Error mask +
| #define XCRE_MAX_VALUE 0xFFFFFFFF | +
+32 bit maximum value +
| #define XCRE_SIGN_MUL -1 | +
+Macro for sign multiplication +
| #define XCRE_SIGNBIT_MASK 0x10000000 | +
+ +
| #define XCRE_STATUS_OFFSET 0x0004 | +
+Status +
| #define XCRE_SYSDEBUG0_OFFSET 0x0014 | +
+System debug 0 +
| #define XCRE_SYSDEBUG1_OFFSET 0x0018 | +
+System debug 1 +
| #define XCRE_SYSDEBUG2_OFFSET 0x001C | +
+System debug 2 +
| #define XCRE_VER_INTERNAL_SHIFT 0x00000008 | +
+Patch ID shift +
| #define XCRE_VER_MAJOR_MASK 0xFF000000 | +
+Version Major mask +
| #define XCRE_VER_MAJOR_SHIFT 0x00000018 | +
+Version Major shift +
| #define XCRE_VER_MINOR_MASK 0x00FF0000 | +
+Version Minor mask +
| #define XCRE_VER_MINOR_SHIFT 0x00000010 | +
+Version Minor shift +
| #define XCRE_VER_PID_MASK 0x00000F00 | +
+Patch ID mask +
| #define XCRE_VER_REV_MASK 0x0000F000 | +
+Version Revision mask +
| #define XCRE_VER_REV_NUM_MASK 0x000000FF | +
+Revision Number mask +
| #define XCRE_VER_REV_SHIFT 0x0000000C | +
+Version Revision shift +
| #define XCRE_VERSION_OFFSET 0x0010 | +
+Version +
| #define XCRESAMPLE_HW_H_ | +
+Prevent circular inclusions by using protection macros +
| #define XCresample_In32 Xil_In32 | +
+Input operations +
| #define XCresample_Out32 Xil_Out32 | +
+Output operations +
| #define XCresample_ReadReg | +( | +BaseAddress, | |||
| + | + | RegOffset | ++ | ) | +XCresample_In32((BaseAddress) + (u32)(RegOffset)) | +
+This macro reads the given register.
+
| BaseAddress | is the Xilinx base address of the Chroma Resampler core | |
| RegOffset | is the register offset of the register (defined at top of this file) |
| #define XCresample_WriteReg | +( | +BaseAddress, | |||
| + | + | RegOffset, | |||
| + | + | Data | ++ | ) | +XCresample_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) | +
+This macro writes into the given register.
+
| BaseAddress | is the Xilinx base address of the Chroma Resampler core | |
| RegOffset | is the register offset of the register (defined at top of this file) | |
| Data | is the 32-bit value to write to the register |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__intr_8c.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__intr_8c.html new file mode 100644 index 00000000..2f6ac1dd --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__intr_8c.html @@ -0,0 +1,136 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------- -------- --------------------------------------------------- + 4.0 adk 03/12/14 First Release. + Implemented XCresample_IntrHandler and + XCresample_SetCallBack functions.
+
+
+#include "xcresample.h"
+
Functions | |
| void | XCresample_IntrHandler (void *InstancePtr) |
| int | XCresample_SetCallBack (XCresample *InstancePtr, u32 HandlerType, void *CallBackFunc, void *CallBackRef) |
| void XCresample_IntrHandler | +( | +void * | +InstancePtr | +) | ++ |
+This function is the interrupt handler for the Chroma Resampler driver.
+This handler reads the pending interrupt from the STATUS register, determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in IRQ_ENABLE register, and finally clears the interrupts.
+The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using Xcresample_SetCallBack() during initialization phase.
+
| InstancePtr | is a pointer to the XCresample instance that just interrupted. |
| int XCresample_SetCallBack | +( | +XCresample * | +InstancePtr, | +|
| + | + | u32 | +HandlerType, | +|
| + | + | void * | +CallBackFunc, | +|
| + | + | void * | +CallBackRef | + |
| + | ) | ++ |
+This routine installs an asynchronous callback function for the given HandlerType:
+
+ HandlerType Callback Function Type + ----------------------- -------------------------------------------------- + XCRE_HANDLER_FRAMEDONE FrameDoneCallBack + XCRE_HANDLER_PROCSTART ProcStartCallBack + XCRE_HANDLER_ERROR ErrCallBack
+
+
| InstancePtr | is a pointer to the XCresample instance to be worked on. | |
| HandlerType | specifies which callback is to be attached. | |
| CallBackFunc | is the address of the callback function. | |
| CallBackRef | is a user data item that will be passed to the callback function when it is invoked. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__selftest_8c.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__selftest_8c.html new file mode 100644 index 00000000..8b0b71e2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__selftest_8c.html @@ -0,0 +1,73 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------ -------- ------------------------------------------------- + 4.0 adk 03/12/14 First release + Implemented XCresample_SelfTest function.
+
+
+#include "xcresample.h"
+#include "xstatus.h"
+
Functions | |
| int | XCresample_SelfTest (XCresample *InstancePtr) |
| int XCresample_SelfTest | +( | +XCresample * | +InstancePtr | +) | ++ |
+This function reads version register of Chroma Resampler core and compares with zero as part of self test.
+
| InstancePtr | is a pointer to the XCresample instance. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__sinit_8c.html b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__sinit_8c.html new file mode 100644 index 00000000..e286021b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/doc/html/api/xcresample__sinit_8c.html @@ -0,0 +1,71 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ------- -------- -------------------------------------------------- + 4.0 adk 03/12/14 First release. + Implemented XCresample_LookupConfig function.
+
+
+#include "xparameters.h"
+#include "xcresample.h"
+
Functions | |
| XCresample_Config * | XCresample_LookupConfig (u16 DeviceId) |
| XCresample_Config* XCresample_LookupConfig | +( | +u16 | +DeviceId | +) | ++ |
+This function returns a reference to an XCresample_Config structure based on the unique device id, DeviceId. The return value will refer to an entry in the device configuration table defined in the xcresample_g.c file.
+
| DeviceId | is the unique device ID of the device for the lookup operation. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.