From 58e0fb3ac252c61403ea6f2677e0e0a729e42c29 Mon Sep 17 00:00:00 2001
From: Sarat Chand Savitala <sarat.chand.savitala@xilinx.com>
Date: Mon, 29 Jun 2015 17:41:27 +0530
Subject: [PATCH] sw_apps:zynqmp_fsbl: Updated reset release sequence for A53

Clock enable is now done before release of reset for A53.

Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
---
 lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c | 60 +++++++++++----------
 1 file changed, 32 insertions(+), 28 deletions(-)

diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
index 2c5dcc71..362b68d2 100644
--- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
+++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
@@ -167,6 +167,14 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 				XFsbl_Out32(APU_CONFIG_0, RegValue);
 			}
 
+			/**
+			 *  Enable the clock
+			 */
+			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
+			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
+			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
+			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
+
 			/**
 			 * Release reset
 			 */
@@ -176,13 +184,6 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 					CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK);
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
-			/**
-			 *  Enable the clock
-			 */
-			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
-			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
-			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
-			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
 			break;
 
 		case XIH_PH_ATTRB_DEST_CPU_A53_1:
@@ -196,6 +197,14 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 				XFsbl_Out32(APU_CONFIG_0, RegValue);
 			}
 
+			/**
+			 *  Enable the clock
+			 */
+			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
+			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
+			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
+			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
+
 			/**
 			 * Release reset
 			 */
@@ -205,13 +214,6 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 					CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK);
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
-			/**
-			 *  Enable the clock
-			 */
-			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
-			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
-			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
-			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
 			break;
 
 		case XIH_PH_ATTRB_DEST_CPU_A53_2:
@@ -225,6 +227,14 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 				XFsbl_Out32(APU_CONFIG_0, RegValue);
 			}
 
+			/**
+			 *  Enable the clock
+			 */
+			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
+			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
+			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
+			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
+
 			/**
 			 * Release reset
 			 */
@@ -235,13 +245,6 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
-			/**
-			 *  Enable the clock
-			 */
-			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
-			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
-			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
-			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
 			break;
 
 		case XIH_PH_ATTRB_DEST_CPU_A53_3:
@@ -255,6 +258,14 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 				XFsbl_Out32(APU_CONFIG_0, RegValue);
 			}
 
+			/**
+			 *  Enable the clock
+			 */
+			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
+			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
+			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
+			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
+
 			/**
 			 * Release reset
 			 */
@@ -265,13 +276,6 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
-			/**
-			 *  Enable the clock
-			 */
-			RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
-			RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
-			             CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
-			XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
 			break;
 
 		case XIH_PH_ATTRB_DEST_CPU_R5_0: