From 5e74e29a0a64fd0358b281712cc91af184b524c9 Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Thu, 1 May 2014 12:07:28 +0530 Subject: [PATCH] srio: Fix for the CR:793212. Fix for the CR:793212. Removed the unnecessary code from the srio driver tcl. Signed-off-by: Kedareswara rao Appana Acked-by: Srikanth Vemula --- .../drivers/srio/data/srio.tcl | 220 +----------- .../examples/xsrio_dma_loopback_example.c | 8 +- XilinxProcessorIPLib/drivers/srio/src/xsrio.c | 131 +++++-- XilinxProcessorIPLib/drivers/srio/src/xsrio.h | 326 ++++++------------ .../drivers/srio/src/xsrio_hw.h | 275 +++++++-------- 5 files changed, 353 insertions(+), 607 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/srio/data/srio.tcl b/XilinxProcessorIPLib/drivers/srio/data/srio.tcl index 0edee13e..a03847ba 100755 --- a/XilinxProcessorIPLib/drivers/srio/data/srio.tcl +++ b/XilinxProcessorIPLib/drivers/srio/data/srio.tcl @@ -43,224 +43,18 @@ # Modification History # # Ver Who Date Changes -# ----- ---- -------- ----------------------------------------------- +# ----- ---- -------- -------------------------------------------------------- # 1.0 adk 16/04/14 Initial release # ############################################################################## -#uses "xillib.tcl" - -set periph_config_params_srio 0 -set periph_ninstances_srio 0 - -proc init_periph_config_struct_srio { deviceid } { - global periph_config_params_srio - set periph_config_params_srio($deviceid) [list] -} - -proc add_field_to_periph_config_struct_srio { deviceid fieldval } { - global periph_config_params_srio - lappend periph_config_params_srio($deviceid) $fieldval -} - -proc get_periph_config_struct_fields_srio { deviceid } { - global periph_config_params_srio - return $periph_config_params_srio($deviceid) -} - -proc xdefine_srio_include_file {drv_handle file_name drv_string} { - global periph_ninstances - - # Open include file - set file_handle [xopen_include_file $file_name] - - # Get all peripherals connected to this driver - set periphs [xget_sw_iplist_for_driver $drv_handle] - - # Handle NUM_INSTANCES - set periph_ninstances 0 - puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */" - foreach periph $periphs { - init_periph_config_struct_srio $periph_ninstances - incr periph_ninstances 1 - } - puts $file_handle "\#define [xget_dname $drv_string NUM_INSTANCES] $periph_ninstances" - - - # Now print all useful parameters for all peripherals - set device_id 0 - foreach periph $periphs { - puts $file_handle "" - - xdefine_srio_params_instance $file_handle $periph $device_id - - xdefine_srio_params_canonical $file_handle $periph $device_id - incr device_id - puts $file_handle "\n" - } - puts $file_handle "\n/******************************************************************/\n" - close $file_handle -} - -proc xdefine_srio_params_instance {file_handle periph device_id} { - set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph] - if {$sriois_memory == 0} { - set sriois_memory 0 - } - - set sriois_processor [get_property CONFIG.C_PE_PROC $periph] - if {$sriois_processor == 0} { - set sriois_processor 0 - } else { - set sriois_processor 2 - } - - set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph] - if {$sriois_bridge == 0} { - set sriois_bridge 0 - } else { - set sriois_bridge 3 - } - - puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */" - - puts $file_handle "\#define [xget_dname $periph "DEVICE_ID"] $device_id" - set value [get_property CONFIG.C_BASEADDR $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_BASEADDR"] $value" - - set value [get_property CONFIG.C_HIGHADDR $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_HIGHADDR"] $value" - - set value [get_property CONFIG.C_DEVICEID_WIDTH $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_DEVICEID_WIDTH"] $value" - - set value [get_property CONFIG.C_IS_HOST $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_IS_HOST"] $value" - - set value [get_property CONFIG.C_TX_DEPTH $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_TX_DEPTH"] $value" - - set value [get_property CONFIG.C_RX_DEPTH $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_RX_DEPTH"] $value" - - set value [get_property CONFIG.C_DISCOVERED $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define [xget_dname $periph "C_DISCOVERED"] $value" - - puts $file_handle "\#define [xget_dname $periph "PE_MEMORY"] $sriois_memory" - puts $file_handle "\#define [xget_dname $periph "PE_PROC"] $sriois_processor" - puts $file_handle "\#define [xget_dname $periph "PE_BRIDGE"] $sriois_bridge" - -} - -proc xdefine_srio_params_canonical {file_handle periph device_id} { - - set sriois_memory [get_property CONFIG.C_PE_MEMORY $periph] - if {$sriois_memory == 0} { - set sriois_memory 0 - } - - set sriois_processor [get_property CONFIG.C_PE_PROC $periph] - if {$sriois_processor == 0} { - set sriois_processor 0 - } else { - set sriois_processor 2 - } - - set sriois_bridge [get_property CONFIG.C_PE_BRIDGE $periph] - if {$sriois_bridge == 0} { - set sriois_bridge 0 - } else { - set sriois_bridge 3 - } - - puts $file_handle "\n/* Canonical definitions for peripheral [string toupper [get_property NAME $periph]] */" - - set canonical_tag [string toupper [format "XPAR_SRIO_%d" $device_id]] - - # Handle device ID - set canonical_name [format "%s_DEVICE_ID" $canonical_tag] - puts $file_handle "\#define $canonical_name $device_id" - add_field_to_periph_config_struct_srio $device_id $canonical_name - - set canonical_name [format "%s_BASEADDR" $canonical_tag] - set value [get_property CONFIG.C_BASEADDR $periph] - if {[llength $value] == 0} { - set value 0 - } - puts $file_handle "\#define $canonical_name $value" - add_field_to_periph_config_struct_srio $device_id $canonical_name - - set canonical_name [format "%s_PE_MEMORY" $canonical_tag] - puts $file_handle "\#define $canonical_name $sriois_memory" - add_field_to_periph_config_struct_srio $device_id $canonical_name - - set canonical_name [format "%s_PE_PROC" $canonical_tag] - puts $file_handle "\#define $canonical_name $sriois_processor" - add_field_to_periph_config_struct_srio $device_id $canonical_name - - set canonical_name [format "%s_PE_BRIDGE" $canonical_tag] - puts $file_handle "\#define $canonical_name $sriois_bridge" - add_field_to_periph_config_struct_srio $device_id $canonical_name - -} - -proc xdefine_srio_config_file {file_name drv_string} { - - global periph_ninstances - - set filename [file join "src" $file_name] - file delete $filename - set config_file [open $filename w] - xprint_generated_header $config_file "Driver configuration" - puts $config_file "\#include \"xparameters.h\"" - puts $config_file "\#include \"[string tolower $drv_string].h\"" - puts $config_file "\n/*" - puts $config_file "* The configuration table for devices" - puts $config_file "*/\n" - puts $config_file [format "%s_Config %s_ConfigTable\[\] =" $drv_string $drv_string] - puts $config_file "\{" - - set start_comma "" - for {set i 0} {$i < $periph_ninstances} {incr i} { - - puts $config_file [format "%s\t\{" $start_comma] - set comma "" - foreach field [get_periph_config_struct_fields_srio $i] { - puts -nonewline $config_file [format "%s\t\t%s" $comma $field] - set comma ",\n" - } - - puts -nonewline $config_file "\n\t\}" - set start_comma ",\n" - } - puts $config_file "\n\};\n" - close $config_file -} - proc generate {drv_handle} { - xdefine_srio_include_file $drv_handle "xparameters.h" "XSrio" - xdefine_srio_config_file "xsrio_g.c" "XSrio" + xdefine_include_file $drv_handle "xparameters.h" "XSrio" "NUM_INSTANCES" \ + "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" \ + "C_DEVICEID" + xdefine_config_file $drv_handle "xsrio_g.c" "XSrio" "DEVICE_ID" "C_BASEADDR" + + xdefine_canonical_xpars $drv_handle "xparameters.h" "Srio" "DEVICE_ID" "C_BASEADDR" } diff --git a/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c b/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c index 53b4cc80..8f819508 100755 --- a/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c +++ b/XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c @@ -231,12 +231,8 @@ int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId) /* SRIO Configuration */ /* Set the Local Configuration Space Base Address */ XSrio_SetLCSBA(InstancePtr, 0xFFF); - /* Set the Water Mark Level to transfer priority 0 packet */ - XSrio_SetWaterMark0(InstancePtr, 0x5); - /* Set the Water Mark Level to transfer priority 1 packet */ - XSrio_SetWaterMark1(InstancePtr, 0x4); - /* Set the Water Mark Level to transfer priority 2 packet */ - XSrio_SetWaterMark2(InstancePtr, 0x3); + /* Set the Water Mark Level to transfer priority 0,1,2 packet */ + XSrio_SetWaterMark(InstancePtr, 0x5, 0x4, 0x3); /* Set the Port Response timeout value */ XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203); diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio.c b/XilinxProcessorIPLib/drivers/srio/src/xsrio.c index 073934f1..870a2cfa 100755 --- a/XilinxProcessorIPLib/drivers/srio/src/xsrio.c +++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio.c @@ -93,19 +93,14 @@ int XSrio_CfgInitialize(XSrio *InstancePtr, InstancePtr->Config.BaseAddress = EffectiveAddress; InstancePtr->Config.DeviceId = Config->DeviceId; - /* Initialization is successful */ - InstancePtr->IsReady = 1; - - /* Configuration of the Device */ - InstancePtr->Config.IsPEMemory = Config->IsPEMemory; - InstancePtr->Config.IsPEProcessor = Config->IsPEProcessor; - InstancePtr->Config.IsPEBridge = Config->IsPEBridge; - /* Port width for the Device */ Portwidth = XSrio_ReadReg(InstancePtr->Config.BaseAddress, XSRIO_PORT_N_ERR_STS_CSR_OFFSET + XSRIO_PORT_N_CTL_CSR_OFFSET); - InstancePtr->PortWidth = ((Portwidth & XSRIO_PORT_N_CTL_PW_CSR_MASK) >> - XSRIO_PORT_N_CTL_PW_CSR_SHIFT); + InstancePtr->PortWidth = ((Portwidth & XSRIO_PORT_N_CTL_CSR_PW_MASK) >> + XSRIO_PORT_N_CTL_CSR_PW_SHIFT); + + /* Initialization is successful */ + InstancePtr->IsReady = 1; return XST_SUCCESS; } @@ -119,7 +114,7 @@ int XSrio_CfgInitialize(XSrio *InstancePtr, * * @return * - XSRIO_PORT_OK Port is initialized with no errors. -* - XSRIO_PORT_UNINITIALIZED Port is not intilized. +* - XSRIO_PORT_UNINITIALIZED Port is not initialized. * No Serial Rapidio link is present. * - XSRIO_PORT_HAS_ERRORS Port is initialized but has errors. * @@ -134,11 +129,11 @@ int XSrio_GetPortStatus(XSrio *InstancePtr) Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress, XSRIO_PORT_N_ERR_STS_CSR_OFFSET); - if(Result & XSRIO_PORT_N_ERR_STS_POK_CSR_MASK) + if(Result & XSRIO_PORT_N_ERR_STS_CSR_POK_MASK) Result = XSRIO_PORT_OK; - else if(Result & XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK) + else if(Result & XSRIO_PORT_N_ERR_STS_CSR_PUINT_MASK) Result = XSRIO_PORT_UNINITIALIZED; - else if(Result & XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK) + else if(Result & XSRIO_PORT_N_ERR_STS_CSR_PERR_MASK) Result = XSRIO_PORT_HAS_ERRORS; return Result; @@ -167,11 +162,11 @@ int XSrio_GetPEType(XSrio *InstancePtr) Result = XSrio_ReadReg(InstancePtr->Config.BaseAddress, XSRIO_PEF_CAR_OFFSET); - if(Result & XSRIO_PEF_MEMORY_CAR_MASK) + if(Result & XSRIO_PEF_CAR_MEMORY_MASK) Result = XSRIO_IS_MEMORY; - else if(Result & XSRIO_PEF_PROCESSOR_CAR_MASK) + else if(Result & XSRIO_PEF_CAR_PROCESSOR_MASK) Result = XSRIO_IS_PROCESSOR; - else if(Result & XSRIO_PEF_BRIDGE_CAR_MASK) + else if(Result & XSRIO_PEF_CAR_BRIDGE_MASK) Result = XSRIO_IS_BRIDGE; return Result; @@ -210,31 +205,31 @@ int XSrio_IsOperationSupported(XSrio *InstancePtr, u8 Operation, u8 Direction) switch (Operation) { case XSRIO_OP_MODE_NREAD: - if(OperationCar & XSRIO_SRCDST_OPS_READ_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_READ_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_NWRITE: - if(OperationCar & XSRIO_SRCDST_OPS_WRITE_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_WRITE_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_SWRITE: - if(OperationCar & XSRIO_SRCDST_OPS_SWRITE_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_SWRITE_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_NWRITE_R: - if(OperationCar & XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_WRITE_RESPONSE_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_DATA_MESSAGE: - if(OperationCar & XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_DATA_MSG_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_DOORBELL: - if(OperationCar & XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_DOORBELL_MASK) Status = XST_SUCCESS; break; case XSRIO_OP_MODE_ATOMIC: - if(OperationCar & XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK) + if(OperationCar & XSRIO_SRCDST_OPS_CAR_ATOMIC_SET_MASK) Status = XST_SUCCESS; break; default: @@ -242,3 +237,91 @@ int XSrio_IsOperationSupported(XSrio *InstancePtr, u8 Operation, u8 Direction) } return Status; } + +/*****************************************************************************/ +/** +* XSrio_SetWaterMark Configures the watermark to transfer a priority packet. +* +* @param InstancePtr is a pointer to the SRIO Gen2 instance to be +* worked on. +* @param WaterMark0 is the water mark value to transfer a priority 0 +* packet. +* @param WaterMark1 is the water mark value to transfer a priority 1 +* packet. +* @param WaterMark2 is the water mark value to transfer a priority 2 +* packet. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XSrio_SetWaterMark(XSrio *InstancePtr, u8 WaterMark0, u8 WaterMark1, + u8 WaterMark2) +{ + int Regval; + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(WaterMark0 > WaterMark1); + Xil_AssertVoid(WaterMark1 > WaterMark2); + Xil_AssertVoid(WaterMark2 > 0); + + Regval = XSrio_ReadReg(InstancePtr->Config.BaseAddress, + XSRIO_IMP_WCSR_OFFSET); + + if (WaterMark0 > WaterMark1) { + Regval = ((Regval & ~XSRIO_IMP_WCSR_WM0_MASK) | + (WaterMark0 & XSRIO_IMP_WCSR_WM0_MASK)); + XSrio_WriteReg((InstancePtr)->Config.BaseAddress, + XSRIO_IMP_WCSR_OFFSET, Regval); + } + + if(WaterMark1 > WaterMark2) { + Regval = ((Regval & ~XSRIO_IMP_WCSR_WM1_MASK) | + ((WaterMark1 << XSRIO_IMP_WCSR_WM1_SHIFT) & + XSRIO_IMP_WCSR_WM1_MASK)); + XSrio_WriteReg((InstancePtr)->Config.BaseAddress, + XSRIO_IMP_WCSR_OFFSET, Regval); + } + + if(WaterMark2 > 0) { + Regval = ((Regval & ~XSRIO_IMP_WCSR_WM2_MASK) | + ((WaterMark2 << XSRIO_IMP_WCSR_WM2_SHIFT) & + XSRIO_IMP_WCSR_WM2_MASK)); + XSrio_WriteReg((InstancePtr)->Config.BaseAddress, + XSRIO_IMP_WCSR_OFFSET, Regval); + } +} + +/*****************************************************************************/ +/** +* XSrio_GetWaterMark API reads the water mark values. +* +* @param InstancePtr is the XSrio instance to operate on. +* @param WaterMark0 is a pointer to a variable where the driver will pass +* back the water mark 0 value. +* @param WaterMark1 is a pointer to a variable where the driver will pass +* back the water mark 1 value. +* @param WaterMark2 is a pointer to a variable where the driver will pass +* back the water mark 2 value. +* +* @return None. +* +* @note: None. +* +*****************************************************************************/ +void XSrio_GetWaterMark(XSrio *InstancePtr, u8 *WaterMark0, u8 *WaterMark1, + u8 *WaterMark2) +{ + int Regval; + Xil_AssertVoid(InstancePtr != NULL); + + Regval = XSrio_ReadReg(InstancePtr->Config.BaseAddress, + XSRIO_IMP_WCSR_OFFSET); + + *WaterMark0 = (Regval & XSRIO_IMP_WCSR_WM0_MASK); + *WaterMark1 = ((Regval & XSRIO_IMP_WCSR_WM1_MASK) >> + XSRIO_IMP_WCSR_WM1_SHIFT); + *WaterMark2 = ((Regval & XSRIO_IMP_WCSR_WM2_MASK) >> + XSRIO_IMP_WCSR_WM2_SHIFT); + +} diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio.h b/XilinxProcessorIPLib/drivers/srio/src/xsrio.h index f6e9822f..f4b76b3b 100755 --- a/XilinxProcessorIPLib/drivers/srio/src/xsrio.h +++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio.h @@ -158,7 +158,7 @@ extern "C" { #define XSRIO_PORT_UNINITIALIZED 1 /**< Port is uninitialized */ #define XSRIO_PORT_HAS_ERRORS 2 /**< Port has errors */ -/* Processing Element(SRIO Gen2 Core Direction Flags */ +/* Processing Element(SRIO Gen2 Core) Direction Flags */ #define XSRIO_DIR_TX 1 /**< Transmit Direction Flag */ #define XSRIO_DIR_RX 2 /**< Receive Direction Flag */ @@ -170,9 +170,6 @@ extern "C" { typedef struct XSrio_Config { u16 DeviceId; /**< Device Id */ u32 BaseAddress; /**< Base Address */ - u8 IsPEMemory; /**< Core is configured as Memory */ - u8 IsPEProcessor; /**< Core is configured as Processor */ - u8 IsPEBridge; /**< Core is Configured as Bridge */ } XSrio_Config; /** @@ -228,7 +225,7 @@ typedef struct XSrio { /****************************************************************************/ /** * -* XSrio_ReadAsmVendorID retruns the Assembly Vendor Id of the core. +* XSrio_ReadAsmVendorID returns the Assembly Vendor Id of the core. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be * worked on. @@ -241,7 +238,7 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_ReadAsmVendorID(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_ASMVID_CAR_MASK) + XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_CAR_ASMVID_MASK) /****************************************************************************/ /** @@ -259,8 +256,8 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_ReadAsmID(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_ASMID_CAR_MASK) >> \ - XSRIO_ASM_ID_ASMID_CAR_SHIFT) + XSRIO_ASM_ID_CAR_OFFSET) & XSRIO_ASM_ID_CAR_ASMID_MASK) >> \ + XSRIO_ASM_ID_CAR_ASMID_SHIFT) /****************************************************************************/ /** @@ -279,7 +276,7 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_GetExFeaturesPointer(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_EFP_CAR_MASK) + XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_CAR_EFP_MASK) /****************************************************************************/ /** @@ -297,8 +294,8 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_ReadAsmRevision(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_ASR_CAR_MASK) >> \ - XSRIO_ASM_INFO_ASR_CAR_SHIFT) + XSRIO_ASM_INFO_CAR_OFFSET) & XSRIO_ASM_INFO_CAR_ASMREV_MASK) >> \ + XSRIO_ASM_INFO_CAR_ASMREV_SHIFT) /****************************************************************************/ /** @@ -319,7 +316,7 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_IsLargeSystem(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CTS_CAR_MASK) ? \ + XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CAR_CTS_MASK) ? \ TRUE : FALSE) /****************************************************************************/ @@ -341,7 +338,7 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_IsCRFSupported(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CRF_CAR_MASK) ? \ + XSRIO_PEF_CAR_OFFSET) & XSRIO_PEF_CAR_CRF_MASK) ? \ TRUE : FALSE) /****************************************************************************/ @@ -404,7 +401,7 @@ typedef struct XSrio { /****************************************************************************/ /** * -* XSrio_SetLCSBA it sets the Local Configuration Space Base Address of +* XSrio_SetLCSBA Configures the Local Configuration Space Base Address of * the SRIO Gen2 core. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -442,7 +439,7 @@ typedef struct XSrio { #define XSrio_GetLargeBaseDeviceID(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_BASE_DID_CSR_OFFSET) & \ - XSRIO_BASE_DID_LBDID_CSR_MASK) + XSRIO_BASE_DID_CSR_LBDID_MASK) /****************************************************************************/ /** @@ -464,8 +461,8 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_BASE_DID_CSR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASI_DID_BDID_CSR_MASK) | \ - (DeviceId & XSRIO_BASE_DID_LBDID_CSR_MASK)))) + XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASE_DID_CSR_BDID_MASK) | \ + (DeviceId & XSRIO_BASE_DID_CSR_LBDID_MASK)))) /****************************************************************************/ /** @@ -485,7 +482,7 @@ typedef struct XSrio { #define XSrio_GetBaseDeviceID(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_BASE_DID_CSR_OFFSET) & \ - XSRIO_BASI_DID_BDID_CSR_MASK) >> XSRIO_BASI_DID_BDID_CSR_SHIFT) + XSRIO_BASE_DID_CSR_BDID_MASK) >> XSRIO_BASE_DID_CSR_BDID_SHIFT) /****************************************************************************/ /** @@ -507,9 +504,9 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_BASE_DID_CSR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASE_DID_LBDID_CSR_MASK) \ - |((DeviceId << XSRIO_BASI_DID_BDID_CSR_SHIFT) \ - & XSRIO_BASI_DID_BDID_CSR_MASK)))) + XSRIO_BASE_DID_CSR_OFFSET) & XSRIO_BASE_DID_CSR_LBDID_MASK) \ + |((DeviceId << XSRIO_BASE_DID_CSR_BDID_SHIFT) \ + & XSRIO_BASE_DID_CSR_BDID_MASK)))) /****************************************************************************/ /** @@ -528,7 +525,7 @@ typedef struct XSrio { #define XSrio_GetHostBaseDevID_LockCSR(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_HOST_DID_LOCK_CSR_OFFSET) & \ - XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK) + XSRIO_HOST_DID_LOCK_CSR_HBDID_MASK) /****************************************************************************/ /** @@ -550,7 +547,7 @@ typedef struct XSrio { #define XSrio_SetHostBaseDevID_LockCSR(InstancePtr, DeviceId) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_HOST_DID_LOCK_CSR_OFFSET, \ - (DeviceId & XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK))) + (DeviceId & XSRIO_HOST_DID_LOCK_CSR_HBDID_MASK))) /****************************************************************************/ /** @@ -647,9 +644,9 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_GetPortLinkTimeOutValue(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_PORT_TOUT_CSR_OFFSET) & \ - XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK) >> \ - XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT) + XSRIO_PORT_LINK_TOUT_CSR_OFFSET ) & \ + XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_MASK) >> \ + XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_SHIFT) /****************************************************************************/ /** @@ -670,9 +667,9 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_SetPortLinkTimeOutValue(InstancePtr, Value) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_PORT_TOUT_CSR_OFFSET, \ - (Value << XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT) & \ - XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK)) + XSRIO_PORT_LINK_TOUT_CSR_OFFSET , \ + (Value << XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_SHIFT) & \ + XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_MASK)) /****************************************************************************/ /** @@ -691,9 +688,9 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_GetPortRespTimeOutValue(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_RSP_TOUT_CSR_OFFSET) & \ - XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK) >> \ - XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT) + XSRIO_PORT_RESP_TOUT_CSR_OFFSET) & \ + XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_MASK) >> \ + XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_SHIFT) /****************************************************************************/ /** @@ -714,9 +711,9 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_SetPortRespTimeOutValue(InstancePtr, Value) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_RSP_TOUT_CSR_OFFSET, \ - (Value << XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT) & \ - XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK)) + XSRIO_PORT_RESP_TOUT_CSR_OFFSET, \ + (Value << XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_SHIFT) & \ + XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_MASK)) /****************************************************************************/ /** @@ -737,13 +734,13 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_IsPEDiscovered(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) & \ - XSRIO_GEN_CTL_DISCOVERED_CSR_MASK) ? TRUE : FALSE) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) & \ + XSRIO_PORT_GEN_CTL_CSR_DISCOVERED_MASK) ? TRUE : FALSE) /****************************************************************************/ /** * -* XSrio_Discovered configures the device as Discovered so that it is +* XSrio_SetDiscovered configures the device as Discovered so that it is * responsible for system exploration. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -752,15 +749,15 @@ typedef struct XSrio { * @return None. * * @note C-style signature: -* void XSrio_Discovered(XSrio *InstancePtr) +* void XSrio_SetDiscovered(XSrio *InstancePtr) * *****************************************************************************/ -#define XSrio_Discovered(InstancePtr) \ +#define XSrio_SetDiscovered(InstancePtr) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET, \ + XSRIO_PORT_GEN_CTL_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) \ - | XSRIO_GEN_CTL_DISCOVERED_CSR_MASK))) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) \ + | XSRIO_PORT_GEN_CTL_CSR_DISCOVERED_MASK))) /****************************************************************************/ /** @@ -781,13 +778,13 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_IsMasterEnabled(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) \ - & XSRIO_GEN_CTL_MENABLE_CSR_MASK) ? TRUE : FALSE) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) \ + & XSRIO_PORT_GEN_CTL_CSR_MENABLE_MASK) ? TRUE : FALSE) /****************************************************************************/ /** * -* XSrio_MasterEnabled configures the device so that it is allowed to issue +* XSrio_SetMasterEnabled configures the device so that it is allowed to issue * requests into the system. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -796,15 +793,15 @@ typedef struct XSrio { * @return None. * * @note C-style signature: -* void XSrio_MasterEnabled(XSrio *InstancePtr) +* void XSrio_SetMasterEnabled(XSrio *InstancePtr) * *****************************************************************************/ -#define XSrio_MasterEnabled(InstancePtr) \ +#define XSrio_SetMasterEnabled(InstancePtr) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET, \ + XSRIO_PORT_GEN_CTL_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) \ - | XSRIO_GEN_CTL_MENABLE_CSR_MASK))) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) \ + | XSRIO_PORT_GEN_CTL_CSR_MENABLE_MASK))) /****************************************************************************/ /** @@ -825,13 +822,13 @@ typedef struct XSrio { *****************************************************************************/ #define XSrio_IsHost(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) \ - & XSRIO_GEN_CTL_HOST_CSR_MASK) ? TRUE : FALSE) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) \ + & XSRIO_PORT_GEN_CTL_CSR_HOST_MASK) ? TRUE : FALSE) /****************************************************************************/ /** * -* XSrio_HostEnabled configures the device to be responsible for system +* XSrio_SetHostEnabled configures the device to be responsible for system * exploration. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -840,15 +837,15 @@ typedef struct XSrio { * @return None. * * @note C-style signature: -* void XSrio_HostEnabled(XSrio *InstancePtr) +* void XSrio_SetHostEnabled(XSrio *InstancePtr) * *****************************************************************************/ -#define XSrio_HostEnabled(InstancePtr) \ +#define XSrio_SetHostEnabled(InstancePtr) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET, \ + XSRIO_PORT_GEN_CTL_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_GEN_CTL_CSR_OFFSET) \ - | XSRIO_GEN_CTL_HOST_CSR_MASK))) + XSRIO_PORT_GEN_CTL_CSR_OFFSET) \ + | XSRIO_PORT_GEN_CTL_CSR_HOST_MASK))) /****************************************************************************/ /** @@ -869,7 +866,7 @@ typedef struct XSrio { #define XSrio_GetCommand(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_MNT_REQ_CSR_OFFSET) & \ - XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK) + XSRIO_PORT_N_MNT_REQ_CSR_CMD_MASK) /****************************************************************************/ /** @@ -891,7 +888,7 @@ typedef struct XSrio { #define XSrio_SendCommand(InstancePtr, Value) \ (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_MNT_REQ_CSR_OFFSET, \ - Value & XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK)) + Value & XSRIO_PORT_N_MNT_REQ_CSR_CMD_MASK)) /****************************************************************************/ /** @@ -916,7 +913,7 @@ typedef struct XSrio { #define XSrio_IsResponseValid(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_MNT_RES_CSR_OFFSET) & \ - XSRIO_PORT_N_MNT_RES_RVALID_CSR_MASK) ? TRUE : FALSE) + XSRIO_PORT_N_MNT_RES_CSR_RVALID_MASK) ? TRUE : FALSE) /****************************************************************************/ /** @@ -937,7 +934,7 @@ typedef struct XSrio { #define XSrio_GetOutboundAckID(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \ - XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK) + XSRIO_PORT_N_ACKID_CSR_OBACKID_MASK) /****************************************************************************/ /** @@ -961,8 +958,8 @@ typedef struct XSrio { XSRIO_PORT_N_ACKID_CSR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \ - XSRIO_PORT_N_ACKID_RESET_OBACKID_CSR_MASK) \ - | (Value & XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK)))) + XSRIO_PORT_N_ACKID_CSR_RESET_OBACKID_MASK) \ + | (Value & XSRIO_PORT_N_ACKID_CSR_OBACKID_MASK)))) /****************************************************************************/ /** @@ -983,8 +980,8 @@ typedef struct XSrio { #define XSrio_GetInboundAckID(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \ - XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK) >> \ - XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT) + XSRIO_PORT_N_ACKID_CSR_IBACKID_MASK) >> \ + XSRIO_PORT_N_ACKID_CSR_IBACKID_SHIFT) /****************************************************************************/ /** @@ -1011,9 +1008,9 @@ typedef struct XSrio { XSRIO_PORT_N_ACKID_CSR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ACKID_CSR_OFFSET) & \ - XSRIO_PORT_N_ACKID_RESET_IBACKID_CSR_MASK) \ - | ((Value << XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT) & \ - XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK)))) + XSRIO_PORT_N_ACKID_CSR_RESET_IBACKID_MASK) \ + | ((Value << XSRIO_PORT_N_ACKID_CSR_IBACKID_SHIFT) & \ + XSRIO_PORT_N_ACKID_CSR_IBACKID_MASK)))) /****************************************************************************/ /** @@ -1035,7 +1032,7 @@ typedef struct XSrio { XSRIO_PORT_N_ACKID_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ACKID_CSR_OFFSET) \ - | XSRIO_PORT_N_ACKID_CLSACKID_CSR_MASK))) + | XSRIO_PORT_N_ACKID_CSR_CLSACKID_MASK))) /****************************************************************************/ /** @@ -1057,7 +1054,7 @@ typedef struct XSrio { #define XSrio_IsEnumerationBoundary(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) & \ - XSRIO_PORT_N_CTL_ENUMB_CSR_MASK) ? TRUE : FALSE) + XSRIO_PORT_N_CTL_CSR_ENUMB_MASK) ? TRUE : FALSE) /****************************************************************************/ /** @@ -1079,12 +1076,12 @@ typedef struct XSrio { XSRIO_PORT_N_CTL_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) \ - | XSRIO_PORT_N_CTL_ENUMB_CSR_MASK))) + | XSRIO_PORT_N_CTL_CSR_ENUMB_MASK))) /****************************************************************************/ /** * -* XSrio_GetPortwidthOverride it gives the port width override value of the +* XSrio_GetPortwidthOverride returns the port width override value of the * SRIO Gen2 core. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -1099,13 +1096,13 @@ typedef struct XSrio { #define XSrio_GetPortwidthOverride(InstancePtr) \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) & \ - XSRIO_PORT_N_CTL_PWO_CSR_MASK) >> XSRIO_PORT_N_CTL_PWO_CSR_SHIFT) + XSRIO_PORT_N_CTL_CSR_PWO_MASK) >> XSRIO_PORT_N_CTL_CSR_PWO_SHIFT) /****************************************************************************/ /** * -* XSrio_SetPortwidthOverride it sets the port width override value of the SRIO -* Gen2 core. +* XSrio_SetPortwidthOverride configures the port width override value of the +* SRIO Gen2 core. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be * worked on. @@ -1122,14 +1119,14 @@ typedef struct XSrio { XSRIO_PORT_N_CTL_CSR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) & \ - XSRIO_PORT_N_CTL_RESET_PWO_CSR_MASK) | \ - ((Value << XSRIO_PORT_N_CTL_PWO_CSR_SHIFT) \ - & XSRIO_PORT_N_CTL_PWO_CSR_MASK)))) + XSRIO_PORT_N_CTL_CSR_RESET_PWO_MASK) | \ + ((Value << XSRIO_PORT_N_CTL_CSR_PWO_SHIFT) \ + & XSRIO_PORT_N_CTL_CSR_PWO_MASK)))) /****************************************************************************/ /** * -* XSrio_GetSerialLaneExtFeaturesPointer it gives the exteneded features pointer +* XSrio_GetSerialLaneExtFeaturesPointer returns the extended features pointer * For the serial lane which will point to the next extended features block * If one exists. * @@ -1150,7 +1147,7 @@ typedef struct XSrio { /****************************************************************************/ /** * -* XSrio_ClrDecodingErrors it will clears the 8B/10B decoding errors and return +* XSrio_ClrDecodingErrors clears the 8B/10B decoding errors and return * Result. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -1169,138 +1166,7 @@ typedef struct XSrio { XSRIO_EFB_LPSL_OFFSET + XSRIO_SLS0_CSR_OFFSET(Lanenum)) & \ XSRIO_SLS0_CSR_DECODING_ERRORS_MASK) \ >> XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT) - -/****************************************************************************/ -/** -* -* XSrio_GetWaterMark0 it gives the water mark0 buffer space value which will be -* Use by the link partner to send a priority 0 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* -* @return Water Mark buffer space value. -* -* @note C-style signature: -* u8 XSrio_GetWaterMark0(XSrio *InstancePtr) -* -*****************************************************************************/ -#define XSrio_GetWaterMark0(InstancePtr) \ - (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET) & \ - XSRIO_IMP_WCSR_WM0_MASK) - -/****************************************************************************/ -/** -* -* XSrio_SetWaterMark0 sets water mark0 buffer space value which will be used -* By the link partner to send a priority 0 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* @param Value to set for a priority 0 packet. -* -* @return None. -* -* @note C-style signature: -* void XSrio_SetWaterMark0(XSrio *InstancePtr, u8 Value) -* -*****************************************************************************/ -#define XSrio_SetWaterMark0(InstancePtr, Value) \ - (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET, \ - ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM0_MASK) | \ - (Value & XSRIO_IMP_WCSR_WM0_MASK)))) - -/****************************************************************************/ -/** -* -* XSrio_GetWaterMark1 returns the water mark1 buffer space value which will be -* Use by the link partner to send a priority 1 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* -* @return Water Mark buffer space value. -* -* @note C-style signature: -* u8 XSrio_GetWaterMark1(XSrio *InstancePtr) -* -*****************************************************************************/ -#define XSrio_GetWaterMark1(InstancePtr) \ - ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET ) & \ - XSRIO_IMP_WCSR_WM1_MASK) >> XSRIO_IMP_WCSR_WM1_SHIFT) - -/****************************************************************************/ -/** -* -* XSrio_SetWaterMark1 sets the water mark1 buffer space value which will be -* Use by the link partner to send a priority 1 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* @param Value to set for a priority 1 packet. -* -* @return None. -* -* @note C-style signature: -* void XSrio_SetWaterMark1(XSrio *InstancePtr, u8 Value) -* -*****************************************************************************/ -#define XSrio_SetWaterMark1(InstancePtr, Value) \ - (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET, \ - ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM1_MASK) |\ - ((Value << XSRIO_IMP_WCSR_WM1_SHIFT) \ - & XSRIO_IMP_WCSR_WM1_MASK)))) - -/****************************************************************************/ -/** -* -* XSrio_GetWaterMark2 returns the water mark2 buffer space value which will be -* Use by the link partner to send a priority 2 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* -* @return Water Mark buffer space value.. -* -* @note C-style signature: -* u8 XSrio_GetWaterMark2(XSrio *InstancePtr) -* -*****************************************************************************/ -#define XSrio_GetWaterMark2(InstancePtr) \ - ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET ) & \ - XSRIO_IMP_WCSR_WM2_MASK) >> XSRIO_IMP_WCSR_WM2_SHIFT) - -/****************************************************************************/ -/** -* -* XSrio_SetWaterMark2 sets the water mark2 buffer space value which will be -* Use by the link partner to send a priority 2 packet. -* -* @param InstancePtr is a pointer to the SRIO Gen2 instance to be -* worked on. -* @param Value to set for a priority 2 packet. -* -* @return None. -* -* @note C-style signature: -* void XSrio_SetWaterMark2(XSrio *InstancePtr, u8 Value) -* -*****************************************************************************/ -#define XSrio_SetWaterMark2(InstancePtr, Value) \ - (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET, \ - ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_WCSR_OFFSET) & XSRIO_IMP_WCSR_RESET_WM2_MASK) | \ - ((Value << XSRIO_IMP_WCSR_WM2_SHIFT) \ - & XSRIO_IMP_WCSR_WM2_MASK)))) - + /****************************************************************************/ /** * @@ -1410,7 +1276,7 @@ typedef struct XSrio { /****************************************************************************/ /** * -* XSrio_RequestDestinationID gets the destination id value which will be +* XSrio_GetDestinationID gets the destination id value which will be * used for outgoing maintenance requests. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -1419,7 +1285,7 @@ typedef struct XSrio { * @return Destination ID value of the outgoing maintenance request. * * @note C-style signature: -* u8 XSrio_RequestDestinationID(XSrio *InstancePtr) +* u8 XSrio_GetDestinationID(XSrio *InstancePtr) * *****************************************************************************/ #define XSrio_GetDestinationID(InstancePtr) \ @@ -1447,13 +1313,13 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_IMP_MRIR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_RST_REQ_DESTID_MASK) | \ + XSRIO_IMP_MRIR_OFFSET) & ~XSRIO_IMP_MRIR_REQ_DESTID_MASK) | \ (Value & XSRIO_IMP_MRIR_REQ_DESTID_MASK)))) /****************************************************************************/ /** * -* XSrio_GetCRF checks whethere the CRF is enabled in the core or not which will +* XSrio_GetCRF checks whether the CRF is enabled in the core or not which will * be used for outgoing maintenance requests. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be @@ -1462,7 +1328,7 @@ typedef struct XSrio { * @return CRF Value used for outgoing maintenance requests. * * @note C-style signature: -* u8 XSrio_RequestCRF(XSrio *InstancePtr) +* u8 XSrio_GetCRF(XSrio *InstancePtr) * *****************************************************************************/ #define XSrio_GetCRF(InstancePtr) \ @@ -1495,7 +1361,7 @@ typedef struct XSrio { /****************************************************************************/ /** * -* XSrio_RequestPriority priority used for outgoing maintenance requests. +* XSrio_GetPriority priority used for outgoing maintenance requests. * * @param InstancePtr is a pointer to the SRIO Gen2 instance to be * worked on. @@ -1503,7 +1369,7 @@ typedef struct XSrio { * @return Priority value. * * @note C-style signature: -* u8 XSrio_RequestPriority(XSrio *InstancePtr) +* u8 XSrio_GetPriority(XSrio *InstancePtr) * *****************************************************************************/ #define XSrio_GetPriority(InstancePtr) \ @@ -1532,7 +1398,7 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_IMP_MRIR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_RST_REQ_PRIO_MASK) | \ + XSRIO_IMP_MRIR_OFFSET) & ~XSRIO_IMP_MRIR_REQ_PRIO_MASK) | \ ((Value << XSRIO_IMP_MRIR_REQ_PRIO_SHIFT)& \ XSRIO_IMP_MRIR_REQ_PRIO_MASK)))) @@ -1578,7 +1444,7 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_IMP_MRIR_OFFSET, \ ((XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_IMP_MRIR_OFFSET) & XSRIO_IMP_MRIR_REQ_RST_TID_MASK) | \ + XSRIO_IMP_MRIR_OFFSET) & ~XSRIO_IMP_MRIR_REQ_TID_MASK) | \ ((Value << XSRIO_IMP_MRIR_REQ_TID_SHIFT)& \ XSRIO_IMP_MRIR_REQ_TID_MASK)))) @@ -1601,8 +1467,8 @@ typedef struct XSrio { (XSrio_WriteReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ERR_STS_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ - XSRIO_PORT_N_ERR_STS_CSR_OFFSET) \ - | (Mask & XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK)))) + XSRIO_PORT_N_ERR_STS_CSR_OFFSET) | \ + (Mask & XSRIO_PORT_N_ERR_STS_CSR_ERR_ALL_MASK)))) /****************************************************************************/ /** @@ -1622,7 +1488,7 @@ typedef struct XSrio { #define XSrio_GetPortErrorStatus(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_ERR_STS_CSR_OFFSET) & \ - XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK) + XSRIO_PORT_N_ERR_STS_CSR_ERR_ALL_MASK) /****************************************************************************/ /** @@ -1644,7 +1510,7 @@ typedef struct XSrio { XSRIO_PORT_N_CTL_CSR_OFFSET, \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) \ - | (Mask & XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK)))) + | (Mask & XSRIO_PORT_N_CTL_CSR_STATUS_ALL_MASK)))) /****************************************************************************/ /** @@ -1664,7 +1530,7 @@ typedef struct XSrio { #define XSrio_GetPortControlStatus(InstancePtr) \ (XSrio_ReadReg((InstancePtr)->Config.BaseAddress, \ XSRIO_PORT_N_CTL_CSR_OFFSET) & \ - XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK) + XSRIO_PORT_N_CTL_CSR_STATUS_ALL_MASK) /*************************** Function Prototypes ******************************/ /** @@ -1676,6 +1542,10 @@ XSrio_Config *XSrio_LookupConfig(u32 DeviceId); int XSrio_GetPortStatus(XSrio *InstancePtr); int XSrio_GetPEType(XSrio *InstancePtr); int XSrio_IsOperationSupported(XSrio * InstancePtr, u8 Operation, u8 Direction); +void XSrio_SetWaterMark(XSrio *InstancePtr, u8 WaterMark0, u8 WaterMark1, + u8 WaterMark2); +void XSrio_GetWaterMark(XSrio *InstancePtr, u8 *WaterMark0, u8 *WaterMark1, + u8 *WaterMark2); #ifdef __cplusplus } diff --git a/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h b/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h index 6f28e97f..c6a39cc6 100755 --- a/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h +++ b/XilinxProcessorIPLib/drivers/srio/src/xsrio_hw.h @@ -75,7 +75,7 @@ extern "C" { */ /** - * Capability Address Register Space 0x00-0x3C Resisters + * Capability Address Register Space 0x00-0x3C Registers */ #define XSRIO_DEV_ID_CAR_OFFSET 0x00 /**< Device Identity CAR */ #define XSRIO_DEV_INFO_CAR_OFFSET 0x04 /**< Device Information CAR */ @@ -109,41 +109,43 @@ extern "C" { /** * Extended Feature Register Space 0x0100-0xFFFC Registers */ -#define XSRIO_EFB_HEADER_OFFSET 0x100 /**< Extended features LP Serial - * Register Block Header - */ -#define XSRIO_PORT_TOUT_CSR_OFFSET 0x120 /**< Port Link Timeout CSR */ -#define XSRIO_RSP_TOUT_CSR_OFFSET 0x124 /**< Port Response Timeout CSR */ -#define XSRIO_GEN_CTL_CSR_OFFSET 0x13c /**< General Control CSR */ -#define XSRIO_PORT_N_MNT_REQ_CSR_OFFSET 0x140 /**< Port n Link Maintenance - * Request CSR - */ -#define XSRIO_PORT_N_MNT_RES_CSR_OFFSET 0X144 /**< Port n Maintenance - * Response CSR - */ -#define XSRIO_PORT_N_ACKID_CSR_OFFSET 0x148 /**< Port n Local Ack ID CSR */ -#define XSRIO_PORT_N_ERR_STS_CSR_OFFSET 0x158 /**< Port n Error and - * Status CSR - */ -#define XSRIO_PORT_N_CTL_CSR_OFFSET 0x15c /**< Port n Control CSR */ -#define XSRIO_EFB_LPSL_OFFSET 0x0400 /**< LP-Serial Lane Extended - * Features offset - */ -#define XSRIO_SL_HEADER_OFFSET 0x00 /**< Serial Lane Block Header */ -#define XSRIO_SLS0_CSR_OFFSET(x) (0x10 + x*0x20) - /**< Serial Lane N - * Status 0 CSR - */ -#define XSRIO_SLS1_CSR_OFFSET(x) (0x14 + x*0x20) - /**< Serial Lane N - * Status 1 CSR - */ +#define XSRIO_EFB_HEADER_OFFSET 0x100 /**< Extended features LP + * Serial Register Block Header + */ +#define XSRIO_PORT_LINK_TOUT_CSR_OFFSET 0x120 /**< Port Link Timeout CSR */ +#define XSRIO_PORT_RESP_TOUT_CSR_OFFSET 0x124 /**< Port Response Timeout + * CSR + */ +#define XSRIO_PORT_GEN_CTL_CSR_OFFSET 0x13c /**< General Control CSR */ +#define XSRIO_PORT_N_MNT_REQ_CSR_OFFSET 0x140 /**< Port n Link Maintenance + * Request CSR + */ +#define XSRIO_PORT_N_MNT_RES_CSR_OFFSET 0x144 /**< Port n Maintenance + * Response CSR + */ +#define XSRIO_PORT_N_ACKID_CSR_OFFSET 0x148 /**< Port n Local Ack ID CSR */ +#define XSRIO_PORT_N_ERR_STS_CSR_OFFSET 0x158 /**< Port n Error and + * Status CSR + */ +#define XSRIO_PORT_N_CTL_CSR_OFFSET 0x15c /**< Port n Control CSR */ +#define XSRIO_EFB_LPSL_OFFSET 0x0400 /**< LP-Serial Lane Extended + * Features offset + */ +#define XSRIO_SL_HEADER_OFFSET 0x00 /**< Serial Lane Block Header */ +#define XSRIO_SLS0_CSR_OFFSET(n) (0x10 + n*0x20) + /**< Serial Lane N + * Status 0 CSR + */ +#define XSRIO_SLS1_CSR_OFFSET(n) (0x14 + n*0x20) + /**< Serial Lane N + * Status 1 CSR + */ /** * Implementation Defined Space 0x010000 - 0xFFFFFC Registers */ #define XSRIO_IMP_WCSR_OFFSET 0x10000 /**< Water Mark CSR */ #define XSRIO_IMP_BCSR_OFFSET 0x10004 /**< Buffer Control CSR */ -#define XSRIO_IMP_MRIR_OFFSET 0x10100 /**< Maintenace Request +#define XSRIO_IMP_MRIR_OFFSET 0x10100 /**< Maintenance Request * Information Register */ @@ -159,14 +161,14 @@ extern "C" { #define XSRIO_DEV_ID_DEVID_CAR_SHIFT 16 /**< Device ID shift */ /*@}*/ -/** @name Device Inforamtion CAR bit definitions. +/** @name Device Information CAR bit definitions. * These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register. * @{ */ -#define XSRIO_DEV_INFO_PATCH_CAR_MASK 0x0000000F /**< Patch Mask */ -#define XSRIO_DEV_INFO_MINREV_CAR_MASK 0x000000F0 /**< Minor Revision Mask */ -#define XSRIO_DEV_INFO_MAJREV_CAR_MASK 0x00000F00 /**< Major Revision Mask */ -#define XSRIO_DEV_INFO_DREV_CAR_MASK 0x000F0000 /**< Device Revision +#define XSRIO_DEV_INFO_CAR_PATCH_MASK 0x0000000F /**< Patch Mask */ +#define XSRIO_DEV_INFO_CAR_MINREV_MASK 0x000000F0 /**< Minor Revision Mask */ +#define XSRIO_DEV_INFO_CAR_MAJREV_MASK 0x00000F00 /**< Major Revision Mask */ +#define XSRIO_DEV_INFO_CAR_DEVREV_MASK 0x000F0000 /**< Device Revision * Lable Mask */ /*@}*/ @@ -175,41 +177,43 @@ extern "C" { * These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register. * @{ */ -#define XSRIO_ASM_ID_ASMID_CAR_MASK 0xFFFF0000 /**< Assembly ID Mask */ -#define XSRIO_ASM_ID_ASMVID_CAR_MASK 0x0000FFFF /**< Assembly Vendor ID Mask */ +#define XSRIO_ASM_ID_CAR_ASMID_MASK 0xFFFF0000 /**< Assembly ID Mask */ +#define XSRIO_ASM_ID_CAR_ASMVID_MASK 0x0000FFFF /**< Assembly Vendor ID Mask */ -#define XSRIO_ASM_ID_ASMID_CAR_SHIFT 16 /**< Assembly ID Shift */ +#define XSRIO_ASM_ID_CAR_ASMID_SHIFT 16 /**< Assembly ID Shift */ /*@}*/ /** @name Assembly Device Information CAR bit definitions. * These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register. * @{ */ -#define XSRIO_ASM_INFO_ASR_CAR_MASK 0xFFFF0000 /**< Assembly Revision Mask */ -#define XSRIO_ASM_INFO_EFP_CAR_MASK 0x0000FFFF /**< Extended Features - * Pointer Mask - */ +#define XSRIO_ASM_INFO_CAR_ASMREV_MASK 0xFFFF0000 /**< Assembly Revision + * Mask + */ +#define XSRIO_ASM_INFO_CAR_EFP_MASK 0x0000FFFF /**< Extended Features + * Pointer Mask + */ -#define XSRIO_ASM_INFO_ASR_CAR_SHIFT 16 /**< Assembly Revision Shift */ +#define XSRIO_ASM_INFO_CAR_ASMREV_SHIFT 16 /**< Assembly Revision Shift */ /*@}*/ /** @name Processing Element Features CAR bit definitions. * These bits are associated with the XSRIO_PEF_CAR_OFFSET register. * @{ */ -#define XSRIO_PEF_EAS_CAR_MASK 0x00000007 /**< Extended Addressing +#define XSRIO_PEF_CAR_EAS_MASK 0x00000007 /**< Extended Addressing * Support Mask */ -#define XSRIO_PEF_EF_CAR_MASK 0x00000008 /**< Extended Features Mask */ -#define XSRIO_PEF_CTS_CAR_MASK 0x00000010 /**< Common Transport Large +#define XSRIO_PEF_CAR_EF_MASK 0x00000008 /**< Extended Features Mask */ +#define XSRIO_PEF_CAR_CTS_MASK 0x00000010 /**< Common Transport Large * System support Mask */ -#define XSRIO_PEF_CRF_CAR_MASK 0x00000020 /**< CRF Support Mask */ -#define XSRIO_PEF_MPORT_CAR_MASK 0x08000000 /**< Multi Port Mask */ -#define XSRIO_PEF_SWITCH_CAR_MASK 0x10000000 /**< Switch Mask */ -#define XSRIO_PEF_PROCESSOR_CAR_MASK 0x20000000 /**< Processor Mask */ -#define XSRIO_PEF_MEMORY_CAR_MASK 0x40000000 /**< Memory Mask */ -#define XSRIO_PEF_BRIDGE_CAR_MASK 0x80000000 /**< Bridge Mask */ +#define XSRIO_PEF_CAR_CRF_MASK 0x00000020 /**< CRF Support Mask */ +#define XSRIO_PEF_CAR_MPORT_MASK 0x08000000 /**< Multi Port Mask */ +#define XSRIO_PEF_CAR_SWITCH_MASK 0x10000000 /**< Switch Mask */ +#define XSRIO_PEF_CAR_PROCESSOR_MASK 0x20000000 /**< Processor Mask */ +#define XSRIO_PEF_CAR_MEMORY_MASK 0x40000000 /**< Memory Mask */ +#define XSRIO_PEF_CAR_BRIDGE_MASK 0x80000000 /**< Bridge Mask */ /*@}*/ /** @name Source Operations CAR bit definitions. @@ -217,49 +221,49 @@ extern "C" { * register and XSRIO_DST_OPS_CAR register. * @{ */ -#define XSRIO_SRCDST_OPS_PORT_WRITE_CAR_MASK 0x00000004 /**< Port write +#define XSRIO_SRCDST_OPS_CAR_PORT_WRITE_MASK 0x00000004 /**< Port write * operation Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_SWP_CAR_MASK 0x00000008 /**< Atomic Swap +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_SWP_MASK 0x00000008 /**< Atomic Swap * Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_CLR_CAR_MASK 0x00000010 /**< Atomic Clear +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_CLR_MASK 0x00000010 /**< Atomic Clear * Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_SET_CAR_MASK 0x00000020 /**< Atomic Set +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_SET_MASK 0x00000020 /**< Atomic Set * Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_DCR_CAR_MASK 0x00000040 /**< Atomic +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_DECR_MASK 0x00000040 /**< Atomic * Decrement Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_INCR_CAR_MASK 0x00000080 /**< Atomic +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_INCR_MASK 0x00000080 /**< Atomic * Increment Mask */ -#define XSRIO_SRCDST_OPS_ATOMIC_TSWP_CAR_MASK 0x00000100 /**< Atomic test +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_TSWP_MASK 0x00000100 /**< Atomic test * and swap Mask */ -#define XSRIO_SRCDST_OPS_ATIOMIC_CSWP_CAR_MASK 0x00000200 /**< Atomic compare +#define XSRIO_SRCDST_OPS_CAR_ATOMIC_CSWP_MASK 0x00000200 /**< Atomic compare * and Swap Mask */ -#define XSRIO_SRCDST_OPS_DOORBELL_CAR_MASK 0x00000400 /**< Doorbell Mask */ -#define XSRIO_SRCDST_OPS_DATA_MSG_CAR_MASK 0x00000800 /**< Data Message +#define XSRIO_SRCDST_OPS_CAR_DOORBELL_MASK 0x00000400 /**< Doorbell Mask */ +#define XSRIO_SRCDST_OPS_CAR_DATA_MSG_MASK 0x00000800 /**< Data Message * Mask */ -#define XSRIO_SRCDST_OPS_WRITE_RESPONSE_CAR_MASK 0x00001000 /**< Write with +#define XSRIO_SRCDST_OPS_CAR_WRITE_RESPONSE_MASK 0x00001000 /**< Write with * Response Mask */ -#define XSRIO_SRCDST_OPS_SWRITE_CAR_MASK 0x00002000 /**< Streaming +#define XSRIO_SRCDST_OPS_CAR_SWRITE_MASK 0x00002000 /**< Streaming * Write Mask */ -#define XSRIO_SRCDST_OPS_WRITE_CAR_MASK 0x00004000 /**< Write Mask */ -#define XSRIO_SRCDST_OPS_READ_CAR_MASK 0x00008000 /**< Read Mask */ +#define XSRIO_SRCDST_OPS_CAR_WRITE_MASK 0x00004000 /**< Write Mask */ +#define XSRIO_SRCDST_OPS_CAR_READ_MASK 0x00008000 /**< Read Mask */ /*@}*/ /** @name PE Logical layer Control CSR bit definitions. * These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register. * @{ */ -#define XSRIO_PELL_CTRL_EAC_CSR_MASK 0x00000007 /**< Extended Addressing +#define XSRIO_PELL_CTRL_CSR_EAC_MASK 0x00000007 /**< Extended Addressing * Control Mask */ /*@}*/ @@ -276,20 +280,20 @@ extern "C" { * These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register. * @{ */ -#define XSRIO_BASE_DID_LBDID_CSR_MASK 0x0000FFFF /**< Large Base Device ID +#define XSRIO_BASE_DID_CSR_LBDID_MASK 0x0000FFFF /**< Large Base Device ID * Mask(16-bit device ID) */ -#define XSRIO_BASI_DID_BDID_CSR_MASK 0x00FF0000 /**< Base Device ID +#define XSRIO_BASE_DID_CSR_BDID_MASK 0x00FF0000 /**< Base Device ID * Mask(8-bit device ID) */ -#define XSRIO_BASI_DID_BDID_CSR_SHIFT 16 /**< Base Device ID Shift */ +#define XSRIO_BASE_DID_CSR_BDID_SHIFT 16 /**< Base Device ID Shift */ /*@}*/ /** @name Host Base Device ID CSR bit definitions. * These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register. * @{ */ -#define XSRIO_HOST_DID_LOCK_HBDID_CSR_MASK 0x0000FFFF /**< Host Base +#define XSRIO_HOST_DID_LOCK_CSR_HBDID_MASK 0x0000FFFF /**< Host Base * Device ID Mask */ /*@}*/ @@ -310,30 +314,36 @@ extern "C" { /*@}*/ /** @name Port Link timeout value CSR bit definitions. - * These bits are associated with the XSRIO_PORT_TOUT_CSR_OFFSET register. + * These bits are associated with the XSRIO_PORT_LINK_TOUT_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Timeout Value Mask */ -#define XSRIO_PORT_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Timeout Value Shift */ +#define XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_MASK 0xFFFFFF00 /**< Timeout Value + * Mask + */ +#define XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_SHIFT 8 /**< Timeout Value + * Shift + */ /*@}*/ /** @name Port response timeout value CSR bit definitions. - * These bits are associated with the XSRIO_RSP_TOUT_CSR_OFFSET register. + * These bits are associated with the XSRIO_PORT_RESP_TOUT_CSR_OFFSET register. * @{ */ -#define XSRIO_RSP_TOUT_TOUTVAL_CSR_MASK 0xFFFFFF00 /**< Response Timeout - * Value Mask - */ -#define XSRIO_RSP_TOUT_TOUTVAL_CSR_SHIFT 8 /**< Response Timeout Shift */ +#define XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_MASK 0xFFFFFF00 /**< Response Timeout + * Value Mask + */ +#define XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_SHIFT 8 /**< Response Timeout + * Shift + */ /*@}*/ /** @name Port General Control CSR bit definitions. - * These bits are associated with the XSRIO_GEN_CTL_CSR_OFFSET register. + * These bits are associated with the XSRIO_PORT_GEN_CTL_CSR_OFFSET register. * @{ */ -#define XSRIO_GEN_CTL_DISCOVERED_CSR_MASK 0x20000000 /**< Discovered Mask */ -#define XSRIO_GEN_CTL_MENABLE_CSR_MASK 0x40000000 /**< Master Enable Mask */ -#define XSRIO_GEN_CTL_HOST_CSR_MASK 0x80000000 /**< Host Mask */ +#define XSRIO_PORT_GEN_CTL_CSR_DISCOVERED_MASK 0x20000000 /**< Discovered Mask */ +#define XSRIO_PORT_GEN_CTL_CSR_MENABLE_MASK 0x40000000 /**< Master Enable Mask */ +#define XSRIO_PORT_GEN_CTL_CSR_HOST_MASK 0x80000000 /**< Host Mask */ /*@}*/ @@ -341,18 +351,18 @@ extern "C" { * These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_N_MNT_REQ_CMD_CSR_MASK 0x00000007 /**< Command Mask */ +#define XSRIO_PORT_N_MNT_REQ_CSR_CMD_MASK 0x00000007 /**< Command Mask */ /*@}*/ /** @name Port n maintenance response CSR bit definitions. * These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_N_MNT_RES_LS_CSR_MASK 0x0000001F /**< link status Mask */ -#define XSRIO_PORT_N_MNT_RES_ACKS_CSR_MASK 0x000007E0 /**< Ack ID status +#define XSRIO_PORT_N_MNT_RES_CSR_LS_MASK 0x0000001F /**< link status Mask */ +#define XSRIO_PORT_N_MNT_RES_CSR_ACKS_MASK 0x000007E0 /**< Ack ID status * Mask */ -#define XSRIO_PORT_N_MNT_RES_RVALID_CSR_MASK 0x80000000 /**< Response Valid +#define XSRIO_PORT_N_MNT_RES_CSR_RVALID_MASK 0x80000000 /**< Response Valid * Mask */ /*@}*/ @@ -361,26 +371,26 @@ extern "C" { * These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_N_ACKID_OBACKID_CSR_MASK 0x0000003F /**< Out bound +#define XSRIO_PORT_N_ACKID_CSR_OBACKID_MASK 0x0000003F /**< Out bound * ACK ID Mask */ -#define XSRIO_PORT_N_ACKID_OSACKID_CSR_MASK 0x00003F00 /**< Out Standing +#define XSRIO_PORT_N_ACKID_CSR_OSACKID_MASK 0x00003F00 /**< Out Standing * ACK ID Mask */ -#define XSRIO_PORT_N_ACKID_IBACKID_CSR_MASK 0x3F000000 /**< In bound +#define XSRIO_PORT_N_ACKID_CSR_IBACKID_MASK 0x3F000000 /**< In bound * ACK ID Mask */ -#define XSRIO_PORT_N_ACKID_CLSACKID_CSR_MASK 0x80000000 /**< Clear +#define XSRIO_PORT_N_ACKID_CSR_CLSACKID_MASK 0x80000000 /**< Clear * Outstanding * ACK ID Mask */ -#define XSRIO_PORT_N_ACKID_RESET_OBACKID_CSR_MASK 0xFFFFFFC0 /**< Out bound ACK +#define XSRIO_PORT_N_ACKID_CSR_RESET_OBACKID_MASK 0xFFFFFFC0 /**< Out bound ACK * ID Reset Mask */ -#define XSRIO_PORT_N_ACKID_RESET_IBACKID_CSR_MASK 0xC0FFFFFF /**< In bound ACK +#define XSRIO_PORT_N_ACKID_CSR_RESET_IBACKID_MASK 0xC0FFFFFF /**< In bound ACK * ID Reset Mask */ -#define XSRIO_PORT_N_ACKID_IBACKID_CSR_SHIFT 24 /**< In bound +#define XSRIO_PORT_N_ACKID_CSR_IBACKID_SHIFT 24 /**< In bound * ACK ID shift */ /*@}*/ @@ -389,99 +399,99 @@ extern "C" { * These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_N_ERR_STS_PUINT_CSR_MASK 0x00000001 /**< Port +#define XSRIO_PORT_N_ERR_STS_CSR_PUINT_MASK 0x00000001 /**< Port * un-initialized Mask */ -#define XSRIO_PORT_N_ERR_STS_POK_CSR_MASK 0x00000002 /**< Port Ok Mask */ -#define XSRIO_PORT_N_ERR_STS_PERR_CSR_MASK 0x00000004 /**< Port Error Mask */ -#define XSRIO_PORT_N_ERR_STS_IERRS_CSR_MASK 0x00000100 /**< Input Error +#define XSRIO_PORT_N_ERR_STS_CSR_POK_MASK 0x00000002 /**< Port Ok Mask */ +#define XSRIO_PORT_N_ERR_STS_CSR_PERR_MASK 0x00000004 /**< Port Error Mask */ +#define XSRIO_PORT_N_ERR_STS_CSR_IERRS_MASK 0x00000100 /**< Input Error * stopped Mask */ -#define XSRIO_PORT_N_ERR_STS_IERRE_CSR_MASK 0x00000200 /**< Input Error +#define XSRIO_PORT_N_ERR_STS_CSR_IERRE_MASK 0x00000200 /**< Input Error * encountered Mask */ -#define XSRIO_PORT_N_ERR_STS_IRTS_CSR_MASK 0x00000400 /**< Input Retry +#define XSRIO_PORT_N_ERR_STS_CSR_IRTS_MASK 0x00000400 /**< Input Retry * Stopped Mask */ -#define XSRIO_PORT_N_ERR_STS_OERRS_CSR_MASK 0x00010000 /**< Output error +#define XSRIO_PORT_N_ERR_STS_CSR_OERRS_MASK 0x00010000 /**< Output error * Stopped Mask */ -#define XSRIO_PORT_N_ERR_STS_OERRE_CSR_MASK 0x00020000 /**< Output error +#define XSRIO_PORT_N_ERR_STS_CSR_OERRE_MASK 0x00020000 /**< Output error * encountered Mask */ -#define XSRIO_PORT_N_ERR_STS_ORTS_CSR_MASK 0x00040000 /**< Output Retry +#define XSRIO_PORT_N_ERR_STS_CSR_ORTS_MASK 0x00040000 /**< Output Retry * Stopped Mask */ -#define XSRIO_PORT_N_ERR_STS_OR_CSR_MASK 0x00080000 /**< Output +#define XSRIO_PORT_N_ERR_STS_CSR_OR_MASK 0x00080000 /**< Output * Retried Mask */ -#define XSRIO_PORT_N_ERR_STS_ORE_CSR_MASK 0x00100000 /**< Output Retry +#define XSRIO_PORT_N_ERR_STS_CSR_ORE_MASK 0x00100000 /**< Output Retry * Encountered Mask */ -#define XSRIO_PORT_N_ERR_STS_FLOWCNTL_CSR_MASK 0x08000000 /**< Flow Control +#define XSRIO_PORT_N_ERR_STS_CSR_FLOWCNTL_MASK 0x08000000 /**< Flow Control * Mode Mask */ -#define XSRIO_PORT_N_ERR_STS_IDL_SEQ_CSR_MASK 0x20000000 /**< Idle sequence +#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQ_MASK 0x20000000 /**< Idle sequence * Mask */ -#define XSRIO_PORT_N_ERR_STS_IDL_SEQE_CSR_MASK 0x40000000 /**< Idle sequence 2 +#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQE_MASK 0x40000000 /**< Idle sequence 2 * Enable Mask */ -#define XSRIO_PORT_N_ERR_STS_IDL_SEQS_CSR_MASK 0x80000000 /**< Idle sequence 2 +#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQS_MASK 0x80000000 /**< Idle sequence 2 * support Mask */ -#define XSRIO_PORT_N_ERR_STS_ERR_ALL_CSR_MASK 0x001FFF07 /**< Port Errors Mask */ +#define XSRIO_PORT_N_ERR_STS_CSR_ERR_ALL_MASK 0x001FFF07 /**< Port Errors Mask */ /*@}*/ /** @name Port n Control CSR bit definitions. * These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register. * @{ */ -#define XSRIO_PORT_N_CTL_PTYPE_CSR_MASK 0x00000001 /**< Port Type Mask */ -#define XSRIO_PORT_N_CTL_EPWDS_CSR_MASK 0x00003000 /**< Extended Port +#define XSRIO_PORT_N_CTL_CSR_PTYPE_MASK 0x00000001 /**< Port Type Mask */ +#define XSRIO_PORT_N_CTL_CSR_EPWDS_MASK 0x00003000 /**< Extended Port * Width Support Mask */ -#define XSRIO_PORT_N_CTL_EPWOR_CSR_MASK 0x0000C000 /**< Extended Port +#define XSRIO_PORT_N_CTL_CSR_EPWOR_MASK 0x0000C000 /**< Extended Port * Width Override Mask */ -#define XSRIO_PORT_N_CTL_ENUMB_CSR_MASK 0x00020000 /**< Enumeration +#define XSRIO_PORT_N_CTL_CSR_ENUMB_MASK 0x00020000 /**< Enumeration * Boundary Mask */ -#define XSRIO_PORT_N_CTL_MCENT_CSR_MASK 0x00080000 /**< Multi-cast Event +#define XSRIO_PORT_N_CTL_CSR_MCENT_MASK 0x00080000 /**< Multi-cast Event * Participant Mask */ -#define XSRIO_PORT_N_CTL_ERRD_CSR_MASK 0x00100000 /**< Error Checking +#define XSRIO_PORT_N_CTL_CSR_ERRD_MASK 0x00100000 /**< Error Checking * Disable Mask */ -#define XSRIO_PORT_N_CTL_IPE_CSR_MASK 0x00200000 /**< Input port +#define XSRIO_PORT_N_CTL_CSR_IPE_MASK 0x00200000 /**< Input port * enable Mask */ -#define XSRIO_PORT_N_CTL_OPE_CSR_MASK 0x00400000 /**< Output port +#define XSRIO_PORT_N_CTL_CSR_OPE_MASK 0x00400000 /**< Output port * enable Mask */ -#define XSRIO_PORT_N_CTL_PD_CSR_MASK 0x00800000 /**< Output port +#define XSRIO_PORT_N_CTL_CSR_PD_MASK 0x00800000 /**< Output port * disable Mask */ -#define XSRIO_PORT_N_CTL_PWO_CSR_MASK 0x07000000 /**< Port width +#define XSRIO_PORT_N_CTL_CSR_PWO_MASK 0x07000000 /**< Port width * Override Mask */ -#define XSRIO_PORT_N_CTL_RESET_PWO_CSR_MASK 0xF8FFFFFF /**< Port wdith +#define XSRIO_PORT_N_CTL_CSR_RESET_PWO_MASK 0xF8FFFFFF /**< Port width * Override Reset Mask */ -#define XSRIO_PORT_N_CTL_IPW_CSR_MASK 0x38000000 /**< Initialized +#define XSRIO_PORT_N_CTL_CSR_IPW_MASK 0x38000000 /**< Initialized * Port width Mask */ -#define XSRIO_PORT_N_CTL_PW_CSR_MASK 0xc0000000 /**< Port width Mask */ -#define XSRIO_PORT_N_CTRL_CSR_STATUS_ALL_MASK 0x00F00000 /**< Port Status All +#define XSRIO_PORT_N_CTL_CSR_PW_MASK 0xc0000000 /**< Port width Mask */ +#define XSRIO_PORT_N_CTL_CSR_STATUS_ALL_MASK 0x00F00000 /**< Port Status All * Mask */ -#define XSRIO_PORT_N_CTL_PWO_CSR_SHIFT 24 /**< Port width +#define XSRIO_PORT_N_CTL_CSR_PWO_SHIFT 24 /**< Port width * Override Shift */ -#define XSRIO_PORT_N_CTL_PW_CSR_SHIFT 30 /**< Port width - * Shift - */ +#define XSRIO_PORT_N_CTL_CSR_PW_SHIFT 30 /**< Port width + * Shift + */ /*@}*/ /** @name LP -Serial Lane Register Block Header bit definitions. @@ -582,10 +592,6 @@ extern "C" { #define XSRIO_IMP_WCSR_WM2_MASK 0x003F0000 /**< Water Mark 2 Mask */ #define XSRIO_IMP_WCSR_WM1_MASK 0x00003F00 /**< Water Mark 1 Mask */ #define XSRIO_IMP_WCSR_WM0_MASK 0x0000003F /**< Water Mark 0 Mask */ -#define XSRIO_IMP_WCSR_RESET_WM0_MASK 0xFFFFFFC0 /**< Water Mark 0 ResetMask */ -#define XSRIO_IMP_WCSR_RESET_WM1_MASK 0xFFFFC0FF /**< Water Mark 1 ResetMask */ -#define XSRIO_IMP_WCSR_RESET_WM2_MASK 0xFFC0FFFF /**< Water Mark 2 ResetMask */ - #define XSRIO_IMP_WCSR_WM1_SHIFT 8 /**< Water Mark 1 Shift */ #define XSRIO_IMP_WCSR_WM2_SHIFT 16 /**< Water Mark 2 Shift */ /*@}*/ @@ -623,9 +629,6 @@ extern "C" { #define XSRIO_IMP_MRIR_REQ_DESTID_MASK 0x0000FFFF /**< Request Destination * ID Mask */ -#define XSRIO_IMP_MRIR_RST_REQ_DESTID_MASK 0xFFFF0000 -#define XSRIO_IMP_MRIR_RST_REQ_PRIO_MASK 0xFFF9FFFF -#define XSRIO_IMP_MRIR_REQ_RST_TID_MASK 0x00FFFFFF #define XSRIO_IMP_MRIR_REQ_PRIO_SHIFT 17 #define XSRIO_IMP_MRIR_REQ_CRF_SHIFT 16 #define XSRIO_IMP_MRIR_REQ_TID_SHIFT 24