From 5f1cd29c7a80d602f8fb12843468f3f8fda49212 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Tue, 20 Oct 2015 23:52:49 -0700 Subject: [PATCH] vphy: Added API to check the lock status of a PLL. Signed-off-by: Andrei-Liviu Simion Acked-by: Srikanth Vemula --- XilinxProcessorIPLib/drivers/vphy/src/xvphy.c | 48 +++++++++++++------ XilinxProcessorIPLib/drivers/vphy/src/xvphy.h | 1 + 2 files changed, 35 insertions(+), 14 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.c b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.c index 57f8bcee..cbb3fea0 100644 --- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.c +++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.c @@ -986,10 +986,38 @@ u32 XVphy_WaitForResetDone(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, * ******************************************************************************/ u32 XVphy_WaitForPllLock(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) +{ + u32 Status = XST_FAILURE; + u8 Retry = 0; + + do { + XVphy_WaitUs(InstancePtr, 1000); + Status = XVphy_IsPllLocked(InstancePtr, QuadId, ChId); + Retry++; + } while ((Status != XST_SUCCESS) && (Retry < 15)); + + return Status; +} + +/*****************************************************************************/ +/** +* This function will check the status of a PLL lock on the specified channel. +* +* @param InstancePtr is a pointer to the XVphy core instance. +* @param QuadId is the GT quad ID to operate on. +* @param ChId is the channel ID which to operate on. +* +* @return +* - XST_SUCCESS if the specified PLL is locked. +* - XST_FAILURE otherwise. +* +* @note None. +* +******************************************************************************/ +u32 XVphy_IsPllLocked(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) { u32 RegVal; u32 MaskVal; - u8 Retry = 0; if (ChId == XVPHY_CHANNEL_ID_CMN0) { MaskVal = XVPHY_PLL_LOCK_STATUS_QPLL0_MASK; @@ -1007,22 +1035,14 @@ u32 XVphy_WaitForPllLock(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId) else { MaskVal = XVPHY_PLL_LOCK_STATUS_CPLL_MASK(ChId); } + RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, + XVPHY_PLL_LOCK_STATUS_REG); - do { - RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, - XVPHY_PLL_LOCK_STATUS_REG); - if (!(RegVal & MaskVal)){ - XVphy_WaitUs(InstancePtr, 1000); - Retry++; - } - } while ((!(RegVal & MaskVal)) && (Retry < 15)); - - if (Retry == 15){ - return XST_FAILURE; - } - else { + if (RegVal & MaskVal) { return XST_SUCCESS; } + + return XST_FAILURE; } /*****************************************************************************/ diff --git a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h index f4ac5084..026b49ec 100644 --- a/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h +++ b/XilinxProcessorIPLib/drivers/vphy/src/xvphy.h @@ -688,6 +688,7 @@ u32 XVphy_WaitForPmaResetDone(XVphy *InstancePtr, u8 QuadId, u32 XVphy_WaitForResetDone(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir); u32 XVphy_WaitForPllLock(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId); +u32 XVphy_IsPllLocked(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId); u32 XVphy_ResetGtPll(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold); u32 XVphy_ResetGtTxRx(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId,