Copyright � 1995-2014 Xilinx, Inc. All rights reserved.
+ + diff --git a/XilinxProcessorIPLib/drivers/sysmon/examples/xsysmon_extmux_example.c b/XilinxProcessorIPLib/drivers/sysmon/examples/xsysmon_extmux_example.c new file mode 100644 index 00000000..7bc0bdc5 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/sysmon/examples/xsysmon_extmux_example.c @@ -0,0 +1,433 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xsysmon_extmux_example.c +* +* This file contains a design example using the driver functions +* of the System Monitor/ADC driver. This example shows the usage of the +* driver/device in interrupt mode with external mux and XADC in Simulateneous +* Sequencer mode. This example hasn't been tested with the analog inputs +* connected through external mux. It is provided to illustrate the usage of +* external mux. +* +* @note +* +* This code assumes that no Operating System is being used. +* +* +*+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------------- +* 5.00a sdm 08/30/11 First release +* 5.03a bss 04/25/13 Modified SysMonIntrExample function to set +* Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" +#include "xintc.h" +#include "stdio.h" +#include "xil_exception.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#define INTR_ID XPAR_INTC_0_SYSMON_0_VEC_ID + +#define printf xil_printf /* Small foot-print printf function */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +static int SysMonIntrExample(XIntc* IntcInstPtr, + XSysMon* SysMonInstPtr, + u16 SysMonDeviceId, + u16 SysMonIntrId); + + +static void SysMonInterruptHandler(void *CallBackRef); + +static int SysMonSetupInterruptSystem(XIntc* IntcInstPtr, + XSysMon *SysMonPtr, + u16 IntrId ); + +/************************** Variable Definitions ****************************/ + +static XSysMon SysMonInst; /* System Monitor driver instance */ +static XIntc IntcInst; /* Instance of the XIntc driver */ + +volatile static int EosFlag = FALSE; /* EOS interrupt */ + +/****************************************************************************/ +/** +* +* Main function that invokes the Interrupt example. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + + int Status; + + /* + * Run the SysMonitor interrupt example, specify the parameters that + * are generated in xparameters.h. + */ + Status = SysMonIntrExample(&IntcInst, &SysMonInst, + SYSMON_DEVICE_ID, INTR_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; + +} + +/****************************************************************************/ +/** +* +* This function runs a test on the XADC device using the driver APIs. +* +* The function does the following tasks: +* - Initiate the XADC device driver instance +* - Run self-test on the device +* - Reset the device +* - Set up sequencer registers to continuously monitor the auxiliary +* channel pairs avaibale in XADC +* - Setup interrupt system +* - Enable interrupts +* - Set up configuration registers to start the sequencer in simultaneous +* sampling mode +* - Wait until End of sequence interrupt occurs and read the conversion +* data +* +* @param IntcInstPtr is a pointer to the Interrupt Controller +* driver Instance. +* @param SysMonInstPtr is a pointer to the XSysMon driver Instance. +* @param SysMonDeviceId is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 06/22/08 Modified the function description of the interrupt +* handler +* 2.00a sdm 09/26/08 Added code to return temperature value to the main +* function. TestappPeripheral prints the temperature +* 4.00a ktn 10/22/09 Updated the example to use HAL processor APIs/macros. +* Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +* 5.03a bss 04/25/13 Modified SysMonIntrExample function to set +* Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" +#include "xintc.h" +#include "xil_exception.h" + + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#ifndef TESTAPP_GEN +#define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#define INTR_ID XPAR_INTC_0_SYSMON_0_VEC_ID +#endif + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +int SysMonIntrExample(XIntc* IntcInstancePtr, + XSysMon* SysMonInstPtr, + u16 SysMonDeviceId, + u16 SysMonIntrId, + int *Temp); + +static void SysMonInterruptHandler(void *CallBackRef); + +static int SysMonSetupInterruptSystem(XIntc* IntcInstancePtr, + XSysMon *SysMonPtr, + u16 IntrId ); + +/************************** Variable Definitions ****************************/ + +#ifndef TESTAPP_GEN +static XSysMon SysMonInst; /* System Monitor driver instance */ +static XIntc InterruptController; /* Instance of the XIntc driver. */ +#endif + +/* + * Shared variables used to test the callbacks. + */ +volatile static int TemperatureIntr = FALSE; /* Temperature alarm intr */ +volatile static int VccauxIntr = FALSE; /* VCCAUX alarm interrupt */ + +#ifndef TESTAPP_GEN +/****************************************************************************/ +/** +* +* Main function that invokes the Interrupt example. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + + int Status; + int Temp; + + /* + * Run the SysMonitor interrupt example, specify the parameters that + * are generated in xparameters.h. + */ + Status = SysMonIntrExample(&InterruptController, + &SysMonInst, + SYSMON_DEVICE_ID, + INTR_ID, + &Temp); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} +#endif /* TESTAPP_GEN */ + +/****************************************************************************/ +/** +* +* This function runs a test on the System Monitor/ADC device using the +* driver APIs. +* +* The function does the following tasks: +* - Initiate the System Monitor/ADC device driver instance +* - Run self-test on the device +* - Reset the device +* - Set up alarms for on-chip temperature and VCCAUX +* - Set up sequence registers to continuously monitor on-chip temperature +* and VCCAUX +* - Setup interrupt system +* - Enable interrupts +* - Set up configuration registers to start the sequence +* - Wait until temperature alarm interrupt or VCCAUX alarm interrupt +* occurs +* +* @param IntcInstancePtr is a pointer to the Interrupt Controller +* driver Instance. +* @param SysMonInstPtr is a pointer to the XSysMon driver Instance. +* @param SysMonDeviceId is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 06/22/08 Added printfs and used conversion macros +* 4.00a ktn 10/22/09 Updated the example to use HAL Processor APIs/macros. +* Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +* 5.01a bss 03/13/12 Updated for Zynq. +* 5.03a bss 04/25/13 Modified SysMonIntrExample function to set +* Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" +#include "stdio.h" +#include "xil_exception.h" + +#ifdef XPAR_INTC_0_DEVICE_ID +#include "xintc.h" +#include
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 07/07/08 Changed the example to read 16 bits of data from the +* the ADC data registers. +* 4.00a ktn 10/22/09 Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +* 5.01a bss 03/13/12 Modified while loop condition to wait for EOS bit +* to become high +* 5.03a bss 04/25/13 Modified SysMonLowLevelExample function to set +* Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon_hw.h" +#include "xparameters.h" +#include "xstatus.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define SYSMON_BASEADDR XPAR_SYSMON_0_BASEADDR + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +int SysMonLowLevelExample(u32 BaseAddress); + +/************************** Variable Definitions ****************************/ + +/****************************************************************************/ +/** +* +* Main function that invokes the example given in this file. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + int Status; + + /* + * Run the SysMonitor Low level example, specify the Base Address that + * is generated in xparameters.h. + */ + Status = SysMonLowLevelExample(SYSMON_BASEADDR); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; + +} + +/****************************************************************************/ +/** +* +* This function runs a test on the System Monitor device using the +* basic driver functions. +* The function does the following tasks: +* - Reset the device +* - Setup alarm thresholds for on-chip temperature and VCCAUX. +* - Setup sequence registers to continuously monitor on-chip temperature +* and VCCAUX. +* - Setup configuration registers to start the sequence. +* - Read latest on-chip temperature and VCCAUX, as well as their maximum +* and minimum values. Also check if alarm(s) are set. +* +* @param BaseAddress is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sdm 09/26/08 Added code to return temperature value to the main +* function. TestappPeripheral prints the temperature +* 4.00a ktn 10/22/09 Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +* 5.03a bss 04/25/13 Modified SysMonPolledExample function to set +* Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +int SysMonPolledExample(u16 SysMonDeviceId, int *Temp); + +/************************** Variable Definitions ****************************/ + +static XSysMon SysMonInst; /* System Monitor driver instance */ + +#ifndef TESTAPP_GEN +/****************************************************************************/ +/** +* +* Main function that invokes the polled example in this file. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + + int Status; + int Temp; + + /* + * Run the SysMonitor polled example, specify the Device ID that is + * generated in xparameters.h . + */ + Status = SysMonPolledExample(SYSMON_DEVICE_ID, &Temp); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif /* TESTAPP_GEN */ + +/****************************************************************************/ +/** +* +* This function runs a test on the System Monitor/ADC device using the +* driver APIs. +* This function does the following tasks: +* - Initiate the System Monitor device driver instance +* - Run self-test on the device +* - Setup alarms for on-chip temperature and VCCAUX +* - Setup the sequence registers to continuously monitor on-chip +* temperature and VCCAUX +* - Setup configuration registers to start the sequence +* - Read latest on-chip temperature and VCCAUX, as well as their maximum +* and minimum values. Also check if alarm(s) are set +* +* @param SysMonDeviceId is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 06/22/08 Added printfs and used conversion macros +* 4.00a ktn 10/22/09 Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +* 5.03a bss 04/25/13 Modified SysMonPolledPrintfExample function to +* set Sequencer Mode as Safe mode instead of Single +* channel mode before configuring Sequencer registers. +* CR #703729 +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" +#include "stdio.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + +#define printf xil_printf /* Small foot-print printf function */ + +/************************** Function Prototypes *****************************/ + +static int SysMonPolledPrintfExample(u16 SysMonDeviceId); +static int SysMonFractionToInt(float FloatNum); + +/************************** Variable Definitions ****************************/ + +static XSysMon SysMonInst; /* System Monitor driver instance */ + +/****************************************************************************/ +/** +* +* Main function that invokes the polled example in this file. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + + int Status; + + /* + * Run the SysMonitor polled example, specify the Device ID that is + * generated in xparameters.h. + */ + Status = SysMonPolledPrintfExample(SYSMON_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* This function runs a test on the System Monitor/ADC device using the +* driver APIs. +* This function does the following tasks: +* - Initiate the System Monitor device driver instance +* - Run self-test on the device +* - Setup the sequence registers to continuously monitor on-chip +* temperature, VCCINT and VCCAUX +* - Setup configuration registers to start the sequence +* - Read the latest on-chip temperature, VCCINT and VCCAUX +* +* @param SysMonDeviceId is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a sv 09/04/07 First release +* 4.00a ktn 10/22/09 Updated the example to use HAL Processor APIs/macros. +* Updated the example to use macros that have been +* renamed to remove _m from the name of the macro. +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" +#include "xparameters.h" +#include "xstatus.h" +#include "xintc.h" +#include "xil_exception.h" + + +/************************** Constant Definitions ****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#ifndef TESTAPP_GEN +#define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#define INTR_ID XPAR_INTC_0_SYSMON_0_VEC_ID +#endif + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +int SysMonSingleChannelIntrExample(XIntc* IntcInstancePtr, + XSysMon* SysMonInstPtr, + u16 SysMonDeviceId, + u16 SysMonIntrId); + + +static void SysMonInterruptHandler(void *CallBackRef); + +static int SysMonSetupInterruptSystem(XIntc* IntcInstancePtr, + XSysMon *SysMonPtr, + u16 IntrId ); + +/************************** Variable Definitions ****************************/ + +#ifndef TESTAPP_GEN +static XSysMon SysMonInst; /* System Monitor driver instance */ +static XIntc InterruptController; /* Instance of the XIntc driver. */ +#endif + +/* + * Shared variables used to test the callbacks. + */ +volatile static int EocFlag = FALSE; /* EOC interrupt */ +volatile static int VccintIntr = FALSE; /* VCCINT alarm interrupt */ + + +#ifndef TESTAPP_GEN +/****************************************************************************/ +/** +* +* Main function that invokes the Single Channel Interrupt example. +* +* @param None. +* +* @return +* - XST_SUCCESS if the example has completed successfully. +* - XST_FAILURE if the example has failed. +* +* @note None. +* +*****************************************************************************/ +int main(void) +{ + + int Status; + + /* + * Run the SysMonitor interrupt example, specify the parameters that + * are generated in xparameters.h. + */ + Status = SysMonSingleChannelIntrExample(&InterruptController, + &SysMonInst, + SYSMON_DEVICE_ID, + INTR_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; + +} +#endif /* TESTAPP_GEN */ + +/****************************************************************************/ +/** +* +* This function runs a test on the System Monitor/ADC device using the +* driver APIs. +* +* The function does the following tasks: +* - Initiate the System Monitor/ADC device driver instance +* - Run self-test on the device +* - Reset the device +* - Set up alarm for VCCINT +* - Set up the configuration registers for single channel continuous mode +* for VCCINT channel +* - Setup interrupt system +* - Enable interrupts +* - Wait until the VCCINT alarm interrupt occurs +* +* @param IntcInstancePtr is a pointer to the Interrupt Controller +* driver Instance. +* @param SysMonInstPtr is a pointer to the XSysMon driver Instance. +* @param SysMonDeviceId is the XPAR_
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 07/07/08 Modified the ADC data functions to return 16 bits of +* data. +* 3.00a sdm 09/02/09 Added APIs for V6 SysMon. +* 4.00a ktn 10/22/09 Updated the file to use the HAL processor APIs/macros. +* The macros have been renamed to remove _m from the name +* of the macro. +* 5.00a sdm 06/15/11 Added support for XADC (7 Series Families). +* 5.01a bss 02/28/12 Added support for Zynq. +* 5.02a bss 11/23/12 Added XSysMon_EnableTempUpdate, +* XSysMon_DisableTempUpdate and XSysMon_SetTempWaitCycles +* APIs (CR #679872) +* 5.03a bss 04/25/13 Modified XSysMon_SetSeqChEnables, +* XSysMon_SetSeqAvgEnables, XSysMon_SetSeqInputMode +* and XSysMon_SetSeqAcqTime APIs to check for Safe Mode +* instead of Single Channel mode. CR #703729 +* 7.0 bss 7/25/14 Modified XSysMon_GetAdcData, +* XSysMon_GetMinMaxMeasurement, +* XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables, +* XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables, +* XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables, +* XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold +* and XSysMon_GetAlarmThreshold to support Ultrascale +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Function Prototypes *****************************/ + +/************************** Variable Definitions ****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes a specific XSysMon device/instance. This function +* must be called prior to using the System Monitor/ADC device. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param ConfigPtr points to the XSysMon device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return +* - XST_SUCCESS if successful. +* +* @note The user needs to first call the XSysMon_LookupConfig() API +* which returns the Configuration structure pointer which is +* passed as a parameter to the XSysMon_CfgInitialize() API. +* +******************************************************************************/ +int XSysMon_CfgInitialize(XSysMon *InstancePtr, XSysMon_Config *ConfigPtr, + u32 EffectiveAddr) +{ + /* + * Assert the input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set the values read from the device config and the base address. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddr; + InstancePtr->Config.IncludeInterrupt = ConfigPtr->IncludeInterrupt; + + /* Store the default Waitcycles value in Mask */ + InstancePtr->Mask = XSM_CONVST_WAITCYCLES_DEFAULT << + XSM_CONVST_WAITCYCLES_SHIFT; + + /* + * Indicate the instance is now ready to use, initialized without error + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the device such that it is in a known state. + */ + XSysMon_Reset(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function forces the software reset of the complete SystemMonitor/ADC +* Hard Macro and the SYSMON ADC Core Logic. +* +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note The Control registers in the SystemMonitor/ADC Hard Macro +* are not affected by this reset, only the Status registers +* are reset. +* Refer to the device data sheet for the device status and +* register values after the reset. +* Use the XSysMon_ResetAdc() to reset only the SystemMonitor/ADC +* Hard Macro. +* +******************************************************************************/ +void XSysMon_Reset(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write the reset value to the Software Reset Register (SRR) to + * Reset the device. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_SRR_OFFSET, + XSM_SRR_IPRST_MASK); +} + +/****************************************************************************/ +/** +* +* The functions reads the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return A 32-bit value representing the contents of the Status Register. +* Use the XSM_SR_*_MASK constants defined in xsysmon_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XSysMon_GetStatus(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Status Register and return the value. + */ + return XSysMon_ReadReg(InstancePtr->Config.BaseAddress, XSM_SR_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function reads the contents of Alarm Output Register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return A 32-bit value read from the Alarm Output Register. +* Use the XSM_AOR_*_MASK constants defined in xsysmon_hw.h to +* interpret the value. +* +* @note None. +* +*****************************************************************************/ +u32 XSysMon_GetAlarmOutputStatus(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Alarm Output Register and return the value. + */ + return (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_AOR_OFFSET) & XSM_AOR_ALARM_ALL_MASK); +} + +/****************************************************************************/ +/** +* +* This function starts the ADC conversion in the Single Channel event driven +* sampling mode. The EOC bit in Status Register will be set once the conversion +* is finished. Refer to the device specification for more details. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note The default state of the CONVST bit is a logic 0. The conversion +* is started when the CONVST bit is set to 1 from 0. +* This bit is cleared in this function so that the next conversion +* can be started by setting this bit. +* +*****************************************************************************/ +void XSysMon_StartAdcConversion(XSysMon *InstancePtr) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Modify only CONVST bit using the InstancePtr->Mask, which + stores previously written value in CONVST register */ + + RegVal = (InstancePtr->Mask) | XSM_CONVST_CONVST_MASK; + + /* + * Start the conversion by setting the CONVST bit to 1 and to 0. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_CONVST_OFFSET, RegVal); + + RegVal = (InstancePtr->Mask) & ~(XSM_CONVST_CONVST_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_CONVST_OFFSET, RegVal); +} + +/*****************************************************************************/ +/** +* +* This function resets the SystemMonitor/ADC Hard Macro in the device. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note The Control registers in the SystemMonitor/ADC Hard Macro +* are not affected by this reset, only the Status registers +* are reset. +* This reset causes the ADC to begin with a new conversion. +* Refer to the device data sheet for the device status and +* register values after the reset. +* Use the XSysMon_Reset() API to reset both the SystemMonitor/ADC +* Hard Macro and the SYSMON ADC Core Logic. +* +******************************************************************************/ +void XSysMon_ResetAdc(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Set the reset bit to the ADC Reset Register (ARR) to + * put the SystemMonitor/ADC Hard Macro in Reset. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_ARR_OFFSET, + XSM_ARR_RST_MASK); + /* + * Clear the reset bit to the ADC Reset Register (ARR) to + * release the reset of SystemMonitor/ADC Hard Macro. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_ARR_OFFSET, 0x0); +} + +/****************************************************************************/ +/** +* +* Get the ADC converted data for the specified channel. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Channel is the channel number. Use the XSM_CH_* defined in +* the file xsysmon.h. +* The valid channels are 0 to 5 and 16 to 31 for all the device +* families. Channel 6 is valid for 7 Series and Zynq. +* Channel 13, 14, 15 are valid for Zynq. 32 to 35 are valid for +* Ultrascale. +* +* @return A 16-bit value representing the ADC converted data for the +* specified channel. The System Monitor/ADC device guarantees +* a 10 bit resolution for the ADC converted data and data is the +* 10 MSB bits of the 16 data read from the device. +* +* @note The channels 7,8,9 are used for calibration of the device and +* hence there is no associated data with this channel. +* Please make sure that the proper channel number is passed. +* +*****************************************************************************/ +u16 XSysMon_GetAdcData(XSysMon *InstancePtr, u8 Channel) +{ + u16 AdcData; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((Channel <= XSM_CH_VBRAM) || + ((Channel >= XSM_CH_VCCPINT) && + (Channel <= XSM_CH_AUX_MAX)) || + ((Channel >= XSM_CH_VUSR0) && + (Channel <= XSM_CH_VUSR3))); + + /* + * Read the selected ADC converted data for the specified channel + * and return the value. + */ + if (Channel <= XSM_CH_AUX_MAX) { + AdcData = (u16) (XSysMon_ReadReg(InstancePtr-> + Config.BaseAddress, XSM_TEMP_OFFSET + + (Channel << 2))); + } else { + AdcData = (u16) (XSysMon_ReadReg(InstancePtr-> + Config.BaseAddress, XSM_VUSR0_OFFSET + + ((Channel - XSM_CH_VUSR0) << 2))); + } + + return AdcData; +} + +/****************************************************************************/ +/** +* +* This function gets the calibration coefficient data for the specified +* parameter. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param CoeffType specifies the calibration coefficient +* to be read. Use XSM_CALIB_* constants defined in xsysmon.h to +* specify the calibration coefficient to be read. +* +* @return A 16-bit value representing the calibration coefficient. +* The System Monitor/ADC device guarantees a 10 bit resolution for +* the ADC converted data and data is the 10 MSB bits of the 16 +* data read from the device. +* +* @note None. +* +*****************************************************************************/ +u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType) +{ + u16 CalibData; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(CoeffType <= XSM_CALIB_GAIN_ERROR_COEFF); + + /* + * Read the selected calibration coefficient. + */ + CalibData = (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SUPPLY_CALIB_OFFSET + (CoeffType << 2)); + + return CalibData; +} + +/****************************************************************************/ +/** +* +* This function reads the Minimum/Maximum measurement for one of the +* following parameters : +* - Minimum Temperature (XSM_MIN_TEMP) - All families +* - Minimum VCCINT (XSM_MIN_VCCINT) - All families +* - Minimum VCCAUX (XSM_MIN_VCCAUX) - All families +* - Maximum Temperature (XSM_MAX_TEMP) - All families +* - Maximum VCCINT (XSM_MAX_VCCINT) - All families +* - Maximum VCCAUX (XSM_MAX_VCCAUX) - All families +* - Maximum VCCBRAM (XSM_MAX_VCCBRAM) - 7 series and Zynq only +* - Minimum VCCBRAM (XSM_MIN_VCCBRAM) - 7 series and Zynq only +* - Maximum VCCPINT (XSM_MAX_VCCPINT) - Zynq only +* - Maximum VCCPAUX (XSM_MAX_VCCPAUX) - Zynq only +* - Maximum VCCPDRO (XSM_MAX_VCCPDRO) - Zynq only +* - Minimum VCCPINT (XSM_MIN_VCCPINT) - Zynq only +* - Minimum VCCPAUX (XSM_MIN_VCCPAUX) - Zynq only +* - Minimum VCCPDRO (XSM_MIN_VCCPDRO) - Zynq only +* - Maximum VUSER0 (XSM_MAX_VUSR0) - Ultrascale +* - Maximum VUSER1 (XSM_MAX_VUSR1) - Ultrascale +* - Maximum VUSER2 (XSM_MAX_VUSR2) - Ultrascale +* - Maximum VUSER3 (XSM_MAX_VUSR3) - Ultrascale +* - Minimum VUSER0 (XSM_MIN_VUSR0) - Ultrascale +* - Minimum VUSER1 (XSM_MIN_VUSR1) - Ultrascale +* - Minimum VUSER2 (XSM_MIN_VUSR2) - Ultrascale +* - Minimum VUSER3 (XSM_MIN_VUSR3) - Ultrascale +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param MeasurementType specifies the parameter for which the +* Minimum/Maximum measurement has to be read. +* Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmon.h to +* specify the data to be read. +* +* @return A 16-bit value representing the maximum/minimum measurement for +* specified parameter. +* The System Monitor/ADC device guarantees a 10 bit resolution for +* the ADC converted data and data is the 10 MSB bits of 16 bit +* data read from the device. +* +*****************************************************************************/ +u16 XSysMon_GetMinMaxMeasurement(XSysMon *InstancePtr, u8 MeasurementType) +{ + u16 MinMaxData; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((MeasurementType <= XSM_MAX_VCCPDRO) || + ((MeasurementType >= XSM_MIN_VCCPINT) && + (MeasurementType <= XSM_MIN_VCCPDRO)) || + ((MeasurementType >= XSM_MAX_VUSR0) && + (MeasurementType <= XSM_MAX_VUSR3)) || + ((MeasurementType >= XSM_MIN_VUSR0) && + (MeasurementType <= XSM_MIN_VUSR3))) + + + /* + * Read and return the specified Minimum/Maximum measurement. + */ + MinMaxData = (u16) (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_MAX_TEMP_OFFSET + (MeasurementType << 2))); + return MinMaxData; +} + +/****************************************************************************/ +/** +* +* This function sets the number of samples of averaging that is to be done for +* all the channels in both the single channel mode and sequence mode of +* operations. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Average is the number of samples of averaging programmed to the +* Configuration Register 0. Use the XSM_AVG_* definitions defined +* in xsysmon.h file : +* - XSM_AVG_0_SAMPLES for no averaging +* - XSM_AVG_16_SAMPLES for 16 samples of averaging +* - XSM_AVG_64_SAMPLES for 64 samples of averaging +* - XSM_AVG_256_SAMPLES for 256 samples of averaging +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XSysMon_SetAvg(XSysMon *InstancePtr, u8 Average) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Average <= XSM_AVG_256_SAMPLES); + + /* + * Write the averaging value into the Configuration Register 0. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR0_OFFSET) & + (~XSM_CFR0_AVG_VALID_MASK); + RegValue |= (((u32) Average << XSM_CFR0_AVG_SHIFT)); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* This function returns the number of samples of averaging configured for all +* the channels in the Configuration Register 0. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return The averaging read from the Configuration Register 0 is +* returned. Use the XSM_AVG_* bit definitions defined in xsysmon.h +* file to interpret the returned value : +* - XSM_AVG_0_SAMPLES means no averaging +* - XSM_AVG_16_SAMPLES means 16 samples of averaging +* - XSM_AVG_64_SAMPLES means 64 samples of averaging +* - XSM_AVG_256_SAMPLES means 256 samples of averaging +* +* @note None. +* +*****************************************************************************/ +u8 XSysMon_GetAvg(XSysMon *InstancePtr) +{ + u32 Average; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the averaging value from the Configuration Register 0. + */ + Average = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR0_OFFSET) & XSM_CFR0_AVG_VALID_MASK; + + return ((u8) (Average >> XSM_CFR0_AVG_SHIFT)); +} + +/****************************************************************************/ +/** +* +* The function sets the given parameters in the Configuration Register 0 in +* the single channel mode. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Channel is the channel number for conversion. The valid +* channels are 0 to 5, 8, and 16 to 31. Channel 6 is +* valid for 7 series and Zynq XADC. Channel 32 to 35 are valid +* for Ultrascale. +* @param IncreaseAcqCycles is a boolean parameter which specifies whether +* the Acquisition time for the external channels has to be +* increased to 10 ADCCLK cycles (specify TRUE) or remain at the +* default 4 ADCCLK cycles (specify FALSE). This parameter is +* only valid for the external channels. +* @param IsEventMode is a boolean parameter that specifies continuous +* sampling (specify FALSE) or event driven sampling mode (specify +* TRUE) for the given channel. +* @param IsDifferentialMode is a boolean parameter which specifies +* unipolar(specify FALSE) or differential mode (specify TRUE) for +* the analog inputs. The input mode is only valid for the +* external channels. +* @return +* - XST_SUCCESS if the given values were written successfully to +* the Configuration Register 0. +* - XST_FAILURE if the channel sequencer is enabled or the input +* parameters are not valid for the selected channel. +* +* @note +* - The number of samples for the averaging for all the channels +* is set by using the function XSysMon_SetAvg. +* - The calibration of the device is done by doing a ADC +* conversion on the calibration channel(channel 8). The input +* parameters IncreaseAcqCycles, IsDifferentialMode and +* IsEventMode are not valid for this channel. +* +*****************************************************************************/ +int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, + int IncreaseAcqCycles, int IsEventMode, + int IsDifferentialMode) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((Channel <= XSM_CH_VREFN) || + (Channel == XSM_CH_CALIBRATION) || + ((Channel >= XSM_CH_AUX_MIN) && + (Channel <= XSM_CH_AUX_MAX)) || + ((Channel >= XSM_CH_VUSR0) && + (Channel <= XSM_CH_VUSR3))); + Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) || + (IncreaseAcqCycles == FALSE)); + Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); + Xil_AssertNonvoid((IsDifferentialMode == TRUE) || + (IsDifferentialMode == FALSE)); + + /* + * Check if the device is in single channel mode else return failure + */ + if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SINGCHAN)) { + return XST_FAILURE; + } + + /* + * Read the Configuration Register 0. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR0_OFFSET) & XSM_CFR0_AVG_VALID_MASK; + + /* + * Select the number of acquisition cycles. The acquisition cycles is + * only valid for the external channels. + */ + if (IncreaseAcqCycles == TRUE) { + if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX)) + || (Channel == XSM_CH_VPVN)) { + RegValue |= XSM_CFR0_ACQ_MASK; + } else { + return XST_FAILURE; + } + } + + /* + * Select the input mode. The input mode is only valid for the + * external channels. + */ + if (IsDifferentialMode == TRUE) { + + if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX)) + || (Channel == XSM_CH_VPVN)) { + RegValue |= XSM_CFR0_DU_MASK; + } else { + return XST_FAILURE; + } + } + + /* + * Select the ADC mode. + */ + if (IsEventMode == TRUE) { + RegValue |= XSM_CFR0_EC_MASK; + } + + /* + * Write the given values into the Configuration Register 0. + */ + RegValue |= (Channel & XSM_CFR0_CHANNEL_MASK); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET, + RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function enables the alarm outputs for the specified alarms in the +* Configuration Registers 1 and 3: +* +* - OT for Over Temperature (XSM_CFR_OT_MASK) +* - ALM0 for On board Temperature (XSM_CFR_ALM_TEMP_MASK) +* - ALM1 for VCCINT (XSM_CFR_ALM_VCCINT_MASK) +* - ALM2 for VCCAUX (XSM_CFR_ALM_VCCAUX_MASK) +* - ALM3 for VBRAM (XSM_CFR_ALM_VBRAM_MASK)for 7 Series and Zynq +* - ALM4 for VCCPINT (XSM_CFR_ALM_VCCPINT_MASK) for Zynq +* - ALM5 for VCCPAUX (XSM_CFR_ALM_VCCPAUX_MASK) for Zynq +* - ALM6 for VCCPDRO (XSM_CFR_ALM_VCCPDRO_MASK) for Zynq +* - ALM8 for VUSER0 (XSM_CFR_ALM_VUSR0_MASK) for Ultrascale +* - ALM9 for VUSER1 (XSM_CFR_ALM_VUSR1_MASK) for Ultrascale +* - ALM10 for VUSER2 (XSM_CFR_ALM_VUSR2_MASK) for Ultrascale +* - ALM11 for VUSER3 (XSM_CFR_ALM_VUSR3_MASK) for Ultrascale +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled +* in the Configuration Register 1. +* Bit positions of 1 will be enabled. Bit positions of 0 will be +* disabled. This mask is formed by OR'ing XSM_CFR_ALM_*_MASK, +* XSM_CFR_ALM_*_MASK and XSM_CFR_OT_MASK masks defined in +* xsysmon_hw.h. +* +* @return None. +* +* @note The implementation of the alarm enables in the Configuration +* register 1 is such that the alarms for bit positions of 1 will +* be disabled and alarms for bit positions of 0 will be enabled. +* The alarm outputs specified by the AlmEnableMask are negated +* before writing to the Configuration Register 1. +* +*****************************************************************************/ +void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(AlmEnableMask <= XSM_CFR_ALM_ALL_MASK); + + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET); + RegValue &= (u32)~XSM_CFR1_ALM_ALL_MASK; + RegValue |= (~AlmEnableMask & XSM_CFR1_ALM_ALL_MASK); + + /* + * Enable/disables the alarm enables for the specified alarm bits in the + * Configuration Register 1. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET, + RegValue); + + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR3_OFFSET); + RegValue &= (u32)~XSM_CFR3_ALM_ALL_MASK; + RegValue |= (~(AlmEnableMask >> 16) & XSM_CFR3_ALM_ALL_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR3_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* This function gets the status of the alarm output enables in the +* Configuration Register 1. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return This is the bit-mask of the enabled alarm outputs in the +* Configuration Register 1. Use the masks XSM_CFR_ALM_*, +* XSM_CFR_ALM*_* and XSM_CFR_OT_MASK defined in +* xsysmon_hw.h to interpret the returned value. +* +* Bit positions of 1 indicate that the alarm output is enabled. +* Bit positions of 0 indicate that the alarm output is disabled. +* +* +* @note The implementation of the alarm enables in the Configuration +* register 1 is such that alarms for the bit positions of 1 will +* be disabled and alarms for bit positions of 0 will be enabled. +* The enabled alarm outputs returned by this function is the +* negated value of the the data read from the Configuration +* Register 1. +* +*****************************************************************************/ +u32 XSysMon_GetAlarmEnables(XSysMon *InstancePtr) +{ + u32 RegValue1; + u32 RegValue2; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the status of alarm output enables from the Configuration + * Register 1. + */ + RegValue1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET) & XSM_CFR1_ALM_ALL_MASK; + RegValue1 = (~RegValue1 & XSM_CFR1_ALM_ALL_MASK); + + RegValue2 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR3_OFFSET) & XSM_CFR3_ALM_ALL_MASK; + RegValue2 = (~RegValue2 & XSM_CFR3_ALM_ALL_MASK); + + return ((RegValue2 << 16) | RegValue1); +} + +/****************************************************************************/ +/** +* +* This function enables the specified calibration in the Configuration +* Register 1 : +* +* - XSM_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction +* - XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset +* correction +* - XSM_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor +* offset correction +* - XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor +* gain and offset correction +* - XSM_CFR1_CAL_DISABLE_MASK : No Calibration +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Calibration is the Calibration to be applied. +* Use XSM_CFR1_CAL*_* bits defined in xsysmon_hw.h. +* Multiple calibrations can be enabled at a time by oring the +* XSM_CFR1_CAL_ADC_* and XSM_CFR1_CAL_PS_* bits. +* Calibration can be disabled by specifying +* XSM_CFR1_CAL_DISABLE_MASK; +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XSysMon_SetCalibEnables(XSysMon *InstancePtr, u16 Calibration) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(((Calibration >= XSM_CFR1_CAL_ADC_OFFSET_MASK) && + (Calibration <= XSM_CFR1_CAL_VALID_MASK)) || + (Calibration == XSM_CFR1_CAL_DISABLE_MASK)); + + /* + * Set the specified calibration in the Configuration Register 1. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET); + + RegValue &= (~ XSM_CFR1_CAL_VALID_MASK); + RegValue |= (Calibration & XSM_CFR1_CAL_VALID_MASK); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* This function reads the value of the calibration enables from the +* Configuration Register 1. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return The value of the calibration enables in the Configuration +* Register 1 : +* - XSM_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction +* - XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset +* correction +* - XSM_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset +* correction +* - XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor gain +* and offset correction +* - XSM_CFR1_CAL_DISABLE_MASK : No Calibration +* +* @note None. +* +*****************************************************************************/ +u16 XSysMon_GetCalibEnables(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the calibration enables from the Configuration Register 1. + */ + return (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET) & XSM_CFR1_CAL_VALID_MASK; +} + +/****************************************************************************/ +/** +* +* This function sets the specified Channel Sequencer Mode in the Configuration +* Register 1 : +* - Default safe mode (XSM_SEQ_MODE_SAFE) +* - One pass through sequence (XSM_SEQ_MODE_ONEPASS) +* - Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS) +* - Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN) +* - Simulataneous sampling mode (XSM_SEQ_MODE_SIMUL) +* - Independent mode (XSM_SEQ_MODE_INDEPENDENT) +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param SequencerMode is the sequencer mode to be set. +* Use XSM_SEQ_MODE_* bits defined in xsysmon.h. +* +* @return None. +* +* @note Only one of the modes can be enabled at a time. +* +*****************************************************************************/ +void XSysMon_SetSequencerMode(XSysMon *InstancePtr, u8 SequencerMode) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((SequencerMode <= XSM_SEQ_MODE_SIMUL) || + (SequencerMode == XSM_SEQ_MODE_INDEPENDENT)); + + /* + * Set the specified sequencer mode in the Configuration Register 1. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET); + RegValue &= (~ XSM_CFR1_SEQ_VALID_MASK); + RegValue |= ((SequencerMode << XSM_CFR1_SEQ_SHIFT) & + XSM_CFR1_SEQ_VALID_MASK); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* This function gets the channel sequencer mode from the Configuration +* Register 1. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return The channel sequencer mode : +* - XSM_SEQ_MODE_SAFE : Default safe mode +* - XSM_SEQ_MODE_ONEPASS : One pass through sequence +* - XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing +* - XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off +* - XSM_SEQ_MODE_SIMUL : Simulataneous sampling mode +* - XSM_SEQ_MODE_INDEPENDENT : Independent mode +* +* @note None. +* +*****************************************************************************/ +u8 XSysMon_GetSequencerMode(XSysMon *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the channel sequencer mode from the Configuration Register 1. + */ + return ((u8) ((XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR1_OFFSET) & XSM_CFR1_SEQ_VALID_MASK) >> + XSM_CFR1_SEQ_SHIFT)); +} + +/****************************************************************************/ +/** +* +* The function enables the Event mode or Continuous mode in the sequencer mode. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param IsEventMode is a boolean parameter that specifies continuous +* sampling (specify FALSE) or event driven sampling mode (specify +* TRUE) for the given channel. +* +* @return None. +* +* @note The Event mode is only available in 7 Series XADC and Zynq. +* This API should be used only with 7 Series XADC and Zynq . +* +*****************************************************************************/ +void XSysMon_SetSequencerEvent(XSysMon *InstancePtr, int IsEventMode) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); + + /* + * Read the Configuration Register 0. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR0_OFFSET); + + /* + * Set the ADC mode. + */ + if (IsEventMode == TRUE) { + RegValue |= XSM_CFR0_EC_MASK; + } else { + RegValue &= ~XSM_CFR0_EC_MASK; + } + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* The function enables the external mux and connects a channel to the mux. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Channel is the channel number used to connect to the external +* Mux. The valid channels are 0 to 6, 8, and 16 to 31. +* +* @return +* - XST_SUCCESS if the given values were written successfully to +* the Configuration Register 0. +* - XST_FAILURE if the channel sequencer is enabled or the input +* parameters are not valid for the selected channel. +* +* @note The External Mux is only available in 7 Series and Zynq XADC. +* This API should be used only with 7 Series and Zynq XADC. +* +*****************************************************************************/ +void XSysMon_SetExtenalMux(XSysMon *InstancePtr, u8 Channel) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((Channel <= XSM_CH_VREFN) || + (Channel == XSM_CH_CALIBRATION) || + ((Channel >= XSM_CH_AUX_MIN) && + (Channel <= XSM_CH_AUX_MAX))); + + /* + * Read the Configuration Register 0 and the clear the channel selection + * bits. + */ + RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR0_OFFSET); + RegValue &= ~(XSM_CFR0_CHANNEL_MASK); + + /* + * Enable the External Mux and select the channel. + */ + RegValue |= (XSM_CFR0_MUX_MASK | Channel); + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET, + RegValue); +} + +/****************************************************************************/ +/** +* +* The function sets the frequency of the ADCCLK by configuring the DCLK to +* ADCCLK ratio in the Configuration Register #2. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Divisor is clock divisor used to derive ADCCLK from DCLK. +* Valid values of the divisor are +* - 8 to 255 for V5 SysMon. +* - 0 to 255 for V6/7 Series and Zynq XADC. +* Values 0, 1, 2 are all mapped to 2. +* Refer to the device specification for more details. +* +* @return None. +* +* @note - The ADCCLK is an internal clock used by the ADC and is +* synchronized to the DCLK clock. The ADCCLK is equal to DCLK +* divided by the user selection in the Configuration Register 2. +* - There is no Assert on the minimum value of the Divisor. Users +* must take care such that the minimum value of Divisor used is +* 8, in case of V5 SysMon. +* +*****************************************************************************/ +void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write the divisor value into the Configuration Register #2. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR2_OFFSET, + Divisor << XSM_CFR2_CD_SHIFT); + +} + +/****************************************************************************/ +/** +* +* The function gets the ADCCLK divisor from the Configuration Register 2. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return The divisor read from the Configuration Register 2. +* +* @note The ADCCLK is an internal clock used by the ADC and is +* synchronized to the DCLK clock. The ADCCLK is equal to DCLK +* divided by the user selection in the Configuration Register 2. +* +*****************************************************************************/ +u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr) +{ + u16 Divisor; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the divisor value from the Configuration Register 2. + */ + Divisor = (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_CFR2_OFFSET); + + return (u8) (Divisor >> XSM_CFR2_CD_SHIFT); +} + +/****************************************************************************/ +/** +* +* This function enables the specified channels in the ADC Channel Selection +* Sequencer Registers. The sequencer must be in the Safe Mode before writing +* to these registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param ChEnableMask is the bit mask of all the channels to be enabled. +* Use XSM_SEQ_CH_* defined in xsysmon_hw.h to specify the Channel +* numbers. Bit masks of 1 will be enabled and bit mask of 0 will +* be disabled. +* The ChEnableMask is a 64 bit mask that is written to the three +* 16 bit ADC Channel Selection Sequencer Registers. +* +* @return +* - XST_SUCCESS if the given values were written successfully to +* the ADC Channel Selection Sequencer Registers. +* - XST_FAILURE if the channel sequencer is enabled. +* +* @note None. +* +*****************************************************************************/ +int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * The sequencer must be in the Safe Mode before writing + * to these registers. Return XST_FAILURE if the channel sequencer + * is enabled. + */ + if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) { + return XST_FAILURE; + } + + /* + * Enable the specified channels in the ADC Channel Selection Sequencer + * Registers. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ00_OFFSET, + (ChEnableMask & XSM_SEQ00_CH_VALID_MASK)); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ01_OFFSET, + (ChEnableMask >> XSM_SEQ_CH_AUX_SHIFT) & + XSM_SEQ01_CH_VALID_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ08_OFFSET, + (ChEnableMask >> XSM_SEQ_CH_VUSR_SHIFT) & + XSM_SEQ08_CH_VALID_MASK); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function gets the channel enable bits status from the ADC Channel +* Selection Sequencer Registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return Gets the channel enable bits. Use XSM_SEQ_CH_* defined in +* xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1 +* are the channels that are enabled and bit mask of 0 are +* the channels that are disabled. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr) +{ + u32 RegValEnable; + u32 RegValEnable1; + u64 RetVal = 0x0; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the channel enable bits for all the channels from the ADC + * Channel Selection Register. + */ + RegValEnable = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ00_OFFSET) & XSM_SEQ00_CH_VALID_MASK; + RegValEnable |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ01_OFFSET) & XSM_SEQ01_CH_VALID_MASK) << + XSM_SEQ_CH_AUX_SHIFT; + + RegValEnable1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ08_OFFSET) & XSM_SEQ08_CH_VALID_MASK; + + RetVal = RegValEnable1; + RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT); + RetVal = RetVal | RegValEnable; + + return RetVal; +} + +/****************************************************************************/ +/** +* +* This function enables the averaging for the specified channels in the ADC +* Channel Averaging Enable Sequencer Registers. The sequencer must be in +* the Safe Mode before writing to these registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param AvgEnableChMask is the bit mask of all the channels for which +* averaging is to be enabled. Use XSM_SEQ_CH__* defined in +* xsysmon_hw.h to specify the Channel numbers. Averaging will be +* enabled for bit masks of 1 and disabled for bit mask of 0. +* The AvgEnableChMask is a 64 bit mask that is written to the +* three 16 bit ADC Channel Averaging Enable Sequencer Registers. +* +* @return +* - XST_SUCCESS if the given values were written successfully to +* the ADC Channel Averaging Enables Sequencer Registers. +* - XST_FAILURE if the channel sequencer is enabled. +* +* @note None. +* +*****************************************************************************/ +int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * The sequencer must be disabled for writing any of these registers. + * Return XST_FAILURE if the channel sequencer is enabled. + */ + if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) { + return XST_FAILURE; + } + + /* + * Enable/disable the averaging for the specified channels in the + * ADC Channel Averaging Enables Sequencer Registers. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ02_OFFSET, + (AvgEnableChMask & XSM_SEQ02_CH_VALID_MASK)); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ03_OFFSET, + (AvgEnableChMask >> XSM_SEQ_CH_AUX_SHIFT) & + XSM_SEQ03_CH_VALID_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ09_OFFSET, + (AvgEnableChMask >> XSM_SEQ_CH_VUSR_SHIFT) & + XSM_SEQ09_CH_VALID_MASK); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function returns the channels for which the averaging has been enabled +* in the ADC Channel Averaging Enables Sequencer Registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @returns The status of averaging (enabled/disabled) for all the channels. +* Use XSM_SEQ_CH__* defined in xsysmon_hw.h to interpret the +* Channel numbers. Bit masks of 1 are the channels for which +* averaging is enabled and bit mask of 0 are the channels for +* averaging is disabled. +* +* @note None. +* +*****************************************************************************/ +u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr) +{ + u32 RegValAvg; + u32 RegValAvg1; + u64 RetVal = 0x0; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the averaging enable status for all the channels from the + * ADC Channel Averaging Enables Sequencer Registers. + */ + RegValAvg = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ02_OFFSET) & XSM_SEQ02_CH_VALID_MASK; + RegValAvg |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ03_OFFSET) & XSM_SEQ03_CH_VALID_MASK) << + XSM_SEQ_CH_AUX_SHIFT; + + RegValAvg1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ09_OFFSET) & XSM_SEQ09_CH_VALID_MASK; + + RetVal = RegValAvg1; + RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT); + RetVal = RetVal | RegValAvg; + + return RetVal; +} + +/****************************************************************************/ +/** +* +* This function sets the Analog input mode for the specified channels in the +* ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in +* the Safe Mode before writing to these registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param InputModeChMask is the bit mask of all the channels for which +* the input mode is differential mode. Use XSM_SEQ_CH__* defined +* in xsysmon_hw.h to specify the channel numbers. Differential +* input mode will be set for bit masks of 1 and unipolar input +* mode for bit masks of 0. +* The InputModeChMask is a 32 bit mask that is written to the two +* 16 bit ADC Channel Analog-Input Mode Sequencer Registers. +* +* @return +* - XST_SUCCESS if the given values were written successfully to +* the ADC Channel Analog-Input Mode Sequencer Registers. +* - XST_FAILURE if the channel sequencer is enabled. +* +* @note None. +* +*****************************************************************************/ +int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * The sequencer must be in the Safe Mode before writing to + * these registers. Return XST_FAILURE if the channel sequencer + * is enabled. + */ + if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) { + return XST_FAILURE; + } + + /* + * Set the input mode for the specified channels in the ADC Channel + * Analog-Input Mode Sequencer Registers. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ04_OFFSET, + (InputModeChMask & XSM_SEQ04_CH_VALID_MASK)); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ05_OFFSET, + (InputModeChMask >> XSM_SEQ_CH_AUX_SHIFT) & + XSM_SEQ05_CH_VALID_MASK); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function gets the Analog input mode for all the channels from +* the ADC Channel Analog-Input Mode Sequencer Registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @returns The input mode for all the channels. +* Use XSM_SEQ_CH_* defined in xsysmon_hw.h to interpret the +* Channel numbers. Bit masks of 1 are the channels for which +* input mode is differential and bit mask of 0 are the channels +* for which input mode is unipolar. +* +* @note None. +* +*****************************************************************************/ +u32 XSysMon_GetSeqInputMode(XSysMon *InstancePtr) +{ + u32 InputMode; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Get the input mode for all the channels from the ADC Channel + * Analog-Input Mode Sequencer Registers. + */ + InputMode = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ04_OFFSET) & XSM_SEQ04_CH_VALID_MASK; + InputMode |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ05_OFFSET) & XSM_SEQ05_CH_VALID_MASK) << + XSM_SEQ_CH_AUX_SHIFT; + + return InputMode; +} + +/****************************************************************************/ +/** +* +* This function sets the number of Acquisition cycles in the ADC Channel +* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode +* before writing to these registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param AcqCyclesChMask is the bit mask of all the channels for which +* the number of acquisition cycles is to be extended. +* Use XSM_SEQ_CH__* defined in xsysmon_hw.h to specify the Channel +* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles +* for bit masks of 1 and will be the default 4 ADCCLK cycles for +* bit masks of 0. +* The AcqCyclesChMask is a 32 bit mask that is written to the two +* 16 bit ADC Channel Acquisition Time Sequencer Registers. +* +* @return +* - XST_SUCCESS if the given values were written successfully to +* the Channel Sequencer Registers. +* - XST_FAILURE if the channel sequencer is enabled. +* +* @note None. +* +*****************************************************************************/ +int XSysMon_SetSeqAcqTime(XSysMon *InstancePtr, u32 AcqCyclesChMask) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * The sequencer must be in the Safe Mode before writing + * to these registers. Return XST_FAILURE if the channel + * sequencer is enabled. + */ + if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) { + return XST_FAILURE; + } + + /* + * Set the Acquisition time for the specified channels in the + * ADC Channel Acquisition Time Sequencer Registers. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ06_OFFSET, + (AcqCyclesChMask & XSM_SEQ06_CH_VALID_MASK)); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_SEQ07_OFFSET, + (AcqCyclesChMask >> XSM_SEQ_CH_AUX_SHIFT) & + XSM_SEQ07_CH_VALID_MASK); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function gets the status of acquisition from the ADC Channel Acquisition +* Time Sequencer Registers. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @returns The acquisition time for all the channels. +* Use XSM_SEQ_CH__* defined in xsysmon_hw.h to interpret the +* Channel numbers. Bit masks of 1 are the channels for which +* acquisition cycles are extended and bit mask of 0 are the +* channels for which acquisition cycles are not extended. +* +* @note None. +* +*****************************************************************************/ +u32 XSysMon_GetSeqAcqTime(XSysMon *InstancePtr) +{ + u32 RegValAcq; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Get the Acquisition cycles for the specified channels from the ADC + * Channel Acquisition Time Sequencer Registers. + */ + RegValAcq = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ06_OFFSET) & XSM_SEQ06_CH_VALID_MASK; + RegValAcq |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_SEQ07_OFFSET) & XSM_SEQ07_CH_VALID_MASK) << + XSM_SEQ_CH_AUX_SHIFT; + + return RegValAcq; +} + +/****************************************************************************/ +/** +* +* This functions sets the contents of the given Alarm Threshold Register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param AlarmThrReg is the index of an Alarm Threshold Register to +* be set. Use XSM_ATR_* constants defined in xsysmon.h to +* specify the index. +* @param Value is the 16-bit threshold value to write into the register. +* +* @return None. +* +* @note Over Temperature upper threshold is programmable only in V6, +* 7 Series/Zynq XADC and UltraScale. +* BRAM high and low voltage threshold registers are available only +* in 7 Series XADC and UltraScale. +* VUSER0 to VUSER3 threshold registers are available only in +* UltraScale. +* All the remaining Alarm Threshold registers specified by the +* constants XSM_ATR_*, are available in all the families of the +* Sysmon. +* +*****************************************************************************/ +void XSysMon_SetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg, u16 Value) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((AlarmThrReg <= XSM_ATR_VUSR3_UPPER) || + ((AlarmThrReg >= XSM_ATR_VUSR0_LOWER) && + (AlarmThrReg <= XSM_ATR_VUSR3_LOWER))); + + /* + * Write the value into the specified Alarm Threshold Register. + */ + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_ATR_TEMP_UPPER_OFFSET + (AlarmThrReg << 2), + Value); +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the specified Alarm Threshold Register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param AlarmThrReg is the index of an Alarm Threshold Register +* to be read. Use XSM_ATR_* constants defined in xsysmon.h +* to specify the index. +* +* @return A 16-bit value representing the contents of the selected Alarm +* Threshold Register. +* +* @note Over Temperature upper threshold is programmable only in V6 and +* 7 Series XADC +* BRAM high and low voltage threshold registers are available only +* in 7 Series and Zynq XADC. +* All the remaining Alarm Threshold registers specified by the +* constants XSM_ATR_*, are available in all the families of the +* Sysmon. +* +*****************************************************************************/ +u16 XSysMon_GetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg) +{ + u16 AlarmThreshold; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_VUSR3_UPPER) || + ((AlarmThrReg >= XSM_ATR_VUSR0_LOWER) && + (AlarmThrReg <= XSM_ATR_VUSR3_LOWER))); + + /* + * Read the specified Alarm Threshold Register and return + * the value. + */ + AlarmThreshold = (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_ATR_TEMP_UPPER_OFFSET + (AlarmThrReg << 2)); + + return AlarmThreshold; +} + +/****************************************************************************/ +/** +* +* This function sets the powerdown temperature for the OverTemp signal in the +* OT Powerdown register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* @param Value is the 16-bit OT Upper Alarm Register powerdown value. +* Valid values are 0 to 0x0FFF. +* +* @return None. +* +* @note This API has been deprecated. Use XSysMon_SetAlarmThreshold(), +* instead. +* This API should be used only with V6/7 Series since the +* upper threshold of OverTemp is programmable in in only V6 +* SysMon/7 Series and Zynq XADC. +* +*****************************************************************************/ +void XSysMon_SetOverTemp(XSysMon *InstancePtr, u16 Value) +{ + u16 OtUpper; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Value <= XSM_ATR_OT_UPPER_VAL_MAX); + + /* + * Read the OT Upper Alarm Threshold Register. + */ + OtUpper = (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET); + OtUpper &= ~(XSM_ATR_OT_UPPER_VAL_MASK); + + /* + * Preserve the OT enable value and write the powerdown value into the + * OT Upper Alarm Threshold Register. + */ + Value = (Value << XSM_ATR_OT_UPPER_VAL_SHIFT) | OtUpper; + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET, Value); +} + +/****************************************************************************/ +/** +* +* This function returns the powerdown temperature of the OverTemp signal in +* the OT Powerdown register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return A 12-bit OT Upper Alarm Register powerdown value. +* +* @note This API has been deprecated. Use XSysMon_GetAlarmThreshold(), +* instead. +* This API should be used only with V6/7 Series since the +* upper threshold of OverTemp is programmable in only V6 +* SysMon/7 Series and Zynq XADC. +* +*****************************************************************************/ +u16 XSysMon_GetOverTemp(XSysMon *InstancePtr) +{ + u16 OtUpper; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the OT upper Alarm Threshold Register and return + * the value. + */ + OtUpper = (u16) XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET); + OtUpper >>= XSM_ATR_OT_UPPER_VAL_SHIFT; + + return OtUpper; +} + +/****************************************************************************/ +/** +* +* This function enables programming of the powerdown temperature for the +* OverTemp signal in the OT Powerdown register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note This API should be used only with V6/7 Series since the +* upper threshold of OverTemp is programmable in only V6 +* SysMon/7 Series and Zynq XADC. +* +*****************************************************************************/ +void XSysMon_EnableUserOverTemp(XSysMon *InstancePtr) +{ + u16 OtUpper; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the OT upper Alarm Threshold Register. + */ + OtUpper = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET); + OtUpper &= ~(XSM_ATR_OT_UPPER_ENB_MASK); + + /* + * Preserve the powerdown value and write OT enable value the into the + * OT Upper Alarm Threshold Register. + */ + OtUpper |= XSM_ATR_OT_UPPER_ENB_VAL; + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET, OtUpper); +} + +/****************************************************************************/ +/** +* +* This function disables programming of the powerdown temperature for the +* OverTemp signal in the OT Powerdown register. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note This API should be used only with V6 SysMon/7 Series and Zynq +* XADC since the upper threshold of OverTemp is programmable +* in only V6 SysMon/7 Series and Zynq XADC. +* +*****************************************************************************/ +void XSysMon_DisableUserOverTemp(XSysMon *InstancePtr) +{ + u16 OtUpper; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the OT Upper Alarm Threshold Register. + */ + OtUpper = XSysMon_ReadReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET); + OtUpper &= ~(XSM_ATR_OT_UPPER_ENB_MASK); + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_ATR_OT_UPPER_OFFSET, OtUpper); +} + +/****************************************************************************/ +/** +* +* This function enables the Temperature updation logic so that temperature +* can be sent over TEMP_OUT port. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XSysMon_EnableTempUpdate(XSysMon *InstancePtr) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegVal = (InstancePtr->Mask) | XSM_CONVST_TEMPUPDT_MASK ; + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_CONVST_OFFSET, RegVal); + + /* Store the written value in Mask */ + InstancePtr->Mask = RegVal; +} + +/****************************************************************************/ +/** +* +* This function disables the Temperature updation logic for TEMP_OUT port +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XSysMon_DisableTempUpdate(XSysMon *InstancePtr) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = (InstancePtr->Mask) & ~(XSM_CONVST_TEMPUPDT_MASK) ; + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_CONVST_OFFSET, RegVal); + + /* Store the written value in Mask */ + InstancePtr->Mask = RegVal; +} + +/****************************************************************************/ +/** +* +* This function sets the number of Wait Cycles for Temperature updation logic +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return None. +* +* @note The default number of wait cycles are 1000(0x3E8). +* +*****************************************************************************/ +void XSysMon_SetTempWaitCycles(XSysMon *InstancePtr, u16 WaitCycles) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegVal = ((InstancePtr->Mask) & ~(XSM_CONVST_WAITCYCLES_MASK)) ; + + RegVal = (WaitCycles << XSM_CONVST_WAITCYCLES_SHIFT) | RegVal; + + XSysMon_WriteReg(InstancePtr->Config.BaseAddress, + XSM_CONVST_OFFSET, RegVal); + + /* Store the written value in Mask */ + InstancePtr->Mask = RegVal; +} diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h new file mode 100644 index 00000000..88a65143 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.h @@ -0,0 +1,617 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xsysmon.h +* +* The XSysMon driver supports the Xilinx System Monitor/ADC device. +* +* The System Monitor/ADC device has the following features: +* - 10-bit, 200-KSPS (kilo samples per second) +* Analog-to-Digital Converter (ADC) +* - Monitoring of on-chip supply voltages and temperature +* - 1 dedicated differential analog-input pair and +* 16 auxiliary differential analog-input pairs +* - Automatic alarms based on user defined limits for the on-chip +* supply voltages and temperature +* - Automatic Channel Sequencer, programmable averaging, programmable +* acquisition time for the external inputs, unipolar or differential +* input selection for the external inputs +* - Inbuilt Calibration +* - Optional interrupt request generation +* - External Mux (7 Series and Zynq XADC) +* +* +* The user should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the System Monitor/ADC device. +* +* +* System Monitor Channel Sequencer Modes +* +* The System Monitor Channel Sequencer supports the following operating modes: +* +* - Default : This is the default mode after power up. +* In this mode of operation the System Monitor operates in +* a sequence mode, monitoring the on chip sensors: +* Temperature, VCCINT, and VCCAUX. +* - One pass through sequence : In this mode the System Monitor +* converts the channels enabled in the Sequencer Channel Enable +* registers for a single pass and then stops. +* - Continuous cycling of sequence : In this mode the System Monitor +* converts the channels enabled in the Sequencer Channel Enable +* registers continuously. +* - Single channel mode: In this mode the System Monitor Channel +* Sequencer is disabled and the System Monitor operates in a +* Single Channel Mode. +* The System Monitor can operate either in a Continuous or Event +* driven sampling mode in the single channel mode. +* - Simultaneous sampling mode: This mode is available only in +* 7 Series and Zynq XADC devices. In this mode both ADCs sample and +* digitizes two different analog input signals at the same time. +* - Independent ADC mode: This mode is available only in 7 Series and +* Zynq XADC devices. In this mode ADC A is used to implement a +* fixed monitoring mode which is similar to default mode, but the +* fixed alarm functions are enabled. ADC B is available to be used +* with the external analog input channels only. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the System Monitor/ADC device. +* +* XSysMon_CfgInitialize() API is used to initialize the System Monitor/ADC +* device. The user needs to first call the XSysMon_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XSysMon_CfgInitialize() API. +* +* +* Interrupts +* +* The System Monitor/ADC device supports interrupt driven mode and the default +* operation mode is polling mode. +* +* The interrupt mode is available only if hardware is configured to support +* interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* device in interrupt mode. +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XSysMon driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* System Monitor/ADC device can be accessed through the JTAG port and the AXI +* interface. The driver implementation does not support the simultaneous access +* of the device by both these interfaces. The user has to care of this situation +* in the user application code. +* +* +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 07/07/08 Added bit definitions for new Alarm Interrupts in the +* Interrupt Registers. Changed the ADC data functions +* to return 16 bits of data. Added macros for conversion +* from Raw Data to Temperature/Voltage and vice-versa. +* 3.00a sdm 02/09/09 Added APIs and bit definitions for V6 SysMon. +* 4.00a ktn 10/22/09 Updated the driver to use the HAL Processor APIs/macros. +* The macros have been renamed to remove _m from the name +* in all the driver files. +* 5.00a sdm 06/15/11 Added support for XADC 7 Series. +* 5.01a bss 02/28/12 Added support for Zynq, +* renamed XSM_ATR_BRAM_UPPER to XSM_ATR_VBRAM_UPPER +* renamed XSM_ATR_BRAM_LOWER to XSM_ATR_VBRAM_LOWER +* 5.02a bss 11/23/12 Added APIs and Macros to support Temperature Updation +* over TEMP_OUT port(CR #679872) +* 5.03a bss 04/25/13 Modified XSysMon_SetSeqChEnables, +* XSysMon_SetSeqAvgEnables, XSysMon_SetSeqInputMode +* and XSysMon_SetSeqAcqTime APIs to check for Safe Mode +* instead of Single Channel mode(CR #703729) in xsysmon.c +* Modified examples: xsysmon_polled_example.c, +* xsysmon_low_level_example.c, +* xsysmon_intr_printf_example.c, xsysmon_intr_example.c +* xsysmon_extmux_example.c and +* xsysmon_polled_printf_example.c to set Sequencer Mode +* as Safe mode instead of Single channel mode before +* configuring Sequencer registers. +* 6.0 adk 19/12/13 Updated as per the New Tcl API's +* 7.0 bss 7/25/14 To support Ultrascale: +* Added XSM_CH_VUSR0 - XSMXSM_CH_VUSR3,XSM_MAX_VUSR0 - +* XSM_MIN_VUSR3,XSM_ATR_VUSR0_UPPER - +* XSM_ATR_VUSR3_LOWER macros. +* Added XSM_IP_OFFSET macro(since register +* offsets are different for Ultrascale comapared to +* earlier familes),Offsets,Masks for VUSER0 to +* VUSER3 channels, Configuration Register 3 and +* Sequence Registers 8 and 9 in xsysmon_hw.h. +* Modified XSysMon_GetAdcData, +* XSysMon_GetMinMaxMeasurement, +* XSysMon_SetSingleChParams, XSysMon_SetAlarmEnables, +* XSysMon_GetAlarmEnables,XSysMon_SetSeqChEnables, +* XSysMon_GetSeqChEnables,XSysMon_SetSeqAvgEnables, +* XSysMon_GetSeqAvgEnables,XSysMon_SetAlarmThreshold +* and XSysMon_GetAlarmThreshold in xsysmon.c. +* Modified driver tcl to generate XPAR_SYSMON_0_IP_TYPE +* parameter. +* +*+* +*****************************************************************************/ + +#ifndef XSYSMON_H /* Prevent circular inclusions */ +#define XSYSMON_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xsysmon_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Indexes for the different channels. + * @{ + */ +#define XSM_CH_TEMP 0x0 /**< On Chip Temperature */ +#define XSM_CH_VCCINT 0x1 /**< VCCINT */ +#define XSM_CH_VCCAUX 0x2 /**< VCCAUX */ +#define XSM_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ +#define XSM_CH_VREFP 0x4 /**< VREFP */ +#define XSM_CH_VREFN 0x5 /**< VREFN */ +#define XSM_CH_VBRAM 0x6 /**< VBRAM - 7 Series and Zynq */ +#define XSM_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ +#define XSM_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ +#define XSM_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ +#define XSM_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel, Zynq */ +#define XSM_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel, Zynq */ +#define XSM_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel, Zynq */ +#define XSM_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ +#define XSM_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ +#define XSM_CH_VUSR0 32 /**< VUSER0 Supply - UltraScale */ +#define XSM_CH_VUSR1 33 /**< VUSER1 Supply - UltraScale */ +#define XSM_CH_VUSR2 34 /**< VUSER2 Supply - UltraScale */ +#define XSM_CH_VUSR3 35 /**< VUSER3 Supply - UltraScale */ + + +/*@}*/ + + +/** + * @name Indexes for reading the Calibration Coefficient Data. + * @{ + */ +#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0 /**< Supply Offset Calib Coefficient */ +#define XSM_CALIB_ADC_OFFSET_COEFF 1 /**< ADC Offset Calib Coefficient */ +#define XSM_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ + +/*@}*/ + + +/** + * @name Indexes for reading the Minimum/Maximum Measurement Data. + * @{ + */ +#define XSM_MAX_TEMP 0 /**< Maximum Temperature Data */ +#define XSM_MAX_VCCINT 1 /**< Maximum VCCINT Data */ +#define XSM_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ +#define XSM_MAX_VCCBRAM 3 /**< Maximum VCCBRAM Data, 7 Series/Zynq */ +#define XSM_MIN_TEMP 4 /**< Minimum Temperature Data */ +#define XSM_MIN_VCCINT 5 /**< Minimum VCCINT Data */ +#define XSM_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ +#define XSM_MIN_VCCBRAM 7 /**< Minimum VCCBRAM Data, 7 Series/Zynq */ +#define XSM_MAX_VCCPINT 8 /**< Maximum VCCPINT Data, Zynq */ +#define XSM_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Data, Zynq */ +#define XSM_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Data, Zynq */ +#define XSM_MIN_VCCPINT 0xC /**< Minimum VCCPINT Data, Zynq */ +#define XSM_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Data, Zynq */ +#define XSM_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Data, Zynq */ +#define XSM_MAX_VUSR0 0x80 /**< Maximum VUSR0 Data, Ultrascale */ +#define XSM_MAX_VUSR1 0x81 /**< Maximum VUSR1 Data, Ultrascale */ +#define XSM_MAX_VUSR2 0x82 /**< Maximum VUSR2 Data, Ultrascale */ +#define XSM_MAX_VUSR3 0x83 /**< Maximum VUSR3 Data, Ultrascale */ +#define XSM_MIN_VUSR0 0x88 /**< Minimum VUSR0 Data, Ultrascale */ +#define XSM_MIN_VUSR1 0x89 /**< Minimum VUSR1 Data, Ultrascale */ +#define XSM_MIN_VUSR2 0x8A /**< Minimum VUSR2 Data, Ultrascale */ +#define XSM_MIN_VUSR3 0x8B /**< Minimum VUSR3 Data, Ultrascale */ + + +/*@}*/ + + +/** + * @name Alarm Threshold(Limit) Register (ATR) indexes. + * @{ + */ +#define XSM_ATR_TEMP_UPPER 0 /**< High user Temperature */ +#define XSM_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit */ +#define XSM_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit */ +#define XSM_ATR_OT_UPPER 3 /**< Lower Over Temperature limit */ +#define XSM_ATR_TEMP_LOWER 4 /**< Low user Temperature */ +#define XSM_ATR_VCCINT_LOWER 5 /**< VCCINT low voltage limit */ +#define XSM_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit */ +#define XSM_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ +#define XSM_ATR_VBRAM_UPPER 8 /**< VBRAM high voltage limit */ +#define XSM_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm, Zynq */ +#define XSM_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm, 7 Series and Zynq*/ +#define XSM_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm, Zynq */ +#define XSM_ATR_VUSR0_UPPER 0x10 /**< VUSER0 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR1_UPPER 0x11 /**< VUSER1 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR2_UPPER 0x12 /**< VUSER2 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR3_UPPER 0x13 /**< VUSER3 Upper Alarm, Ultrascale */ +#define XSM_ATR_VUSR0_LOWER 0x18 /**< VUSER0 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR1_LOWER 0x19 /**< VUSER1 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR2_LOWER 0x1A /**< VUSER2 Lower Alarm, Ultrascale */ +#define XSM_ATR_VUSR3_LOWER 0x1B /**< VUSER3 Lower Alarm, Ultrascale */ + +/*@}*/ + + +/** + * @name Averaging to be done for the channels. + * @{ + */ +#define XSM_AVG_0_SAMPLES 0 /**< No Averaging */ +#define XSM_AVG_16_SAMPLES 1 /**< Average 16 samples */ +#define XSM_AVG_64_SAMPLES 2 /**< Average 64 samples */ +#define XSM_AVG_256_SAMPLES 3 /**< Average 256 samples */ + +/*@}*/ + + +/** + * @name Channel Sequencer Modes of operation. + * @{ + */ +#define XSM_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ +#define XSM_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ +#define XSM_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Seqquencer */ +#define XSM_SEQ_MODE_SINGCHAN 3 /**< Single channel - No Sequencing */ +#define XSM_SEQ_MODE_SIMUL 4 /**< Simultaneous Cycling Sequencer, + * 7 Series and Zynq XADC only */ +#define XSM_SEQ_MODE_INDEPENDENT 8 /**< Independent ADC Sequencer, + * 7 Series and Zynq XADC only */ + +/*@}*/ + +/* For backwards compatabilty */ +#define XSM_CH_CALIBRATION XSM_CH_ADC_CALIB +#define XSM_ATR_BRAM_UPPER XSM_ATR_VBRAM_UPPER +#define XSM_ATR_BRAM_LOWER XSM_ATR_VBRAM_LOWER + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the System Monitor/ADC + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ + int IncludeInterrupt; /**< Supports Interrupt driven mode */ + u8 IpType; /**< 1 - System Management */ + /**< 0 - XADC/System Monoitor */ +} XSysMon_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every System Monitor/ADC device in the system. A pointer to + * a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSysMon_Config Config; /**< XSysMon_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Mask; /**< Store the previously written value + in CONVST register */ +} XSysMon; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the SysMonitor/ADC device is in Event Sampling mode. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return +* - TRUE if the device is in Event Sampling Mode. +* - FALSE if the device is in Continuous Sampling Mode. +* +* @note C-Style signature: +* int XSysMon_IsEventSamplingMode(XSysMon *InstancePtr); +* +*****************************************************************************/ +#define XSysMon_IsEventSamplingModeSet(InstancePtr) \ + (((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XSM_CFR0_OFFSET) & XSM_CFR0_EC_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro checks if the Dynamic Reconfiguration Port (DRP) transaction from +* the JTAG is in progress. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return +* - TRUE if the DRP transaction from JTAG is in Progress. +* - FALSE if there is no DRP transaction from the JTAG. +* +* @note C-Style signature: +* int XSysMon_IsDrpBusy(XSysMon *InstancePtr); +* +*****************************************************************************/ +#define XSysMon_IsDrpBusy(InstancePtr) \ + ((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XSM_SR_OFFSET) & XSM_SR_JTAG_BUSY_MASK) ? \ + TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro checks if the Dynamic Reconfiguration Port (DRP) is locked by the +* JTAG. +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return +* - TRUE if the DRP is locked by the JTAG. +* - FALSE if the DRP is not locked by the JTAG. +* +* @note C-Style signature: +* int XSysMon_IsDrpLocked(XSysMon *InstancePtr); +* +*****************************************************************************/ +#define XSysMon_IsDrpLocked(InstancePtr) \ + (((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XSM_SR_OFFSET) & XSM_SR_JTAG_LOCKED_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro converts System Monitor/ADC Raw Data to Temperature(centigrades). +* +* @param AdcData is the SysMon Raw ADC Data. +* +* @return The Temperature in centigrades. +* +* @note C-Style signature: +* float XSysMon_RawToTemperature(u32 AdcData); +* +*****************************************************************************/ +#define XSysMon_RawToTemperature(AdcData) \ + ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) + +/****************************************************************************/ +/** +* +* This macro converts System Monitor/ADC Raw Data to Voltage(volts). +* +* @param AdcData is the System Monitor/ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_RawToVoltage(u32 AdcData); +* +*****************************************************************************/ +#define XSysMon_RawToVoltage(AdcData) \ + ((((float)(AdcData))* (3.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts Temperature in centigrades to System Monitor/ADC Raw Data. +* +* @param Temperature is the Temperature in centigrades to be +* converted to System Monitor/ADC Raw Data. +* +* @return The System Monitor/ADC Raw Data. +* +* @note C-Style signature: +* int XSysMon_TemperatureToRaw(float Temperature); +* +*****************************************************************************/ +#define XSysMon_TemperatureToRaw(Temperature) \ + ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) + +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to System Monitor/ADC Raw Data. +* +* @param Voltage is the Voltage in volts to be converted to +* System Monitor/ADC Raw Data. +* +* @return The System Monitor/ADC Raw Data. +* +* @note C-Style signature: +* int XSysMon_VoltageToRaw(float Voltage); +* +*****************************************************************************/ +#define XSysMon_VoltageToRaw(Voltage) \ + ((int)((Voltage)*65536.0f/3.0f)) + + +/************************** Function Prototypes *****************************/ + +/** + * Functions in xsysmon_sinit.c + */ +XSysMon_Config *XSysMon_LookupConfig(u16 DeviceId); + +/** + * Functions in xsysmon.c + */ +int XSysMon_CfgInitialize(XSysMon *InstancePtr, + XSysMon_Config *ConfigPtr, u32 EffectiveAddr); + +void XSysMon_Reset(XSysMon *InstancePtr); + +u32 XSysMon_GetStatus(XSysMon *InstancePtr); + +u32 XSysMon_GetAlarmOutputStatus(XSysMon *InstancePtr); + +void XSysMon_StartAdcConversion(XSysMon *InstancePtr); + +void XSysMon_ResetAdc(XSysMon *InstancePtr); + +u16 XSysMon_GetAdcData(XSysMon *InstancePtr, u8 Channel); + +u16 XSysMon_GetCalibCoefficient(XSysMon *InstancePtr, u8 CoeffType); + +u16 XSysMon_GetMinMaxMeasurement(XSysMon *InstancePtr, u8 MeasurementType); + +void XSysMon_SetAvg(XSysMon *InstancePtr, u8 Average); +u8 XSysMon_GetAvg(XSysMon *InstancePtr); + +int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel, + int IncreaseAcqCycles, int IsEventMode, + int IsDifferentialMode); + +void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask); +u32 XSysMon_GetAlarmEnables(XSysMon *InstancePtr); + +void XSysMon_SetCalibEnables(XSysMon *InstancePtr, u16 Calibration); +u16 XSysMon_GetCalibEnables(XSysMon *InstancePtr); + +void XSysMon_SetSequencerMode(XSysMon *InstancePtr, u8 SequencerMode); +u8 XSysMon_GetSequencerMode(XSysMon *InstancePtr); +void XSysMon_SetSequencerEvent(XSysMon *InstancePtr, int IsEventMode); + +void XSysMon_SetExtenalMux(XSysMon *InstancePtr, u8 Channel); + +void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor); +u8 XSysMon_GetAdcClkDivisor(XSysMon *InstancePtr); + +int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask); +u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr); + +int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask); +u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr); + +int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask); +u32 XSysMon_GetSeqInputMode(XSysMon *InstancePtr); + +int XSysMon_SetSeqAcqTime(XSysMon *InstancePtr, u32 AcqCyclesChMask); +u32 XSysMon_GetSeqAcqTime(XSysMon *InstancePtr); + +void XSysMon_SetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg, u16 Value); +u16 XSysMon_GetAlarmThreshold(XSysMon *InstancePtr, u8 AlarmThrReg); + +void XSysMon_SetOverTemp(XSysMon *InstancePtr, u16 Value); +u16 XSysMon_GetOverTemp(XSysMon *InstancePtr); + +void XSysMon_EnableUserOverTemp(XSysMon *InstancePtr); +void XSysMon_DisableUserOverTemp(XSysMon *InstancePtr); + +void XSysMon_EnableTempUpdate(XSysMon *InstancePtr); +void XSysMon_DisableTempUpdate(XSysMon *InstancePtr); +void XSysMon_SetTempWaitCycles(XSysMon *InstancePtr, u16 WaitCycles); + + +/** + * Functions in xsysmon_selftest.c + */ +int XSysMon_SelfTest(XSysMon *InstancePtr); + +/** + * Functions in xsysmon_intr.c + */ +void XSysMon_IntrGlobalEnable(XSysMon *InstancePtr); +void XSysMon_IntrGlobalDisable(XSysMon *InstancePtr); + +void XSysMon_IntrEnable(XSysMon *InstancePtr, u32 Mask); +void XSysMon_IntrDisable(XSysMon *InstancePtr, u32 Mask); +u32 XSysMon_IntrGetEnabled(XSysMon *InstancePtr); + +u32 XSysMon_IntrGetStatus(XSysMon *InstancePtr); +void XSysMon_IntrClear(XSysMon *InstancePtr, u32 Mask); + + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_g.c b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_g.c new file mode 100644 index 00000000..b5578e90 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_g.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsysmon_g.c +* +* This file contains a configuration table that specifies the configuration +* of System Monitor/ADC devices in the system. +* +* See xsysmon.h for more information about this driver. +* +* @note None. +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xsysmon.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Prototypes ******************************/ + +/** + * This table contains configuration information for each System Monitor/ADC + * device in the system. + */ +XSysMon_Config XSysMon_ConfigTable[XPAR_XSYSMON_NUM_INSTANCES] = +{ + { + XPAR_SYSMON_0_DEVICE_ID, /**< Unique ID of device */ + XPAR_SYSMON_0_BASEADDR, /**< Base address of device */ + XPAR_SYSMON_0_INCLUDE_INTR /**< Include interrupt module */ + } +}; diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h new file mode 100644 index 00000000..9a8a7310 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_hw.h @@ -0,0 +1,683 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xsysmon_hw.h +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the System Monitor/ADC device or XADC. +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 2.00a sv 07/07/08 Added bit definitions for new Alarm Interrupts in the +* Interrupt Registers. +* 3.00a sdm 02/09/09 Added register and bit definitions for V6 SysMon. +* 4.00a ktn 10/22/09 The macros have been renamed to remove _m from the name +* of the macro. +* 5.00a sdm 06/15/11 Added new definitions for XADC. +* 5.01a bss 02/15/12 Updated for Zynq. +* 5.02a bss 11/23/12 Added macros XSM_CONVST_TEMPUPDT_MASK, +* XSM_CONVST_WAITCYCLES_MASK and +* XSM_CONVST_WAITCYCLES_SHIFT (CR #679872) +* 7.0 bss 7/25/14 To support Ultrascale: +* Added XSM_IP_OFFSET macro. +* Added Offsets and Masks for VUSER0 to VUSER3 channels. +* Added Configuration Register 3 and Sequence Registers +* 8 and 9. +* +*+* +*****************************************************************************/ + +#ifndef XSYSMON_HW_H /* Prevent circular inclusions */ +#define XSYSMON_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions ****************************/ + +#define SYSTEM_MANAGEMENT 1 /* Ultrascale */ +#define XADC 0 /* 7 Series, Zynq */ + + +#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT +#define XSM_IP_OFFSET 0x200 +#else +#define XSM_IP_OFFSET 0x00 +#endif + + +/**@name Register offsets + * + * The following constants provide access to each of the registers of the + * System Monitor/ADC device. + * @{ + */ + +/* + * System Monitor/ADC Local Registers + */ +#define XSM_SRR_OFFSET 0x00 /**< Software Reset Register */ +#define XSM_SR_OFFSET 0x04 /**< Status Register */ +#define XSM_AOR_OFFSET 0x08 /**< Alarm Output Register */ +#define XSM_CONVST_OFFSET 0x0C /**< ADC Convert Start Register */ +#define XSM_ARR_OFFSET 0x10 /**< ADC Reset Register */ + +/* + * System Monitor/ADC Interrupt Registers + */ +#define XSM_GIER_OFFSET 0x5C /**< Global Interrupt Enable */ +#define XSM_IPISR_OFFSET 0x60 /**< Interrupt Status Register */ +#define XSM_IPIER_OFFSET 0x68 /**< Interrupt Enable register */ + +/* + * System Monitor/ADC Internal Channel Registers + */ +#define XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200) + /**< On-chip Temperature Reg */ +#define XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204) + /**< On-chip VCCINT Data Reg */ +#define XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208) + /**< On-chip VCCAUX Data Reg */ +#define XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C) + /**< ADC out of VP/VN */ +#define XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210) + /**< On-chip VREFP Data Reg */ +#define XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214) + /**< On-chip VREFN Data Reg */ +#define XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218) + /**< On-chip VBRAM Data,7-series/Zynq */ +#define XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220) + /**< Supply Offset Data Reg */ +#define XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224) + /**< ADC Offset Data Reg */ +#define XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228) + /**< Gain Error Data Reg */ +#define XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C) + /**< PS VCCPINT Data Reg - Zynq */ +#define XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230) + /**< PS VCCPAUX Data Reg - Zynq */ +#define XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234) + /**< PS VCCPDRO Data Reg - Zynq */ +#define XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408) + /**< VUSER0 Supply - Ultrascale */ +#define XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C) + /**< VUSER0 Supply - Ultrascale */ + +/* + * System Monitor/ADC External Channel Registers + */ +#define XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240) + /**< ADC out of VAUXP0/VAUXN0 */ +#define XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244) + /**< ADC out of VAUXP1/VAUXN1 */ +#define XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248) + /**< ADC out of VAUXP2/VAUXN2 */ +#define XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C) + /**< ADC out of VAUXP3/VAUXN3 */ +#define XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250) + /**< ADC out of VAUXP4/VAUXN4 */ +#define XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254) + /**< ADC out of VAUXP5/VAUXN5 */ +#define XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258) + /**< ADC out of VAUXP6/VAUXN6 */ +#define XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C) + /**< ADC out of VAUXP7/VAUXN7 */ +#define XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260) + /**< ADC out of VAUXP8/VAUXN8 */ +#define XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264) + /**< ADC out of VAUXP9/VAUXN9 */ +#define XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268) + /**< ADC out of VAUXP10/VAUXN10 */ +#define XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C) + /**< ADC out of VAUXP11/VAUXN11 */ +#define XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270) + /**< ADC out of VAUXP12/VAUXN12 */ +#define XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274) + /**< ADC out of VAUXP13/VAUXN13 */ +#define XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278) + /**< ADC out of VAUXP14/VAUXN14 */ +#define XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C) + /**< ADC out of VAUXP15/VAUXN15 */ + +/* + * System Monitor/ADC Registers for Maximum/Minimum data captured for the + * on chip Temperature/VCCINT/VCCAUX data. + */ +#define XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280) + /**< Maximum Temperature Reg */ +#define XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284) + /**< Maximum VCCINT Register */ +#define XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288) + /**< Maximum VCCAUX Register */ +#define XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C) + /**< Maximum VBRAM Reg, 7 Series/Zynq */ +#define XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290) + /**< Minimum Temperature Reg */ +#define XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294) + /**< Minimum VCCINT Register */ +#define XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298) + /**< Minimum VCCAUX Register */ +#define XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C) + /**< Maximum VBRAM Reg, 7 Series/Zynq */ +#define XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0) + /**< Max VCCPINT Register, Zynq */ +#define XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4) + /**< Max VCCPAUX Register, Zynq */ +#define XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8) + /**< Max VCCPDRO Register, Zynq */ +#define XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC) + /**< Min VCCPINT Register, Zynq */ +#define XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0) + /**< Min VCCPAUX Register, Zynq */ +#define XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4) + /**< Min VCCPDRO Register, Zynq */ +#define XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480) + /**< Maximum VUSER0 Supply Reg */ +#define XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484) + /**< Maximum VUSER1 Supply Reg */ +#define XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488) + /**< Maximum VUSER2 Supply Reg */ +#define XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C) + /**< Maximum VUSER3 Supply Reg */ +#define XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0) + /**< Minimum VUSER0 Supply Reg */ +#define XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4) + /**< Minimum VUSER1 Supply Reg */ +#define XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8) + /**< Minimum VUSER2 Supply Reg */ +#define XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC) + /**< Minimum VUSER3 Supply Reg */ + + +#define XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC) /**< General Status */ + +/* + * System Monitor/ADC Configuration Registers + */ +#define XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300) + /**< Configuration Register 0 */ +#define XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304) + /**< Configuration Register 1 */ +#define XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308) + /**< Configuration Register 2 */ +#define XSM_CFR3_OFFSET (XSM_IP_OFFSET + 0x30C) + /**< Configuration Register 2 */ + +/* + * System Monitor/ADC Sequence Registers + */ +#define XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320) + /**< Seq Reg 00 Adc Channel Selection */ +#define XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324) + /**< Seq Reg 01 Adc Channel Selection */ +#define XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328) + /**< Seq Reg 02 Adc Average Enable */ +#define XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C) + /**< Seq Reg 03 Adc Average Enable */ +#define XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330) + /**< Seq Reg 04 Adc Input Mode Select */ +#define XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334) + /**< Seq Reg 05 Adc Input Mode Select */ +#define XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338) + /**< Seq Reg 06 Adc Acquisition Select */ +#define XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C) + /**< Seq Reg 07 Adc Acquisition Select */ +#define XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318) + /**< Seq Reg 08 Adc Channel Selection */ +#define XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C) + /**< Seq Reg 09 Adc Average Enable */ + +/* + * System Monitor/ADC Alarm Threshold/Limit Registers (ATR) + */ +#define XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340) + /**< Temp Upper Alarm Register */ +#define XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344) + /**< VCCINT Upper Alarm Reg */ +#define XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348) + /**< VCCAUX Upper Alarm Reg */ +#define XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C) + /**< Over Temp Upper Alarm Reg */ +#define XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350) + /**< Temp Lower Alarm Register */ +#define XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354) + /**< VCCINT Lower Alarm Reg */ +#define XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358) + /**< VCCAUX Lower Alarm Reg */ +#define XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C) + /**< Over Temp Lower Alarm Reg */ +#define XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360) + /**< VBBAM Upper Alarm,7 Series */ +#define XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364) + /**< VCCPINT Upper Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368) + /**< VCCPAUX Upper Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C) + /**< VCCPDRO Upper Alarm, Zynq */ +#define XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370) + /**< VRBAM Lower Alarm, 7 Series*/ +#define XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374) + /**< VCCPINT Lower Alarm, Zynq */ +#define XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378) + /**< VCCPAUX Lower Alarm, Zynq */ +#define XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C) + /**< VCCPDRO Lower Alarm, Zynq */ +#define XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380) + /**< VUSER0 Upper Alarm Reg */ +#define XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384) + /**< VUSER1 Upper Alarm Reg */ +#define XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388) + /**< VUSER2 Upper Alarm Reg */ +#define XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C) + /**< VUSER3 Upper Alarm Reg */ +#define XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0) + /**< VUSER0 Lower Alarm Reg */ +#define XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4) + /**< VUSER1 Lower Alarm Reg */ +#define XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8) + /**< VUSER2 Lower Alarm Reg */ +#define XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC) + /**< VUSER3 Lower Alarm Reg */ + +/*@}*/ + +/** + * @name System Monitor/ADC Software Reset Register (SRR) mask(s) + * @{ + */ +#define XSM_SRR_IPRST_MASK 0x0000000A /**< Device Reset Mask */ + +/*@}*/ + +/** + * @name System Monitor/ADC Status Register (SR) mask(s) + * @{ + */ +#define XSM_SR_JTAG_BUSY_MASK 0x00000400 /**< JTAG is busy */ +#define XSM_SR_JTAG_MODIFIED_MASK 0x00000200 /**< JTAG Write has occurred */ +#define XSM_SR_JTAG_LOCKED_MASK 0x00000100 /**< JTAG is locked */ +#define XSM_SR_BUSY_MASK 0x00000080 /**< ADC is busy in conversion */ +#define XSM_SR_EOS_MASK 0x00000040 /**< End of Sequence */ +#define XSM_SR_EOC_MASK 0x00000020 /**< End of Conversion */ +#define XSM_SR_CH_MASK 0x0000001F /**< Input ADC channel */ + +/*@}*/ + +/** + * @name System Monitor/ADC Alarm Output Register (AOR) mask(s) + * @{ + */ +#define XSM_AOR_ALARM_ALL_MASK 0x00001FFF /**< Mask for all Alarms */ +#define XSM_AOR_VUSR3_MASK 0x00001000 /**< ALM11 - VUSER3 Alarm Mask */ +#define XSM_AOR_VUSR2_MASK 0x00000800 /**< ALM10 - VUSER2 Alarm Mask */ +#define XSM_AOR_VUSR1_MASK 0x00000400 /**< ALM9 - VUSER1 Alarm Mask */ +#define XSM_AOR_VUSR0_MASK 0x00000200 /**< ALM8 - VUSER0 Alarm Mask */ +#define XSM_AOR_ALL_MASK 0x00000100 /**< ALM7 - All Alarms 0 to 6 */ +#define XSM_AOR_VCCPDRO_MASK 0x00000080 /**< ALM6 - VCCPDRO Mask, Zynq */ +#define XSM_AOR_VCCPAUX_MASK 0x00000040 /**< ALM5 - VCCPAUX Mask, Zynq */ +#define XSM_AOR_VCCPINT_MASK 0x00000020 /**< ALM4 - VCCPINT Mask, Zynq */ +#define XSM_AOR_VBRAM_MASK 0x00000010 /**< ALM3 - VBRAM Output Mask + * - 7 Series and Zynq */ +#define XSM_AOR_VCCAUX_MASK 0x00000008 /**< ALM2 - VCCAUX Output Mask */ +#define XSM_AOR_VCCINT_MASK 0x00000004 /**< ALM1 - VCCINT Alarm Mask */ +#define XSM_AOR_TEMP_MASK 0x00000002 /**< ALM0 - Temp sensor Alarm Mask */ +#define XSM_AOR_OT_MASK 0x00000001 /**< Over Temp Alarm Output */ + +/*@}*/ + +/** + * @name System Monitor/ADC CONVST Register (CONVST) mask(s) + * @{ + */ +#define XSM_CONVST_CONVST_MASK 0x00000001 + /**< Conversion Start Mask */ +#define XSM_CONVST_TEMPUPDT_MASK 0x00000002 + /**< Temperature Update + Enable Mask */ +#define XSM_CONVST_WAITCYCLES_SHIFT 2 /**< Wait Cycles Shift */ +#define XSM_CONVST_WAITCYCLES_MASK 0x0003FFFC /**< Wait Cycles Mask */ +#define XSM_CONVST_WAITCYCLES_DEFAULT 0x03E8 /**< Wait Cycles + default value */ +/*@}*/ + +/** + * @name System Monitor/ADC Reset Register (ARR) mask(s) + * @{ + */ +#define XSM_ARR_RST_MASK 0x00000001 /**< ADC Reset bit mask */ + +/*@}*/ + +/** + * @name Global Interrupt Enable Register (GIER) mask(s) + * @{ + */ +#define XSM_GIER_GIE_MASK 0x80000000 /**< Global interrupt enable */ +/*@}*/ + +/** + * @name System Monitor/ADC device Interrupt Status/Enable Registers + * + * Interrupt Status Register (IPISR) + * + * This register holds the interrupt status flags for the device. + * + * Interrupt Enable Register (IPIER) + * + * This register is used to enable interrupt sources for the device. + * Writing a '1' to a bit in this register enables the corresponding Interrupt. + * Writing a '0' to a bit in this register disables the corresponding Interrupt + * + * IPISR/IPIER registers have the same bit definitions and are only defined + * once. + * @{ + */ +#define XSM_IPIXR_VBRAM_MASK 0x00000400 /**< ALM3 - VBRAM Output Mask + * - 7 Series and Zynq */ +#define XSM_IPIXR_TEMP_DEACTIVE_MASK 0x00000200 /**< Alarm 0 DEACTIVE */ +#define XSM_IPIXR_OT_DEACTIVE_MASK 0x00000100 /**< Over Temp DEACTIVE */ +#define XSM_IPIXR_JTAG_MODIFIED_MASK 0x00000080 /**< JTAG Modified */ +#define XSM_IPIXR_JTAG_LOCKED_MASK 0x00000040 /**< JTAG Locked */ +#define XSM_IPIXR_EOC_MASK 0x00000020 /**< End Of Conversion */ +#define XSM_IPIXR_EOS_MASK 0x00000010 /**< End Of Sequence */ +#define XSM_IPIXR_VCCAUX_MASK 0x00000008 /**< Alarm 2 - VCCAUX */ +#define XSM_IPIXR_VCCINT_MASK 0x00000004 /**< Alarm 1 - VCCINT */ +#define XSM_IPIXR_TEMP_MASK 0x00000002 /**< Alarm 0 - Temp ACTIVE */ +#define XSM_IPIXR_OT_MASK 0x00000001 /**< Over Temperature ACTIVE */ +#define XSM_IPIXR_VUSR0_MASK 0x00004000 /**< Alarm 8 VUSER0 */ +#define XSM_IPIXR_VUSR1_MASK 0x00008000 /**< Alarm 9 VUSER1 */ +#define XSM_IPIXR_VUSR2_MASK 0x00010000 /**< Alarm 10 VUSER2 */ +#define XSM_IPIXR_VUSR3_MASK 0x00020000 /**< Alarm 11 VUSER3 */ +#define XSM_IPIXR_ALL_MASK 0x0003C7FF /**< Mask of all interrupts */ + + +/*@}*/ + +/** + * @name Mask for all ADC converted data including Minimum/Maximum Measurements + * and Threshold data. + * @{ + */ +#define XSM_ADCDATA_MAX_MASK 0x03FF + +/*@}*/ + +/** + * @name Configuration Register 0 (CFR0) mask(s) + * @{ + */ +#define XSM_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ +#define XSM_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ +#define XSM_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ +#define XSM_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ +#define XSM_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ +#define XSM_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ +#define XSM_CFR0_AVG_SHIFT 12 /**< Shift for the Averaging bits */ +#define XSM_CFR0_MUX_MASK 0x0800 /**< External Mux Mask Enable + * - 7 Series and Zynq */ +#define XSM_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ +#define XSM_CFR0_EC_MASK 0x0200 /**< Event driven/Continuous mode */ +#define XSM_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ +#define XSM_CFR0_CHANNEL_MASK 0x003F /**< Channel number bit Mask */ + +/*@}*/ + +/** + * @name Configuration Register 1 (CFR1) mask(s) + * @{ + */ +#define XSM_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ +#define XSM_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ +#define XSM_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ +#define XSM_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ +#define XSM_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ +#define XSM_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling + * Mask */ +#define XSM_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ +#define XSM_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ +#define XSM_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alarm 6 - VCCPDRO, Zynq */ +#define XSM_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alarm 5 - VCCPAUX, Zynq */ +#define XSM_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alarm 4 - VCCPINT, Zynq */ +#define XSM_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alarm 3 - VBRAM Enable + * 7 Series and Zynq */ +#define XSM_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ +#define XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power + Supply Gain/Offset + Enable */ +#define XSM_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power + Supply Offset Enable */ +#define XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain + Offset Enable */ +#define XSM_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset + Enable */ +#define XSM_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ +#define XSM_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ +#define XSM_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ +#define XSM_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ +#define XSM_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ +#define XSM_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ + +/*@}*/ + +/** + * @name Configuration Register 2 (CFR2) mask(s) + * @{ + */ +#define XSM_CFR2_CD_VALID_MASK 0xFF00 /**
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* 4.00a ktn 10/22/09 Updated the file to use the HAL APIs/macros. +* +*+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xsysmon.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constant defines the test value to be written + * to the Alarm Threshold Register + */ +#define XSM_ATR_TEST_VALUE 0x55 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* Run a self-test on the driver/device. The test +* - Resets the device, +* - Writes a value into the Alarm Threshold register and reads it back +* for comparison. +* - Resets the device again. +* +* +* @param InstancePtr is a pointer to the XSysMon instance. +* +* @return +* - XST_SUCCESS if the value read from the Alarm Threshold +* register is the same as the value written. +* - XST_FAILURE Otherwise +* +* @note This is a destructive test in that resets of the device are +* performed. Refer to the device specification for the +* device status after the reset operation. +* +******************************************************************************/ +int XSysMon_SelfTest(XSysMon *InstancePtr) +{ + int Status; + u32 RegValue; + + /* + * Assert the argument + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + /* + * Reset the device to get it back to its default state + */ + XSysMon_Reset(InstancePtr); + + /* + * Write a value into the Alarm Threshold registers, read it back, and + * do the comparison + */ + XSysMon_SetAlarmThreshold(InstancePtr, XSM_ATR_VCCINT_UPPER, + XSM_ATR_TEST_VALUE); + RegValue = XSysMon_GetAlarmThreshold(InstancePtr, XSM_ATR_VCCINT_UPPER); + + if (RegValue == XSM_ATR_TEST_VALUE) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + /* + * Reset the device again to its default state. + */ + XSysMon_Reset(InstancePtr); + + + /* + * Return the test result. + */ + return Status; +} diff --git a/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_sinit.c b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_sinit.c new file mode 100644 index 00000000..f316c0a9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/sysmon/src/xsysmon_sinit.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsysmon_sinit.c +* +* This file contains the implementation of the XSysMon driver's static +* initialization functionality. +* +* @note None. +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a xd/sv 05/22/07 First release +* +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xsysmon.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XSysMon_Config XSysMon_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* This function looks up the device configuration based on the unique device ID. +* The table XSysMon_ConfigTable contains the configuration info for each device +* in the system. +* +* @param DeviceId contains the ID of the device for which the +* device configuration pointer is to be returned. +* +* @return +* - A pointer to the configuration found. +* - NULL if the specified device ID was not found. +* +* @note None. +* +******************************************************************************/ +XSysMon_Config *XSysMon_LookupConfig(u16 DeviceId) +{ + XSysMon_Config *CfgPtr = NULL; + u32 Index; + + for (Index=0; Index < XPAR_XSYSMON_NUM_INSTANCES; Index++) { + if (XSysMon_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XSysMon_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +}