diff --git a/lib/sw_apps/zynqmp_pmufw/data/zynqmp_pmufw.tcl b/lib/sw_apps/zynqmp_pmufw/data/zynqmp_pmufw.tcl index 1bf86350..1307dd14 100644 --- a/lib/sw_apps/zynqmp_pmufw/data/zynqmp_pmufw.tcl +++ b/lib/sw_apps/zynqmp_pmufw/data/zynqmp_pmufw.tcl @@ -31,57 +31,57 @@ #******************************************************************************/ proc swapp_get_name {} { - return "ZynqMP PMU Firmware"; + return "ZynqMP PMU Firmware"; } proc swapp_get_description {} { - return "Platform Management Unit Firmware for ZynqMP."; + return "Platform Management Unit Firmware for ZynqMP."; } proc check_standalone_os {} { - set oslist [get_os]; + set oslist [get_os]; - if { [llength $oslist] != 1 } { - return 0; - } - set os [lindex $oslist 0]; + if { [llength $oslist] != 1 } { + return 0; + } + set os [lindex $oslist 0]; - if { $os != "standalone" } { - error "This application is supported only on the Standalone Board Support Package."; - } + if { $os != "standalone" } { + error "This application is supported only on the Standalone Board Support Package."; + } } proc swapp_is_supported_sw {} { - return 1; + return 1; } proc swapp_is_supported_hw {} { + # check processor type + set proc_instance [get_sw_processor]; + set hw_processor [get_property HW_INSTANCE $proc_instance] + set proc_type [get_property IP_NAME [get_cells $hw_processor]]; - # check processor type - set proc_instance [get_sw_processor]; - set hw_processor [get_property HW_INSTANCE $proc_instance] + if {($proc_type != "psu_microblaze")} { + error "This application is supported only for PMU Microblaze processor (psu_microblaze)."; + } - set proc_type [get_property IP_NAME [get_cells $hw_processor]]; - - if {($proc_type != "psu_microblaze") && ($proc_type != "microblaze")} { - error "This application is supported only for PMU Microblaze processor (psu_microblaze)."; - } - - return 1; + return 1; } proc get_stdout {} { - set os [get_os]; - set stdout [get_property CONFIG.STDOUT $os]; - return $stdout; + set os [get_os]; + set stdout [get_property CONFIG.STDOUT $os]; + return $stdout; } proc swapp_generate {} { - # Nothing to be done here for now + # PMU Firmware uses its own startup file. so set the -nostartfiles flag + set_property -name APP_LINKER_FLAGS -value {-nostartfiles} -objects [current_sw_design] + # Set PMU Microblaze HW related compiler flags + set_property -name APP_COMPILER_FLAGS -value {-mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul} -objects [current_sw_design] } proc swapp_get_linker_constraints {} { - - # don't generate a linker script. PMU Firmware has its own linker script - return "lscript no"; + # don't generate a linker script. PMU Firmware has its own linker script + return "lscript no"; } diff --git a/lib/sw_apps/zynqmp_pmufw/src/apu.h b/lib/sw_apps/zynqmp_pmufw/src/apu.h new file mode 100644 index 00000000..65d42ae0 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/apu.h @@ -0,0 +1,614 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _APU_H_ +#define _APU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * APU Base Address + */ +#define APU_BASEADDR ((u32)0XFD5C0000U) + +/** + * Register: APU_ERR_CTRL + */ +#define APU_ERR_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000000U) ) + +#define APU_ERR_CTRL_PSLVERR_SHIFT 0 +#define APU_ERR_CTRL_PSLVERR_WIDTH 1 +#define APU_ERR_CTRL_PSLVERR_MASK ((u32)0X00000001U) + +/** + * Register: APU_ISR + */ +#define APU_ISR ( ( APU_BASEADDR ) + ((u32)0X00000010U) ) + +#define APU_ISR_INV_APB_SHIFT 0 +#define APU_ISR_INV_APB_WIDTH 1 +#define APU_ISR_INV_APB_MASK ((u32)0X00000001U) + +/** + * Register: APU_IMR + */ +#define APU_IMR ( ( APU_BASEADDR ) + ((u32)0X00000014U) ) + +#define APU_IMR_INV_APB_SHIFT 0 +#define APU_IMR_INV_APB_WIDTH 1 +#define APU_IMR_INV_APB_MASK ((u32)0X00000001U) + +/** + * Register: APU_IEN + */ +#define APU_IEN ( ( APU_BASEADDR ) + ((u32)0X00000018U) ) + +#define APU_IEN_INV_APB_SHIFT 0 +#define APU_IEN_INV_APB_WIDTH 1 +#define APU_IEN_INV_APB_MASK ((u32)0X00000001U) + +/** + * Register: APU_IDS + */ +#define APU_IDS ( ( APU_BASEADDR ) + ((u32)0X0000001CU) ) + +#define APU_IDS_INV_APB_SHIFT 0 +#define APU_IDS_INV_APB_WIDTH 1 +#define APU_IDS_INV_APB_MASK ((u32)0X00000001U) + +/** + * Register: APU_CONFIG_0 + */ +#define APU_CONFIG_0 ( ( APU_BASEADDR ) + ((u32)0X00000020U) ) + +#define APU_CONFIG_0_CFGTE_SHIFT 24 +#define APU_CONFIG_0_CFGTE_WIDTH 4 +#define APU_CONFIG_0_CFGTE_MASK ((u32)0X0F000000U) + +#define APU_CONFIG_0_CFGEND_SHIFT 16 +#define APU_CONFIG_0_CFGEND_WIDTH 4 +#define APU_CONFIG_0_CFGEND_MASK ((u32)0X000F0000U) + +#define APU_CONFIG_0_VINITHI_SHIFT 8 +#define APU_CONFIG_0_VINITHI_WIDTH 4 +#define APU_CONFIG_0_VINITHI_MASK ((u32)0X00000F00U) + +#define APU_CONFIG_0_AA64NAA32_SHIFT 0 +#define APU_CONFIG_0_AA64NAA32_WIDTH 4 +#define APU_CONFIG_0_AA64NAA32_MASK ((u32)0X0000000FU) + +/** + * Register: APU_CONFIG_1 + */ +#define APU_CONFIG_1 ( ( APU_BASEADDR ) + ((u32)0X00000024U) ) + +#define APU_CONFIG_1_L2RSTDISABLE_SHIFT 29 +#define APU_CONFIG_1_L2RSTDISABLE_WIDTH 1 +#define APU_CONFIG_1_L2RSTDISABLE_MASK ((u32)0X20000000U) + +#define APU_CONFIG_1_L1RSTDISABLE_SHIFT 28 +#define APU_CONFIG_1_L1RSTDISABLE_WIDTH 1 +#define APU_CONFIG_1_L1RSTDISABLE_MASK ((u32)0X10000000U) + +#define APU_CONFIG_1_CP15DISABLE_SHIFT 0 +#define APU_CONFIG_1_CP15DISABLE_WIDTH 4 +#define APU_CONFIG_1_CP15DISABLE_MASK ((u32)0X0000000FU) + +/** + * Register: APU_RVBARADDR0L + */ +#define APU_RVBARADDR0L ( ( APU_BASEADDR ) + ((u32)0X00000040U) ) + +#define APU_RVBARADDR0L_ADDR_SHIFT 2 +#define APU_RVBARADDR0L_ADDR_WIDTH 30 +#define APU_RVBARADDR0L_ADDR_MASK ((u32)0XFFFFFFFCU) + +/** + * Register: APU_RVBARADDR0H + */ +#define APU_RVBARADDR0H ( ( APU_BASEADDR ) + ((u32)0X00000044U) ) + +#define APU_RVBARADDR0H_ADDR_SHIFT 0 +#define APU_RVBARADDR0H_ADDR_WIDTH 8 +#define APU_RVBARADDR0H_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: APU_RVBARADDR1L + */ +#define APU_RVBARADDR1L ( ( APU_BASEADDR ) + ((u32)0X00000048U) ) + +#define APU_RVBARADDR1L_ADDR_SHIFT 2 +#define APU_RVBARADDR1L_ADDR_WIDTH 30 +#define APU_RVBARADDR1L_ADDR_MASK ((u32)0XFFFFFFFCU) + +/** + * Register: APU_RVBARADDR1H + */ +#define APU_RVBARADDR1H ( ( APU_BASEADDR ) + ((u32)0X0000004CU) ) + +#define APU_RVBARADDR1H_ADDR_SHIFT 0 +#define APU_RVBARADDR1H_ADDR_WIDTH 8 +#define APU_RVBARADDR1H_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: APU_RVBARADDR2L + */ +#define APU_RVBARADDR2L ( ( APU_BASEADDR ) + ((u32)0X00000050U) ) + +#define APU_RVBARADDR2L_ADDR_SHIFT 2 +#define APU_RVBARADDR2L_ADDR_WIDTH 30 +#define APU_RVBARADDR2L_ADDR_MASK ((u32)0XFFFFFFFCU) + +/** + * Register: APU_RVBARADDR2H + */ +#define APU_RVBARADDR2H ( ( APU_BASEADDR ) + ((u32)0X00000054U) ) + +#define APU_RVBARADDR2H_ADDR_SHIFT 0 +#define APU_RVBARADDR2H_ADDR_WIDTH 8 +#define APU_RVBARADDR2H_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: APU_RVBARADDR3L + */ +#define APU_RVBARADDR3L ( ( APU_BASEADDR ) + ((u32)0X00000058U) ) + +#define APU_RVBARADDR3L_ADDR_SHIFT 2 +#define APU_RVBARADDR3L_ADDR_WIDTH 30 +#define APU_RVBARADDR3L_ADDR_MASK ((u32)0XFFFFFFFCU) + +/** + * Register: APU_RVBARADDR3H + */ +#define APU_RVBARADDR3H ( ( APU_BASEADDR ) + ((u32)0X0000005CU) ) + +#define APU_RVBARADDR3H_ADDR_SHIFT 0 +#define APU_RVBARADDR3H_ADDR_WIDTH 8 +#define APU_RVBARADDR3H_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: APU_ACE_CTRL + */ +#define APU_ACE_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000060U) ) + +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_WIDTH 4 +#define APU_ACE_CTRL_AWQOS_MASK ((u32)0X000F0000U) + +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_WIDTH 4 +#define APU_ACE_CTRL_ARQOS_MASK ((u32)0X0000000FU) + +/** + * Register: APU_SNOOP_CTRL + */ +#define APU_SNOOP_CTRL ( ( APU_BASEADDR ) + ((u32)0X00000080U) ) + +#define APU_SNOOP_CTRL_ACE_INACT_SHIFT 4 +#define APU_SNOOP_CTRL_ACE_INACT_WIDTH 1 +#define APU_SNOOP_CTRL_ACE_INACT_MASK ((u32)0X00000010U) + +#define APU_SNOOP_CTRL_ACP_INACT_SHIFT 0 +#define APU_SNOOP_CTRL_ACP_INACT_WIDTH 1 +#define APU_SNOOP_CTRL_ACP_INACT_MASK ((u32)0X00000001U) + +/** + * Register: APU_PWRCTL + */ +#define APU_PWRCTL ( ( APU_BASEADDR ) + ((u32)0X00000090U) ) + +#define APU_PWRCTL_CLREXMONREQ_SHIFT 17 +#define APU_PWRCTL_CLREXMONREQ_WIDTH 1 +#define APU_PWRCTL_CLREXMONREQ_MASK ((u32)0X00020000U) + +#define APU_PWRCTL_L2FLUSHREQ_SHIFT 16 +#define APU_PWRCTL_L2FLUSHREQ_WIDTH 1 +#define APU_PWRCTL_L2FLUSHREQ_MASK ((u32)0X00010000U) + +#define APU_PWRCTL_CPUPWRDWNREQ_SHIFT 0 +#define APU_PWRCTL_CPUPWRDWNREQ_WIDTH 4 +#define APU_PWRCTL_CPUPWRDWNREQ_MASK ((u32)0X0000000FU) + +/** + * Register: APU_PWRSTAT + */ +#define APU_PWRSTAT ( ( APU_BASEADDR ) + ((u32)0X00000094U) ) + +#define APU_PWRSTAT_CLREXMONACK_SHIFT 17 +#define APU_PWRSTAT_CLREXMONACK_WIDTH 1 +#define APU_PWRSTAT_CLREXMONACK_MASK ((u32)0X00020000U) + +#define APU_PWRSTAT_L2FLUSHDONE_SHIFT 16 +#define APU_PWRSTAT_L2FLUSHDONE_WIDTH 1 +#define APU_PWRSTAT_L2FLUSHDONE_MASK ((u32)0X00010000U) + +#define APU_PWRSTAT_DBGNOPWRDWN_SHIFT 0 +#define APU_PWRSTAT_DBGNOPWRDWN_WIDTH 4 +#define APU_PWRSTAT_DBGNOPWRDWN_MASK ((u32)0X0000000FU) + +/** + * Register: APU_ECO + */ +#define APU_ECO ( ( APU_BASEADDR ) + ((u32)0X000000ECU) ) + +#define APU_ECO_SPARE_SHIFT 0 +#define APU_ECO_SPARE_WIDTH 32 +#define APU_ECO_SPARE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: APU_RAM_ADJ_0 + */ +#define APU_RAM_ADJ_0 ( ( APU_BASEADDR ) + ((u32)0X000000F0U) ) + +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_SHIFT 29 +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_ITAG_EMAS_MASK ((u32)0X20000000U) + +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_SHIFT 27 +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_ITAG_EMAW_MASK ((u32)0X18000000U) + +#define APU_RAM_ADJ_0_L1_ITAG_EMA_SHIFT 24 +#define APU_RAM_ADJ_0_L1_ITAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_ITAG_EMA_MASK ((u32)0X07000000U) + +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_SHIFT 21 +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_IDATA_EMAS_MASK ((u32)0X00200000U) + +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_SHIFT 19 +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_IDATA_EMAW_MASK ((u32)0X00180000U) + +#define APU_RAM_ADJ_0_L1_IDATA_EMA_SHIFT 16 +#define APU_RAM_ADJ_0_L1_IDATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_IDATA_EMA_MASK ((u32)0X00070000U) + +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_SHIFT 13 +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_DTAG_EMAS_MASK ((u32)0X00002000U) + +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_SHIFT 11 +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_DTAG_EMAW_MASK ((u32)0X00001800U) + +#define APU_RAM_ADJ_0_L1_DTAG_EMA_SHIFT 8 +#define APU_RAM_ADJ_0_L1_DTAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_DTAG_EMA_MASK ((u32)0X00000700U) + +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_SHIFT 5 +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_0_L1_DDATA_EMAS_MASK ((u32)0X00000020U) + +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_SHIFT 3 +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_0_L1_DDATA_EMAW_MASK ((u32)0X00000018U) + +#define APU_RAM_ADJ_0_L1_DDATA_EMA_SHIFT 0 +#define APU_RAM_ADJ_0_L1_DDATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_0_L1_DDATA_EMA_MASK ((u32)0X00000007U) + +/** + * Register: APU_RAM_ADJ_1 + */ +#define APU_RAM_ADJ_1 ( ( APU_BASEADDR ) + ((u32)0X000000F4U) ) + +#define APU_RAM_ADJ_1_TLB_EMAS_SHIFT 29 +#define APU_RAM_ADJ_1_TLB_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_TLB_EMAS_MASK ((u32)0X20000000U) + +#define APU_RAM_ADJ_1_TLB_EMAW_SHIFT 27 +#define APU_RAM_ADJ_1_TLB_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_TLB_EMAW_MASK ((u32)0X18000000U) + +#define APU_RAM_ADJ_1_TLB_EMA_SHIFT 24 +#define APU_RAM_ADJ_1_TLB_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_TLB_EMA_MASK ((u32)0X07000000U) + +#define APU_RAM_ADJ_1_DIRTY_EMAS_SHIFT 21 +#define APU_RAM_ADJ_1_DIRTY_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_DIRTY_EMAS_MASK ((u32)0X00200000U) + +#define APU_RAM_ADJ_1_DIRTY_EMAW_SHIFT 19 +#define APU_RAM_ADJ_1_DIRTY_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_DIRTY_EMAW_MASK ((u32)0X00180000U) + +#define APU_RAM_ADJ_1_DIRTY_EMA_SHIFT 16 +#define APU_RAM_ADJ_1_DIRTY_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_DIRTY_EMA_MASK ((u32)0X00070000U) + +#define APU_RAM_ADJ_1_BTAC1_EMAS_SHIFT 13 +#define APU_RAM_ADJ_1_BTAC1_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_BTAC1_EMAS_MASK ((u32)0X00002000U) + +#define APU_RAM_ADJ_1_BTAC1_EMAW_SHIFT 11 +#define APU_RAM_ADJ_1_BTAC1_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_BTAC1_EMAW_MASK ((u32)0X00001800U) + +#define APU_RAM_ADJ_1_BTAC1_EMA_SHIFT 8 +#define APU_RAM_ADJ_1_BTAC1_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_BTAC1_EMA_MASK ((u32)0X00000700U) + +#define APU_RAM_ADJ_1_BTAC0_EMAS_SHIFT 5 +#define APU_RAM_ADJ_1_BTAC0_EMAS_WIDTH 1 +#define APU_RAM_ADJ_1_BTAC0_EMAS_MASK ((u32)0X00000020U) + +#define APU_RAM_ADJ_1_BTAC0_EMAW_SHIFT 3 +#define APU_RAM_ADJ_1_BTAC0_EMAW_WIDTH 2 +#define APU_RAM_ADJ_1_BTAC0_EMAW_MASK ((u32)0X00000018U) + +#define APU_RAM_ADJ_1_BTAC0_EMA_SHIFT 0 +#define APU_RAM_ADJ_1_BTAC0_EMA_WIDTH 3 +#define APU_RAM_ADJ_1_BTAC0_EMA_MASK ((u32)0X00000007U) + +/** + * Register: APU_RAM_ADJ_2 + */ +#define APU_RAM_ADJ_2 ( ( APU_BASEADDR ) + ((u32)0X000000F8U) ) + +#define APU_RAM_ADJ_2_ETF_EMAS_SHIFT 29 +#define APU_RAM_ADJ_2_ETF_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_ETF_EMAS_MASK ((u32)0X20000000U) + +#define APU_RAM_ADJ_2_ETF_EMAW_SHIFT 27 +#define APU_RAM_ADJ_2_ETF_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_ETF_EMAW_MASK ((u32)0X18000000U) + +#define APU_RAM_ADJ_2_ETF_EMA_SHIFT 24 +#define APU_RAM_ADJ_2_ETF_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_ETF_EMA_MASK ((u32)0X07000000U) + +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_SHIFT 13 +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_SCU_TAG_EMAS_MASK ((u32)0X00002000U) + +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_SHIFT 11 +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_SCU_TAG_EMAW_MASK ((u32)0X00001800U) + +#define APU_RAM_ADJ_2_SCU_TAG_EMA_SHIFT 8 +#define APU_RAM_ADJ_2_SCU_TAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_SCU_TAG_EMA_MASK ((u32)0X00000700U) + +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_SHIFT 5 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_WIDTH 1 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAS_MASK ((u32)0X00000020U) + +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_SHIFT 3 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_WIDTH 2 +#define APU_RAM_ADJ_2_L2_VICTIM_EMAW_MASK ((u32)0X00000018U) + +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_SHIFT 0 +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_WIDTH 3 +#define APU_RAM_ADJ_2_L2_VICTIM_EMA_MASK ((u32)0X00000007U) + +/** + * Register: APU_RAM_ADJ_3 + */ +#define APU_RAM_ADJ_3 ( ( APU_BASEADDR ) + ((u32)0X000000FCU) ) + +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_SHIFT 29 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAS_MASK ((u32)0X20000000U) + +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_SHIFT 27 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_TAGECC_EMAW_MASK ((u32)0X18000000U) + +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_SHIFT 24 +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_TAGECC_EMA_MASK ((u32)0X07000000U) + +#define APU_RAM_ADJ_3_L2_TAG_EMAS_SHIFT 21 +#define APU_RAM_ADJ_3_L2_TAG_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_TAG_EMAS_MASK ((u32)0X00200000U) + +#define APU_RAM_ADJ_3_L2_TAG_EMAW_SHIFT 19 +#define APU_RAM_ADJ_3_L2_TAG_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_TAG_EMAW_MASK ((u32)0X00180000U) + +#define APU_RAM_ADJ_3_L2_TAG_EMA_SHIFT 16 +#define APU_RAM_ADJ_3_L2_TAG_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_TAG_EMA_MASK ((u32)0X00070000U) + +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_SHIFT 13 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAS_MASK ((u32)0X00002000U) + +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_SHIFT 11 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_DATAECC_EMAW_MASK ((u32)0X00001800U) + +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_SHIFT 8 +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_DATAECC_EMA_MASK ((u32)0X00000700U) + +#define APU_RAM_ADJ_3_L2_DATA_EMAS_SHIFT 5 +#define APU_RAM_ADJ_3_L2_DATA_EMAS_WIDTH 1 +#define APU_RAM_ADJ_3_L2_DATA_EMAS_MASK ((u32)0X00000020U) + +#define APU_RAM_ADJ_3_L2_DATA_EMAW_SHIFT 3 +#define APU_RAM_ADJ_3_L2_DATA_EMAW_WIDTH 2 +#define APU_RAM_ADJ_3_L2_DATA_EMAW_MASK ((u32)0X00000018U) + +#define APU_RAM_ADJ_3_L2_DATA_EMA_SHIFT 0 +#define APU_RAM_ADJ_3_L2_DATA_EMA_WIDTH 3 +#define APU_RAM_ADJ_3_L2_DATA_EMA_MASK ((u32)0X00000007U) + +/** + * Register: APU_XPD_REG0 + */ +#define APU_XPD_REG0 ( ( APU_BASEADDR ) + ((u32)0X00000600U) ) + +#define APU_XPD_REG0_PRE_LOAD_SHIFT 0 +#define APU_XPD_REG0_PRE_LOAD_WIDTH 32 +#define APU_XPD_REG0_PRE_LOAD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: APU_XPD_REG1 + */ +#define APU_XPD_REG1 ( ( APU_BASEADDR ) + ((u32)0X00000604U) ) + +#define APU_XPD_REG1_EXPECTED_SHIFT 0 +#define APU_XPD_REG1_EXPECTED_WIDTH 32 +#define APU_XPD_REG1_EXPECTED_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: APU_XPD_CTRL0 + */ +#define APU_XPD_CTRL0 ( ( APU_BASEADDR ) + ((u32)0X00000608U) ) + +#define APU_XPD_CTRL0_DELAY_SPARE_SHIFT 25 +#define APU_XPD_CTRL0_DELAY_SPARE_WIDTH 5 +#define APU_XPD_CTRL0_DELAY_SPARE_MASK ((u32)0X3E000000U) + +#define APU_XPD_CTRL0_CMP_SEL_SHIFT 24 +#define APU_XPD_CTRL0_CMP_SEL_WIDTH 1 +#define APU_XPD_CTRL0_CMP_SEL_MASK ((u32)0X01000000U) + +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_SHIFT 19 +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_WIDTH 5 +#define APU_XPD_CTRL0_DELAY_CELL_TYPE_MASK ((u32)0X00F80000U) + +#define APU_XPD_CTRL0_DELAY_VT_TYPE_SHIFT 17 +#define APU_XPD_CTRL0_DELAY_VT_TYPE_WIDTH 2 +#define APU_XPD_CTRL0_DELAY_VT_TYPE_MASK ((u32)0X00060000U) + +#define APU_XPD_CTRL0_DELAY_VALUE_SHIFT 6 +#define APU_XPD_CTRL0_DELAY_VALUE_WIDTH 11 +#define APU_XPD_CTRL0_DELAY_VALUE_MASK ((u32)0X0001FFC0U) + +#define APU_XPD_CTRL0_PATH_SEL_SHIFT 0 +#define APU_XPD_CTRL0_PATH_SEL_WIDTH 6 +#define APU_XPD_CTRL0_PATH_SEL_MASK ((u32)0X0000003FU) + +/** + * Register: APU_XPD_CTRL1 + */ +#define APU_XPD_CTRL1 ( ( APU_BASEADDR ) + ((u32)0X0000060CU) ) + +#define APU_XPD_CTRL1_CLK_SPARE_SHIFT 12 +#define APU_XPD_CTRL1_CLK_SPARE_WIDTH 4 +#define APU_XPD_CTRL1_CLK_SPARE_MASK ((u32)0X0000F000U) + +#define APU_XPD_CTRL1_CLK_PHASE_SEL_SHIFT 10 +#define APU_XPD_CTRL1_CLK_PHASE_SEL_WIDTH 2 +#define APU_XPD_CTRL1_CLK_PHASE_SEL_MASK ((u32)0X00000C00U) + +#define APU_XPD_CTRL1_CLK_VT_TYPE_SHIFT 8 +#define APU_XPD_CTRL1_CLK_VT_TYPE_WIDTH 2 +#define APU_XPD_CTRL1_CLK_VT_TYPE_MASK ((u32)0X00000300U) + +#define APU_XPD_CTRL1_CLK_CELL_TYPE_SHIFT 6 +#define APU_XPD_CTRL1_CLK_CELL_TYPE_WIDTH 2 +#define APU_XPD_CTRL1_CLK_CELL_TYPE_MASK ((u32)0X000000C0U) + +#define APU_XPD_CTRL1_CLK_INSERT_DLY_SHIFT 2 +#define APU_XPD_CTRL1_CLK_INSERT_DLY_WIDTH 4 +#define APU_XPD_CTRL1_CLK_INSERT_DLY_MASK ((u32)0X0000003CU) + +#define APU_XPD_CTRL1_CLK_SEL_SHIFT 0 +#define APU_XPD_CTRL1_CLK_SEL_WIDTH 2 +#define APU_XPD_CTRL1_CLK_SEL_MASK ((u32)0X00000003U) + +/** + * Register: APU_XPD_CTRL2 + */ +#define APU_XPD_CTRL2 ( ( APU_BASEADDR ) + ((u32)0X00000614U) ) + +#define APU_XPD_CTRL2_CTRL_SPARE_SHIFT 1 +#define APU_XPD_CTRL2_CTRL_SPARE_WIDTH 2 +#define APU_XPD_CTRL2_CTRL_SPARE_MASK ((u32)0X00000006U) + +#define APU_XPD_CTRL2_ENABLE_SHIFT 0 +#define APU_XPD_CTRL2_ENABLE_WIDTH 1 +#define APU_XPD_CTRL2_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: APU_XPD_CTRL3 + */ +#define APU_XPD_CTRL3 ( ( APU_BASEADDR ) + ((u32)0X00000618U) ) + +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_SHIFT 3 +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_WIDTH 12 +#define APU_XPD_CTRL3_DCYCLE_CNT_VALUE_MASK ((u32)0X00007FF8U) + +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_SHIFT 2 +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_HIGH_LOW_MASK ((u32)0X00000004U) + +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_SHIFT 1 +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_CNT_CLR_MASK ((u32)0X00000002U) + +#define APU_XPD_CTRL3_DCYCLE_START_SHIFT 0 +#define APU_XPD_CTRL3_DCYCLE_START_WIDTH 1 +#define APU_XPD_CTRL3_DCYCLE_START_MASK ((u32)0X00000001U) + +/** + * Register: APU_XPD_SOFT_RST + */ +#define APU_XPD_SOFT_RST ( ( APU_BASEADDR ) + ((u32)0X0000061CU) ) + +#define APU_XPD_SOFT_RST_CLK2_SHIFT 2 +#define APU_XPD_SOFT_RST_CLK2_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK2_MASK ((u32)0X00000004U) + +#define APU_XPD_SOFT_RST_CLK1_SHIFT 1 +#define APU_XPD_SOFT_RST_CLK1_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK1_MASK ((u32)0X00000002U) + +#define APU_XPD_SOFT_RST_CLK0_SHIFT 0 +#define APU_XPD_SOFT_RST_CLK0_WIDTH 1 +#define APU_XPD_SOFT_RST_CLK0_MASK ((u32)0X00000001U) + +/** + * Register: APU_XPD_STAT + */ +#define APU_XPD_STAT ( ( APU_BASEADDR ) + ((u32)0X00000620U) ) + +#define APU_XPD_STAT_CMP_RESULT_SHIFT 1 +#define APU_XPD_STAT_CMP_RESULT_WIDTH 1 +#define APU_XPD_STAT_CMP_RESULT_MASK ((u32)0X00000002U) + +#define APU_XPD_STAT_CMP_DONE_SHIFT 0 +#define APU_XPD_STAT_CMP_DONE_WIDTH 1 +#define APU_XPD_STAT_CMP_DONE_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _APU_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/crf_apb.h b/lib/sw_apps/zynqmp_pmufw/src/crf_apb.h new file mode 100644 index 00000000..d250b4d5 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/crf_apb.h @@ -0,0 +1,939 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _CRF_APB_H_ +#define _CRF_APB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * CRF_APB Base Address + */ +#define CRF_APB_BASEADDR ((u32)0XFD1A0000U) + +/** + * Register: CRF_APB_ERR_CTRL + */ +#define CRF_APB_ERR_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000000U) ) + +#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_SHIFT 0 +#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_WIDTH 1 +#define CRF_APB_ERR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_IR_STATUS + */ +#define CRF_APB_IR_STATUS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000004U) ) + +#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_SHIFT 0 +#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_WIDTH 1 +#define CRF_APB_IR_STATUS_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_IR_MASK + */ +#define CRF_APB_IR_MASK ( ( CRF_APB_BASEADDR ) + ((u32)0X00000008U) ) + +#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_SHIFT 0 +#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_WIDTH 1 +#define CRF_APB_IR_MASK_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_IR_ENABLE + */ +#define CRF_APB_IR_ENABLE ( ( CRF_APB_BASEADDR ) + ((u32)0X0000000CU) ) + +#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_SHIFT 0 +#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_WIDTH 1 +#define CRF_APB_IR_ENABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_IR_DISABLE + */ +#define CRF_APB_IR_DISABLE ( ( CRF_APB_BASEADDR ) + ((u32)0X00000010U) ) + +#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_SHIFT 0 +#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_WIDTH 1 +#define CRF_APB_IR_DISABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_CRF_ECO + */ +#define CRF_APB_CRF_ECO ( ( CRF_APB_BASEADDR ) + ((u32)0X00000018U) ) + +#define CRF_APB_CRF_ECO_REG_SHIFT 0 +#define CRF_APB_CRF_ECO_REG_WIDTH 32 +#define CRF_APB_CRF_ECO_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRF_APB_CRF_WPROT + */ +#define CRF_APB_CRF_WPROT ( ( CRF_APB_BASEADDR ) + ((u32)0X0000001CU) ) + +#define CRF_APB_CRF_WPROT_ACTIVE_SHIFT 0 +#define CRF_APB_CRF_WPROT_ACTIVE_WIDTH 1 +#define CRF_APB_CRF_WPROT_ACTIVE_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_APLL_CTRL + */ +#define CRF_APB_APLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000020U) ) + +#define CRF_APB_APLL_CTRL_POST_SRC_SHIFT 24 +#define CRF_APB_APLL_CTRL_POST_SRC_WIDTH 3 +#define CRF_APB_APLL_CTRL_POST_SRC_MASK ((u32)0X07000000U) + +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_WIDTH 3 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U) + +#define CRF_APB_APLL_CTRL_CLKOUTDIV_SHIFT 17 +#define CRF_APB_APLL_CTRL_CLKOUTDIV_WIDTH 1 +#define CRF_APB_APLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U) + +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_WIDTH 1 +#define CRF_APB_APLL_CTRL_DIV2_MASK ((u32)0X00010000U) + +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_WIDTH 7 +#define CRF_APB_APLL_CTRL_FBDIV_MASK ((u32)0X00007F00U) + +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_WIDTH 1 +#define CRF_APB_APLL_CTRL_BYPASS_MASK ((u32)0X00000008U) + +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_WIDTH 1 +#define CRF_APB_APLL_CTRL_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_APLL_CFG + */ +#define CRF_APB_APLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000024U) ) + +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_WIDTH 7 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U) + +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_WIDTH 10 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U) + +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_WIDTH 2 +#define CRF_APB_APLL_CFG_LFHF_MASK ((u32)0X00000C00U) + +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_WIDTH 4 +#define CRF_APB_APLL_CFG_CP_MASK ((u32)0X000001E0U) + +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_WIDTH 4 +#define CRF_APB_APLL_CFG_RES_MASK ((u32)0X0000000FU) + +/** + * Register: CRF_APB_APLL_FRAC_CFG + */ +#define CRF_APB_APLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000028U) ) + +#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 +#define CRF_APB_APLL_FRAC_CFG_ENABLED_WIDTH 1 +#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U) + +#define CRF_APB_APLL_FRAC_CFG_SEED_SHIFT 22 +#define CRF_APB_APLL_FRAC_CFG_SEED_WIDTH 3 +#define CRF_APB_APLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U) + +#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define CRF_APB_APLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U) + +#define CRF_APB_APLL_FRAC_CFG_ORDER_SHIFT 18 +#define CRF_APB_APLL_FRAC_CFG_ORDER_WIDTH 1 +#define CRF_APB_APLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U) + +#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 +#define CRF_APB_APLL_FRAC_CFG_DATA_WIDTH 16 +#define CRF_APB_APLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000002CU) ) + +#define CRF_APB_DPLL_CTRL_POST_SRC_SHIFT 24 +#define CRF_APB_DPLL_CTRL_POST_SRC_WIDTH 3 +#define CRF_APB_DPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U) + +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_WIDTH 3 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U) + +#define CRF_APB_DPLL_CTRL_CLKOUTDIV_SHIFT 17 +#define CRF_APB_DPLL_CTRL_CLKOUTDIV_WIDTH 1 +#define CRF_APB_DPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U) + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 +#define CRF_APB_DPLL_CTRL_DIV2_MASK ((u32)0X00010000U) + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U) + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK ((u32)0X00000008U) + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 +#define CRF_APB_DPLL_CTRL_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000030U) ) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U) + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U) + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 +#define CRF_APB_DPLL_CFG_LFHF_MASK ((u32)0X00000C00U) + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 +#define CRF_APB_DPLL_CFG_CP_MASK ((u32)0X000001E0U) + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 +#define CRF_APB_DPLL_CFG_RES_MASK ((u32)0X0000000FU) + +/** + * Register: CRF_APB_DPLL_FRAC_CFG + */ +#define CRF_APB_DPLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000034U) ) + +#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 +#define CRF_APB_DPLL_FRAC_CFG_ENABLED_WIDTH 1 +#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U) + +#define CRF_APB_DPLL_FRAC_CFG_SEED_SHIFT 22 +#define CRF_APB_DPLL_FRAC_CFG_SEED_WIDTH 3 +#define CRF_APB_DPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U) + +#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define CRF_APB_DPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U) + +#define CRF_APB_DPLL_FRAC_CFG_ORDER_SHIFT 18 +#define CRF_APB_DPLL_FRAC_CFG_ORDER_WIDTH 1 +#define CRF_APB_DPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U) + +#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 +#define CRF_APB_DPLL_FRAC_CFG_DATA_WIDTH 16 +#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRF_APB_VPLL_CTRL + */ +#define CRF_APB_VPLL_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000038U) ) + +#define CRF_APB_VPLL_CTRL_POST_SRC_SHIFT 24 +#define CRF_APB_VPLL_CTRL_POST_SRC_WIDTH 3 +#define CRF_APB_VPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U) + +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_WIDTH 3 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U) + +#define CRF_APB_VPLL_CTRL_CLKOUTDIV_SHIFT 17 +#define CRF_APB_VPLL_CTRL_CLKOUTDIV_WIDTH 1 +#define CRF_APB_VPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U) + +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_WIDTH 1 +#define CRF_APB_VPLL_CTRL_DIV2_MASK ((u32)0X00010000U) + +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_WIDTH 7 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U) + +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_WIDTH 1 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK ((u32)0X00000008U) + +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_WIDTH 1 +#define CRF_APB_VPLL_CTRL_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_VPLL_CFG + */ +#define CRF_APB_VPLL_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X0000003CU) ) + +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_WIDTH 7 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U) + +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_WIDTH 10 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U) + +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_WIDTH 2 +#define CRF_APB_VPLL_CFG_LFHF_MASK ((u32)0X00000C00U) + +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_WIDTH 4 +#define CRF_APB_VPLL_CFG_CP_MASK ((u32)0X000001E0U) + +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_WIDTH 4 +#define CRF_APB_VPLL_CFG_RES_MASK ((u32)0X0000000FU) + +/** + * Register: CRF_APB_VPLL_FRAC_CFG + */ +#define CRF_APB_VPLL_FRAC_CFG ( ( CRF_APB_BASEADDR ) + ((u32)0X00000040U) ) + +#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 +#define CRF_APB_VPLL_FRAC_CFG_ENABLED_WIDTH 1 +#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U) + +#define CRF_APB_VPLL_FRAC_CFG_SEED_SHIFT 22 +#define CRF_APB_VPLL_FRAC_CFG_SEED_WIDTH 3 +#define CRF_APB_VPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U) + +#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define CRF_APB_VPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U) + +#define CRF_APB_VPLL_FRAC_CFG_ORDER_SHIFT 18 +#define CRF_APB_VPLL_FRAC_CFG_ORDER_WIDTH 1 +#define CRF_APB_VPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U) + +#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 +#define CRF_APB_VPLL_FRAC_CFG_DATA_WIDTH 16 +#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000044U) ) + +#define CRF_APB_PLL_STATUS_VPLL_STABLE_SHIFT 5 +#define CRF_APB_PLL_STATUS_VPLL_STABLE_WIDTH 1 +#define CRF_APB_PLL_STATUS_VPLL_STABLE_MASK ((u32)0X00000020U) + +#define CRF_APB_PLL_STATUS_DPLL_STABLE_SHIFT 4 +#define CRF_APB_PLL_STATUS_DPLL_STABLE_WIDTH 1 +#define CRF_APB_PLL_STATUS_DPLL_STABLE_MASK ((u32)0X00000010U) + +#define CRF_APB_PLL_STATUS_APLL_STABLE_SHIFT 3 +#define CRF_APB_PLL_STATUS_APLL_STABLE_WIDTH 1 +#define CRF_APB_PLL_STATUS_APLL_STABLE_MASK ((u32)0X00000008U) + +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_WIDTH 1 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK ((u32)0X00000004U) + +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_WIDTH 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK ((u32)0X00000002U) + +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_WIDTH 1 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_APLL_TO_LPD_CTRL + */ +#define CRF_APB_APLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000048U) ) + +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +/** + * Register: CRF_APB_DPLL_TO_LPD_CTRL + */ +#define CRF_APB_DPLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000004CU) ) + +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +/** + * Register: CRF_APB_VPLL_TO_LPD_CTRL + */ +#define CRF_APB_VPLL_TO_LPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000050U) ) + +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +/** + * Register: CRF_APB_ACPU_CTRL + */ +#define CRF_APB_ACPU_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000060U) ) + +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_WIDTH 1 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK ((u32)0X02000000U) + +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_WIDTH 1 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK ((u32)0X01000000U) + +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DBG_TRACE_CTRL + */ +#define CRF_APB_DBG_TRACE_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000064U) ) + +#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_TRACE_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DBG_FPD_CTRL + */ +#define CRF_APB_DBG_FPD_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000068U) ) + +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DP_VIDEO_REF_CTRL + */ +#define CRF_APB_DP_VIDEO_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000070U) ) + +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DP_AUDIO_REF_CTRL + */ +#define CRF_APB_DP_AUDIO_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000074U) ) + +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DP_STC_REF_CTRL + */ +#define CRF_APB_DP_STC_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X0000007CU) ) + +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DDR_CTRL + */ +#define CRF_APB_DDR_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000080U) ) + +#define CRF_APB_DDR_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DDR_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DDR_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_GPU_REF_CTRL + */ +#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X00000084U) ) + +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_WIDTH 1 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK ((u32)0X04000000U) + +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_WIDTH 1 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK ((u32)0X02000000U) + +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_SATA_REF_CTRL + */ +#define CRF_APB_SATA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000A0U) ) + +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_PCIE_REF_CTRL + */ +#define CRF_APB_PCIE_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000B4U) ) + +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_GDMA_REF_CTRL + */ +#define CRF_APB_GDMA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000B8U) ) + +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DPDMA_REF_CTRL + */ +#define CRF_APB_DPDMA_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000BCU) ) + +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_TOPSW_MAIN_CTRL + */ +#define CRF_APB_TOPSW_MAIN_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C0U) ) + +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_TOPSW_LSBUS_CTRL + */ +#define CRF_APB_TOPSW_LSBUS_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C4U) ) + +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_GTGREF0_REF_CTRL + */ +#define CRF_APB_GTGREF0_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000C8U) ) + +#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT300_REF_CTRL + */ +#define CRF_APB_DFT300_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D0U) ) + +#define CRF_APB_DFT300_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT300_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT300_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT300_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT300_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT300_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT300_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT270_REF_CTRL + */ +#define CRF_APB_DFT270_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D4U) ) + +#define CRF_APB_DFT270_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT270_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT270_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT270_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT270_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT270_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT270_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT250_REF_CTRL + */ +#define CRF_APB_DFT250_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000D8U) ) + +#define CRF_APB_DFT250_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT250_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT250_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT250_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT250_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT250_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT250_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT125_REF_CTRL + */ +#define CRF_APB_DFT125_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000DCU) ) + +#define CRF_APB_DFT125_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT125_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT125_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT125_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT125_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT125_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT125_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT150_REF_CTRL + */ +#define CRF_APB_DFT150_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F0U) ) + +#define CRF_APB_DFT150_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT150_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT150_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT150_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT150_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT150_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT150_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DFT333_REF_CTRL + */ +#define CRF_APB_DFT333_REF_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F4U) ) + +#define CRF_APB_DFT333_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DFT333_REF_CTRL_CLKACT_WIDTH 1 +#define CRF_APB_DFT333_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DFT333_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DFT333_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DFT333_REF_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DFT333_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_DBG_TSTMP_CTRL + */ +#define CRF_APB_DBG_TSTMP_CTRL ( ( CRF_APB_BASEADDR ) + ((u32)0X000000F8U) ) + +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_WIDTH 6 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_WIDTH 3 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRF_APB_RST_FPD_TOP + */ +#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + ((u32)0X00000100U) ) + +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK ((u32)0X00080000U) + +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK ((u32)0X00040000U) + +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK ((u32)0X00020000U) + +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK ((u32)0X00010000U) + +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK ((u32)0X00008000U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK ((u32)0X00001000U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK ((u32)0X00000800U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK ((u32)0X00000400U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK ((u32)0X00000200U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK ((u32)0X00000100U) + +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK ((u32)0X00000080U) + +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK ((u32)0X00000040U) + +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK ((u32)0X00000020U) + +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK ((u32)0X00000010U) + +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK ((u32)0X00000008U) + +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK ((u32)0X00000004U) + +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK ((u32)0X00000002U) + +/** + * Register: CRF_APB_RST_FPD_APU + */ +#define CRF_APB_RST_FPD_APU ( ( CRF_APB_BASEADDR ) + ((u32)0X00000104U) ) + +#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_SHIFT 13 +#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK ((u32)0X00002000U) + +#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK ((u32)0X00001000U) + +#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK ((u32)0X00000800U) + +#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK ((u32)0X00000400U) + +#define CRF_APB_RST_FPD_APU_APU_L2_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_APU_APU_L2_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK ((u32)0X00000100U) + +#define CRF_APB_RST_FPD_APU_ACPU3_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_APU_ACPU3_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK ((u32)0X00000008U) + +#define CRF_APB_RST_FPD_APU_ACPU2_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_APU_ACPU2_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK ((u32)0X00000004U) + +#define CRF_APB_RST_FPD_APU_ACPU1_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_APU_ACPU1_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK ((u32)0X00000002U) + +#define CRF_APB_RST_FPD_APU_ACPU0_RESET_SHIFT 0 +#define CRF_APB_RST_FPD_APU_ACPU0_RESET_WIDTH 1 +#define CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRF_APB_RST_DDR_SS + */ +#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + ((u32)0X00000108U) ) + +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_WIDTH 1 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK ((u32)0X00000008U) + +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_WIDTH 1 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK ((u32)0X00000004U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _CRF_APB_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/crl_apb.h b/lib/sw_apps/zynqmp_pmufw/src/crl_apb.h new file mode 100644 index 00000000..9940a487 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/crl_apb.h @@ -0,0 +1,2495 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _CRL_APB_H_ +#define _CRL_APB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * CRL_APB Base Address + */ +#define CRL_APB_BASEADDR ((u32)0XFF5E0000U) + +/** + * Register: CRL_APB_ERR_CTRL + */ +#define CRL_APB_ERR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000000U) ) + +#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_SHIFT 0 +#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_WIDTH 1 +#define CRL_APB_ERR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IR_STATUS + */ +#define CRL_APB_IR_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000004U) ) + +#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_SHIFT 0 +#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_WIDTH 1 +#define CRL_APB_IR_STATUS_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IR_MASK + */ +#define CRL_APB_IR_MASK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000008U) ) + +#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_SHIFT 0 +#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_WIDTH 1 +#define CRL_APB_IR_MASK_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IR_ENABLE + */ +#define CRL_APB_IR_ENABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X0000000CU) ) + +#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_SHIFT 0 +#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_WIDTH 1 +#define CRL_APB_IR_ENABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IR_DISABLE + */ +#define CRL_APB_IR_DISABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X00000010U) ) + +#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_SHIFT 0 +#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_WIDTH 1 +#define CRL_APB_IR_DISABLE_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CRL_ECO + */ +#define CRL_APB_CRL_ECO ( ( CRL_APB_BASEADDR ) + ((u32)0X00000018U) ) + +#define CRL_APB_CRL_ECO_REG_SHIFT 0 +#define CRL_APB_CRL_ECO_REG_WIDTH 32 +#define CRL_APB_CRL_ECO_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CRL_WPROT + */ +#define CRL_APB_CRL_WPROT ( ( CRL_APB_BASEADDR ) + ((u32)0X0000001CU) ) + +#define CRL_APB_CRL_WPROT_ACTIVE_SHIFT 0 +#define CRL_APB_CRL_WPROT_ACTIVE_WIDTH 1 +#define CRL_APB_CRL_WPROT_ACTIVE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IOPLL_CTRL + */ +#define CRL_APB_IOPLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000020U) ) + +#define CRL_APB_IOPLL_CTRL_POST_SRC_SHIFT 24 +#define CRL_APB_IOPLL_CTRL_POST_SRC_WIDTH 3 +#define CRL_APB_IOPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U) + +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_WIDTH 3 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U) + +#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_SHIFT 17 +#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_WIDTH 1 +#define CRL_APB_IOPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U) + +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_WIDTH 1 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK ((u32)0X00010000U) + +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_WIDTH 7 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U) + +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_WIDTH 1 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK ((u32)0X00000008U) + +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_WIDTH 1 +#define CRL_APB_IOPLL_CTRL_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IOPLL_CFG + */ +#define CRL_APB_IOPLL_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000024U) ) + +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_WIDTH 7 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U) + +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_WIDTH 10 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U) + +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_WIDTH 2 +#define CRL_APB_IOPLL_CFG_LFHF_MASK ((u32)0X00000C00U) + +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_WIDTH 4 +#define CRL_APB_IOPLL_CFG_CP_MASK ((u32)0X000001E0U) + +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_WIDTH 4 +#define CRL_APB_IOPLL_CFG_RES_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_IOPLL_FRAC_CFG + */ +#define CRL_APB_IOPLL_FRAC_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000028U) ) + +#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 +#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_WIDTH 1 +#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U) + +#define CRL_APB_IOPLL_FRAC_CFG_SEED_SHIFT 22 +#define CRL_APB_IOPLL_FRAC_CFG_SEED_WIDTH 3 +#define CRL_APB_IOPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U) + +#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define CRL_APB_IOPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U) + +#define CRL_APB_IOPLL_FRAC_CFG_ORDER_SHIFT 18 +#define CRL_APB_IOPLL_FRAC_CFG_ORDER_WIDTH 1 +#define CRL_APB_IOPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U) + +#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 +#define CRL_APB_IOPLL_FRAC_CFG_DATA_WIDTH 16 +#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_RPLL_CTRL + */ +#define CRL_APB_RPLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000030U) ) + +#define CRL_APB_RPLL_CTRL_POST_SRC_SHIFT 24 +#define CRL_APB_RPLL_CTRL_POST_SRC_WIDTH 3 +#define CRL_APB_RPLL_CTRL_POST_SRC_MASK ((u32)0X07000000U) + +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_WIDTH 3 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK ((u32)0X00700000U) + +#define CRL_APB_RPLL_CTRL_CLKOUTDIV_SHIFT 17 +#define CRL_APB_RPLL_CTRL_CLKOUTDIV_WIDTH 1 +#define CRL_APB_RPLL_CTRL_CLKOUTDIV_MASK ((u32)0X00020000U) + +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_WIDTH 1 +#define CRL_APB_RPLL_CTRL_DIV2_MASK ((u32)0X00010000U) + +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_WIDTH 7 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK ((u32)0X00007F00U) + +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_WIDTH 1 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK ((u32)0X00000008U) + +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_WIDTH 1 +#define CRL_APB_RPLL_CTRL_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RPLL_CFG + */ +#define CRL_APB_RPLL_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000034U) ) + +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_WIDTH 7 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK ((u32)0XFE000000U) + +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_WIDTH 10 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK ((u32)0X007FE000U) + +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_WIDTH 2 +#define CRL_APB_RPLL_CFG_LFHF_MASK ((u32)0X00000C00U) + +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_WIDTH 4 +#define CRL_APB_RPLL_CFG_CP_MASK ((u32)0X000001E0U) + +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_WIDTH 4 +#define CRL_APB_RPLL_CFG_RES_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_RPLL_FRAC_CFG + */ +#define CRL_APB_RPLL_FRAC_CFG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000038U) ) + +#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 +#define CRL_APB_RPLL_FRAC_CFG_ENABLED_WIDTH 1 +#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK ((u32)0X80000000U) + +#define CRL_APB_RPLL_FRAC_CFG_SEED_SHIFT 22 +#define CRL_APB_RPLL_FRAC_CFG_SEED_WIDTH 3 +#define CRL_APB_RPLL_FRAC_CFG_SEED_MASK ((u32)0X01C00000U) + +#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define CRL_APB_RPLL_FRAC_CFG_ALGRTHM_MASK ((u32)0X00080000U) + +#define CRL_APB_RPLL_FRAC_CFG_ORDER_SHIFT 18 +#define CRL_APB_RPLL_FRAC_CFG_ORDER_WIDTH 1 +#define CRL_APB_RPLL_FRAC_CFG_ORDER_MASK ((u32)0X00040000U) + +#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 +#define CRL_APB_RPLL_FRAC_CFG_DATA_WIDTH 16 +#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_PLL_STATUS + */ +#define CRL_APB_PLL_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000040U) ) + +#define CRL_APB_PLL_STATUS_RPLL_STABLE_SHIFT 4 +#define CRL_APB_PLL_STATUS_RPLL_STABLE_WIDTH 1 +#define CRL_APB_PLL_STATUS_RPLL_STABLE_MASK ((u32)0X00000010U) + +#define CRL_APB_PLL_STATUS_IOPLL_STABLE_SHIFT 3 +#define CRL_APB_PLL_STATUS_IOPLL_STABLE_WIDTH 1 +#define CRL_APB_PLL_STATUS_IOPLL_STABLE_MASK ((u32)0X00000008U) + +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_WIDTH 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK ((u32)0X00000002U) + +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_WIDTH 1 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_IOPLL_TO_FPD_CTRL + */ +#define CRL_APB_IOPLL_TO_FPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000044U) ) + +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +/** + * Register: CRL_APB_RPLL_TO_FPD_CTRL + */ +#define CRL_APB_RPLL_TO_FPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000048U) ) + +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +/** + * Register: CRL_APB_USB3_DUAL_REF_CTRL + */ +#define CRL_APB_USB3_DUAL_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000004CU) ) + +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_GEM0_REF_CTRL + */ +#define CRL_APB_GEM0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000050U) ) + +#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_WIDTH 1 +#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U) + +#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_GEM1_REF_CTRL + */ +#define CRL_APB_GEM1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000054U) ) + +#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_WIDTH 1 +#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U) + +#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_GEM2_REF_CTRL + */ +#define CRL_APB_GEM2_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000058U) ) + +#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_WIDTH 1 +#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U) + +#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM2_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM2_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_GEM3_REF_CTRL + */ +#define CRL_APB_GEM3_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000005CU) ) + +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_WIDTH 1 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK ((u32)0X04000000U) + +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_USB0_BUS_REF_CTRL + */ +#define CRL_APB_USB0_BUS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000060U) ) + +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_USB1_BUS_REF_CTRL + */ +#define CRL_APB_USB1_BUS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000064U) ) + +#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK ((u32)0X02000000U) + +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_QSPI_REF_CTRL + */ +#define CRL_APB_QSPI_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000068U) ) + +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_SDIO0_REF_CTRL + */ +#define CRL_APB_SDIO0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000006CU) ) + +#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_SDIO1_REF_CTRL + */ +#define CRL_APB_SDIO1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000070U) ) + +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_UART0_REF_CTRL + */ +#define CRL_APB_UART0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000074U) ) + +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_UART1_REF_CTRL + */ +#define CRL_APB_UART1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000078U) ) + +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_SPI0_REF_CTRL + */ +#define CRL_APB_SPI0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000007CU) ) + +#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SPI0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SPI0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_SPI1_REF_CTRL + */ +#define CRL_APB_SPI1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000080U) ) + +#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SPI1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SPI1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_CAN0_REF_CTRL + */ +#define CRL_APB_CAN0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000084U) ) + +#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_CAN1_REF_CTRL + */ +#define CRL_APB_CAN1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000088U) ) + +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_CPU_R5_CTRL + */ +#define CRL_APB_CPU_R5_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000090U) ) + +#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_SHIFT 25 +#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_WIDTH 1 +#define CRL_APB_CPU_R5_CTRL_CLKACT_CORE_MASK ((u32)0X02000000U) + +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_IOU_SWITCH_CTRL + */ +#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000009CU) ) + +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_CSU_PLL_CTRL + */ +#define CRL_APB_CSU_PLL_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A0U) ) + +#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CSU_PLL_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CSU_PLL_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PCAP_CTRL + */ +#define CRL_APB_PCAP_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A4U) ) + +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_LPD_SWITCH_CTRL + */ +#define CRL_APB_LPD_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000A8U) ) + +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_LPD_LSBUS_CTRL + */ +#define CRL_APB_LPD_LSBUS_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000ACU) ) + +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_DBG_LPD_CTRL + */ +#define CRL_APB_DBG_LPD_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B0U) ) + +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_NAND_REF_CTRL + */ +#define CRL_APB_NAND_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B4U) ) + +#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_NAND_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_NAND_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_NAND_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_NAND_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_ADMA_REF_CTRL + */ +#define CRL_APB_ADMA_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000B8U) ) + +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PL0_REF_CTRL + */ +#define CRL_APB_PL0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C0U) ) + +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PL1_REF_CTRL + */ +#define CRL_APB_PL1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C4U) ) + +#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PL2_REF_CTRL + */ +#define CRL_APB_PL2_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000C8U) ) + +#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL2_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL2_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL2_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL2_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PL3_REF_CTRL + */ +#define CRL_APB_PL3_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000CCU) ) + +#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL3_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL3_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL3_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL3_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PL0_THR_CTRL + */ +#define CRL_APB_PL0_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D0U) ) + +#define CRL_APB_PL0_THR_CTRL_CURR_VAL_SHIFT 16 +#define CRL_APB_PL0_THR_CTRL_CURR_VAL_WIDTH 16 +#define CRL_APB_PL0_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U) + +#define CRL_APB_PL0_THR_CTRL_RUNNING_SHIFT 15 +#define CRL_APB_PL0_THR_CTRL_RUNNING_WIDTH 1 +#define CRL_APB_PL0_THR_CTRL_RUNNING_MASK ((u32)0X00008000U) + +#define CRL_APB_PL0_THR_CTRL_CPU_START_SHIFT 1 +#define CRL_APB_PL0_THR_CTRL_CPU_START_WIDTH 1 +#define CRL_APB_PL0_THR_CTRL_CPU_START_MASK ((u32)0X00000002U) + +#define CRL_APB_PL0_THR_CTRL_CNT_RST_SHIFT 0 +#define CRL_APB_PL0_THR_CTRL_CNT_RST_WIDTH 1 +#define CRL_APB_PL0_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PL0_THR_CNT + */ +#define CRL_APB_PL0_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D4U) ) + +#define CRL_APB_PL0_THR_CNT_LAST_CNT_SHIFT 0 +#define CRL_APB_PL0_THR_CNT_LAST_CNT_WIDTH 16 +#define CRL_APB_PL0_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_PL1_THR_CTRL + */ +#define CRL_APB_PL1_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000D8U) ) + +#define CRL_APB_PL1_THR_CTRL_CURR_VAL_SHIFT 16 +#define CRL_APB_PL1_THR_CTRL_CURR_VAL_WIDTH 16 +#define CRL_APB_PL1_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U) + +#define CRL_APB_PL1_THR_CTRL_RUNNING_SHIFT 15 +#define CRL_APB_PL1_THR_CTRL_RUNNING_WIDTH 1 +#define CRL_APB_PL1_THR_CTRL_RUNNING_MASK ((u32)0X00008000U) + +#define CRL_APB_PL1_THR_CTRL_CPU_START_SHIFT 1 +#define CRL_APB_PL1_THR_CTRL_CPU_START_WIDTH 1 +#define CRL_APB_PL1_THR_CTRL_CPU_START_MASK ((u32)0X00000002U) + +#define CRL_APB_PL1_THR_CTRL_CNT_RST_SHIFT 0 +#define CRL_APB_PL1_THR_CTRL_CNT_RST_WIDTH 1 +#define CRL_APB_PL1_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PL1_THR_CNT + */ +#define CRL_APB_PL1_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000DCU) ) + +#define CRL_APB_PL1_THR_CNT_LAST_CNT_SHIFT 0 +#define CRL_APB_PL1_THR_CNT_LAST_CNT_WIDTH 16 +#define CRL_APB_PL1_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_PL2_THR_CTRL + */ +#define CRL_APB_PL2_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E0U) ) + +#define CRL_APB_PL2_THR_CTRL_CURR_VAL_SHIFT 16 +#define CRL_APB_PL2_THR_CTRL_CURR_VAL_WIDTH 16 +#define CRL_APB_PL2_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U) + +#define CRL_APB_PL2_THR_CTRL_RUNNING_SHIFT 15 +#define CRL_APB_PL2_THR_CTRL_RUNNING_WIDTH 1 +#define CRL_APB_PL2_THR_CTRL_RUNNING_MASK ((u32)0X00008000U) + +#define CRL_APB_PL2_THR_CTRL_CPU_START_SHIFT 1 +#define CRL_APB_PL2_THR_CTRL_CPU_START_WIDTH 1 +#define CRL_APB_PL2_THR_CTRL_CPU_START_MASK ((u32)0X00000002U) + +#define CRL_APB_PL2_THR_CTRL_CNT_RST_SHIFT 0 +#define CRL_APB_PL2_THR_CTRL_CNT_RST_WIDTH 1 +#define CRL_APB_PL2_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PL2_THR_CNT + */ +#define CRL_APB_PL2_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E4U) ) + +#define CRL_APB_PL2_THR_CNT_LAST_CNT_SHIFT 0 +#define CRL_APB_PL2_THR_CNT_LAST_CNT_WIDTH 16 +#define CRL_APB_PL2_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_PL3_THR_CTRL + */ +#define CRL_APB_PL3_THR_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000000E8U) ) + +#define CRL_APB_PL3_THR_CTRL_CURR_VAL_SHIFT 16 +#define CRL_APB_PL3_THR_CTRL_CURR_VAL_WIDTH 16 +#define CRL_APB_PL3_THR_CTRL_CURR_VAL_MASK ((u32)0XFFFF0000U) + +#define CRL_APB_PL3_THR_CTRL_RUNNING_SHIFT 15 +#define CRL_APB_PL3_THR_CTRL_RUNNING_WIDTH 1 +#define CRL_APB_PL3_THR_CTRL_RUNNING_MASK ((u32)0X00008000U) + +#define CRL_APB_PL3_THR_CTRL_CPU_START_SHIFT 1 +#define CRL_APB_PL3_THR_CTRL_CPU_START_WIDTH 1 +#define CRL_APB_PL3_THR_CTRL_CPU_START_MASK ((u32)0X00000002U) + +#define CRL_APB_PL3_THR_CTRL_CNT_RST_SHIFT 0 +#define CRL_APB_PL3_THR_CTRL_CNT_RST_WIDTH 1 +#define CRL_APB_PL3_THR_CTRL_CNT_RST_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PL3_THR_CNT + */ +#define CRL_APB_PL3_THR_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000000FCU) ) + +#define CRL_APB_PL3_THR_CNT_LAST_CNT_SHIFT 0 +#define CRL_APB_PL3_THR_CNT_LAST_CNT_WIDTH 16 +#define CRL_APB_PL3_THR_CNT_LAST_CNT_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_GEM_TSU_REF_CTRL + */ +#define CRL_APB_GEM_TSU_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000100U) ) + +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_DLL_REF_CTRL + */ +#define CRL_APB_DLL_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000104U) ) + +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_AMS_REF_CTRL + */ +#define CRL_APB_AMS_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000108U) ) + +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_I2C0_REF_CTRL + */ +#define CRL_APB_I2C0_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000120U) ) + +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_I2C1_REF_CTRL + */ +#define CRL_APB_I2C1_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000124U) ) + +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_TIMESTAMP_REF_CTRL + */ +#define CRL_APB_TIMESTAMP_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000128U) ) + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_SAFTEY_CHK + */ +#define CRL_APB_SAFTEY_CHK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000130U) ) + +#define CRL_APB_SAFTEY_CHK_CHK_VAL_SHIFT 0 +#define CRL_APB_SAFTEY_CHK_CHK_VAL_WIDTH 32 +#define CRL_APB_SAFTEY_CHK_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CLKMON_STATUS + */ +#define CRL_APB_CLKMON_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000140U) ) + +#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_SHIFT 15 +#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA7_OVER_ERR_MASK ((u32)0X00008000U) + +#define CRL_APB_CLKMON_STATUS_MON7_ERR_SHIFT 14 +#define CRL_APB_CLKMON_STATUS_MON7_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON7_ERR_MASK ((u32)0X00004000U) + +#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_SHIFT 13 +#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA6_OVER_ERR_MASK ((u32)0X00002000U) + +#define CRL_APB_CLKMON_STATUS_MON6_ERR_SHIFT 12 +#define CRL_APB_CLKMON_STATUS_MON6_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON6_ERR_MASK ((u32)0X00001000U) + +#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_SHIFT 11 +#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA5_OVER_ERR_MASK ((u32)0X00000800U) + +#define CRL_APB_CLKMON_STATUS_MON5_ERR_SHIFT 10 +#define CRL_APB_CLKMON_STATUS_MON5_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON5_ERR_MASK ((u32)0X00000400U) + +#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_SHIFT 9 +#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA4_OVER_ERR_MASK ((u32)0X00000200U) + +#define CRL_APB_CLKMON_STATUS_MON4_ERR_SHIFT 8 +#define CRL_APB_CLKMON_STATUS_MON4_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON4_ERR_MASK ((u32)0X00000100U) + +#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_SHIFT 7 +#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA3_OVER_ERR_MASK ((u32)0X00000080U) + +#define CRL_APB_CLKMON_STATUS_MON3_ERR_SHIFT 6 +#define CRL_APB_CLKMON_STATUS_MON3_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON3_ERR_MASK ((u32)0X00000040U) + +#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_SHIFT 5 +#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA2_OVER_ERR_MASK ((u32)0X00000020U) + +#define CRL_APB_CLKMON_STATUS_MON2_ERR_SHIFT 4 +#define CRL_APB_CLKMON_STATUS_MON2_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON2_ERR_MASK ((u32)0X00000010U) + +#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_SHIFT 3 +#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA1_OVER_ERR_MASK ((u32)0X00000008U) + +#define CRL_APB_CLKMON_STATUS_MON1_ERR_SHIFT 2 +#define CRL_APB_CLKMON_STATUS_MON1_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON1_ERR_MASK ((u32)0X00000004U) + +#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_SHIFT 1 +#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_CNTA0_OVER_ERR_MASK ((u32)0X00000002U) + +#define CRL_APB_CLKMON_STATUS_MON0_ERR_SHIFT 0 +#define CRL_APB_CLKMON_STATUS_MON0_ERR_WIDTH 1 +#define CRL_APB_CLKMON_STATUS_MON0_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CLKMON_MASK + */ +#define CRL_APB_CLKMON_MASK ( ( CRL_APB_BASEADDR ) + ((u32)0X00000144U) ) + +#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_SHIFT 15 +#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA7_OVER_ERR_MASK ((u32)0X00008000U) + +#define CRL_APB_CLKMON_MASK_MON7_ERR_SHIFT 14 +#define CRL_APB_CLKMON_MASK_MON7_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON7_ERR_MASK ((u32)0X00004000U) + +#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_SHIFT 13 +#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA6_OVER_ERR_MASK ((u32)0X00002000U) + +#define CRL_APB_CLKMON_MASK_MON6_ERR_SHIFT 12 +#define CRL_APB_CLKMON_MASK_MON6_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON6_ERR_MASK ((u32)0X00001000U) + +#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_SHIFT 11 +#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA5_OVER_ERR_MASK ((u32)0X00000800U) + +#define CRL_APB_CLKMON_MASK_MON5_ERR_SHIFT 10 +#define CRL_APB_CLKMON_MASK_MON5_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON5_ERR_MASK ((u32)0X00000400U) + +#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_SHIFT 9 +#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA4_OVER_ERR_MASK ((u32)0X00000200U) + +#define CRL_APB_CLKMON_MASK_MON4_ERR_SHIFT 8 +#define CRL_APB_CLKMON_MASK_MON4_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON4_ERR_MASK ((u32)0X00000100U) + +#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_SHIFT 7 +#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA3_OVER_ERR_MASK ((u32)0X00000080U) + +#define CRL_APB_CLKMON_MASK_MON3_ERR_SHIFT 6 +#define CRL_APB_CLKMON_MASK_MON3_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON3_ERR_MASK ((u32)0X00000040U) + +#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_SHIFT 5 +#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA2_OVER_ERR_MASK ((u32)0X00000020U) + +#define CRL_APB_CLKMON_MASK_MON2_ERR_SHIFT 4 +#define CRL_APB_CLKMON_MASK_MON2_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON2_ERR_MASK ((u32)0X00000010U) + +#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_SHIFT 3 +#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA1_OVER_ERR_MASK ((u32)0X00000008U) + +#define CRL_APB_CLKMON_MASK_MON1_ERR_SHIFT 2 +#define CRL_APB_CLKMON_MASK_MON1_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON1_ERR_MASK ((u32)0X00000004U) + +#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_SHIFT 1 +#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_CNTA0_OVER_ERR_MASK ((u32)0X00000002U) + +#define CRL_APB_CLKMON_MASK_MON0_ERR_SHIFT 0 +#define CRL_APB_CLKMON_MASK_MON0_ERR_WIDTH 1 +#define CRL_APB_CLKMON_MASK_MON0_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CLKMON_ENABLE + */ +#define CRL_APB_CLKMON_ENABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X00000148U) ) + +#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_SHIFT 15 +#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA7_OVER_ERR_MASK ((u32)0X00008000U) + +#define CRL_APB_CLKMON_ENABLE_MON7_ERR_SHIFT 14 +#define CRL_APB_CLKMON_ENABLE_MON7_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON7_ERR_MASK ((u32)0X00004000U) + +#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_SHIFT 13 +#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA6_OVER_ERR_MASK ((u32)0X00002000U) + +#define CRL_APB_CLKMON_ENABLE_MON6_ERR_SHIFT 12 +#define CRL_APB_CLKMON_ENABLE_MON6_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON6_ERR_MASK ((u32)0X00001000U) + +#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_SHIFT 11 +#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA5_OVER_ERR_MASK ((u32)0X00000800U) + +#define CRL_APB_CLKMON_ENABLE_MON5_ERR_SHIFT 10 +#define CRL_APB_CLKMON_ENABLE_MON5_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON5_ERR_MASK ((u32)0X00000400U) + +#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_SHIFT 9 +#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA4_OVER_ERR_MASK ((u32)0X00000200U) + +#define CRL_APB_CLKMON_ENABLE_MON4_ERR_SHIFT 8 +#define CRL_APB_CLKMON_ENABLE_MON4_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON4_ERR_MASK ((u32)0X00000100U) + +#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_SHIFT 7 +#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA3_OVER_ERR_MASK ((u32)0X00000080U) + +#define CRL_APB_CLKMON_ENABLE_MON3_ERR_SHIFT 6 +#define CRL_APB_CLKMON_ENABLE_MON3_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON3_ERR_MASK ((u32)0X00000040U) + +#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_SHIFT 5 +#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA2_OVER_ERR_MASK ((u32)0X00000020U) + +#define CRL_APB_CLKMON_ENABLE_MON2_ERR_SHIFT 4 +#define CRL_APB_CLKMON_ENABLE_MON2_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON2_ERR_MASK ((u32)0X00000010U) + +#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_SHIFT 3 +#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA1_OVER_ERR_MASK ((u32)0X00000008U) + +#define CRL_APB_CLKMON_ENABLE_MON1_ERR_SHIFT 2 +#define CRL_APB_CLKMON_ENABLE_MON1_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON1_ERR_MASK ((u32)0X00000004U) + +#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_SHIFT 1 +#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_CNTA0_OVER_ERR_MASK ((u32)0X00000002U) + +#define CRL_APB_CLKMON_ENABLE_MON0_ERR_SHIFT 0 +#define CRL_APB_CLKMON_ENABLE_MON0_ERR_WIDTH 1 +#define CRL_APB_CLKMON_ENABLE_MON0_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CLKMON_DISABLE + */ +#define CRL_APB_CLKMON_DISABLE ( ( CRL_APB_BASEADDR ) + ((u32)0X0000014CU) ) + +#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_SHIFT 15 +#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA7_OVER_ERR_MASK ((u32)0X00008000U) + +#define CRL_APB_CLKMON_DISABLE_MON7_ERR_SHIFT 14 +#define CRL_APB_CLKMON_DISABLE_MON7_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON7_ERR_MASK ((u32)0X00004000U) + +#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_SHIFT 13 +#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA6_OVER_ERR_MASK ((u32)0X00002000U) + +#define CRL_APB_CLKMON_DISABLE_MON6_ERR_SHIFT 12 +#define CRL_APB_CLKMON_DISABLE_MON6_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON6_ERR_MASK ((u32)0X00001000U) + +#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_SHIFT 11 +#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA5_OVER_ERR_MASK ((u32)0X00000800U) + +#define CRL_APB_CLKMON_DISABLE_MON5_ERR_SHIFT 10 +#define CRL_APB_CLKMON_DISABLE_MON5_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON5_ERR_MASK ((u32)0X00000400U) + +#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_SHIFT 9 +#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA4_OVER_ERR_MASK ((u32)0X00000200U) + +#define CRL_APB_CLKMON_DISABLE_MON4_ERR_SHIFT 8 +#define CRL_APB_CLKMON_DISABLE_MON4_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON4_ERR_MASK ((u32)0X00000100U) + +#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_SHIFT 7 +#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA3_OVER_ERR_MASK ((u32)0X00000080U) + +#define CRL_APB_CLKMON_DISABLE_MON3_ERR_SHIFT 6 +#define CRL_APB_CLKMON_DISABLE_MON3_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON3_ERR_MASK ((u32)0X00000040U) + +#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_SHIFT 5 +#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA2_OVER_ERR_MASK ((u32)0X00000020U) + +#define CRL_APB_CLKMON_DISABLE_MON2_ERR_SHIFT 4 +#define CRL_APB_CLKMON_DISABLE_MON2_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON2_ERR_MASK ((u32)0X00000010U) + +#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_SHIFT 3 +#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA1_OVER_ERR_MASK ((u32)0X00000008U) + +#define CRL_APB_CLKMON_DISABLE_MON1_ERR_SHIFT 2 +#define CRL_APB_CLKMON_DISABLE_MON1_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON1_ERR_MASK ((u32)0X00000004U) + +#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_SHIFT 1 +#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_CNTA0_OVER_ERR_MASK ((u32)0X00000002U) + +#define CRL_APB_CLKMON_DISABLE_MON0_ERR_SHIFT 0 +#define CRL_APB_CLKMON_DISABLE_MON0_ERR_WIDTH 1 +#define CRL_APB_CLKMON_DISABLE_MON0_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CLKMON_TRIGGER + */ +#define CRL_APB_CLKMON_TRIGGER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000150U) ) + +#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_SHIFT 15 +#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA7_OVER_ERR_MASK ((u32)0X00008000U) + +#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_SHIFT 14 +#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON7_ERR_MASK ((u32)0X00004000U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_SHIFT 13 +#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA6_OVER_ERR_MASK ((u32)0X00002000U) + +#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_SHIFT 12 +#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON6_ERR_MASK ((u32)0X00001000U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_SHIFT 11 +#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA5_OVER_ERR_MASK ((u32)0X00000800U) + +#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_SHIFT 10 +#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON5_ERR_MASK ((u32)0X00000400U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_SHIFT 9 +#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA4_OVER_ERR_MASK ((u32)0X00000200U) + +#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_SHIFT 8 +#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON4_ERR_MASK ((u32)0X00000100U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_SHIFT 7 +#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA3_OVER_ERR_MASK ((u32)0X00000080U) + +#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_SHIFT 6 +#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON3_ERR_MASK ((u32)0X00000040U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_SHIFT 5 +#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA2_OVER_ERR_MASK ((u32)0X00000020U) + +#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_SHIFT 4 +#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON2_ERR_MASK ((u32)0X00000010U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_SHIFT 3 +#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA1_OVER_ERR_MASK ((u32)0X00000008U) + +#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_SHIFT 2 +#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON1_ERR_MASK ((u32)0X00000004U) + +#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_SHIFT 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_CNTA0_OVER_ERR_MASK ((u32)0X00000002U) + +#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_SHIFT 0 +#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_WIDTH 1 +#define CRL_APB_CLKMON_TRIGGER_MON0_ERR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR0_CLKA_UPPER + */ +#define CRL_APB_CHKR0_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000160U) ) + +#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR0_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR0_CLKA_LOWER + */ +#define CRL_APB_CHKR0_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000164U) ) + +#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR0_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR0_CLKB_CNT + */ +#define CRL_APB_CHKR0_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000168U) ) + +#define CRL_APB_CHKR0_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR0_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR0_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR0_CTRL + */ +#define CRL_APB_CHKR0_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000016CU) ) + +#define CRL_APB_CHKR0_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR0_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR0_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR0_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR0_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR0_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR0_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR0_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR0_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR1_CLKA_UPPER + */ +#define CRL_APB_CHKR1_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000170U) ) + +#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR1_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR1_CLKA_LOWER + */ +#define CRL_APB_CHKR1_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000174U) ) + +#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR1_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR1_CLKB_CNT + */ +#define CRL_APB_CHKR1_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000178U) ) + +#define CRL_APB_CHKR1_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR1_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR1_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR1_CTRL + */ +#define CRL_APB_CHKR1_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000017CU) ) + +#define CRL_APB_CHKR1_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR1_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR1_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR1_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR1_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR1_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR1_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR1_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR1_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR2_CLKA_UPPER + */ +#define CRL_APB_CHKR2_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000180U) ) + +#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR2_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR2_CLKA_LOWER + */ +#define CRL_APB_CHKR2_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000184U) ) + +#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR2_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR2_CLKB_CNT + */ +#define CRL_APB_CHKR2_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000188U) ) + +#define CRL_APB_CHKR2_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR2_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR2_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR2_CTRL + */ +#define CRL_APB_CHKR2_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000018CU) ) + +#define CRL_APB_CHKR2_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR2_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR2_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR2_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR2_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR2_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR2_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR2_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR2_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR3_CLKA_UPPER + */ +#define CRL_APB_CHKR3_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000190U) ) + +#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR3_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR3_CLKA_LOWER + */ +#define CRL_APB_CHKR3_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000194U) ) + +#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR3_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR3_CLKB_CNT + */ +#define CRL_APB_CHKR3_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X00000198U) ) + +#define CRL_APB_CHKR3_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR3_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR3_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR3_CTRL + */ +#define CRL_APB_CHKR3_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X0000019CU) ) + +#define CRL_APB_CHKR3_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR3_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR3_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR3_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR3_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR3_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR3_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR3_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR3_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR4_CLKA_UPPER + */ +#define CRL_APB_CHKR4_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A0U) ) + +#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR4_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR4_CLKA_LOWER + */ +#define CRL_APB_CHKR4_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A4U) ) + +#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR4_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR4_CLKB_CNT + */ +#define CRL_APB_CHKR4_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001A8U) ) + +#define CRL_APB_CHKR4_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR4_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR4_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR4_CTRL + */ +#define CRL_APB_CHKR4_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001ACU) ) + +#define CRL_APB_CHKR4_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR4_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR4_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR4_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR4_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR4_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR4_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR4_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR4_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR5_CLKA_UPPER + */ +#define CRL_APB_CHKR5_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B0U) ) + +#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR5_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR5_CLKA_LOWER + */ +#define CRL_APB_CHKR5_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B4U) ) + +#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR5_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR5_CLKB_CNT + */ +#define CRL_APB_CHKR5_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001B8U) ) + +#define CRL_APB_CHKR5_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR5_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR5_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR5_CTRL + */ +#define CRL_APB_CHKR5_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001BCU) ) + +#define CRL_APB_CHKR5_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR5_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR5_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR5_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR5_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR5_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR5_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR5_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR5_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR6_CLKA_UPPER + */ +#define CRL_APB_CHKR6_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C0U) ) + +#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR6_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR6_CLKA_LOWER + */ +#define CRL_APB_CHKR6_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C4U) ) + +#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR6_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR6_CLKB_CNT + */ +#define CRL_APB_CHKR6_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001C8U) ) + +#define CRL_APB_CHKR6_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR6_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR6_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR6_CTRL + */ +#define CRL_APB_CHKR6_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001CCU) ) + +#define CRL_APB_CHKR6_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR6_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR6_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR6_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR6_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR6_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR6_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR6_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR6_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_CHKR7_CLKA_UPPER + */ +#define CRL_APB_CHKR7_CLKA_UPPER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D0U) ) + +#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR7_CLKA_UPPER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR7_CLKA_LOWER + */ +#define CRL_APB_CHKR7_CLKA_LOWER ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D4U) ) + +#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_SHIFT 0 +#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_WIDTH 32 +#define CRL_APB_CHKR7_CLKA_LOWER_THRSHLD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR7_CLKB_CNT + */ +#define CRL_APB_CHKR7_CLKB_CNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001D8U) ) + +#define CRL_APB_CHKR7_CLKB_CNT_VALUE_SHIFT 0 +#define CRL_APB_CHKR7_CLKB_CNT_VALUE_WIDTH 32 +#define CRL_APB_CHKR7_CLKB_CNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_CHKR7_CTRL + */ +#define CRL_APB_CHKR7_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001DCU) ) + +#define CRL_APB_CHKR7_CTRL_START_SINGLE_SHIFT 8 +#define CRL_APB_CHKR7_CTRL_START_SINGLE_WIDTH 1 +#define CRL_APB_CHKR7_CTRL_START_SINGLE_MASK ((u32)0X00000100U) + +#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_SHIFT 7 +#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_WIDTH 1 +#define CRL_APB_CHKR7_CTRL_START_CONTINUOUS_MASK ((u32)0X00000080U) + +#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_SHIFT 5 +#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_WIDTH 1 +#define CRL_APB_CHKR7_CTRL_CLKB_MUX_CTRL_MASK ((u32)0X00000020U) + +#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_SHIFT 1 +#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_WIDTH 3 +#define CRL_APB_CHKR7_CTRL_CLKA_MUX_CTRL_MASK ((u32)0X0000000EU) + +#define CRL_APB_CHKR7_CTRL_ENABLE_SHIFT 0 +#define CRL_APB_CHKR7_CTRL_ENABLE_WIDTH 1 +#define CRL_APB_CHKR7_CTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PICDEBUG_TEMP_CTRL + */ +#define CRL_APB_PICDEBUG_TEMP_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E0U) ) + +#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PICDEBUG_TEMP_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PICDEBUG_REF_CTRL + */ +#define CRL_APB_PICDEBUG_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E4U) ) + +#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_PICDEBUG_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_WIDTH 6 +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR1_MASK ((u32)0X003F0000U) + +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_PICDEBUG_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_PICDEBUG_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_PICDEBUG_CTRL + */ +#define CRL_APB_PICDEBUG_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001E8U) ) + +#define CRL_APB_PICDEBUG_CTRL_START_SHIFT 4 +#define CRL_APB_PICDEBUG_CTRL_START_WIDTH 1 +#define CRL_APB_PICDEBUG_CTRL_START_MASK ((u32)0X00000010U) + +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_SHIFT 2 +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_WIDTH 2 +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_SEL_MASK ((u32)0X0000000CU) + +#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_SHIFT 1 +#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_WIDTH 1 +#define CRL_APB_PICDEBUG_CTRL_CNT_LOAD_MASK ((u32)0X00000002U) + +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_SHIFT 0 +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_WIDTH 1 +#define CRL_APB_PICDEBUG_CTRL_TRIGGER_EN_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_PICDEBUG_LCNT + */ +#define CRL_APB_PICDEBUG_LCNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001ECU) ) + +#define CRL_APB_PICDEBUG_LCNT_VALUE_SHIFT 0 +#define CRL_APB_PICDEBUG_LCNT_VALUE_WIDTH 32 +#define CRL_APB_PICDEBUG_LCNT_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: CRL_APB_PICDEBUG_UCNT + */ +#define CRL_APB_PICDEBUG_UCNT ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F0U) ) + +#define CRL_APB_PICDEBUG_UCNT_VALUE_SHIFT 0 +#define CRL_APB_PICDEBUG_UCNT_VALUE_WIDTH 16 +#define CRL_APB_PICDEBUG_UCNT_VALUE_MASK ((u32)0X0000FFFFU) + +/** + * Register: CRL_APB_USB3_DUAL_SCAN_CTRL + */ +#define CRL_APB_USB3_DUAL_SCAN_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F4U) ) + +#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_USB3_DUAL_SCAN_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_DFT_OSC_REF_CTRL + */ +#define CRL_APB_DFT_OSC_REF_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X000001F8U) ) + +#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_WIDTH 1 +#define CRL_APB_DFT_OSC_REF_CTRL_CLKACT_MASK ((u32)0X01000000U) + +#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_WIDTH 6 +#define CRL_APB_DFT_OSC_REF_CTRL_DIVISOR0_MASK ((u32)0X00003F00U) + +#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_WIDTH 3 +#define CRL_APB_DFT_OSC_REF_CTRL_SRCSEL_MASK ((u32)0X00000007U) + +/** + * Register: CRL_APB_BOOT_MODE_USER + */ +#define CRL_APB_BOOT_MODE_USER ( ( CRL_APB_BASEADDR ) + ((u32)0X00000200U) ) + +#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_SHIFT 12 +#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_WIDTH 4 +#define CRL_APB_BOOT_MODE_USER_ALT_BOOT_MODE_MASK ((u32)0X0000F000U) + +#define CRL_APB_BOOT_MODE_USER_USE_ALT_SHIFT 8 +#define CRL_APB_BOOT_MODE_USER_USE_ALT_WIDTH 1 +#define CRL_APB_BOOT_MODE_USER_USE_ALT_MASK ((u32)0X00000100U) + +#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_SHIFT 0 +#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_WIDTH 4 +#define CRL_APB_BOOT_MODE_USER_BOOT_MODE_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_BOOT_MODE_POR + */ +#define CRL_APB_BOOT_MODE_POR ( ( CRL_APB_BASEADDR ) + ((u32)0X00000204U) ) + +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_SHIFT 8 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_WIDTH 4 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE2_MASK ((u32)0X00000F00U) + +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_SHIFT 4 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_WIDTH 4 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE1_MASK ((u32)0X000000F0U) + +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_SHIFT 0 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_WIDTH 4 +#define CRL_APB_BOOT_MODE_POR_BOOT_MODE0_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_MIMIC_RST + */ +#define CRL_APB_MIMIC_RST ( ( CRL_APB_BASEADDR ) + ((u32)0X00000214U) ) + +#define CRL_APB_MIMIC_RST_PSONLY_SHIFT 5 +#define CRL_APB_MIMIC_RST_PSONLY_WIDTH 1 +#define CRL_APB_MIMIC_RST_PSONLY_MASK ((u32)0X00000020U) + +#define CRL_APB_MIMIC_RST_DEBUG_ONLY_SHIFT 4 +#define CRL_APB_MIMIC_RST_DEBUG_ONLY_WIDTH 1 +#define CRL_APB_MIMIC_RST_DEBUG_ONLY_MASK ((u32)0X00000010U) + +#define CRL_APB_MIMIC_RST_DEBUG_SYS_SHIFT 3 +#define CRL_APB_MIMIC_RST_DEBUG_SYS_WIDTH 1 +#define CRL_APB_MIMIC_RST_DEBUG_SYS_MASK ((u32)0X00000008U) + +#define CRL_APB_MIMIC_RST_SOFT_SHIFT 2 +#define CRL_APB_MIMIC_RST_SOFT_WIDTH 1 +#define CRL_APB_MIMIC_RST_SOFT_MASK ((u32)0X00000004U) + +#define CRL_APB_MIMIC_RST_SRST_SHIFT 1 +#define CRL_APB_MIMIC_RST_SRST_WIDTH 1 +#define CRL_APB_MIMIC_RST_SRST_MASK ((u32)0X00000002U) + +#define CRL_APB_MIMIC_RST_PMU_SYS_SHIFT 0 +#define CRL_APB_MIMIC_RST_PMU_SYS_WIDTH 1 +#define CRL_APB_MIMIC_RST_PMU_SYS_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RESET_CTRL + */ +#define CRL_APB_RESET_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000218U) ) + +#define CRL_APB_RESET_CTRL_SOFT_RESET_SHIFT 4 +#define CRL_APB_RESET_CTRL_SOFT_RESET_WIDTH 1 +#define CRL_APB_RESET_CTRL_SOFT_RESET_MASK ((u32)0X00000010U) + +#define CRL_APB_RESET_CTRL_SRST_DIS_SHIFT 0 +#define CRL_APB_RESET_CTRL_SRST_DIS_WIDTH 1 +#define CRL_APB_RESET_CTRL_SRST_DIS_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_BLOCKONLY_RST + */ +#define CRL_APB_BLOCKONLY_RST ( ( CRL_APB_BASEADDR ) + ((u32)0X0000021CU) ) + +#define CRL_APB_BLOCKONLY_RST_MIMIC_SHIFT 3 +#define CRL_APB_BLOCKONLY_RST_MIMIC_WIDTH 1 +#define CRL_APB_BLOCKONLY_RST_MIMIC_MASK ((u32)0X00000008U) + +#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_SHIFT 0 +#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_WIDTH 1 +#define CRL_APB_BLOCKONLY_RST_DEBUG_ONLY_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RESET_REASON + */ +#define CRL_APB_RESET_REASON ( ( CRL_APB_BASEADDR ) + ((u32)0X00000220U) ) + +#define CRL_APB_RESET_REASON_MIMIC_SHIFT 15 +#define CRL_APB_RESET_REASON_MIMIC_WIDTH 1 +#define CRL_APB_RESET_REASON_MIMIC_MASK ((u32)0X00008000U) + +#define CRL_APB_RESET_REASON_DEBUG_SYS_SHIFT 6 +#define CRL_APB_RESET_REASON_DEBUG_SYS_WIDTH 1 +#define CRL_APB_RESET_REASON_DEBUG_SYS_MASK ((u32)0X00000040U) + +#define CRL_APB_RESET_REASON_SOFT_SHIFT 5 +#define CRL_APB_RESET_REASON_SOFT_WIDTH 1 +#define CRL_APB_RESET_REASON_SOFT_MASK ((u32)0X00000020U) + +#define CRL_APB_RESET_REASON_SRST_SHIFT 4 +#define CRL_APB_RESET_REASON_SRST_WIDTH 1 +#define CRL_APB_RESET_REASON_SRST_MASK ((u32)0X00000010U) + +#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_SHIFT 3 +#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_WIDTH 1 +#define CRL_APB_RESET_REASON_PSONLY_RESET_REQ_MASK ((u32)0X00000008U) + +#define CRL_APB_RESET_REASON_PMU_SYS_RESET_SHIFT 2 +#define CRL_APB_RESET_REASON_PMU_SYS_RESET_WIDTH 1 +#define CRL_APB_RESET_REASON_PMU_SYS_RESET_MASK ((u32)0X00000004U) + +#define CRL_APB_RESET_REASON_INTERNAL_POR_SHIFT 1 +#define CRL_APB_RESET_REASON_INTERNAL_POR_WIDTH 1 +#define CRL_APB_RESET_REASON_INTERNAL_POR_MASK ((u32)0X00000002U) + +#define CRL_APB_RESET_REASON_EXTERNAL_POR_SHIFT 0 +#define CRL_APB_RESET_REASON_EXTERNAL_POR_WIDTH 1 +#define CRL_APB_RESET_REASON_EXTERNAL_POR_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RST_LPD_IOU0 + */ +#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000230U) ) + +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK ((u32)0X00000008U) + +#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU0_GEM2_RESET_MASK ((u32)0X00000004U) + +#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU0_GEM1_RESET_MASK ((u32)0X00000002U) + +#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU0_GEM0_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RST_LPD_IOU1 + */ +#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000234U) ) + +/** + * Register: CRL_APB_RST_LPD_IOU2 + */ +#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000238U) ) + +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK ((u32)0X00100000U) + +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK ((u32)0X00080000U) + +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK ((u32)0X00040000U) + +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK ((u32)0X00020000U) + +#define CRL_APB_RST_LPD_IOU2_NAND_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_IOU2_NAND_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_NAND_RESET_MASK ((u32)0X00010000U) + +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK ((u32)0X00008000U) + +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK ((u32)0X00004000U) + +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK ((u32)0X00002000U) + +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK ((u32)0X00001000U) + +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK ((u32)0X00000800U) + +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK ((u32)0X00000400U) + +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK ((u32)0X00000200U) + +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK ((u32)0X00000100U) + +#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_SHIFT 7 +#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_CAN0_RESET_MASK ((u32)0X00000080U) + +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK ((u32)0X00000040U) + +#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_SHIFT 5 +#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_SDIO0_RESET_MASK ((u32)0X00000020U) + +#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_SPI1_RESET_MASK ((u32)0X00000010U) + +#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_SPI0_RESET_MASK ((u32)0X00000008U) + +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK ((u32)0X00000004U) + +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK ((u32)0X00000002U) + +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RST_LPD_TOP + */ +#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + ((u32)0X0000023CU) ) + +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK ((u32)0X00800000U) + +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK ((u32)0X00100000U) + +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK ((u32)0X00080000U) + +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK ((u32)0X00020000U) + +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK ((u32)0X00010000U) + +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK ((u32)0X00008000U) + +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK ((u32)0X00004000U) + +#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK ((u32)0X00000800U) + +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK ((u32)0X00000400U) + +#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 9 +#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK ((u32)0X00000200U) + +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK ((u32)0X00000100U) + +#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 7 +#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK ((u32)0X00000080U) + +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK ((u32)0X00000040U) + +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK ((u32)0X00000010U) + +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK ((u32)0X00000008U) + +#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK ((u32)0X00000004U) + +#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ((u32)0X00000002U) + +#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_RST_LPD_DBG + */ +#define CRL_APB_RST_LPD_DBG ( ( CRL_APB_BASEADDR ) + ((u32)0X00000240U) ) + +#define CRL_APB_RST_LPD_DBG_DBG_ACK_SHIFT 15 +#define CRL_APB_RST_LPD_DBG_DBG_ACK_WIDTH 1 +#define CRL_APB_RST_LPD_DBG_DBG_ACK_MASK ((u32)0X00008000U) + +#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_SHIFT 5 +#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_DBG_RPU_DBG1_RESET_MASK ((u32)0X00000020U) + +#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_DBG_RPU_DBG0_RESET_MASK ((u32)0X00000010U) + +#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_DBG_DBG_LPD_RESET_MASK ((u32)0X00000002U) + +#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_WIDTH 1 +#define CRL_APB_RST_LPD_DBG_DBG_FPD_RESET_MASK ((u32)0X00000001U) + +/** + * Register: CRL_APB_BOOT_PIN_CTRL + */ +#define CRL_APB_BOOT_PIN_CTRL ( ( CRL_APB_BASEADDR ) + ((u32)0X00000250U) ) + +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_WIDTH 4 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK ((u32)0X00000F00U) + +#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_SHIFT 4 +#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_WIDTH 4 +#define CRL_APB_BOOT_PIN_CTRL_IN_VAL_MASK ((u32)0X000000F0U) + +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_WIDTH 4 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL0 + */ +#define CRL_APB_DED_IOB_CTRL0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000254U) ) + +#define CRL_APB_DED_IOB_CTRL0_DRIVE0_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL0_DRIVE0_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL0_DRIVE0_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL1 + */ +#define CRL_APB_DED_IOB_CTRL1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000258U) ) + +#define CRL_APB_DED_IOB_CTRL1_DRIVE1_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL1_DRIVE1_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL1_DRIVE1_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL2 + */ +#define CRL_APB_DED_IOB_CTRL2 ( ( CRL_APB_BASEADDR ) + ((u32)0X0000025CU) ) + +#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL2_SCHMITT_CMOS_N_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL3 + */ +#define CRL_APB_DED_IOB_CTRL3 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000260U) ) + +#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL3_PULL_HIGH_LOW_N_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL4 + */ +#define CRL_APB_DED_IOB_CTRL4 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000264U) ) + +#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL4_PULL_ENABLE_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_DED_IOB_CTRL5 + */ +#define CRL_APB_DED_IOB_CTRL5 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000268U) ) + +#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_SHIFT 0 +#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_WIDTH 4 +#define CRL_APB_DED_IOB_CTRL5_SLOW_FAST_SLEW_N_MASK ((u32)0X0000000FU) + +/** + * Register: CRL_APB_BANK3_CTRL0 + */ +#define CRL_APB_BANK3_CTRL0 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000270U) ) + +#define CRL_APB_BANK3_CTRL0_DRIVE0_SHIFT 0 +#define CRL_APB_BANK3_CTRL0_DRIVE0_WIDTH 10 +#define CRL_APB_BANK3_CTRL0_DRIVE0_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_CTRL1 + */ +#define CRL_APB_BANK3_CTRL1 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000274U) ) + +#define CRL_APB_BANK3_CTRL1_DRIVE1_SHIFT 0 +#define CRL_APB_BANK3_CTRL1_DRIVE1_WIDTH 10 +#define CRL_APB_BANK3_CTRL1_DRIVE1_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_CTRL2 + */ +#define CRL_APB_BANK3_CTRL2 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000278U) ) + +#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_SHIFT 0 +#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_WIDTH 10 +#define CRL_APB_BANK3_CTRL2_SCHMITT_CMOS_N_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_CTRL3 + */ +#define CRL_APB_BANK3_CTRL3 ( ( CRL_APB_BASEADDR ) + ((u32)0X0000027CU) ) + +#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_SHIFT 0 +#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_WIDTH 10 +#define CRL_APB_BANK3_CTRL3_PULL_HIGH_LOW_N_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_CTRL4 + */ +#define CRL_APB_BANK3_CTRL4 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000280U) ) + +#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_SHIFT 0 +#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_WIDTH 10 +#define CRL_APB_BANK3_CTRL4_PULL_ENABLE_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_CTRL5 + */ +#define CRL_APB_BANK3_CTRL5 ( ( CRL_APB_BASEADDR ) + ((u32)0X00000284U) ) + +#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_SHIFT 0 +#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_WIDTH 10 +#define CRL_APB_BANK3_CTRL5_SLOW_FAST_SLEW_N_MASK ((u32)0X000003FFU) + +/** + * Register: CRL_APB_BANK3_STATUS + */ +#define CRL_APB_BANK3_STATUS ( ( CRL_APB_BASEADDR ) + ((u32)0X00000288U) ) + +#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_SHIFT 0 +#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_WIDTH 1 +#define CRL_APB_BANK3_STATUS_VMODE_1P8_3P3_N_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _CRL_APB_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/ipi.h b/lib/sw_apps/zynqmp_pmufw/src/ipi.h new file mode 100644 index 00000000..1df43731 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/ipi.h @@ -0,0 +1,3347 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _IPI_H_ +#define _IPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * IPI Base Address + */ +#define IPI_BASEADDR ((u32)0XFF300000U) + +/** + * Register: IPI_APU_TRIG + */ +#define IPI_APU_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00000000U) ) + +#define IPI_APU_TRIG_PL_3_SHIFT 27 +#define IPI_APU_TRIG_PL_3_WIDTH 1 +#define IPI_APU_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_TRIG_PL_2_SHIFT 26 +#define IPI_APU_TRIG_PL_2_WIDTH 1 +#define IPI_APU_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_TRIG_PL_1_SHIFT 25 +#define IPI_APU_TRIG_PL_1_WIDTH 1 +#define IPI_APU_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_TRIG_PL_0_SHIFT 24 +#define IPI_APU_TRIG_PL_0_WIDTH 1 +#define IPI_APU_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_TRIG_PMU_3_SHIFT 19 +#define IPI_APU_TRIG_PMU_3_WIDTH 1 +#define IPI_APU_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_TRIG_PMU_2_SHIFT 18 +#define IPI_APU_TRIG_PMU_2_WIDTH 1 +#define IPI_APU_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_TRIG_PMU_1_SHIFT 17 +#define IPI_APU_TRIG_PMU_1_WIDTH 1 +#define IPI_APU_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_TRIG_PMU_0_SHIFT 16 +#define IPI_APU_TRIG_PMU_0_WIDTH 1 +#define IPI_APU_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_TRIG_RPU_1_SHIFT 9 +#define IPI_APU_TRIG_RPU_1_WIDTH 1 +#define IPI_APU_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_TRIG_RPU_0_SHIFT 8 +#define IPI_APU_TRIG_RPU_0_WIDTH 1 +#define IPI_APU_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_TRIG_APU_SHIFT 0 +#define IPI_APU_TRIG_APU_WIDTH 1 +#define IPI_APU_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_APU_OBS + */ +#define IPI_APU_OBS ( ( IPI_BASEADDR ) + ((u32)0X00000004U) ) + +#define IPI_APU_OBS_PL_3_SHIFT 27 +#define IPI_APU_OBS_PL_3_WIDTH 1 +#define IPI_APU_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_OBS_PL_2_SHIFT 26 +#define IPI_APU_OBS_PL_2_WIDTH 1 +#define IPI_APU_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_OBS_PL_1_SHIFT 25 +#define IPI_APU_OBS_PL_1_WIDTH 1 +#define IPI_APU_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_OBS_PL_0_SHIFT 24 +#define IPI_APU_OBS_PL_0_WIDTH 1 +#define IPI_APU_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_OBS_PMU_3_SHIFT 19 +#define IPI_APU_OBS_PMU_3_WIDTH 1 +#define IPI_APU_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_OBS_PMU_2_SHIFT 18 +#define IPI_APU_OBS_PMU_2_WIDTH 1 +#define IPI_APU_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_OBS_PMU_1_SHIFT 17 +#define IPI_APU_OBS_PMU_1_WIDTH 1 +#define IPI_APU_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_OBS_PMU_0_SHIFT 16 +#define IPI_APU_OBS_PMU_0_WIDTH 1 +#define IPI_APU_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_OBS_RPU_1_SHIFT 9 +#define IPI_APU_OBS_RPU_1_WIDTH 1 +#define IPI_APU_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_OBS_RPU_0_SHIFT 8 +#define IPI_APU_OBS_RPU_0_WIDTH 1 +#define IPI_APU_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_OBS_APU_SHIFT 0 +#define IPI_APU_OBS_APU_WIDTH 1 +#define IPI_APU_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_APU_ISR + */ +#define IPI_APU_ISR ( ( IPI_BASEADDR ) + ((u32)0X00000010U) ) + +#define IPI_APU_ISR_PL_3_SHIFT 27 +#define IPI_APU_ISR_PL_3_WIDTH 1 +#define IPI_APU_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_ISR_PL_2_SHIFT 26 +#define IPI_APU_ISR_PL_2_WIDTH 1 +#define IPI_APU_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_ISR_PL_1_SHIFT 25 +#define IPI_APU_ISR_PL_1_WIDTH 1 +#define IPI_APU_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_ISR_PL_0_SHIFT 24 +#define IPI_APU_ISR_PL_0_WIDTH 1 +#define IPI_APU_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_ISR_PMU_3_SHIFT 19 +#define IPI_APU_ISR_PMU_3_WIDTH 1 +#define IPI_APU_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_ISR_PMU_2_SHIFT 18 +#define IPI_APU_ISR_PMU_2_WIDTH 1 +#define IPI_APU_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_ISR_PMU_1_SHIFT 17 +#define IPI_APU_ISR_PMU_1_WIDTH 1 +#define IPI_APU_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_ISR_PMU_0_SHIFT 16 +#define IPI_APU_ISR_PMU_0_WIDTH 1 +#define IPI_APU_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_ISR_RPU_1_SHIFT 9 +#define IPI_APU_ISR_RPU_1_WIDTH 1 +#define IPI_APU_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_ISR_RPU_0_SHIFT 8 +#define IPI_APU_ISR_RPU_0_WIDTH 1 +#define IPI_APU_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_ISR_APU_SHIFT 0 +#define IPI_APU_ISR_APU_WIDTH 1 +#define IPI_APU_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_APU_IMR + */ +#define IPI_APU_IMR ( ( IPI_BASEADDR ) + ((u32)0X00000014U) ) + +#define IPI_APU_IMR_PL_3_SHIFT 27 +#define IPI_APU_IMR_PL_3_WIDTH 1 +#define IPI_APU_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_IMR_PL_2_SHIFT 26 +#define IPI_APU_IMR_PL_2_WIDTH 1 +#define IPI_APU_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_IMR_PL_1_SHIFT 25 +#define IPI_APU_IMR_PL_1_WIDTH 1 +#define IPI_APU_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_IMR_PL_0_SHIFT 24 +#define IPI_APU_IMR_PL_0_WIDTH 1 +#define IPI_APU_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_IMR_PMU_3_SHIFT 19 +#define IPI_APU_IMR_PMU_3_WIDTH 1 +#define IPI_APU_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_IMR_PMU_2_SHIFT 18 +#define IPI_APU_IMR_PMU_2_WIDTH 1 +#define IPI_APU_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_IMR_PMU_1_SHIFT 17 +#define IPI_APU_IMR_PMU_1_WIDTH 1 +#define IPI_APU_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_IMR_PMU_0_SHIFT 16 +#define IPI_APU_IMR_PMU_0_WIDTH 1 +#define IPI_APU_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_IMR_RPU_1_SHIFT 9 +#define IPI_APU_IMR_RPU_1_WIDTH 1 +#define IPI_APU_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_IMR_RPU_0_SHIFT 8 +#define IPI_APU_IMR_RPU_0_WIDTH 1 +#define IPI_APU_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_IMR_APU_SHIFT 0 +#define IPI_APU_IMR_APU_WIDTH 1 +#define IPI_APU_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_APU_IER + */ +#define IPI_APU_IER ( ( IPI_BASEADDR ) + ((u32)0X00000018U) ) + +#define IPI_APU_IER_PL_3_SHIFT 27 +#define IPI_APU_IER_PL_3_WIDTH 1 +#define IPI_APU_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_IER_PL_2_SHIFT 26 +#define IPI_APU_IER_PL_2_WIDTH 1 +#define IPI_APU_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_IER_PL_1_SHIFT 25 +#define IPI_APU_IER_PL_1_WIDTH 1 +#define IPI_APU_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_IER_PL_0_SHIFT 24 +#define IPI_APU_IER_PL_0_WIDTH 1 +#define IPI_APU_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_IER_PMU_3_SHIFT 19 +#define IPI_APU_IER_PMU_3_WIDTH 1 +#define IPI_APU_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_IER_PMU_2_SHIFT 18 +#define IPI_APU_IER_PMU_2_WIDTH 1 +#define IPI_APU_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_IER_PMU_1_SHIFT 17 +#define IPI_APU_IER_PMU_1_WIDTH 1 +#define IPI_APU_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_IER_PMU_0_SHIFT 16 +#define IPI_APU_IER_PMU_0_WIDTH 1 +#define IPI_APU_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_IER_RPU_1_SHIFT 9 +#define IPI_APU_IER_RPU_1_WIDTH 1 +#define IPI_APU_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_IER_RPU_0_SHIFT 8 +#define IPI_APU_IER_RPU_0_WIDTH 1 +#define IPI_APU_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_IER_APU_SHIFT 0 +#define IPI_APU_IER_APU_WIDTH 1 +#define IPI_APU_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_APU_IDR + */ +#define IPI_APU_IDR ( ( IPI_BASEADDR ) + ((u32)0X0000001CU) ) + +#define IPI_APU_IDR_PL_3_SHIFT 27 +#define IPI_APU_IDR_PL_3_WIDTH 1 +#define IPI_APU_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_APU_IDR_PL_2_SHIFT 26 +#define IPI_APU_IDR_PL_2_WIDTH 1 +#define IPI_APU_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_APU_IDR_PL_1_SHIFT 25 +#define IPI_APU_IDR_PL_1_WIDTH 1 +#define IPI_APU_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_APU_IDR_PL_0_SHIFT 24 +#define IPI_APU_IDR_PL_0_WIDTH 1 +#define IPI_APU_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_APU_IDR_PMU_3_SHIFT 19 +#define IPI_APU_IDR_PMU_3_WIDTH 1 +#define IPI_APU_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_APU_IDR_PMU_2_SHIFT 18 +#define IPI_APU_IDR_PMU_2_WIDTH 1 +#define IPI_APU_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_APU_IDR_PMU_1_SHIFT 17 +#define IPI_APU_IDR_PMU_1_WIDTH 1 +#define IPI_APU_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_APU_IDR_PMU_0_SHIFT 16 +#define IPI_APU_IDR_PMU_0_WIDTH 1 +#define IPI_APU_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_APU_IDR_RPU_1_SHIFT 9 +#define IPI_APU_IDR_RPU_1_WIDTH 1 +#define IPI_APU_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_APU_IDR_RPU_0_SHIFT 8 +#define IPI_APU_IDR_RPU_0_WIDTH 1 +#define IPI_APU_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_APU_IDR_APU_SHIFT 0 +#define IPI_APU_IDR_APU_WIDTH 1 +#define IPI_APU_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_TRIG + */ +#define IPI_RPU_0_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00010000U) ) + +#define IPI_RPU_0_TRIG_PL_3_SHIFT 27 +#define IPI_RPU_0_TRIG_PL_3_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_TRIG_PL_2_SHIFT 26 +#define IPI_RPU_0_TRIG_PL_2_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_TRIG_PL_1_SHIFT 25 +#define IPI_RPU_0_TRIG_PL_1_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_TRIG_PL_0_SHIFT 24 +#define IPI_RPU_0_TRIG_PL_0_WIDTH 1 +#define IPI_RPU_0_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_TRIG_PMU_3_SHIFT 19 +#define IPI_RPU_0_TRIG_PMU_3_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_TRIG_PMU_2_SHIFT 18 +#define IPI_RPU_0_TRIG_PMU_2_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_TRIG_PMU_1_SHIFT 17 +#define IPI_RPU_0_TRIG_PMU_1_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_TRIG_PMU_0_SHIFT 16 +#define IPI_RPU_0_TRIG_PMU_0_WIDTH 1 +#define IPI_RPU_0_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_TRIG_RPU_1_SHIFT 9 +#define IPI_RPU_0_TRIG_RPU_1_WIDTH 1 +#define IPI_RPU_0_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_TRIG_RPU_0_SHIFT 8 +#define IPI_RPU_0_TRIG_RPU_0_WIDTH 1 +#define IPI_RPU_0_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_TRIG_APU_SHIFT 0 +#define IPI_RPU_0_TRIG_APU_WIDTH 1 +#define IPI_RPU_0_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_OBS + */ +#define IPI_RPU_0_OBS ( ( IPI_BASEADDR ) + ((u32)0X00010004U) ) + +#define IPI_RPU_0_OBS_PL_3_SHIFT 27 +#define IPI_RPU_0_OBS_PL_3_WIDTH 1 +#define IPI_RPU_0_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_OBS_PL_2_SHIFT 26 +#define IPI_RPU_0_OBS_PL_2_WIDTH 1 +#define IPI_RPU_0_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_OBS_PL_1_SHIFT 25 +#define IPI_RPU_0_OBS_PL_1_WIDTH 1 +#define IPI_RPU_0_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_OBS_PL_0_SHIFT 24 +#define IPI_RPU_0_OBS_PL_0_WIDTH 1 +#define IPI_RPU_0_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_OBS_PMU_3_SHIFT 19 +#define IPI_RPU_0_OBS_PMU_3_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_OBS_PMU_2_SHIFT 18 +#define IPI_RPU_0_OBS_PMU_2_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_OBS_PMU_1_SHIFT 17 +#define IPI_RPU_0_OBS_PMU_1_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_OBS_PMU_0_SHIFT 16 +#define IPI_RPU_0_OBS_PMU_0_WIDTH 1 +#define IPI_RPU_0_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_OBS_RPU_1_SHIFT 9 +#define IPI_RPU_0_OBS_RPU_1_WIDTH 1 +#define IPI_RPU_0_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_OBS_RPU_0_SHIFT 8 +#define IPI_RPU_0_OBS_RPU_0_WIDTH 1 +#define IPI_RPU_0_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_OBS_APU_SHIFT 0 +#define IPI_RPU_0_OBS_APU_WIDTH 1 +#define IPI_RPU_0_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_ISR + */ +#define IPI_RPU_0_ISR ( ( IPI_BASEADDR ) + ((u32)0X00010010U) ) + +#define IPI_RPU_0_ISR_PL_3_SHIFT 27 +#define IPI_RPU_0_ISR_PL_3_WIDTH 1 +#define IPI_RPU_0_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_ISR_PL_2_SHIFT 26 +#define IPI_RPU_0_ISR_PL_2_WIDTH 1 +#define IPI_RPU_0_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_ISR_PL_1_SHIFT 25 +#define IPI_RPU_0_ISR_PL_1_WIDTH 1 +#define IPI_RPU_0_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_ISR_PL_0_SHIFT 24 +#define IPI_RPU_0_ISR_PL_0_WIDTH 1 +#define IPI_RPU_0_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_ISR_PMU_3_SHIFT 19 +#define IPI_RPU_0_ISR_PMU_3_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_ISR_PMU_2_SHIFT 18 +#define IPI_RPU_0_ISR_PMU_2_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_ISR_PMU_1_SHIFT 17 +#define IPI_RPU_0_ISR_PMU_1_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_ISR_PMU_0_SHIFT 16 +#define IPI_RPU_0_ISR_PMU_0_WIDTH 1 +#define IPI_RPU_0_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_ISR_RPU_1_SHIFT 9 +#define IPI_RPU_0_ISR_RPU_1_WIDTH 1 +#define IPI_RPU_0_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_ISR_RPU_0_SHIFT 8 +#define IPI_RPU_0_ISR_RPU_0_WIDTH 1 +#define IPI_RPU_0_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_ISR_APU_SHIFT 0 +#define IPI_RPU_0_ISR_APU_WIDTH 1 +#define IPI_RPU_0_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_IMR + */ +#define IPI_RPU_0_IMR ( ( IPI_BASEADDR ) + ((u32)0X00010014U) ) + +#define IPI_RPU_0_IMR_PL_3_SHIFT 27 +#define IPI_RPU_0_IMR_PL_3_WIDTH 1 +#define IPI_RPU_0_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_IMR_PL_2_SHIFT 26 +#define IPI_RPU_0_IMR_PL_2_WIDTH 1 +#define IPI_RPU_0_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_IMR_PL_1_SHIFT 25 +#define IPI_RPU_0_IMR_PL_1_WIDTH 1 +#define IPI_RPU_0_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_IMR_PL_0_SHIFT 24 +#define IPI_RPU_0_IMR_PL_0_WIDTH 1 +#define IPI_RPU_0_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_IMR_PMU_3_SHIFT 19 +#define IPI_RPU_0_IMR_PMU_3_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_IMR_PMU_2_SHIFT 18 +#define IPI_RPU_0_IMR_PMU_2_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_IMR_PMU_1_SHIFT 17 +#define IPI_RPU_0_IMR_PMU_1_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_IMR_PMU_0_SHIFT 16 +#define IPI_RPU_0_IMR_PMU_0_WIDTH 1 +#define IPI_RPU_0_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_IMR_RPU_1_SHIFT 9 +#define IPI_RPU_0_IMR_RPU_1_WIDTH 1 +#define IPI_RPU_0_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_IMR_RPU_0_SHIFT 8 +#define IPI_RPU_0_IMR_RPU_0_WIDTH 1 +#define IPI_RPU_0_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_IMR_APU_SHIFT 0 +#define IPI_RPU_0_IMR_APU_WIDTH 1 +#define IPI_RPU_0_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_IER + */ +#define IPI_RPU_0_IER ( ( IPI_BASEADDR ) + ((u32)0X00010018U) ) + +#define IPI_RPU_0_IER_PL_3_SHIFT 27 +#define IPI_RPU_0_IER_PL_3_WIDTH 1 +#define IPI_RPU_0_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_IER_PL_2_SHIFT 26 +#define IPI_RPU_0_IER_PL_2_WIDTH 1 +#define IPI_RPU_0_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_IER_PL_1_SHIFT 25 +#define IPI_RPU_0_IER_PL_1_WIDTH 1 +#define IPI_RPU_0_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_IER_PL_0_SHIFT 24 +#define IPI_RPU_0_IER_PL_0_WIDTH 1 +#define IPI_RPU_0_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_IER_PMU_3_SHIFT 19 +#define IPI_RPU_0_IER_PMU_3_WIDTH 1 +#define IPI_RPU_0_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_IER_PMU_2_SHIFT 18 +#define IPI_RPU_0_IER_PMU_2_WIDTH 1 +#define IPI_RPU_0_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_IER_PMU_1_SHIFT 17 +#define IPI_RPU_0_IER_PMU_1_WIDTH 1 +#define IPI_RPU_0_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_IER_PMU_0_SHIFT 16 +#define IPI_RPU_0_IER_PMU_0_WIDTH 1 +#define IPI_RPU_0_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_IER_RPU_1_SHIFT 9 +#define IPI_RPU_0_IER_RPU_1_WIDTH 1 +#define IPI_RPU_0_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_IER_RPU_0_SHIFT 8 +#define IPI_RPU_0_IER_RPU_0_WIDTH 1 +#define IPI_RPU_0_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_IER_APU_SHIFT 0 +#define IPI_RPU_0_IER_APU_WIDTH 1 +#define IPI_RPU_0_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_0_IDR + */ +#define IPI_RPU_0_IDR ( ( IPI_BASEADDR ) + ((u32)0X0001001CU) ) + +#define IPI_RPU_0_IDR_PL_3_SHIFT 27 +#define IPI_RPU_0_IDR_PL_3_WIDTH 1 +#define IPI_RPU_0_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_0_IDR_PL_2_SHIFT 26 +#define IPI_RPU_0_IDR_PL_2_WIDTH 1 +#define IPI_RPU_0_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_0_IDR_PL_1_SHIFT 25 +#define IPI_RPU_0_IDR_PL_1_WIDTH 1 +#define IPI_RPU_0_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_0_IDR_PL_0_SHIFT 24 +#define IPI_RPU_0_IDR_PL_0_WIDTH 1 +#define IPI_RPU_0_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_0_IDR_PMU_3_SHIFT 19 +#define IPI_RPU_0_IDR_PMU_3_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_0_IDR_PMU_2_SHIFT 18 +#define IPI_RPU_0_IDR_PMU_2_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_0_IDR_PMU_1_SHIFT 17 +#define IPI_RPU_0_IDR_PMU_1_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_0_IDR_PMU_0_SHIFT 16 +#define IPI_RPU_0_IDR_PMU_0_WIDTH 1 +#define IPI_RPU_0_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_0_IDR_RPU_1_SHIFT 9 +#define IPI_RPU_0_IDR_RPU_1_WIDTH 1 +#define IPI_RPU_0_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_0_IDR_RPU_0_SHIFT 8 +#define IPI_RPU_0_IDR_RPU_0_WIDTH 1 +#define IPI_RPU_0_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_0_IDR_APU_SHIFT 0 +#define IPI_RPU_0_IDR_APU_WIDTH 1 +#define IPI_RPU_0_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_TRIG + */ +#define IPI_RPU_1_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00020000U) ) + +#define IPI_RPU_1_TRIG_PL_3_SHIFT 27 +#define IPI_RPU_1_TRIG_PL_3_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_TRIG_PL_2_SHIFT 26 +#define IPI_RPU_1_TRIG_PL_2_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_TRIG_PL_1_SHIFT 25 +#define IPI_RPU_1_TRIG_PL_1_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_TRIG_PL_0_SHIFT 24 +#define IPI_RPU_1_TRIG_PL_0_WIDTH 1 +#define IPI_RPU_1_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_TRIG_PMU_3_SHIFT 19 +#define IPI_RPU_1_TRIG_PMU_3_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_TRIG_PMU_2_SHIFT 18 +#define IPI_RPU_1_TRIG_PMU_2_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_TRIG_PMU_1_SHIFT 17 +#define IPI_RPU_1_TRIG_PMU_1_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_TRIG_PMU_0_SHIFT 16 +#define IPI_RPU_1_TRIG_PMU_0_WIDTH 1 +#define IPI_RPU_1_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_TRIG_RPU_1_SHIFT 9 +#define IPI_RPU_1_TRIG_RPU_1_WIDTH 1 +#define IPI_RPU_1_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_TRIG_RPU_0_SHIFT 8 +#define IPI_RPU_1_TRIG_RPU_0_WIDTH 1 +#define IPI_RPU_1_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_TRIG_APU_SHIFT 0 +#define IPI_RPU_1_TRIG_APU_WIDTH 1 +#define IPI_RPU_1_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_OBS + */ +#define IPI_RPU_1_OBS ( ( IPI_BASEADDR ) + ((u32)0X00020004U) ) + +#define IPI_RPU_1_OBS_PL_3_SHIFT 27 +#define IPI_RPU_1_OBS_PL_3_WIDTH 1 +#define IPI_RPU_1_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_OBS_PL_2_SHIFT 26 +#define IPI_RPU_1_OBS_PL_2_WIDTH 1 +#define IPI_RPU_1_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_OBS_PL_1_SHIFT 25 +#define IPI_RPU_1_OBS_PL_1_WIDTH 1 +#define IPI_RPU_1_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_OBS_PL_0_SHIFT 24 +#define IPI_RPU_1_OBS_PL_0_WIDTH 1 +#define IPI_RPU_1_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_OBS_PMU_3_SHIFT 19 +#define IPI_RPU_1_OBS_PMU_3_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_OBS_PMU_2_SHIFT 18 +#define IPI_RPU_1_OBS_PMU_2_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_OBS_PMU_1_SHIFT 17 +#define IPI_RPU_1_OBS_PMU_1_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_OBS_PMU_0_SHIFT 16 +#define IPI_RPU_1_OBS_PMU_0_WIDTH 1 +#define IPI_RPU_1_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_OBS_RPU_1_SHIFT 9 +#define IPI_RPU_1_OBS_RPU_1_WIDTH 1 +#define IPI_RPU_1_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_OBS_RPU_0_SHIFT 8 +#define IPI_RPU_1_OBS_RPU_0_WIDTH 1 +#define IPI_RPU_1_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_OBS_APU_SHIFT 0 +#define IPI_RPU_1_OBS_APU_WIDTH 1 +#define IPI_RPU_1_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_ISR + */ +#define IPI_RPU_1_ISR ( ( IPI_BASEADDR ) + ((u32)0X00020010U) ) + +#define IPI_RPU_1_ISR_PL_3_SHIFT 27 +#define IPI_RPU_1_ISR_PL_3_WIDTH 1 +#define IPI_RPU_1_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_ISR_PL_2_SHIFT 26 +#define IPI_RPU_1_ISR_PL_2_WIDTH 1 +#define IPI_RPU_1_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_ISR_PL_1_SHIFT 25 +#define IPI_RPU_1_ISR_PL_1_WIDTH 1 +#define IPI_RPU_1_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_ISR_PL_0_SHIFT 24 +#define IPI_RPU_1_ISR_PL_0_WIDTH 1 +#define IPI_RPU_1_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_ISR_PMU_3_SHIFT 19 +#define IPI_RPU_1_ISR_PMU_3_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_ISR_PMU_2_SHIFT 18 +#define IPI_RPU_1_ISR_PMU_2_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_ISR_PMU_1_SHIFT 17 +#define IPI_RPU_1_ISR_PMU_1_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_ISR_PMU_0_SHIFT 16 +#define IPI_RPU_1_ISR_PMU_0_WIDTH 1 +#define IPI_RPU_1_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_ISR_RPU_1_SHIFT 9 +#define IPI_RPU_1_ISR_RPU_1_WIDTH 1 +#define IPI_RPU_1_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_ISR_RPU_0_SHIFT 8 +#define IPI_RPU_1_ISR_RPU_0_WIDTH 1 +#define IPI_RPU_1_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_ISR_APU_SHIFT 0 +#define IPI_RPU_1_ISR_APU_WIDTH 1 +#define IPI_RPU_1_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_IMR + */ +#define IPI_RPU_1_IMR ( ( IPI_BASEADDR ) + ((u32)0X00020014U) ) + +#define IPI_RPU_1_IMR_PL_3_SHIFT 27 +#define IPI_RPU_1_IMR_PL_3_WIDTH 1 +#define IPI_RPU_1_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_IMR_PL_2_SHIFT 26 +#define IPI_RPU_1_IMR_PL_2_WIDTH 1 +#define IPI_RPU_1_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_IMR_PL_1_SHIFT 25 +#define IPI_RPU_1_IMR_PL_1_WIDTH 1 +#define IPI_RPU_1_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_IMR_PL_0_SHIFT 24 +#define IPI_RPU_1_IMR_PL_0_WIDTH 1 +#define IPI_RPU_1_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_IMR_PMU_3_SHIFT 19 +#define IPI_RPU_1_IMR_PMU_3_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_IMR_PMU_2_SHIFT 18 +#define IPI_RPU_1_IMR_PMU_2_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_IMR_PMU_1_SHIFT 17 +#define IPI_RPU_1_IMR_PMU_1_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_IMR_PMU_0_SHIFT 16 +#define IPI_RPU_1_IMR_PMU_0_WIDTH 1 +#define IPI_RPU_1_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_IMR_RPU_1_SHIFT 9 +#define IPI_RPU_1_IMR_RPU_1_WIDTH 1 +#define IPI_RPU_1_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_IMR_RPU_0_SHIFT 8 +#define IPI_RPU_1_IMR_RPU_0_WIDTH 1 +#define IPI_RPU_1_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_IMR_APU_SHIFT 0 +#define IPI_RPU_1_IMR_APU_WIDTH 1 +#define IPI_RPU_1_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_IER + */ +#define IPI_RPU_1_IER ( ( IPI_BASEADDR ) + ((u32)0X00020018U) ) + +#define IPI_RPU_1_IER_PL_3_SHIFT 27 +#define IPI_RPU_1_IER_PL_3_WIDTH 1 +#define IPI_RPU_1_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_IER_PL_2_SHIFT 26 +#define IPI_RPU_1_IER_PL_2_WIDTH 1 +#define IPI_RPU_1_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_IER_PL_1_SHIFT 25 +#define IPI_RPU_1_IER_PL_1_WIDTH 1 +#define IPI_RPU_1_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_IER_PL_0_SHIFT 24 +#define IPI_RPU_1_IER_PL_0_WIDTH 1 +#define IPI_RPU_1_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_IER_PMU_3_SHIFT 19 +#define IPI_RPU_1_IER_PMU_3_WIDTH 1 +#define IPI_RPU_1_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_IER_PMU_2_SHIFT 18 +#define IPI_RPU_1_IER_PMU_2_WIDTH 1 +#define IPI_RPU_1_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_IER_PMU_1_SHIFT 17 +#define IPI_RPU_1_IER_PMU_1_WIDTH 1 +#define IPI_RPU_1_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_IER_PMU_0_SHIFT 16 +#define IPI_RPU_1_IER_PMU_0_WIDTH 1 +#define IPI_RPU_1_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_IER_RPU_1_SHIFT 9 +#define IPI_RPU_1_IER_RPU_1_WIDTH 1 +#define IPI_RPU_1_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_IER_RPU_0_SHIFT 8 +#define IPI_RPU_1_IER_RPU_0_WIDTH 1 +#define IPI_RPU_1_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_IER_APU_SHIFT 0 +#define IPI_RPU_1_IER_APU_WIDTH 1 +#define IPI_RPU_1_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_RPU_1_IDR + */ +#define IPI_RPU_1_IDR ( ( IPI_BASEADDR ) + ((u32)0X0002001CU) ) + +#define IPI_RPU_1_IDR_PL_3_SHIFT 27 +#define IPI_RPU_1_IDR_PL_3_WIDTH 1 +#define IPI_RPU_1_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_RPU_1_IDR_PL_2_SHIFT 26 +#define IPI_RPU_1_IDR_PL_2_WIDTH 1 +#define IPI_RPU_1_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_RPU_1_IDR_PL_1_SHIFT 25 +#define IPI_RPU_1_IDR_PL_1_WIDTH 1 +#define IPI_RPU_1_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_RPU_1_IDR_PL_0_SHIFT 24 +#define IPI_RPU_1_IDR_PL_0_WIDTH 1 +#define IPI_RPU_1_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_RPU_1_IDR_PMU_3_SHIFT 19 +#define IPI_RPU_1_IDR_PMU_3_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_RPU_1_IDR_PMU_2_SHIFT 18 +#define IPI_RPU_1_IDR_PMU_2_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_RPU_1_IDR_PMU_1_SHIFT 17 +#define IPI_RPU_1_IDR_PMU_1_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_RPU_1_IDR_PMU_0_SHIFT 16 +#define IPI_RPU_1_IDR_PMU_0_WIDTH 1 +#define IPI_RPU_1_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_RPU_1_IDR_RPU_1_SHIFT 9 +#define IPI_RPU_1_IDR_RPU_1_WIDTH 1 +#define IPI_RPU_1_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_RPU_1_IDR_RPU_0_SHIFT 8 +#define IPI_RPU_1_IDR_RPU_0_WIDTH 1 +#define IPI_RPU_1_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_RPU_1_IDR_APU_SHIFT 0 +#define IPI_RPU_1_IDR_APU_WIDTH 1 +#define IPI_RPU_1_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_TRIG + */ +#define IPI_PMU_0_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00030000U) ) + +#define IPI_PMU_0_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_0_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_0_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_0_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_0_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_0_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_0_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_0_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_0_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_0_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_0_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_0_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_0_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_0_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_0_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_TRIG_APU_SHIFT 0 +#define IPI_PMU_0_TRIG_APU_WIDTH 1 +#define IPI_PMU_0_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_OBS + */ +#define IPI_PMU_0_OBS ( ( IPI_BASEADDR ) + ((u32)0X00030004U) ) + +#define IPI_PMU_0_OBS_PL_3_SHIFT 27 +#define IPI_PMU_0_OBS_PL_3_WIDTH 1 +#define IPI_PMU_0_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_OBS_PL_2_SHIFT 26 +#define IPI_PMU_0_OBS_PL_2_WIDTH 1 +#define IPI_PMU_0_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_OBS_PL_1_SHIFT 25 +#define IPI_PMU_0_OBS_PL_1_WIDTH 1 +#define IPI_PMU_0_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_OBS_PL_0_SHIFT 24 +#define IPI_PMU_0_OBS_PL_0_WIDTH 1 +#define IPI_PMU_0_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_0_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_0_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_0_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_0_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_0_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_0_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_0_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_0_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_0_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_OBS_APU_SHIFT 0 +#define IPI_PMU_0_OBS_APU_WIDTH 1 +#define IPI_PMU_0_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_ISR + */ +#define IPI_PMU_0_ISR ( ( IPI_BASEADDR ) + ((u32)0X00030010U) ) + +#define IPI_PMU_0_ISR_PL_3_SHIFT 27 +#define IPI_PMU_0_ISR_PL_3_WIDTH 1 +#define IPI_PMU_0_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_ISR_PL_2_SHIFT 26 +#define IPI_PMU_0_ISR_PL_2_WIDTH 1 +#define IPI_PMU_0_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_ISR_PL_1_SHIFT 25 +#define IPI_PMU_0_ISR_PL_1_WIDTH 1 +#define IPI_PMU_0_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_ISR_PL_0_SHIFT 24 +#define IPI_PMU_0_ISR_PL_0_WIDTH 1 +#define IPI_PMU_0_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_0_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_0_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_0_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_0_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_0_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_0_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_0_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_0_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_0_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_ISR_APU_SHIFT 0 +#define IPI_PMU_0_ISR_APU_WIDTH 1 +#define IPI_PMU_0_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_IMR + */ +#define IPI_PMU_0_IMR ( ( IPI_BASEADDR ) + ((u32)0X00030014U) ) + +#define IPI_PMU_0_IMR_PL_3_SHIFT 27 +#define IPI_PMU_0_IMR_PL_3_WIDTH 1 +#define IPI_PMU_0_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_IMR_PL_2_SHIFT 26 +#define IPI_PMU_0_IMR_PL_2_WIDTH 1 +#define IPI_PMU_0_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_IMR_PL_1_SHIFT 25 +#define IPI_PMU_0_IMR_PL_1_WIDTH 1 +#define IPI_PMU_0_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_IMR_PL_0_SHIFT 24 +#define IPI_PMU_0_IMR_PL_0_WIDTH 1 +#define IPI_PMU_0_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_0_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_0_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_0_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_0_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_0_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_0_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_0_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_0_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_0_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_IMR_APU_SHIFT 0 +#define IPI_PMU_0_IMR_APU_WIDTH 1 +#define IPI_PMU_0_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_IER + */ +#define IPI_PMU_0_IER ( ( IPI_BASEADDR ) + ((u32)0X00030018U) ) + +#define IPI_PMU_0_IER_PL_3_SHIFT 27 +#define IPI_PMU_0_IER_PL_3_WIDTH 1 +#define IPI_PMU_0_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_IER_PL_2_SHIFT 26 +#define IPI_PMU_0_IER_PL_2_WIDTH 1 +#define IPI_PMU_0_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_IER_PL_1_SHIFT 25 +#define IPI_PMU_0_IER_PL_1_WIDTH 1 +#define IPI_PMU_0_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_IER_PL_0_SHIFT 24 +#define IPI_PMU_0_IER_PL_0_WIDTH 1 +#define IPI_PMU_0_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_IER_PMU_3_SHIFT 19 +#define IPI_PMU_0_IER_PMU_3_WIDTH 1 +#define IPI_PMU_0_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_IER_PMU_2_SHIFT 18 +#define IPI_PMU_0_IER_PMU_2_WIDTH 1 +#define IPI_PMU_0_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_IER_PMU_1_SHIFT 17 +#define IPI_PMU_0_IER_PMU_1_WIDTH 1 +#define IPI_PMU_0_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_IER_PMU_0_SHIFT 16 +#define IPI_PMU_0_IER_PMU_0_WIDTH 1 +#define IPI_PMU_0_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_IER_RPU_1_SHIFT 9 +#define IPI_PMU_0_IER_RPU_1_WIDTH 1 +#define IPI_PMU_0_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_IER_RPU_0_SHIFT 8 +#define IPI_PMU_0_IER_RPU_0_WIDTH 1 +#define IPI_PMU_0_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_IER_APU_SHIFT 0 +#define IPI_PMU_0_IER_APU_WIDTH 1 +#define IPI_PMU_0_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_0_IDR + */ +#define IPI_PMU_0_IDR ( ( IPI_BASEADDR ) + ((u32)0X0003001CU) ) + +#define IPI_PMU_0_IDR_PL_3_SHIFT 27 +#define IPI_PMU_0_IDR_PL_3_WIDTH 1 +#define IPI_PMU_0_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_0_IDR_PL_2_SHIFT 26 +#define IPI_PMU_0_IDR_PL_2_WIDTH 1 +#define IPI_PMU_0_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_0_IDR_PL_1_SHIFT 25 +#define IPI_PMU_0_IDR_PL_1_WIDTH 1 +#define IPI_PMU_0_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_0_IDR_PL_0_SHIFT 24 +#define IPI_PMU_0_IDR_PL_0_WIDTH 1 +#define IPI_PMU_0_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_0_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_0_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_0_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_0_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_0_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_0_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_0_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_0_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_0_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_0_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_0_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_0_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_0_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_0_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_0_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_0_IDR_APU_SHIFT 0 +#define IPI_PMU_0_IDR_APU_WIDTH 1 +#define IPI_PMU_0_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_TRIG + */ +#define IPI_PMU_1_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00031000U) ) + +#define IPI_PMU_1_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_1_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_1_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_1_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_1_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_1_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_1_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_1_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_1_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_1_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_1_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_1_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_1_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_1_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_1_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_TRIG_APU_SHIFT 0 +#define IPI_PMU_1_TRIG_APU_WIDTH 1 +#define IPI_PMU_1_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_OBS + */ +#define IPI_PMU_1_OBS ( ( IPI_BASEADDR ) + ((u32)0X00031004U) ) + +#define IPI_PMU_1_OBS_PL_3_SHIFT 27 +#define IPI_PMU_1_OBS_PL_3_WIDTH 1 +#define IPI_PMU_1_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_OBS_PL_2_SHIFT 26 +#define IPI_PMU_1_OBS_PL_2_WIDTH 1 +#define IPI_PMU_1_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_OBS_PL_1_SHIFT 25 +#define IPI_PMU_1_OBS_PL_1_WIDTH 1 +#define IPI_PMU_1_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_OBS_PL_0_SHIFT 24 +#define IPI_PMU_1_OBS_PL_0_WIDTH 1 +#define IPI_PMU_1_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_1_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_1_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_1_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_1_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_1_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_1_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_1_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_1_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_1_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_OBS_APU_SHIFT 0 +#define IPI_PMU_1_OBS_APU_WIDTH 1 +#define IPI_PMU_1_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_ISR + */ +#define IPI_PMU_1_ISR ( ( IPI_BASEADDR ) + ((u32)0X00031010U) ) + +#define IPI_PMU_1_ISR_PL_3_SHIFT 27 +#define IPI_PMU_1_ISR_PL_3_WIDTH 1 +#define IPI_PMU_1_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_ISR_PL_2_SHIFT 26 +#define IPI_PMU_1_ISR_PL_2_WIDTH 1 +#define IPI_PMU_1_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_ISR_PL_1_SHIFT 25 +#define IPI_PMU_1_ISR_PL_1_WIDTH 1 +#define IPI_PMU_1_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_ISR_PL_0_SHIFT 24 +#define IPI_PMU_1_ISR_PL_0_WIDTH 1 +#define IPI_PMU_1_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_1_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_1_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_1_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_1_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_1_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_1_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_1_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_1_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_1_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_ISR_APU_SHIFT 0 +#define IPI_PMU_1_ISR_APU_WIDTH 1 +#define IPI_PMU_1_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_IMR + */ +#define IPI_PMU_1_IMR ( ( IPI_BASEADDR ) + ((u32)0X00031014U) ) + +#define IPI_PMU_1_IMR_PL_3_SHIFT 27 +#define IPI_PMU_1_IMR_PL_3_WIDTH 1 +#define IPI_PMU_1_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_IMR_PL_2_SHIFT 26 +#define IPI_PMU_1_IMR_PL_2_WIDTH 1 +#define IPI_PMU_1_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_IMR_PL_1_SHIFT 25 +#define IPI_PMU_1_IMR_PL_1_WIDTH 1 +#define IPI_PMU_1_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_IMR_PL_0_SHIFT 24 +#define IPI_PMU_1_IMR_PL_0_WIDTH 1 +#define IPI_PMU_1_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_1_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_1_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_1_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_1_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_1_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_1_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_1_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_1_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_1_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_IMR_APU_SHIFT 0 +#define IPI_PMU_1_IMR_APU_WIDTH 1 +#define IPI_PMU_1_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_IER + */ +#define IPI_PMU_1_IER ( ( IPI_BASEADDR ) + ((u32)0X00031018U) ) + +#define IPI_PMU_1_IER_PL_3_SHIFT 27 +#define IPI_PMU_1_IER_PL_3_WIDTH 1 +#define IPI_PMU_1_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_IER_PL_2_SHIFT 26 +#define IPI_PMU_1_IER_PL_2_WIDTH 1 +#define IPI_PMU_1_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_IER_PL_1_SHIFT 25 +#define IPI_PMU_1_IER_PL_1_WIDTH 1 +#define IPI_PMU_1_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_IER_PL_0_SHIFT 24 +#define IPI_PMU_1_IER_PL_0_WIDTH 1 +#define IPI_PMU_1_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_IER_PMU_3_SHIFT 19 +#define IPI_PMU_1_IER_PMU_3_WIDTH 1 +#define IPI_PMU_1_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_IER_PMU_2_SHIFT 18 +#define IPI_PMU_1_IER_PMU_2_WIDTH 1 +#define IPI_PMU_1_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_IER_PMU_1_SHIFT 17 +#define IPI_PMU_1_IER_PMU_1_WIDTH 1 +#define IPI_PMU_1_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_IER_PMU_0_SHIFT 16 +#define IPI_PMU_1_IER_PMU_0_WIDTH 1 +#define IPI_PMU_1_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_IER_RPU_1_SHIFT 9 +#define IPI_PMU_1_IER_RPU_1_WIDTH 1 +#define IPI_PMU_1_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_IER_RPU_0_SHIFT 8 +#define IPI_PMU_1_IER_RPU_0_WIDTH 1 +#define IPI_PMU_1_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_IER_APU_SHIFT 0 +#define IPI_PMU_1_IER_APU_WIDTH 1 +#define IPI_PMU_1_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_1_IDR + */ +#define IPI_PMU_1_IDR ( ( IPI_BASEADDR ) + ((u32)0X0003101CU) ) + +#define IPI_PMU_1_IDR_PL_3_SHIFT 27 +#define IPI_PMU_1_IDR_PL_3_WIDTH 1 +#define IPI_PMU_1_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_1_IDR_PL_2_SHIFT 26 +#define IPI_PMU_1_IDR_PL_2_WIDTH 1 +#define IPI_PMU_1_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_1_IDR_PL_1_SHIFT 25 +#define IPI_PMU_1_IDR_PL_1_WIDTH 1 +#define IPI_PMU_1_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_1_IDR_PL_0_SHIFT 24 +#define IPI_PMU_1_IDR_PL_0_WIDTH 1 +#define IPI_PMU_1_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_1_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_1_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_1_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_1_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_1_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_1_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_1_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_1_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_1_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_1_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_1_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_1_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_1_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_1_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_1_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_1_IDR_APU_SHIFT 0 +#define IPI_PMU_1_IDR_APU_WIDTH 1 +#define IPI_PMU_1_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_TRIG + */ +#define IPI_PMU_2_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00032000U) ) + +#define IPI_PMU_2_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_2_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_2_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_2_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_2_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_2_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_2_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_2_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_2_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_2_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_2_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_2_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_2_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_2_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_2_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_TRIG_APU_SHIFT 0 +#define IPI_PMU_2_TRIG_APU_WIDTH 1 +#define IPI_PMU_2_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_OBS + */ +#define IPI_PMU_2_OBS ( ( IPI_BASEADDR ) + ((u32)0X00032004U) ) + +#define IPI_PMU_2_OBS_PL_3_SHIFT 27 +#define IPI_PMU_2_OBS_PL_3_WIDTH 1 +#define IPI_PMU_2_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_OBS_PL_2_SHIFT 26 +#define IPI_PMU_2_OBS_PL_2_WIDTH 1 +#define IPI_PMU_2_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_OBS_PL_1_SHIFT 25 +#define IPI_PMU_2_OBS_PL_1_WIDTH 1 +#define IPI_PMU_2_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_OBS_PL_0_SHIFT 24 +#define IPI_PMU_2_OBS_PL_0_WIDTH 1 +#define IPI_PMU_2_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_2_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_2_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_2_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_2_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_2_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_2_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_2_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_2_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_2_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_OBS_APU_SHIFT 0 +#define IPI_PMU_2_OBS_APU_WIDTH 1 +#define IPI_PMU_2_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_ISR + */ +#define IPI_PMU_2_ISR ( ( IPI_BASEADDR ) + ((u32)0X00032010U) ) + +#define IPI_PMU_2_ISR_PL_3_SHIFT 27 +#define IPI_PMU_2_ISR_PL_3_WIDTH 1 +#define IPI_PMU_2_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_ISR_PL_2_SHIFT 26 +#define IPI_PMU_2_ISR_PL_2_WIDTH 1 +#define IPI_PMU_2_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_ISR_PL_1_SHIFT 25 +#define IPI_PMU_2_ISR_PL_1_WIDTH 1 +#define IPI_PMU_2_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_ISR_PL_0_SHIFT 24 +#define IPI_PMU_2_ISR_PL_0_WIDTH 1 +#define IPI_PMU_2_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_2_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_2_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_2_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_2_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_2_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_2_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_2_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_2_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_2_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_ISR_APU_SHIFT 0 +#define IPI_PMU_2_ISR_APU_WIDTH 1 +#define IPI_PMU_2_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_IMR + */ +#define IPI_PMU_2_IMR ( ( IPI_BASEADDR ) + ((u32)0X00032014U) ) + +#define IPI_PMU_2_IMR_PL_3_SHIFT 27 +#define IPI_PMU_2_IMR_PL_3_WIDTH 1 +#define IPI_PMU_2_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_IMR_PL_2_SHIFT 26 +#define IPI_PMU_2_IMR_PL_2_WIDTH 1 +#define IPI_PMU_2_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_IMR_PL_1_SHIFT 25 +#define IPI_PMU_2_IMR_PL_1_WIDTH 1 +#define IPI_PMU_2_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_IMR_PL_0_SHIFT 24 +#define IPI_PMU_2_IMR_PL_0_WIDTH 1 +#define IPI_PMU_2_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_2_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_2_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_2_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_2_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_2_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_2_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_2_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_2_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_2_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_IMR_APU_SHIFT 0 +#define IPI_PMU_2_IMR_APU_WIDTH 1 +#define IPI_PMU_2_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_IER + */ +#define IPI_PMU_2_IER ( ( IPI_BASEADDR ) + ((u32)0X00032018U) ) + +#define IPI_PMU_2_IER_PL_3_SHIFT 27 +#define IPI_PMU_2_IER_PL_3_WIDTH 1 +#define IPI_PMU_2_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_IER_PL_2_SHIFT 26 +#define IPI_PMU_2_IER_PL_2_WIDTH 1 +#define IPI_PMU_2_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_IER_PL_1_SHIFT 25 +#define IPI_PMU_2_IER_PL_1_WIDTH 1 +#define IPI_PMU_2_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_IER_PL_0_SHIFT 24 +#define IPI_PMU_2_IER_PL_0_WIDTH 1 +#define IPI_PMU_2_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_IER_PMU_3_SHIFT 19 +#define IPI_PMU_2_IER_PMU_3_WIDTH 1 +#define IPI_PMU_2_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_IER_PMU_2_SHIFT 18 +#define IPI_PMU_2_IER_PMU_2_WIDTH 1 +#define IPI_PMU_2_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_IER_PMU_1_SHIFT 17 +#define IPI_PMU_2_IER_PMU_1_WIDTH 1 +#define IPI_PMU_2_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_IER_PMU_0_SHIFT 16 +#define IPI_PMU_2_IER_PMU_0_WIDTH 1 +#define IPI_PMU_2_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_IER_RPU_1_SHIFT 9 +#define IPI_PMU_2_IER_RPU_1_WIDTH 1 +#define IPI_PMU_2_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_IER_RPU_0_SHIFT 8 +#define IPI_PMU_2_IER_RPU_0_WIDTH 1 +#define IPI_PMU_2_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_IER_APU_SHIFT 0 +#define IPI_PMU_2_IER_APU_WIDTH 1 +#define IPI_PMU_2_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_2_IDR + */ +#define IPI_PMU_2_IDR ( ( IPI_BASEADDR ) + ((u32)0X0003201CU) ) + +#define IPI_PMU_2_IDR_PL_3_SHIFT 27 +#define IPI_PMU_2_IDR_PL_3_WIDTH 1 +#define IPI_PMU_2_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_2_IDR_PL_2_SHIFT 26 +#define IPI_PMU_2_IDR_PL_2_WIDTH 1 +#define IPI_PMU_2_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_2_IDR_PL_1_SHIFT 25 +#define IPI_PMU_2_IDR_PL_1_WIDTH 1 +#define IPI_PMU_2_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_2_IDR_PL_0_SHIFT 24 +#define IPI_PMU_2_IDR_PL_0_WIDTH 1 +#define IPI_PMU_2_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_2_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_2_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_2_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_2_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_2_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_2_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_2_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_2_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_2_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_2_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_2_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_2_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_2_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_2_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_2_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_2_IDR_APU_SHIFT 0 +#define IPI_PMU_2_IDR_APU_WIDTH 1 +#define IPI_PMU_2_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_TRIG + */ +#define IPI_PMU_3_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00033000U) ) + +#define IPI_PMU_3_TRIG_PL_3_SHIFT 27 +#define IPI_PMU_3_TRIG_PL_3_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_TRIG_PL_2_SHIFT 26 +#define IPI_PMU_3_TRIG_PL_2_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_TRIG_PL_1_SHIFT 25 +#define IPI_PMU_3_TRIG_PL_1_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_TRIG_PL_0_SHIFT 24 +#define IPI_PMU_3_TRIG_PL_0_WIDTH 1 +#define IPI_PMU_3_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_TRIG_PMU_3_SHIFT 19 +#define IPI_PMU_3_TRIG_PMU_3_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_TRIG_PMU_2_SHIFT 18 +#define IPI_PMU_3_TRIG_PMU_2_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_TRIG_PMU_1_SHIFT 17 +#define IPI_PMU_3_TRIG_PMU_1_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_TRIG_PMU_0_SHIFT 16 +#define IPI_PMU_3_TRIG_PMU_0_WIDTH 1 +#define IPI_PMU_3_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_TRIG_RPU_1_SHIFT 9 +#define IPI_PMU_3_TRIG_RPU_1_WIDTH 1 +#define IPI_PMU_3_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_TRIG_RPU_0_SHIFT 8 +#define IPI_PMU_3_TRIG_RPU_0_WIDTH 1 +#define IPI_PMU_3_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_TRIG_APU_SHIFT 0 +#define IPI_PMU_3_TRIG_APU_WIDTH 1 +#define IPI_PMU_3_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_OBS + */ +#define IPI_PMU_3_OBS ( ( IPI_BASEADDR ) + ((u32)0X00033004U) ) + +#define IPI_PMU_3_OBS_PL_3_SHIFT 27 +#define IPI_PMU_3_OBS_PL_3_WIDTH 1 +#define IPI_PMU_3_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_OBS_PL_2_SHIFT 26 +#define IPI_PMU_3_OBS_PL_2_WIDTH 1 +#define IPI_PMU_3_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_OBS_PL_1_SHIFT 25 +#define IPI_PMU_3_OBS_PL_1_WIDTH 1 +#define IPI_PMU_3_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_OBS_PL_0_SHIFT 24 +#define IPI_PMU_3_OBS_PL_0_WIDTH 1 +#define IPI_PMU_3_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_OBS_PMU_3_SHIFT 19 +#define IPI_PMU_3_OBS_PMU_3_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_OBS_PMU_2_SHIFT 18 +#define IPI_PMU_3_OBS_PMU_2_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_OBS_PMU_1_SHIFT 17 +#define IPI_PMU_3_OBS_PMU_1_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_OBS_PMU_0_SHIFT 16 +#define IPI_PMU_3_OBS_PMU_0_WIDTH 1 +#define IPI_PMU_3_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_OBS_RPU_1_SHIFT 9 +#define IPI_PMU_3_OBS_RPU_1_WIDTH 1 +#define IPI_PMU_3_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_OBS_RPU_0_SHIFT 8 +#define IPI_PMU_3_OBS_RPU_0_WIDTH 1 +#define IPI_PMU_3_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_OBS_APU_SHIFT 0 +#define IPI_PMU_3_OBS_APU_WIDTH 1 +#define IPI_PMU_3_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_ISR + */ +#define IPI_PMU_3_ISR ( ( IPI_BASEADDR ) + ((u32)0X00033010U) ) + +#define IPI_PMU_3_ISR_PL_3_SHIFT 27 +#define IPI_PMU_3_ISR_PL_3_WIDTH 1 +#define IPI_PMU_3_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_ISR_PL_2_SHIFT 26 +#define IPI_PMU_3_ISR_PL_2_WIDTH 1 +#define IPI_PMU_3_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_ISR_PL_1_SHIFT 25 +#define IPI_PMU_3_ISR_PL_1_WIDTH 1 +#define IPI_PMU_3_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_ISR_PL_0_SHIFT 24 +#define IPI_PMU_3_ISR_PL_0_WIDTH 1 +#define IPI_PMU_3_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_ISR_PMU_3_SHIFT 19 +#define IPI_PMU_3_ISR_PMU_3_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_ISR_PMU_2_SHIFT 18 +#define IPI_PMU_3_ISR_PMU_2_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_ISR_PMU_1_SHIFT 17 +#define IPI_PMU_3_ISR_PMU_1_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_ISR_PMU_0_SHIFT 16 +#define IPI_PMU_3_ISR_PMU_0_WIDTH 1 +#define IPI_PMU_3_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_ISR_RPU_1_SHIFT 9 +#define IPI_PMU_3_ISR_RPU_1_WIDTH 1 +#define IPI_PMU_3_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_ISR_RPU_0_SHIFT 8 +#define IPI_PMU_3_ISR_RPU_0_WIDTH 1 +#define IPI_PMU_3_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_ISR_APU_SHIFT 0 +#define IPI_PMU_3_ISR_APU_WIDTH 1 +#define IPI_PMU_3_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_IMR + */ +#define IPI_PMU_3_IMR ( ( IPI_BASEADDR ) + ((u32)0X00033014U) ) + +#define IPI_PMU_3_IMR_PL_3_SHIFT 27 +#define IPI_PMU_3_IMR_PL_3_WIDTH 1 +#define IPI_PMU_3_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_IMR_PL_2_SHIFT 26 +#define IPI_PMU_3_IMR_PL_2_WIDTH 1 +#define IPI_PMU_3_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_IMR_PL_1_SHIFT 25 +#define IPI_PMU_3_IMR_PL_1_WIDTH 1 +#define IPI_PMU_3_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_IMR_PL_0_SHIFT 24 +#define IPI_PMU_3_IMR_PL_0_WIDTH 1 +#define IPI_PMU_3_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_IMR_PMU_3_SHIFT 19 +#define IPI_PMU_3_IMR_PMU_3_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_IMR_PMU_2_SHIFT 18 +#define IPI_PMU_3_IMR_PMU_2_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_IMR_PMU_1_SHIFT 17 +#define IPI_PMU_3_IMR_PMU_1_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_IMR_PMU_0_SHIFT 16 +#define IPI_PMU_3_IMR_PMU_0_WIDTH 1 +#define IPI_PMU_3_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_IMR_RPU_1_SHIFT 9 +#define IPI_PMU_3_IMR_RPU_1_WIDTH 1 +#define IPI_PMU_3_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_IMR_RPU_0_SHIFT 8 +#define IPI_PMU_3_IMR_RPU_0_WIDTH 1 +#define IPI_PMU_3_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_IMR_APU_SHIFT 0 +#define IPI_PMU_3_IMR_APU_WIDTH 1 +#define IPI_PMU_3_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_IER + */ +#define IPI_PMU_3_IER ( ( IPI_BASEADDR ) + ((u32)0X00033018U) ) + +#define IPI_PMU_3_IER_PL_3_SHIFT 27 +#define IPI_PMU_3_IER_PL_3_WIDTH 1 +#define IPI_PMU_3_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_IER_PL_2_SHIFT 26 +#define IPI_PMU_3_IER_PL_2_WIDTH 1 +#define IPI_PMU_3_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_IER_PL_1_SHIFT 25 +#define IPI_PMU_3_IER_PL_1_WIDTH 1 +#define IPI_PMU_3_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_IER_PL_0_SHIFT 24 +#define IPI_PMU_3_IER_PL_0_WIDTH 1 +#define IPI_PMU_3_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_IER_PMU_3_SHIFT 19 +#define IPI_PMU_3_IER_PMU_3_WIDTH 1 +#define IPI_PMU_3_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_IER_PMU_2_SHIFT 18 +#define IPI_PMU_3_IER_PMU_2_WIDTH 1 +#define IPI_PMU_3_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_IER_PMU_1_SHIFT 17 +#define IPI_PMU_3_IER_PMU_1_WIDTH 1 +#define IPI_PMU_3_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_IER_PMU_0_SHIFT 16 +#define IPI_PMU_3_IER_PMU_0_WIDTH 1 +#define IPI_PMU_3_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_IER_RPU_1_SHIFT 9 +#define IPI_PMU_3_IER_RPU_1_WIDTH 1 +#define IPI_PMU_3_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_IER_RPU_0_SHIFT 8 +#define IPI_PMU_3_IER_RPU_0_WIDTH 1 +#define IPI_PMU_3_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_IER_APU_SHIFT 0 +#define IPI_PMU_3_IER_APU_WIDTH 1 +#define IPI_PMU_3_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PMU_3_IDR + */ +#define IPI_PMU_3_IDR ( ( IPI_BASEADDR ) + ((u32)0X0003301CU) ) + +#define IPI_PMU_3_IDR_PL_3_SHIFT 27 +#define IPI_PMU_3_IDR_PL_3_WIDTH 1 +#define IPI_PMU_3_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PMU_3_IDR_PL_2_SHIFT 26 +#define IPI_PMU_3_IDR_PL_2_WIDTH 1 +#define IPI_PMU_3_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PMU_3_IDR_PL_1_SHIFT 25 +#define IPI_PMU_3_IDR_PL_1_WIDTH 1 +#define IPI_PMU_3_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PMU_3_IDR_PL_0_SHIFT 24 +#define IPI_PMU_3_IDR_PL_0_WIDTH 1 +#define IPI_PMU_3_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PMU_3_IDR_PMU_3_SHIFT 19 +#define IPI_PMU_3_IDR_PMU_3_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PMU_3_IDR_PMU_2_SHIFT 18 +#define IPI_PMU_3_IDR_PMU_2_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PMU_3_IDR_PMU_1_SHIFT 17 +#define IPI_PMU_3_IDR_PMU_1_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PMU_3_IDR_PMU_0_SHIFT 16 +#define IPI_PMU_3_IDR_PMU_0_WIDTH 1 +#define IPI_PMU_3_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PMU_3_IDR_RPU_1_SHIFT 9 +#define IPI_PMU_3_IDR_RPU_1_WIDTH 1 +#define IPI_PMU_3_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PMU_3_IDR_RPU_0_SHIFT 8 +#define IPI_PMU_3_IDR_RPU_0_WIDTH 1 +#define IPI_PMU_3_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PMU_3_IDR_APU_SHIFT 0 +#define IPI_PMU_3_IDR_APU_WIDTH 1 +#define IPI_PMU_3_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_TRIG + */ +#define IPI_PL_0_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00040000U) ) + +#define IPI_PL_0_TRIG_PL_3_SHIFT 27 +#define IPI_PL_0_TRIG_PL_3_WIDTH 1 +#define IPI_PL_0_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_TRIG_PL_2_SHIFT 26 +#define IPI_PL_0_TRIG_PL_2_WIDTH 1 +#define IPI_PL_0_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_TRIG_PL_1_SHIFT 25 +#define IPI_PL_0_TRIG_PL_1_WIDTH 1 +#define IPI_PL_0_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_TRIG_PL_0_SHIFT 24 +#define IPI_PL_0_TRIG_PL_0_WIDTH 1 +#define IPI_PL_0_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_0_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_0_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_0_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_0_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_0_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_0_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_0_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_0_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_0_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_TRIG_APU_SHIFT 0 +#define IPI_PL_0_TRIG_APU_WIDTH 1 +#define IPI_PL_0_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_OBS + */ +#define IPI_PL_0_OBS ( ( IPI_BASEADDR ) + ((u32)0X00040004U) ) + +#define IPI_PL_0_OBS_PL_3_SHIFT 27 +#define IPI_PL_0_OBS_PL_3_WIDTH 1 +#define IPI_PL_0_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_OBS_PL_2_SHIFT 26 +#define IPI_PL_0_OBS_PL_2_WIDTH 1 +#define IPI_PL_0_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_OBS_PL_1_SHIFT 25 +#define IPI_PL_0_OBS_PL_1_WIDTH 1 +#define IPI_PL_0_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_OBS_PL_0_SHIFT 24 +#define IPI_PL_0_OBS_PL_0_WIDTH 1 +#define IPI_PL_0_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_OBS_PMU_3_SHIFT 19 +#define IPI_PL_0_OBS_PMU_3_WIDTH 1 +#define IPI_PL_0_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_OBS_PMU_2_SHIFT 18 +#define IPI_PL_0_OBS_PMU_2_WIDTH 1 +#define IPI_PL_0_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_OBS_PMU_1_SHIFT 17 +#define IPI_PL_0_OBS_PMU_1_WIDTH 1 +#define IPI_PL_0_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_OBS_PMU_0_SHIFT 16 +#define IPI_PL_0_OBS_PMU_0_WIDTH 1 +#define IPI_PL_0_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_OBS_RPU_1_SHIFT 9 +#define IPI_PL_0_OBS_RPU_1_WIDTH 1 +#define IPI_PL_0_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_OBS_RPU_0_SHIFT 8 +#define IPI_PL_0_OBS_RPU_0_WIDTH 1 +#define IPI_PL_0_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_OBS_APU_SHIFT 0 +#define IPI_PL_0_OBS_APU_WIDTH 1 +#define IPI_PL_0_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_ISR + */ +#define IPI_PL_0_ISR ( ( IPI_BASEADDR ) + ((u32)0X00040010U) ) + +#define IPI_PL_0_ISR_PL_3_SHIFT 27 +#define IPI_PL_0_ISR_PL_3_WIDTH 1 +#define IPI_PL_0_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_ISR_PL_2_SHIFT 26 +#define IPI_PL_0_ISR_PL_2_WIDTH 1 +#define IPI_PL_0_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_ISR_PL_1_SHIFT 25 +#define IPI_PL_0_ISR_PL_1_WIDTH 1 +#define IPI_PL_0_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_ISR_PL_0_SHIFT 24 +#define IPI_PL_0_ISR_PL_0_WIDTH 1 +#define IPI_PL_0_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_ISR_PMU_3_SHIFT 19 +#define IPI_PL_0_ISR_PMU_3_WIDTH 1 +#define IPI_PL_0_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_ISR_PMU_2_SHIFT 18 +#define IPI_PL_0_ISR_PMU_2_WIDTH 1 +#define IPI_PL_0_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_ISR_PMU_1_SHIFT 17 +#define IPI_PL_0_ISR_PMU_1_WIDTH 1 +#define IPI_PL_0_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_ISR_PMU_0_SHIFT 16 +#define IPI_PL_0_ISR_PMU_0_WIDTH 1 +#define IPI_PL_0_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_ISR_RPU_1_SHIFT 9 +#define IPI_PL_0_ISR_RPU_1_WIDTH 1 +#define IPI_PL_0_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_ISR_RPU_0_SHIFT 8 +#define IPI_PL_0_ISR_RPU_0_WIDTH 1 +#define IPI_PL_0_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_ISR_APU_SHIFT 0 +#define IPI_PL_0_ISR_APU_WIDTH 1 +#define IPI_PL_0_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_IMR + */ +#define IPI_PL_0_IMR ( ( IPI_BASEADDR ) + ((u32)0X00040014U) ) + +#define IPI_PL_0_IMR_PL_3_SHIFT 27 +#define IPI_PL_0_IMR_PL_3_WIDTH 1 +#define IPI_PL_0_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_IMR_PL_2_SHIFT 26 +#define IPI_PL_0_IMR_PL_2_WIDTH 1 +#define IPI_PL_0_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_IMR_PL_1_SHIFT 25 +#define IPI_PL_0_IMR_PL_1_WIDTH 1 +#define IPI_PL_0_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_IMR_PL_0_SHIFT 24 +#define IPI_PL_0_IMR_PL_0_WIDTH 1 +#define IPI_PL_0_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_IMR_PMU_3_SHIFT 19 +#define IPI_PL_0_IMR_PMU_3_WIDTH 1 +#define IPI_PL_0_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_IMR_PMU_2_SHIFT 18 +#define IPI_PL_0_IMR_PMU_2_WIDTH 1 +#define IPI_PL_0_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_IMR_PMU_1_SHIFT 17 +#define IPI_PL_0_IMR_PMU_1_WIDTH 1 +#define IPI_PL_0_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_IMR_PMU_0_SHIFT 16 +#define IPI_PL_0_IMR_PMU_0_WIDTH 1 +#define IPI_PL_0_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_IMR_RPU_1_SHIFT 9 +#define IPI_PL_0_IMR_RPU_1_WIDTH 1 +#define IPI_PL_0_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_IMR_RPU_0_SHIFT 8 +#define IPI_PL_0_IMR_RPU_0_WIDTH 1 +#define IPI_PL_0_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_IMR_APU_SHIFT 0 +#define IPI_PL_0_IMR_APU_WIDTH 1 +#define IPI_PL_0_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_IER + */ +#define IPI_PL_0_IER ( ( IPI_BASEADDR ) + ((u32)0X00040018U) ) + +#define IPI_PL_0_IER_PL_3_SHIFT 27 +#define IPI_PL_0_IER_PL_3_WIDTH 1 +#define IPI_PL_0_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_IER_PL_2_SHIFT 26 +#define IPI_PL_0_IER_PL_2_WIDTH 1 +#define IPI_PL_0_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_IER_PL_1_SHIFT 25 +#define IPI_PL_0_IER_PL_1_WIDTH 1 +#define IPI_PL_0_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_IER_PL_0_SHIFT 24 +#define IPI_PL_0_IER_PL_0_WIDTH 1 +#define IPI_PL_0_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_IER_PMU_3_SHIFT 19 +#define IPI_PL_0_IER_PMU_3_WIDTH 1 +#define IPI_PL_0_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_IER_PMU_2_SHIFT 18 +#define IPI_PL_0_IER_PMU_2_WIDTH 1 +#define IPI_PL_0_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_IER_PMU_1_SHIFT 17 +#define IPI_PL_0_IER_PMU_1_WIDTH 1 +#define IPI_PL_0_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_IER_PMU_0_SHIFT 16 +#define IPI_PL_0_IER_PMU_0_WIDTH 1 +#define IPI_PL_0_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_IER_RPU_1_SHIFT 9 +#define IPI_PL_0_IER_RPU_1_WIDTH 1 +#define IPI_PL_0_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_IER_RPU_0_SHIFT 8 +#define IPI_PL_0_IER_RPU_0_WIDTH 1 +#define IPI_PL_0_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_IER_APU_SHIFT 0 +#define IPI_PL_0_IER_APU_WIDTH 1 +#define IPI_PL_0_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_0_IDR + */ +#define IPI_PL_0_IDR ( ( IPI_BASEADDR ) + ((u32)0X0004001CU) ) + +#define IPI_PL_0_IDR_PL_3_SHIFT 27 +#define IPI_PL_0_IDR_PL_3_WIDTH 1 +#define IPI_PL_0_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_0_IDR_PL_2_SHIFT 26 +#define IPI_PL_0_IDR_PL_2_WIDTH 1 +#define IPI_PL_0_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_0_IDR_PL_1_SHIFT 25 +#define IPI_PL_0_IDR_PL_1_WIDTH 1 +#define IPI_PL_0_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_0_IDR_PL_0_SHIFT 24 +#define IPI_PL_0_IDR_PL_0_WIDTH 1 +#define IPI_PL_0_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_0_IDR_PMU_3_SHIFT 19 +#define IPI_PL_0_IDR_PMU_3_WIDTH 1 +#define IPI_PL_0_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_0_IDR_PMU_2_SHIFT 18 +#define IPI_PL_0_IDR_PMU_2_WIDTH 1 +#define IPI_PL_0_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_0_IDR_PMU_1_SHIFT 17 +#define IPI_PL_0_IDR_PMU_1_WIDTH 1 +#define IPI_PL_0_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_0_IDR_PMU_0_SHIFT 16 +#define IPI_PL_0_IDR_PMU_0_WIDTH 1 +#define IPI_PL_0_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_0_IDR_RPU_1_SHIFT 9 +#define IPI_PL_0_IDR_RPU_1_WIDTH 1 +#define IPI_PL_0_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_0_IDR_RPU_0_SHIFT 8 +#define IPI_PL_0_IDR_RPU_0_WIDTH 1 +#define IPI_PL_0_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_0_IDR_APU_SHIFT 0 +#define IPI_PL_0_IDR_APU_WIDTH 1 +#define IPI_PL_0_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_TRIG + */ +#define IPI_PL_1_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00050000U) ) + +#define IPI_PL_1_TRIG_PL_3_SHIFT 27 +#define IPI_PL_1_TRIG_PL_3_WIDTH 1 +#define IPI_PL_1_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_TRIG_PL_2_SHIFT 26 +#define IPI_PL_1_TRIG_PL_2_WIDTH 1 +#define IPI_PL_1_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_TRIG_PL_1_SHIFT 25 +#define IPI_PL_1_TRIG_PL_1_WIDTH 1 +#define IPI_PL_1_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_TRIG_PL_0_SHIFT 24 +#define IPI_PL_1_TRIG_PL_0_WIDTH 1 +#define IPI_PL_1_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_1_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_1_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_1_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_1_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_1_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_1_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_1_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_1_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_1_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_TRIG_APU_SHIFT 0 +#define IPI_PL_1_TRIG_APU_WIDTH 1 +#define IPI_PL_1_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_OBS + */ +#define IPI_PL_1_OBS ( ( IPI_BASEADDR ) + ((u32)0X00050004U) ) + +#define IPI_PL_1_OBS_PL_3_SHIFT 27 +#define IPI_PL_1_OBS_PL_3_WIDTH 1 +#define IPI_PL_1_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_OBS_PL_2_SHIFT 26 +#define IPI_PL_1_OBS_PL_2_WIDTH 1 +#define IPI_PL_1_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_OBS_PL_1_SHIFT 25 +#define IPI_PL_1_OBS_PL_1_WIDTH 1 +#define IPI_PL_1_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_OBS_PL_0_SHIFT 24 +#define IPI_PL_1_OBS_PL_0_WIDTH 1 +#define IPI_PL_1_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_OBS_PMU_3_SHIFT 19 +#define IPI_PL_1_OBS_PMU_3_WIDTH 1 +#define IPI_PL_1_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_OBS_PMU_2_SHIFT 18 +#define IPI_PL_1_OBS_PMU_2_WIDTH 1 +#define IPI_PL_1_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_OBS_PMU_1_SHIFT 17 +#define IPI_PL_1_OBS_PMU_1_WIDTH 1 +#define IPI_PL_1_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_OBS_PMU_0_SHIFT 16 +#define IPI_PL_1_OBS_PMU_0_WIDTH 1 +#define IPI_PL_1_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_OBS_RPU_1_SHIFT 9 +#define IPI_PL_1_OBS_RPU_1_WIDTH 1 +#define IPI_PL_1_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_OBS_RPU_0_SHIFT 8 +#define IPI_PL_1_OBS_RPU_0_WIDTH 1 +#define IPI_PL_1_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_OBS_APU_SHIFT 0 +#define IPI_PL_1_OBS_APU_WIDTH 1 +#define IPI_PL_1_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_ISR + */ +#define IPI_PL_1_ISR ( ( IPI_BASEADDR ) + ((u32)0X00050010U) ) + +#define IPI_PL_1_ISR_PL_3_SHIFT 27 +#define IPI_PL_1_ISR_PL_3_WIDTH 1 +#define IPI_PL_1_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_ISR_PL_2_SHIFT 26 +#define IPI_PL_1_ISR_PL_2_WIDTH 1 +#define IPI_PL_1_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_ISR_PL_1_SHIFT 25 +#define IPI_PL_1_ISR_PL_1_WIDTH 1 +#define IPI_PL_1_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_ISR_PL_0_SHIFT 24 +#define IPI_PL_1_ISR_PL_0_WIDTH 1 +#define IPI_PL_1_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_ISR_PMU_3_SHIFT 19 +#define IPI_PL_1_ISR_PMU_3_WIDTH 1 +#define IPI_PL_1_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_ISR_PMU_2_SHIFT 18 +#define IPI_PL_1_ISR_PMU_2_WIDTH 1 +#define IPI_PL_1_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_ISR_PMU_1_SHIFT 17 +#define IPI_PL_1_ISR_PMU_1_WIDTH 1 +#define IPI_PL_1_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_ISR_PMU_0_SHIFT 16 +#define IPI_PL_1_ISR_PMU_0_WIDTH 1 +#define IPI_PL_1_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_ISR_RPU_1_SHIFT 9 +#define IPI_PL_1_ISR_RPU_1_WIDTH 1 +#define IPI_PL_1_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_ISR_RPU_0_SHIFT 8 +#define IPI_PL_1_ISR_RPU_0_WIDTH 1 +#define IPI_PL_1_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_ISR_APU_SHIFT 0 +#define IPI_PL_1_ISR_APU_WIDTH 1 +#define IPI_PL_1_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_IMR + */ +#define IPI_PL_1_IMR ( ( IPI_BASEADDR ) + ((u32)0X00050014U) ) + +#define IPI_PL_1_IMR_PL_3_SHIFT 27 +#define IPI_PL_1_IMR_PL_3_WIDTH 1 +#define IPI_PL_1_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_IMR_PL_2_SHIFT 26 +#define IPI_PL_1_IMR_PL_2_WIDTH 1 +#define IPI_PL_1_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_IMR_PL_1_SHIFT 25 +#define IPI_PL_1_IMR_PL_1_WIDTH 1 +#define IPI_PL_1_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_IMR_PL_0_SHIFT 24 +#define IPI_PL_1_IMR_PL_0_WIDTH 1 +#define IPI_PL_1_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_IMR_PMU_3_SHIFT 19 +#define IPI_PL_1_IMR_PMU_3_WIDTH 1 +#define IPI_PL_1_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_IMR_PMU_2_SHIFT 18 +#define IPI_PL_1_IMR_PMU_2_WIDTH 1 +#define IPI_PL_1_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_IMR_PMU_1_SHIFT 17 +#define IPI_PL_1_IMR_PMU_1_WIDTH 1 +#define IPI_PL_1_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_IMR_PMU_0_SHIFT 16 +#define IPI_PL_1_IMR_PMU_0_WIDTH 1 +#define IPI_PL_1_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_IMR_RPU_1_SHIFT 9 +#define IPI_PL_1_IMR_RPU_1_WIDTH 1 +#define IPI_PL_1_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_IMR_RPU_0_SHIFT 8 +#define IPI_PL_1_IMR_RPU_0_WIDTH 1 +#define IPI_PL_1_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_IMR_APU_SHIFT 0 +#define IPI_PL_1_IMR_APU_WIDTH 1 +#define IPI_PL_1_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_IER + */ +#define IPI_PL_1_IER ( ( IPI_BASEADDR ) + ((u32)0X00050018U) ) + +#define IPI_PL_1_IER_PL_3_SHIFT 27 +#define IPI_PL_1_IER_PL_3_WIDTH 1 +#define IPI_PL_1_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_IER_PL_2_SHIFT 26 +#define IPI_PL_1_IER_PL_2_WIDTH 1 +#define IPI_PL_1_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_IER_PL_1_SHIFT 25 +#define IPI_PL_1_IER_PL_1_WIDTH 1 +#define IPI_PL_1_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_IER_PL_0_SHIFT 24 +#define IPI_PL_1_IER_PL_0_WIDTH 1 +#define IPI_PL_1_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_IER_PMU_3_SHIFT 19 +#define IPI_PL_1_IER_PMU_3_WIDTH 1 +#define IPI_PL_1_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_IER_PMU_2_SHIFT 18 +#define IPI_PL_1_IER_PMU_2_WIDTH 1 +#define IPI_PL_1_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_IER_PMU_1_SHIFT 17 +#define IPI_PL_1_IER_PMU_1_WIDTH 1 +#define IPI_PL_1_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_IER_PMU_0_SHIFT 16 +#define IPI_PL_1_IER_PMU_0_WIDTH 1 +#define IPI_PL_1_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_IER_RPU_1_SHIFT 9 +#define IPI_PL_1_IER_RPU_1_WIDTH 1 +#define IPI_PL_1_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_IER_RPU_0_SHIFT 8 +#define IPI_PL_1_IER_RPU_0_WIDTH 1 +#define IPI_PL_1_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_IER_APU_SHIFT 0 +#define IPI_PL_1_IER_APU_WIDTH 1 +#define IPI_PL_1_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_1_IDR + */ +#define IPI_PL_1_IDR ( ( IPI_BASEADDR ) + ((u32)0X0005001CU) ) + +#define IPI_PL_1_IDR_PL_3_SHIFT 27 +#define IPI_PL_1_IDR_PL_3_WIDTH 1 +#define IPI_PL_1_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_1_IDR_PL_2_SHIFT 26 +#define IPI_PL_1_IDR_PL_2_WIDTH 1 +#define IPI_PL_1_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_1_IDR_PL_1_SHIFT 25 +#define IPI_PL_1_IDR_PL_1_WIDTH 1 +#define IPI_PL_1_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_1_IDR_PL_0_SHIFT 24 +#define IPI_PL_1_IDR_PL_0_WIDTH 1 +#define IPI_PL_1_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_1_IDR_PMU_3_SHIFT 19 +#define IPI_PL_1_IDR_PMU_3_WIDTH 1 +#define IPI_PL_1_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_1_IDR_PMU_2_SHIFT 18 +#define IPI_PL_1_IDR_PMU_2_WIDTH 1 +#define IPI_PL_1_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_1_IDR_PMU_1_SHIFT 17 +#define IPI_PL_1_IDR_PMU_1_WIDTH 1 +#define IPI_PL_1_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_1_IDR_PMU_0_SHIFT 16 +#define IPI_PL_1_IDR_PMU_0_WIDTH 1 +#define IPI_PL_1_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_1_IDR_RPU_1_SHIFT 9 +#define IPI_PL_1_IDR_RPU_1_WIDTH 1 +#define IPI_PL_1_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_1_IDR_RPU_0_SHIFT 8 +#define IPI_PL_1_IDR_RPU_0_WIDTH 1 +#define IPI_PL_1_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_1_IDR_APU_SHIFT 0 +#define IPI_PL_1_IDR_APU_WIDTH 1 +#define IPI_PL_1_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_TRIG + */ +#define IPI_PL_2_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00060000U) ) + +#define IPI_PL_2_TRIG_PL_3_SHIFT 27 +#define IPI_PL_2_TRIG_PL_3_WIDTH 1 +#define IPI_PL_2_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_TRIG_PL_2_SHIFT 26 +#define IPI_PL_2_TRIG_PL_2_WIDTH 1 +#define IPI_PL_2_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_TRIG_PL_1_SHIFT 25 +#define IPI_PL_2_TRIG_PL_1_WIDTH 1 +#define IPI_PL_2_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_TRIG_PL_0_SHIFT 24 +#define IPI_PL_2_TRIG_PL_0_WIDTH 1 +#define IPI_PL_2_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_2_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_2_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_2_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_2_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_2_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_2_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_2_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_2_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_2_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_TRIG_APU_SHIFT 0 +#define IPI_PL_2_TRIG_APU_WIDTH 1 +#define IPI_PL_2_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_OBS + */ +#define IPI_PL_2_OBS ( ( IPI_BASEADDR ) + ((u32)0X00060004U) ) + +#define IPI_PL_2_OBS_PL_3_SHIFT 27 +#define IPI_PL_2_OBS_PL_3_WIDTH 1 +#define IPI_PL_2_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_OBS_PL_2_SHIFT 26 +#define IPI_PL_2_OBS_PL_2_WIDTH 1 +#define IPI_PL_2_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_OBS_PL_1_SHIFT 25 +#define IPI_PL_2_OBS_PL_1_WIDTH 1 +#define IPI_PL_2_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_OBS_PL_0_SHIFT 24 +#define IPI_PL_2_OBS_PL_0_WIDTH 1 +#define IPI_PL_2_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_OBS_PMU_3_SHIFT 19 +#define IPI_PL_2_OBS_PMU_3_WIDTH 1 +#define IPI_PL_2_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_OBS_PMU_2_SHIFT 18 +#define IPI_PL_2_OBS_PMU_2_WIDTH 1 +#define IPI_PL_2_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_OBS_PMU_1_SHIFT 17 +#define IPI_PL_2_OBS_PMU_1_WIDTH 1 +#define IPI_PL_2_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_OBS_PMU_0_SHIFT 16 +#define IPI_PL_2_OBS_PMU_0_WIDTH 1 +#define IPI_PL_2_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_OBS_RPU_1_SHIFT 9 +#define IPI_PL_2_OBS_RPU_1_WIDTH 1 +#define IPI_PL_2_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_OBS_RPU_0_SHIFT 8 +#define IPI_PL_2_OBS_RPU_0_WIDTH 1 +#define IPI_PL_2_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_OBS_APU_SHIFT 0 +#define IPI_PL_2_OBS_APU_WIDTH 1 +#define IPI_PL_2_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_ISR + */ +#define IPI_PL_2_ISR ( ( IPI_BASEADDR ) + ((u32)0X00060010U) ) + +#define IPI_PL_2_ISR_PL_3_SHIFT 27 +#define IPI_PL_2_ISR_PL_3_WIDTH 1 +#define IPI_PL_2_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_ISR_PL_2_SHIFT 26 +#define IPI_PL_2_ISR_PL_2_WIDTH 1 +#define IPI_PL_2_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_ISR_PL_1_SHIFT 25 +#define IPI_PL_2_ISR_PL_1_WIDTH 1 +#define IPI_PL_2_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_ISR_PL_0_SHIFT 24 +#define IPI_PL_2_ISR_PL_0_WIDTH 1 +#define IPI_PL_2_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_ISR_PMU_3_SHIFT 19 +#define IPI_PL_2_ISR_PMU_3_WIDTH 1 +#define IPI_PL_2_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_ISR_PMU_2_SHIFT 18 +#define IPI_PL_2_ISR_PMU_2_WIDTH 1 +#define IPI_PL_2_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_ISR_PMU_1_SHIFT 17 +#define IPI_PL_2_ISR_PMU_1_WIDTH 1 +#define IPI_PL_2_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_ISR_PMU_0_SHIFT 16 +#define IPI_PL_2_ISR_PMU_0_WIDTH 1 +#define IPI_PL_2_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_ISR_RPU_1_SHIFT 9 +#define IPI_PL_2_ISR_RPU_1_WIDTH 1 +#define IPI_PL_2_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_ISR_RPU_0_SHIFT 8 +#define IPI_PL_2_ISR_RPU_0_WIDTH 1 +#define IPI_PL_2_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_ISR_APU_SHIFT 0 +#define IPI_PL_2_ISR_APU_WIDTH 1 +#define IPI_PL_2_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_IMR + */ +#define IPI_PL_2_IMR ( ( IPI_BASEADDR ) + ((u32)0X00060014U) ) + +#define IPI_PL_2_IMR_PL_3_SHIFT 27 +#define IPI_PL_2_IMR_PL_3_WIDTH 1 +#define IPI_PL_2_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_IMR_PL_2_SHIFT 26 +#define IPI_PL_2_IMR_PL_2_WIDTH 1 +#define IPI_PL_2_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_IMR_PL_1_SHIFT 25 +#define IPI_PL_2_IMR_PL_1_WIDTH 1 +#define IPI_PL_2_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_IMR_PL_0_SHIFT 24 +#define IPI_PL_2_IMR_PL_0_WIDTH 1 +#define IPI_PL_2_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_IMR_PMU_3_SHIFT 19 +#define IPI_PL_2_IMR_PMU_3_WIDTH 1 +#define IPI_PL_2_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_IMR_PMU_2_SHIFT 18 +#define IPI_PL_2_IMR_PMU_2_WIDTH 1 +#define IPI_PL_2_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_IMR_PMU_1_SHIFT 17 +#define IPI_PL_2_IMR_PMU_1_WIDTH 1 +#define IPI_PL_2_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_IMR_PMU_0_SHIFT 16 +#define IPI_PL_2_IMR_PMU_0_WIDTH 1 +#define IPI_PL_2_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_IMR_RPU_1_SHIFT 9 +#define IPI_PL_2_IMR_RPU_1_WIDTH 1 +#define IPI_PL_2_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_IMR_RPU_0_SHIFT 8 +#define IPI_PL_2_IMR_RPU_0_WIDTH 1 +#define IPI_PL_2_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_IMR_APU_SHIFT 0 +#define IPI_PL_2_IMR_APU_WIDTH 1 +#define IPI_PL_2_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_IER + */ +#define IPI_PL_2_IER ( ( IPI_BASEADDR ) + ((u32)0X00060018U) ) + +#define IPI_PL_2_IER_PL_3_SHIFT 27 +#define IPI_PL_2_IER_PL_3_WIDTH 1 +#define IPI_PL_2_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_IER_PL_2_SHIFT 26 +#define IPI_PL_2_IER_PL_2_WIDTH 1 +#define IPI_PL_2_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_IER_PL_1_SHIFT 25 +#define IPI_PL_2_IER_PL_1_WIDTH 1 +#define IPI_PL_2_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_IER_PL_0_SHIFT 24 +#define IPI_PL_2_IER_PL_0_WIDTH 1 +#define IPI_PL_2_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_IER_PMU_3_SHIFT 19 +#define IPI_PL_2_IER_PMU_3_WIDTH 1 +#define IPI_PL_2_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_IER_PMU_2_SHIFT 18 +#define IPI_PL_2_IER_PMU_2_WIDTH 1 +#define IPI_PL_2_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_IER_PMU_1_SHIFT 17 +#define IPI_PL_2_IER_PMU_1_WIDTH 1 +#define IPI_PL_2_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_IER_PMU_0_SHIFT 16 +#define IPI_PL_2_IER_PMU_0_WIDTH 1 +#define IPI_PL_2_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_IER_RPU_1_SHIFT 9 +#define IPI_PL_2_IER_RPU_1_WIDTH 1 +#define IPI_PL_2_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_IER_RPU_0_SHIFT 8 +#define IPI_PL_2_IER_RPU_0_WIDTH 1 +#define IPI_PL_2_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_IER_APU_SHIFT 0 +#define IPI_PL_2_IER_APU_WIDTH 1 +#define IPI_PL_2_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_2_IDR + */ +#define IPI_PL_2_IDR ( ( IPI_BASEADDR ) + ((u32)0X0006001CU) ) + +#define IPI_PL_2_IDR_PL_3_SHIFT 27 +#define IPI_PL_2_IDR_PL_3_WIDTH 1 +#define IPI_PL_2_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_2_IDR_PL_2_SHIFT 26 +#define IPI_PL_2_IDR_PL_2_WIDTH 1 +#define IPI_PL_2_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_2_IDR_PL_1_SHIFT 25 +#define IPI_PL_2_IDR_PL_1_WIDTH 1 +#define IPI_PL_2_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_2_IDR_PL_0_SHIFT 24 +#define IPI_PL_2_IDR_PL_0_WIDTH 1 +#define IPI_PL_2_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_2_IDR_PMU_3_SHIFT 19 +#define IPI_PL_2_IDR_PMU_3_WIDTH 1 +#define IPI_PL_2_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_2_IDR_PMU_2_SHIFT 18 +#define IPI_PL_2_IDR_PMU_2_WIDTH 1 +#define IPI_PL_2_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_2_IDR_PMU_1_SHIFT 17 +#define IPI_PL_2_IDR_PMU_1_WIDTH 1 +#define IPI_PL_2_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_2_IDR_PMU_0_SHIFT 16 +#define IPI_PL_2_IDR_PMU_0_WIDTH 1 +#define IPI_PL_2_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_2_IDR_RPU_1_SHIFT 9 +#define IPI_PL_2_IDR_RPU_1_WIDTH 1 +#define IPI_PL_2_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_2_IDR_RPU_0_SHIFT 8 +#define IPI_PL_2_IDR_RPU_0_WIDTH 1 +#define IPI_PL_2_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_2_IDR_APU_SHIFT 0 +#define IPI_PL_2_IDR_APU_WIDTH 1 +#define IPI_PL_2_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_TRIG + */ +#define IPI_PL_3_TRIG ( ( IPI_BASEADDR ) + ((u32)0X00070000U) ) + +#define IPI_PL_3_TRIG_PL_3_SHIFT 27 +#define IPI_PL_3_TRIG_PL_3_WIDTH 1 +#define IPI_PL_3_TRIG_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_TRIG_PL_2_SHIFT 26 +#define IPI_PL_3_TRIG_PL_2_WIDTH 1 +#define IPI_PL_3_TRIG_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_TRIG_PL_1_SHIFT 25 +#define IPI_PL_3_TRIG_PL_1_WIDTH 1 +#define IPI_PL_3_TRIG_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_TRIG_PL_0_SHIFT 24 +#define IPI_PL_3_TRIG_PL_0_WIDTH 1 +#define IPI_PL_3_TRIG_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_TRIG_PMU_3_SHIFT 19 +#define IPI_PL_3_TRIG_PMU_3_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_TRIG_PMU_2_SHIFT 18 +#define IPI_PL_3_TRIG_PMU_2_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_TRIG_PMU_1_SHIFT 17 +#define IPI_PL_3_TRIG_PMU_1_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_TRIG_PMU_0_SHIFT 16 +#define IPI_PL_3_TRIG_PMU_0_WIDTH 1 +#define IPI_PL_3_TRIG_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_TRIG_RPU_1_SHIFT 9 +#define IPI_PL_3_TRIG_RPU_1_WIDTH 1 +#define IPI_PL_3_TRIG_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_TRIG_RPU_0_SHIFT 8 +#define IPI_PL_3_TRIG_RPU_0_WIDTH 1 +#define IPI_PL_3_TRIG_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_TRIG_APU_SHIFT 0 +#define IPI_PL_3_TRIG_APU_WIDTH 1 +#define IPI_PL_3_TRIG_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_OBS + */ +#define IPI_PL_3_OBS ( ( IPI_BASEADDR ) + ((u32)0X00070004U) ) + +#define IPI_PL_3_OBS_PL_3_SHIFT 27 +#define IPI_PL_3_OBS_PL_3_WIDTH 1 +#define IPI_PL_3_OBS_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_OBS_PL_2_SHIFT 26 +#define IPI_PL_3_OBS_PL_2_WIDTH 1 +#define IPI_PL_3_OBS_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_OBS_PL_1_SHIFT 25 +#define IPI_PL_3_OBS_PL_1_WIDTH 1 +#define IPI_PL_3_OBS_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_OBS_PL_0_SHIFT 24 +#define IPI_PL_3_OBS_PL_0_WIDTH 1 +#define IPI_PL_3_OBS_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_OBS_PMU_3_SHIFT 19 +#define IPI_PL_3_OBS_PMU_3_WIDTH 1 +#define IPI_PL_3_OBS_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_OBS_PMU_2_SHIFT 18 +#define IPI_PL_3_OBS_PMU_2_WIDTH 1 +#define IPI_PL_3_OBS_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_OBS_PMU_1_SHIFT 17 +#define IPI_PL_3_OBS_PMU_1_WIDTH 1 +#define IPI_PL_3_OBS_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_OBS_PMU_0_SHIFT 16 +#define IPI_PL_3_OBS_PMU_0_WIDTH 1 +#define IPI_PL_3_OBS_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_OBS_RPU_1_SHIFT 9 +#define IPI_PL_3_OBS_RPU_1_WIDTH 1 +#define IPI_PL_3_OBS_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_OBS_RPU_0_SHIFT 8 +#define IPI_PL_3_OBS_RPU_0_WIDTH 1 +#define IPI_PL_3_OBS_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_OBS_APU_SHIFT 0 +#define IPI_PL_3_OBS_APU_WIDTH 1 +#define IPI_PL_3_OBS_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_ISR + */ +#define IPI_PL_3_ISR ( ( IPI_BASEADDR ) + ((u32)0X00070010U) ) + +#define IPI_PL_3_ISR_PL_3_SHIFT 27 +#define IPI_PL_3_ISR_PL_3_WIDTH 1 +#define IPI_PL_3_ISR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_ISR_PL_2_SHIFT 26 +#define IPI_PL_3_ISR_PL_2_WIDTH 1 +#define IPI_PL_3_ISR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_ISR_PL_1_SHIFT 25 +#define IPI_PL_3_ISR_PL_1_WIDTH 1 +#define IPI_PL_3_ISR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_ISR_PL_0_SHIFT 24 +#define IPI_PL_3_ISR_PL_0_WIDTH 1 +#define IPI_PL_3_ISR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_ISR_PMU_3_SHIFT 19 +#define IPI_PL_3_ISR_PMU_3_WIDTH 1 +#define IPI_PL_3_ISR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_ISR_PMU_2_SHIFT 18 +#define IPI_PL_3_ISR_PMU_2_WIDTH 1 +#define IPI_PL_3_ISR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_ISR_PMU_1_SHIFT 17 +#define IPI_PL_3_ISR_PMU_1_WIDTH 1 +#define IPI_PL_3_ISR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_ISR_PMU_0_SHIFT 16 +#define IPI_PL_3_ISR_PMU_0_WIDTH 1 +#define IPI_PL_3_ISR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_ISR_RPU_1_SHIFT 9 +#define IPI_PL_3_ISR_RPU_1_WIDTH 1 +#define IPI_PL_3_ISR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_ISR_RPU_0_SHIFT 8 +#define IPI_PL_3_ISR_RPU_0_WIDTH 1 +#define IPI_PL_3_ISR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_ISR_APU_SHIFT 0 +#define IPI_PL_3_ISR_APU_WIDTH 1 +#define IPI_PL_3_ISR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_IMR + */ +#define IPI_PL_3_IMR ( ( IPI_BASEADDR ) + ((u32)0X00070014U) ) + +#define IPI_PL_3_IMR_PL_3_SHIFT 27 +#define IPI_PL_3_IMR_PL_3_WIDTH 1 +#define IPI_PL_3_IMR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_IMR_PL_2_SHIFT 26 +#define IPI_PL_3_IMR_PL_2_WIDTH 1 +#define IPI_PL_3_IMR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_IMR_PL_1_SHIFT 25 +#define IPI_PL_3_IMR_PL_1_WIDTH 1 +#define IPI_PL_3_IMR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_IMR_PL_0_SHIFT 24 +#define IPI_PL_3_IMR_PL_0_WIDTH 1 +#define IPI_PL_3_IMR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_IMR_PMU_3_SHIFT 19 +#define IPI_PL_3_IMR_PMU_3_WIDTH 1 +#define IPI_PL_3_IMR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_IMR_PMU_2_SHIFT 18 +#define IPI_PL_3_IMR_PMU_2_WIDTH 1 +#define IPI_PL_3_IMR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_IMR_PMU_1_SHIFT 17 +#define IPI_PL_3_IMR_PMU_1_WIDTH 1 +#define IPI_PL_3_IMR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_IMR_PMU_0_SHIFT 16 +#define IPI_PL_3_IMR_PMU_0_WIDTH 1 +#define IPI_PL_3_IMR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_IMR_RPU_1_SHIFT 9 +#define IPI_PL_3_IMR_RPU_1_WIDTH 1 +#define IPI_PL_3_IMR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_IMR_RPU_0_SHIFT 8 +#define IPI_PL_3_IMR_RPU_0_WIDTH 1 +#define IPI_PL_3_IMR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_IMR_APU_SHIFT 0 +#define IPI_PL_3_IMR_APU_WIDTH 1 +#define IPI_PL_3_IMR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_IER + */ +#define IPI_PL_3_IER ( ( IPI_BASEADDR ) + ((u32)0X00070018U) ) + +#define IPI_PL_3_IER_PL_3_SHIFT 27 +#define IPI_PL_3_IER_PL_3_WIDTH 1 +#define IPI_PL_3_IER_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_IER_PL_2_SHIFT 26 +#define IPI_PL_3_IER_PL_2_WIDTH 1 +#define IPI_PL_3_IER_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_IER_PL_1_SHIFT 25 +#define IPI_PL_3_IER_PL_1_WIDTH 1 +#define IPI_PL_3_IER_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_IER_PL_0_SHIFT 24 +#define IPI_PL_3_IER_PL_0_WIDTH 1 +#define IPI_PL_3_IER_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_IER_PMU_3_SHIFT 19 +#define IPI_PL_3_IER_PMU_3_WIDTH 1 +#define IPI_PL_3_IER_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_IER_PMU_2_SHIFT 18 +#define IPI_PL_3_IER_PMU_2_WIDTH 1 +#define IPI_PL_3_IER_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_IER_PMU_1_SHIFT 17 +#define IPI_PL_3_IER_PMU_1_WIDTH 1 +#define IPI_PL_3_IER_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_IER_PMU_0_SHIFT 16 +#define IPI_PL_3_IER_PMU_0_WIDTH 1 +#define IPI_PL_3_IER_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_IER_RPU_1_SHIFT 9 +#define IPI_PL_3_IER_RPU_1_WIDTH 1 +#define IPI_PL_3_IER_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_IER_RPU_0_SHIFT 8 +#define IPI_PL_3_IER_RPU_0_WIDTH 1 +#define IPI_PL_3_IER_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_IER_APU_SHIFT 0 +#define IPI_PL_3_IER_APU_WIDTH 1 +#define IPI_PL_3_IER_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_PL_3_IDR + */ +#define IPI_PL_3_IDR ( ( IPI_BASEADDR ) + ((u32)0X0007001CU) ) + +#define IPI_PL_3_IDR_PL_3_SHIFT 27 +#define IPI_PL_3_IDR_PL_3_WIDTH 1 +#define IPI_PL_3_IDR_PL_3_MASK ((u32)0X08000000U) + +#define IPI_PL_3_IDR_PL_2_SHIFT 26 +#define IPI_PL_3_IDR_PL_2_WIDTH 1 +#define IPI_PL_3_IDR_PL_2_MASK ((u32)0X04000000U) + +#define IPI_PL_3_IDR_PL_1_SHIFT 25 +#define IPI_PL_3_IDR_PL_1_WIDTH 1 +#define IPI_PL_3_IDR_PL_1_MASK ((u32)0X02000000U) + +#define IPI_PL_3_IDR_PL_0_SHIFT 24 +#define IPI_PL_3_IDR_PL_0_WIDTH 1 +#define IPI_PL_3_IDR_PL_0_MASK ((u32)0X01000000U) + +#define IPI_PL_3_IDR_PMU_3_SHIFT 19 +#define IPI_PL_3_IDR_PMU_3_WIDTH 1 +#define IPI_PL_3_IDR_PMU_3_MASK ((u32)0X00080000U) + +#define IPI_PL_3_IDR_PMU_2_SHIFT 18 +#define IPI_PL_3_IDR_PMU_2_WIDTH 1 +#define IPI_PL_3_IDR_PMU_2_MASK ((u32)0X00040000U) + +#define IPI_PL_3_IDR_PMU_1_SHIFT 17 +#define IPI_PL_3_IDR_PMU_1_WIDTH 1 +#define IPI_PL_3_IDR_PMU_1_MASK ((u32)0X00020000U) + +#define IPI_PL_3_IDR_PMU_0_SHIFT 16 +#define IPI_PL_3_IDR_PMU_0_WIDTH 1 +#define IPI_PL_3_IDR_PMU_0_MASK ((u32)0X00010000U) + +#define IPI_PL_3_IDR_RPU_1_SHIFT 9 +#define IPI_PL_3_IDR_RPU_1_WIDTH 1 +#define IPI_PL_3_IDR_RPU_1_MASK ((u32)0X00000200U) + +#define IPI_PL_3_IDR_RPU_0_SHIFT 8 +#define IPI_PL_3_IDR_RPU_0_WIDTH 1 +#define IPI_PL_3_IDR_RPU_0_MASK ((u32)0X00000100U) + +#define IPI_PL_3_IDR_APU_SHIFT 0 +#define IPI_PL_3_IDR_APU_WIDTH 1 +#define IPI_PL_3_IDR_APU_MASK ((u32)0X00000001U) + +/** + * Register: IPI_IPI_CTRL + */ +#define IPI_IPI_CTRL ( ( IPI_BASEADDR ) + ((u32)0X00080000U) ) + +#define IPI_IPI_CTRL_SLVERR_ENABLE_SHIFT 0 +#define IPI_IPI_CTRL_SLVERR_ENABLE_WIDTH 1 +#define IPI_IPI_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: IPI_IPI_ISR + */ +#define IPI_IPI_ISR ( ( IPI_BASEADDR ) + ((u32)0X00080010U) ) + +#define IPI_IPI_ISR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_ISR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_ISR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: IPI_IPI_IMR + */ +#define IPI_IPI_IMR ( ( IPI_BASEADDR ) + ((u32)0X00080014U) ) + +#define IPI_IPI_IMR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IMR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IMR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: IPI_IPI_IER + */ +#define IPI_IPI_IER ( ( IPI_BASEADDR ) + ((u32)0X00080018U) ) + +#define IPI_IPI_IER_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IER_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IER_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: IPI_IPI_ECO + */ +#define IPI_IPI_ECO ( ( IPI_BASEADDR ) + ((u32)0X00080020U) ) + +#define IPI_IPI_ECO_ECO_SHIFT 0 +#define IPI_IPI_ECO_ECO_WIDTH 32 +#define IPI_IPI_ECO_ECO_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: IPI_SAFETY_CHK + */ +#define IPI_SAFETY_CHK ( ( IPI_BASEADDR ) + ((u32)0X00080030U) ) + +#define IPI_SAFETY_CHK_DATA_SHIFT 0 +#define IPI_SAFETY_CHK_DATA_WIDTH 32 +#define IPI_SAFETY_CHK_DATA_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: IPI_IPI_IDR + */ +#define IPI_IPI_IDR ( ( IPI_BASEADDR ) + ((u32)0X000C001CU) ) + +#define IPI_IPI_IDR_ADDR_DECODE_ERR_SHIFT 0 +#define IPI_IPI_IDR_ADDR_DECODE_ERR_WIDTH 1 +#define IPI_IPI_IDR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _IPI_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/ipi_buffer.h b/lib/sw_apps/zynqmp_pmufw/src/ipi_buffer.h new file mode 100644 index 00000000..bb631a02 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/ipi_buffer.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * IPI buffer related definitions. + *********************************************************************/ + +#ifndef IPI_BUFFER_H_ +#define IPI_BUFFER_H_ + +#define IPI_BUFFER_BASEADDR 0xFF990000U + +#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U) +#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U) +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U) +#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U) +#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U) +#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U) +#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U) + +#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U +#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U +#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U +#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U +#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U +#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/lpd_slcr.h b/lib/sw_apps/zynqmp_pmufw/src/lpd_slcr.h new file mode 100644 index 00000000..0a6af799 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/lpd_slcr.h @@ -0,0 +1,6671 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _LPD_SLCR_H_ +#define _LPD_SLCR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * LPD_SLCR Base Address + */ +#define LPD_SLCR_BASEADDR ((u32)0XFF410000U) + +/** + * Register: LPD_SLCR_WPROT0 + */ +#define LPD_SLCR_WPROT0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000000U) ) + +#define LPD_SLCR_WPROT0_ACTIVE_SHIFT 0 +#define LPD_SLCR_WPROT0_ACTIVE_WIDTH 1 +#define LPD_SLCR_WPROT0_ACTIVE_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_CTRL + */ +#define LPD_SLCR_CTRL ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000004U) ) + +#define LPD_SLCR_CTRL_SLVERR_ENABLE_SHIFT 0 +#define LPD_SLCR_CTRL_SLVERR_ENABLE_WIDTH 1 +#define LPD_SLCR_CTRL_SLVERR_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISR + */ +#define LPD_SLCR_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000008U) ) + +#define LPD_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0 +#define LPD_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1 +#define LPD_SLCR_ISR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_IMR + */ +#define LPD_SLCR_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000000CU) ) + +#define LPD_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0 +#define LPD_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1 +#define LPD_SLCR_IMR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_IER + */ +#define LPD_SLCR_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000010U) ) + +#define LPD_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0 +#define LPD_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1 +#define LPD_SLCR_IER_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_IDR + */ +#define LPD_SLCR_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000014U) ) + +#define LPD_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0 +#define LPD_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1 +#define LPD_SLCR_IDR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ITR + */ +#define LPD_SLCR_ITR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000018U) ) + +#define LPD_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0 +#define LPD_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1 +#define LPD_SLCR_ITR_ADDR_DECODE_ERR_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ECO + */ +#define LPD_SLCR_ECO ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000001CU) ) + +#define LPD_SLCR_ECO_FIELD_SHIFT 0 +#define LPD_SLCR_ECO_FIELD_WIDTH 32 +#define LPD_SLCR_ECO_FIELD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT0 + */ +#define LPD_SLCR_PERSISTENT0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000020U) ) + +#define LPD_SLCR_PERSISTENT0_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT0_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT0_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT1 + */ +#define LPD_SLCR_PERSISTENT1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000024U) ) + +#define LPD_SLCR_PERSISTENT1_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT1_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT2 + */ +#define LPD_SLCR_PERSISTENT2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000028U) ) + +#define LPD_SLCR_PERSISTENT2_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT2_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT2_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT3 + */ +#define LPD_SLCR_PERSISTENT3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000002CU) ) + +#define LPD_SLCR_PERSISTENT3_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT3_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT3_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT4 + */ +#define LPD_SLCR_PERSISTENT4 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000030U) ) + +#define LPD_SLCR_PERSISTENT4_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT4_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT4_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT5 + */ +#define LPD_SLCR_PERSISTENT5 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000034U) ) + +#define LPD_SLCR_PERSISTENT5_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT5_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT5_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT6 + */ +#define LPD_SLCR_PERSISTENT6 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000038U) ) + +#define LPD_SLCR_PERSISTENT6_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT6_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT6_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_PERSISTENT7 + */ +#define LPD_SLCR_PERSISTENT7 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000003CU) ) + +#define LPD_SLCR_PERSISTENT7_REG_SHIFT 0 +#define LPD_SLCR_PERSISTENT7_REG_WIDTH 32 +#define LPD_SLCR_PERSISTENT7_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_SAFETY_CHK0 + */ +#define LPD_SLCR_SAFETY_CHK0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000040U) ) + +#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_SHIFT 0 +#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_WIDTH 32 +#define LPD_SLCR_SAFETY_CHK0_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_SAFETY_CHK1 + */ +#define LPD_SLCR_SAFETY_CHK1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000044U) ) + +#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_SHIFT 0 +#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_WIDTH 32 +#define LPD_SLCR_SAFETY_CHK1_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_SAFETY_CHK2 + */ +#define LPD_SLCR_SAFETY_CHK2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000048U) ) + +#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_SHIFT 0 +#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_WIDTH 32 +#define LPD_SLCR_SAFETY_CHK2_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_SAFETY_CHK3 + */ +#define LPD_SLCR_SAFETY_CHK3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000004CU) ) + +#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_SHIFT 0 +#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_WIDTH 32 +#define LPD_SLCR_SAFETY_CHK3_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_CSUPMU_WDT_CLK_SEL + */ +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00000050U) ) + +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_WIDTH 1 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ADMA_CFG + */ +#define LPD_SLCR_ADMA_CFG ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000200CU) ) + +#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_SHIFT 5 +#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_WIDTH 2 +#define LPD_SLCR_ADMA_CFG_BUS_WIDTH_MASK ((u32)0X00000060U) + +#define LPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0 +#define LPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5 +#define LPD_SLCR_ADMA_CFG_NUM_CH_MASK ((u32)0X0000001FU) + +/** + * Register: LPD_SLCR_ADMA_RAM + */ +#define LPD_SLCR_ADMA_RAM ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00002010U) ) + +#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_SHIFT 12 +#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_WIDTH 3 +#define LPD_SLCR_ADMA_RAM_RAM1_EMAB_MASK ((u32)0X00007000U) + +#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_SHIFT 11 +#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_WIDTH 1 +#define LPD_SLCR_ADMA_RAM_RAM1_EMASA_MASK ((u32)0X00000800U) + +#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_SHIFT 8 +#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_WIDTH 3 +#define LPD_SLCR_ADMA_RAM_RAM1_EMAA_MASK ((u32)0X00000700U) + +#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_SHIFT 4 +#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_WIDTH 3 +#define LPD_SLCR_ADMA_RAM_RAM0_EMAB_MASK ((u32)0X00000070U) + +#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_SHIFT 3 +#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_WIDTH 1 +#define LPD_SLCR_ADMA_RAM_RAM0_EMASA_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_SHIFT 0 +#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_WIDTH 3 +#define LPD_SLCR_ADMA_RAM_RAM0_EMAA_MASK ((u32)0X00000007U) + +/** + * Register: LPD_SLCR_ERR_AIBAXI_ISR + */ +#define LPD_SLCR_ERR_AIBAXI_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003000U) ) + +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26 +#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23 +#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22 +#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAXI_IMR + */ +#define LPD_SLCR_ERR_AIBAXI_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003008U) ) + +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26 +#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23 +#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22 +#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAXI_IER + */ +#define LPD_SLCR_ERR_AIBAXI_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003010U) ) + +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26 +#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23 +#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22 +#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAXI_IDR + */ +#define LPD_SLCR_ERR_AIBAXI_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003018U) ) + +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26 +#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23 +#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22 +#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1 +#define LPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAPB_ISR + */ +#define LPD_SLCR_ERR_AIBAPB_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003020U) ) + +#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0 +#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1 +#define LPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAPB_IMR + */ +#define LPD_SLCR_ERR_AIBAPB_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003024U) ) + +#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0 +#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1 +#define LPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAPB_IER + */ +#define LPD_SLCR_ERR_AIBAPB_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003028U) ) + +#define LPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0 +#define LPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1 +#define LPD_SLCR_ERR_AIBAPB_IER_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_AIBAPB_IDR + */ +#define LPD_SLCR_ERR_AIBAPB_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000302CU) ) + +#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0 +#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1 +#define LPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAXI_REQ + */ +#define LPD_SLCR_ISO_AIBAXI_REQ ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003030U) ) + +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26 +#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23 +#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22 +#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAXI_TYPE + */ +#define LPD_SLCR_ISO_AIBAXI_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003038U) ) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26 +#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23 +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22 +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAXI_ACK + */ +#define LPD_SLCR_ISO_AIBAXI_ACK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003040U) ) + +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK ((u32)0X10000000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_SHIFT 27 +#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_LPD_DDR_MASK ((u32)0X08000000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26 +#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK ((u32)0X04000000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK ((u32)0X01000000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23 +#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK ((u32)0X00800000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22 +#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK ((u32)0X00400000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK ((u32)0X00080000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK ((u32)0X00040000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK ((u32)0X00020000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK ((u32)0X00000008U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK ((u32)0X00000004U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1 +#define LPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAPB_REQ + */ +#define LPD_SLCR_ISO_AIBAPB_REQ ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003048U) ) + +#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0 +#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1 +#define LPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAPB_TYPE + */ +#define LPD_SLCR_ISO_AIBAPB_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000304CU) ) + +#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0 +#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1 +#define LPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ISO_AIBAPB_ACK + */ +#define LPD_SLCR_ISO_AIBAPB_ACK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00003050U) ) + +#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0 +#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1 +#define LPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_ATB_ISR + */ +#define LPD_SLCR_ERR_ATB_ISR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006000U) ) + +#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1 +#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0 +#define LPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1 +#define LPD_SLCR_ERR_ATB_ISR_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_ATB_IMR + */ +#define LPD_SLCR_ERR_ATB_IMR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006004U) ) + +#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1 +#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0 +#define LPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IMR_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_ATB_IER + */ +#define LPD_SLCR_ERR_ATB_IER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006008U) ) + +#define LPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1 +#define LPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IER_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0 +#define LPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IER_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ERR_ATB_IDR + */ +#define LPD_SLCR_ERR_ATB_IDR ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000600CU) ) + +#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1 +#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0 +#define LPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1 +#define LPD_SLCR_ERR_ATB_IDR_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ATB_CMD_STORE_EN + */ +#define LPD_SLCR_ATB_CMD_STORE_EN ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006010U) ) + +#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1 +#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1 +#define LPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0 +#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1 +#define LPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ATB_RESP_EN + */ +#define LPD_SLCR_ATB_RESP_EN ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006014U) ) + +#define LPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1 +#define LPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1 +#define LPD_SLCR_ATB_RESP_EN_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0 +#define LPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1 +#define LPD_SLCR_ATB_RESP_EN_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ATB_RESP_TYPE + */ +#define LPD_SLCR_ATB_RESP_TYPE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006018U) ) + +#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1 +#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1 +#define LPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0 +#define LPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1 +#define LPD_SLCR_ATB_RESP_TYPE_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ATB_ERR_INJECT + */ +#define LPD_SLCR_ATB_ERR_INJECT ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000601CU) ) + +#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_SHIFT 1 +#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_WIDTH 1 +#define LPD_SLCR_ATB_ERR_INJECT_AFIFS2_MASK ((u32)0X00000002U) + +#define LPD_SLCR_ATB_ERR_INJECT_LPDM_SHIFT 0 +#define LPD_SLCR_ATB_ERR_INJECT_LPDM_WIDTH 1 +#define LPD_SLCR_ATB_ERR_INJECT_LPDM_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_ATB_PRESCALE + */ +#define LPD_SLCR_ATB_PRESCALE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00006020U) ) + +#define LPD_SLCR_ATB_PRESCALE_ENABLE_SHIFT 16 +#define LPD_SLCR_ATB_PRESCALE_ENABLE_WIDTH 1 +#define LPD_SLCR_ATB_PRESCALE_ENABLE_MASK ((u32)0X00010000U) + +#define LPD_SLCR_ATB_PRESCALE_VALUE_SHIFT 0 +#define LPD_SLCR_ATB_PRESCALE_VALUE_WIDTH 16 +#define LPD_SLCR_ATB_PRESCALE_VALUE_MASK ((u32)0X0000FFFFU) + +/** + * Register: LPD_SLCR_MUTEX0 + */ +#define LPD_SLCR_MUTEX0 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007000U) ) + +#define LPD_SLCR_MUTEX0_ID_SHIFT 0 +#define LPD_SLCR_MUTEX0_ID_WIDTH 32 +#define LPD_SLCR_MUTEX0_ID_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_MUTEX1 + */ +#define LPD_SLCR_MUTEX1 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007004U) ) + +#define LPD_SLCR_MUTEX1_ID_SHIFT 0 +#define LPD_SLCR_MUTEX1_ID_WIDTH 32 +#define LPD_SLCR_MUTEX1_ID_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_MUTEX2 + */ +#define LPD_SLCR_MUTEX2 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00007008U) ) + +#define LPD_SLCR_MUTEX2_ID_SHIFT 0 +#define LPD_SLCR_MUTEX2_ID_WIDTH 32 +#define LPD_SLCR_MUTEX2_ID_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_MUTEX3 + */ +#define LPD_SLCR_MUTEX3 ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000700CU) ) + +#define LPD_SLCR_MUTEX3_ID_SHIFT 0 +#define LPD_SLCR_MUTEX3_ID_WIDTH 32 +#define LPD_SLCR_MUTEX3_ID_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: LPD_SLCR_GICP0_IRQ_STATUS + */ +#define LPD_SLCR_GICP0_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008000U) ) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP0_IRQ_MASK + */ +#define LPD_SLCR_GICP0_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008004U) ) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP0_IRQ_ENABLE + */ +#define LPD_SLCR_GICP0_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008008U) ) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP0_IRQ_DISABLE + */ +#define LPD_SLCR_GICP0_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000800CU) ) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP0_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP0_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008010U) ) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP0_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP1_IRQ_STATUS + */ +#define LPD_SLCR_GICP1_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008014U) ) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP1_IRQ_MASK + */ +#define LPD_SLCR_GICP1_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008018U) ) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP1_IRQ_ENABLE + */ +#define LPD_SLCR_GICP1_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000801CU) ) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP1_IRQ_DISABLE + */ +#define LPD_SLCR_GICP1_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008020U) ) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP1_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP1_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008024U) ) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP1_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP2_IRQ_STATUS + */ +#define LPD_SLCR_GICP2_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008028U) ) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP2_IRQ_MASK + */ +#define LPD_SLCR_GICP2_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000802CU) ) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP2_IRQ_ENABLE + */ +#define LPD_SLCR_GICP2_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008030U) ) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP2_IRQ_DISABLE + */ +#define LPD_SLCR_GICP2_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008034U) ) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP2_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP2_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008038U) ) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP2_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP3_IRQ_STATUS + */ +#define LPD_SLCR_GICP3_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000803CU) ) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP3_IRQ_MASK + */ +#define LPD_SLCR_GICP3_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008040U) ) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP3_IRQ_ENABLE + */ +#define LPD_SLCR_GICP3_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008044U) ) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP3_IRQ_DISABLE + */ +#define LPD_SLCR_GICP3_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008048U) ) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP3_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP3_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000804CU) ) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP3_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP4_IRQ_STATUS + */ +#define LPD_SLCR_GICP4_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008050U) ) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP4_IRQ_MASK + */ +#define LPD_SLCR_GICP4_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008054U) ) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP4_IRQ_ENABLE + */ +#define LPD_SLCR_GICP4_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008058U) ) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP4_IRQ_DISABLE + */ +#define LPD_SLCR_GICP4_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000805CU) ) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP4_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP4_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008060U) ) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP4_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP5_IRQ_STATUS + */ +#define LPD_SLCR_GICP5_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008064U) ) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP5_IRQ_MASK + */ +#define LPD_SLCR_GICP5_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008068U) ) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP5_IRQ_ENABLE + */ +#define LPD_SLCR_GICP5_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000806CU) ) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP5_IRQ_DISABLE + */ +#define LPD_SLCR_GICP5_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008070U) ) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP5_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP5_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008074U) ) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP5_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP6_IRQ_STATUS + */ +#define LPD_SLCR_GICP6_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008078U) ) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP6_IRQ_MASK + */ +#define LPD_SLCR_GICP6_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000807CU) ) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP6_IRQ_ENABLE + */ +#define LPD_SLCR_GICP6_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008080U) ) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP6_IRQ_DISABLE + */ +#define LPD_SLCR_GICP6_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008084U) ) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP6_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP6_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008088U) ) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP6_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP7_IRQ_STATUS + */ +#define LPD_SLCR_GICP7_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000808CU) ) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_SHIFT 31 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_SHIFT 30 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_SHIFT 29 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_SHIFT 28 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_SHIFT 27 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_SHIFT 26 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_SHIFT 25 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_SHIFT 24 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_SHIFT 23 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_SHIFT 22 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_SHIFT 21 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_SHIFT 20 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_SHIFT 19 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_SHIFT 18 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_SHIFT 17 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_SHIFT 16 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_SHIFT 15 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_SHIFT 14 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_SHIFT 13 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_SHIFT 12 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_SHIFT 11 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_SHIFT 10 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_SHIFT 9 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_SHIFT 8 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP7_IRQ_MASK + */ +#define LPD_SLCR_GICP7_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008090U) ) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_SHIFT 31 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_SHIFT 30 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_SHIFT 29 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_SHIFT 28 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_SHIFT 27 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_SHIFT 26 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_SHIFT 25 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_SHIFT 24 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_SHIFT 23 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_SHIFT 22 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_SHIFT 21 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_SHIFT 20 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_SHIFT 19 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_SHIFT 18 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_SHIFT 17 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_SHIFT 16 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_SHIFT 15 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_SHIFT 14 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_SHIFT 13 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_SHIFT 12 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_SHIFT 11 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_SHIFT 10 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_SHIFT 9 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_SHIFT 8 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP7_IRQ_ENABLE + */ +#define LPD_SLCR_GICP7_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008094U) ) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP7_IRQ_DISABLE + */ +#define LPD_SLCR_GICP7_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00008098U) ) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_SHIFT 31 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_SHIFT 30 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_SHIFT 29 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_SHIFT 28 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_SHIFT 27 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_SHIFT 26 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_SHIFT 25 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_SHIFT 24 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_SHIFT 23 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_SHIFT 22 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_SHIFT 21 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_SHIFT 20 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_SHIFT 19 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_SHIFT 18 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_SHIFT 17 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_SHIFT 16 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_SHIFT 15 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_SHIFT 14 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_SHIFT 13 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_SHIFT 12 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_SHIFT 11 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_SHIFT 10 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_SHIFT 9 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_SHIFT 8 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP7_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP7_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000809CU) ) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_SHIFT 31 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC31_MASK ((u32)0X80000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_SHIFT 30 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC30_MASK ((u32)0X40000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_SHIFT 29 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC29_MASK ((u32)0X20000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_SHIFT 28 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC28_MASK ((u32)0X10000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_SHIFT 27 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC27_MASK ((u32)0X08000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_SHIFT 26 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC26_MASK ((u32)0X04000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_SHIFT 25 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC25_MASK ((u32)0X02000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_SHIFT 24 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC24_MASK ((u32)0X01000000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_SHIFT 23 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC23_MASK ((u32)0X00800000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_SHIFT 22 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC22_MASK ((u32)0X00400000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_SHIFT 21 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC21_MASK ((u32)0X00200000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_SHIFT 20 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC20_MASK ((u32)0X00100000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_SHIFT 19 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC19_MASK ((u32)0X00080000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_SHIFT 18 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC18_MASK ((u32)0X00040000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_SHIFT 17 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC17_MASK ((u32)0X00020000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_SHIFT 16 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC16_MASK ((u32)0X00010000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_SHIFT 15 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC15_MASK ((u32)0X00008000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_SHIFT 14 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC14_MASK ((u32)0X00004000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_SHIFT 13 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC13_MASK ((u32)0X00002000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_SHIFT 12 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC12_MASK ((u32)0X00001000U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_SHIFT 11 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC11_MASK ((u32)0X00000800U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_SHIFT 10 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC10_MASK ((u32)0X00000400U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_SHIFT 9 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC9_MASK ((u32)0X00000200U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_SHIFT 8 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC8_MASK ((u32)0X00000100U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP7_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP_PMU_IRQ_STATUS + */ +#define LPD_SLCR_GICP_PMU_IRQ_STATUS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A0U) ) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_SHIFT 7 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_SHIFT 6 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_SHIFT 5 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_SHIFT 4 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_SHIFT 3 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_SHIFT 2 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_SHIFT 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_SHIFT 0 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_STATUS_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP_PMU_IRQ_MASK + */ +#define LPD_SLCR_GICP_PMU_IRQ_MASK ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A4U) ) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_SHIFT 7 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_SHIFT 6 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_SHIFT 5 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_SHIFT 4 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_SHIFT 3 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_SHIFT 2 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_SHIFT 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_SHIFT 0 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_MASK_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP_PMU_IRQ_ENABLE + */ +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080A8U) ) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_ENABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP_PMU_IRQ_DISABLE + */ +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080ACU) ) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_SHIFT 7 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_SHIFT 6 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_SHIFT 5 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_SHIFT 4 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_SHIFT 3 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_SHIFT 2 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_SHIFT 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_SHIFT 0 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_DISABLE_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_GICP_PMU_IRQ_TRIGGER + */ +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER ( ( LPD_SLCR_BASEADDR ) + ((u32)0X000080B0U) ) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_SHIFT 7 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC7_MASK ((u32)0X00000080U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_SHIFT 6 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC6_MASK ((u32)0X00000040U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_SHIFT 5 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_SHIFT 4 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_SHIFT 3 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_SHIFT 2 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_SHIFT 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_SHIFT 0 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_WIDTH 1 +#define LPD_SLCR_GICP_PMU_IRQ_TRIGGER_SRC0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_AFI_FS + */ +#define LPD_SLCR_AFI_FS ( ( LPD_SLCR_BASEADDR ) + ((u32)0X00009000U) ) + +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK ((u32)0X00000300U) + +/** + * Register: LPD_SLCR_LPD_CCI + */ +#define LPD_SLCR_LPD_CCI ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A000U) ) + +#define LPD_SLCR_LPD_CCI_SPARE_SHIFT 28 +#define LPD_SLCR_LPD_CCI_SPARE_WIDTH 4 +#define LPD_SLCR_LPD_CCI_SPARE_MASK ((u32)0XF0000000U) + +#define LPD_SLCR_LPD_CCI_QVNVNETS4_SHIFT 27 +#define LPD_SLCR_LPD_CCI_QVNVNETS4_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNVNETS4_MASK ((u32)0X08000000U) + +#define LPD_SLCR_LPD_CCI_QVNVNETS3_SHIFT 26 +#define LPD_SLCR_LPD_CCI_QVNVNETS3_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNVNETS3_MASK ((u32)0X04000000U) + +#define LPD_SLCR_LPD_CCI_QVNVNETS2_SHIFT 25 +#define LPD_SLCR_LPD_CCI_QVNVNETS2_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNVNETS2_MASK ((u32)0X02000000U) + +#define LPD_SLCR_LPD_CCI_QVNVNETS1_SHIFT 24 +#define LPD_SLCR_LPD_CCI_QVNVNETS1_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNVNETS1_MASK ((u32)0X01000000U) + +#define LPD_SLCR_LPD_CCI_QVNVNETS0_SHIFT 23 +#define LPD_SLCR_LPD_CCI_QVNVNETS0_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNVNETS0_MASK ((u32)0X00800000U) + +#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_SHIFT 18 +#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_WIDTH 5 +#define LPD_SLCR_LPD_CCI_QOSOVERRIDE_MASK ((u32)0X007C0000U) + +#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_SHIFT 17 +#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNENABLE_M2_MASK ((u32)0X00020000U) + +#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_SHIFT 16 +#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_WIDTH 1 +#define LPD_SLCR_LPD_CCI_QVNENABLE_M1_MASK ((u32)0X00010000U) + +#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_SHIFT 13 +#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_WIDTH 3 +#define LPD_SLCR_LPD_CCI_STRIPING_GRANULE_MASK ((u32)0X0000E000U) + +#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_SHIFT 12 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN4_MASK ((u32)0X00001000U) + +#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_SHIFT 11 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN3_MASK ((u32)0X00000800U) + +#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_SHIFT 10 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ACCHANNELEN0_MASK ((u32)0X00000400U) + +#define LPD_SLCR_LPD_CCI_ECOREVNUM_SHIFT 6 +#define LPD_SLCR_LPD_CCI_ECOREVNUM_WIDTH 4 +#define LPD_SLCR_LPD_CCI_ECOREVNUM_MASK ((u32)0X000003C0U) + +#define LPD_SLCR_LPD_CCI_ASA2_SHIFT 5 +#define LPD_SLCR_LPD_CCI_ASA2_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ASA2_MASK ((u32)0X00000020U) + +#define LPD_SLCR_LPD_CCI_ASA1_SHIFT 4 +#define LPD_SLCR_LPD_CCI_ASA1_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ASA1_MASK ((u32)0X00000010U) + +#define LPD_SLCR_LPD_CCI_ASA0_SHIFT 3 +#define LPD_SLCR_LPD_CCI_ASA0_WIDTH 1 +#define LPD_SLCR_LPD_CCI_ASA0_MASK ((u32)0X00000008U) + +#define LPD_SLCR_LPD_CCI_OWO2_SHIFT 2 +#define LPD_SLCR_LPD_CCI_OWO2_WIDTH 1 +#define LPD_SLCR_LPD_CCI_OWO2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_LPD_CCI_OWO1_SHIFT 1 +#define LPD_SLCR_LPD_CCI_OWO1_WIDTH 1 +#define LPD_SLCR_LPD_CCI_OWO1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_LPD_CCI_OWO0_SHIFT 0 +#define LPD_SLCR_LPD_CCI_OWO0_WIDTH 1 +#define LPD_SLCR_LPD_CCI_OWO0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_LPD_CCI_ADDRMAP + */ +#define LPD_SLCR_LPD_CCI_ADDRMAP ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A004U) ) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_15_SHIFT 30 +#define LPD_SLCR_LPD_CCI_ADDRMAP_15_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_15_MASK ((u32)0XC0000000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_14_SHIFT 28 +#define LPD_SLCR_LPD_CCI_ADDRMAP_14_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_14_MASK ((u32)0X30000000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_13_SHIFT 26 +#define LPD_SLCR_LPD_CCI_ADDRMAP_13_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_13_MASK ((u32)0X0C000000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_12_SHIFT 24 +#define LPD_SLCR_LPD_CCI_ADDRMAP_12_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_12_MASK ((u32)0X03000000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_11_SHIFT 22 +#define LPD_SLCR_LPD_CCI_ADDRMAP_11_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_11_MASK ((u32)0X00C00000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_10_SHIFT 20 +#define LPD_SLCR_LPD_CCI_ADDRMAP_10_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_10_MASK ((u32)0X00300000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_9_SHIFT 18 +#define LPD_SLCR_LPD_CCI_ADDRMAP_9_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_9_MASK ((u32)0X000C0000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_8_SHIFT 16 +#define LPD_SLCR_LPD_CCI_ADDRMAP_8_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_8_MASK ((u32)0X00030000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_7_SHIFT 14 +#define LPD_SLCR_LPD_CCI_ADDRMAP_7_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_7_MASK ((u32)0X0000C000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_6_SHIFT 12 +#define LPD_SLCR_LPD_CCI_ADDRMAP_6_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_6_MASK ((u32)0X00003000U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_5_SHIFT 10 +#define LPD_SLCR_LPD_CCI_ADDRMAP_5_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_5_MASK ((u32)0X00000C00U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_4_SHIFT 8 +#define LPD_SLCR_LPD_CCI_ADDRMAP_4_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_4_MASK ((u32)0X00000300U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_3_SHIFT 6 +#define LPD_SLCR_LPD_CCI_ADDRMAP_3_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_3_MASK ((u32)0X000000C0U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_2_SHIFT 4 +#define LPD_SLCR_LPD_CCI_ADDRMAP_2_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_2_MASK ((u32)0X00000030U) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_1_SHIFT 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_1_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_1_MASK ((u32)0X0000000CU) + +#define LPD_SLCR_LPD_CCI_ADDRMAP_0_SHIFT 0 +#define LPD_SLCR_LPD_CCI_ADDRMAP_0_WIDTH 2 +#define LPD_SLCR_LPD_CCI_ADDRMAP_0_MASK ((u32)0X00000003U) + +/** + * Register: LPD_SLCR_LPD_CCI_QVNPREALLOC + */ +#define LPD_SLCR_LPD_CCI_QVNPREALLOC ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A008U) ) + +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_SHIFT 20 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_WIDTH 4 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM2_MASK ((u32)0X00F00000U) + +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_SHIFT 16 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_WIDTH 4 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_WM1_MASK ((u32)0X000F0000U) + +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_SHIFT 8 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_WIDTH 4 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM2_MASK ((u32)0X00000F00U) + +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_SHIFT 4 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_WIDTH 4 +#define LPD_SLCR_LPD_CCI_QVNPREALLOC_RM1_MASK ((u32)0X000000F0U) + +/** + * Register: LPD_SLCR_LPD_SMMU + */ +#define LPD_SLCR_LPD_SMMU ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A020U) ) + +#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_SHIFT 7 +#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_INTEG_SEC_OVERRIDE_MASK ((u32)0X00000080U) + +#define LPD_SLCR_LPD_SMMU_CTTW_SHIFT 6 +#define LPD_SLCR_LPD_SMMU_CTTW_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_CTTW_MASK ((u32)0X00000040U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_SHIFT 5 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU5_MASK ((u32)0X00000020U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_SHIFT 4 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU4_MASK ((u32)0X00000010U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_SHIFT 3 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU3_MASK ((u32)0X00000008U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_SHIFT 2 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU2_MASK ((u32)0X00000004U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_SHIFT 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU1_MASK ((u32)0X00000002U) + +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_SHIFT 0 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_WIDTH 1 +#define LPD_SLCR_LPD_SMMU_SYSBARDISABLE_TBU0_MASK ((u32)0X00000001U) + +/** + * Register: LPD_SLCR_LPD_APU + */ +#define LPD_SLCR_LPD_APU ( ( LPD_SLCR_BASEADDR ) + ((u32)0X0000A040U) ) + +#define LPD_SLCR_LPD_APU_BRDC_BARRIER_SHIFT 3 +#define LPD_SLCR_LPD_APU_BRDC_BARRIER_WIDTH 1 +#define LPD_SLCR_LPD_APU_BRDC_BARRIER_MASK ((u32)0X00000008U) + +#define LPD_SLCR_LPD_APU_BRDC_CMNT_SHIFT 2 +#define LPD_SLCR_LPD_APU_BRDC_CMNT_WIDTH 1 +#define LPD_SLCR_LPD_APU_BRDC_CMNT_MASK ((u32)0X00000004U) + +#define LPD_SLCR_LPD_APU_BRDC_INNER_SHIFT 1 +#define LPD_SLCR_LPD_APU_BRDC_INNER_WIDTH 1 +#define LPD_SLCR_LPD_APU_BRDC_INNER_MASK ((u32)0X00000002U) + +#define LPD_SLCR_LPD_APU_BRDC_OUTER_SHIFT 0 +#define LPD_SLCR_LPD_APU_BRDC_OUTER_WIDTH 1 +#define LPD_SLCR_LPD_APU_BRDC_OUTER_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _LPD_SLCR_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/lscript.ld b/lib/sw_apps/zynqmp_pmufw/src/lscript.ld index b8fddd51..993f3208 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/lscript.ld +++ b/lib/sw_apps/zynqmp_pmufw/src/lscript.ld @@ -36,7 +36,7 @@ _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000; MEMORY { - /* This setting considers entire RAM. ROM entitiesare not considered */ + /* This setting considers entire RAM. ROM entities are not considered */ PMU_RAM : ORIGIN = 0xFFDC0000, LENGTH = 0x0001FF00 /* 128KB - _PERSISTENT256 */ } @@ -52,18 +52,17 @@ SECTIONS KEEP (*(.vectors.reset)) } > PMU_RAM -/* Only Reset vector is initialized. Other vectors are all zeros */ - .vectors.sw_exception 0xFFDC0008 : { - FILL(0x00000000); + KEEP (*(.vectors.sw_exception)) } > PMU_RAM .vectors.interrupt 0xFFDC0010 : { - FILL(0x00000000) + KEEP (*(.vectors.interrupt)) } > PMU_RAM .vectors.hw_exception 0xFFDC0020 : { - FILL(0x00000000) + KEEP (*(.vectors.hw_exception)) + _MB_RESERVED_START = .; } > PMU_RAM .text 0xFFDC0050: { @@ -170,3 +169,117 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); _end = .; } + +XpbrACPU0SleepHandler = 0xffd00f98; +XpbrACPU0WakeHandler = 0xffd00d4c; +XpbrACPU1SleepHandler = 0xffd00fbc; +XpbrACPU1WakeHandler = 0xffd00d70; +XpbrACPU2SleepHandler = 0xffd00fe0; +XpbrACPU2WakeHandler = 0xffd00d94; +XpbrACPU3SleepHandler = 0xffd01004; +XpbrACPU3WakeHandler = 0xffd00db8; +XpbrCsuSecureLockdownHandler = 0xffd01e60; +XpbrDapFpdWakeHandler = 0xffd01c70; +XpbrDapRpuWakeHandler = 0xffd01cd8; +XpbrDefaultWakeHandler = 0xffd036d0; +XpbrFpdGicProxyWakeHandler = 0xffd00f04; +XpbrFPIsolationReqHandler = 0xffd01518; +XpbrFPLockIsoHandler = 0xffd0156c; +XpbrGpi1Router = 0xffd038ac; +XpbrGpi2Router = 0xffd03960; +XpbrGpi3Handler = 0xffd00d30; +XpbrHwExceptionHandler = 0xffd03d6c; +XpbrHwRstReqHandler = 0xffd01be0; +XpbrIpi0Handler = 0xffd00cf4; +XpbrIsoReqRouter = 0xffd03b94; +XpbrMio0WakeHandler = 0xffd00e5c; +XpbrMio1WakeHandler = 0xffd00e78; +XpbrMio2WakeHandler = 0xffd00e94; +XpbrMio3WakeHandler = 0xffd00eb0; +XpbrMio4WakeHandler = 0xffd00ecc; +XpbrMio5WakeHandler = 0xffd00ee8; +XpbrNullInterruptHandler = 0xffd03d8c; +XpbrNullServiceHandler = 0xffd020e0; +XpbrPLIsolationReqHandler = 0xffd01534; +XpbrPLNonPCAPIsoReqHandler = 0xffd01550; +XpbrPwrDnACPU0Handler = 0xffd0158c; +XpbrPwrDnACPU1Handler = 0xffd015b0; +XpbrPwrDnACPU2Handler = 0xffd015d4; +XpbrPwrDnACPU3Handler = 0xffd015f8; +XpbrPwrDnFpdHandler = 0xffd01814; +XpbrPwrDnGpuHandler = 0xffd0184c; +XpbrPwrDnL2Bank0Handler = 0xffd01664; +XpbrPwrDnOcmBank0Handler = 0xffd0173c; +XpbrPwrDnOcmBank1Handler = 0xffd01760; +XpbrPwrDnOcmBank2Handler = 0xffd01784; +XpbrPwrDnOcmBank3Handler = 0xffd017a8; +XpbrPwrDnPldHandler = 0xffd01830; +XpbrPwrDnPp0Handler = 0xffd0161c; +XpbrPwrDnPp1Handler = 0xffd01640; +XpbrPwrDnR50Handler = 0xffd01878; +XpbrPwrDnR51Handler = 0xffd01894; +XpbrPwrDnReqRouter = 0xffd03ad4; +XpbrPwrDnRpuHandler = 0xffd01688; +XpbrPwrDnTcm0AHandler = 0xffd016ac; +XpbrPwrDnTcm0BHandler = 0xffd016d0; +XpbrPwrDnTcm1AHandler = 0xffd016f4; +XpbrPwrDnTcm1BHandler = 0xffd01718; +XpbrPwrDnUsb0Handler = 0xffd017cc; +XpbrPwrDnUsb1Handler = 0xffd017f0; +XpbrPwrUpACPU0Handler = 0xffd018b0; +XpbrPwrUpACPU1Handler = 0xffd018d4; +XpbrPwrUpACPU2Handler = 0xffd018f8; +XpbrPwrUpACPU3Handler = 0xffd0191c; +XpbrPwrUpFpdHandler = 0xffd01b38; +XpbrPwrUpL2Bank0Handler = 0xffd01988; +XpbrPwrUpOcmBank0Handler = 0xffd01a60; +XpbrPwrUpOcmBank1Handler = 0xffd01a84; +XpbrPwrUpOcmBank2Handler = 0xffd01aa8; +XpbrPwrUpOcmBank3Handler = 0xffd01acc; +XpbrPwrUpPldHandler = 0xffd01b54; +XpbrPwrUpPp0Handler = 0xffd01940; +XpbrPwrUpPp1Handler = 0xffd01964; +XpbrPwrUpReqRouter = 0xffd03a14; +XpbrPwrUpRpuHandler = 0xffd019ac; +XpbrPwrUpTcm0AHandler = 0xffd019d0; +XpbrPwrUpTcm0BHandler = 0xffd019f4; +XpbrPwrUpTcm1AHandler = 0xffd01a18; +XpbrPwrUpTcm1BHandler = 0xffd01a3c; +XpbrPwrUpUsb0Handler = 0xffd01af0; +XpbrPwrUpUsb1Handler = 0xffd01b14; +XpbrR50SleepHandler = 0xffd01028; +XpbrR50WakeHandler = 0xffd00ddc; +XpbrR51SleepHandler = 0xffd0104c; +XpbrR51WakeHandler = 0xffd00e00; +XpbrROMExceptionHandler = 0xffd03d14; +XpbrRstACPU0Handler = 0xffd01124; +XpbrRstACPU1Handler = 0xffd01158; +XpbrRstACPU2Handler = 0xffd0118c; +XpbrRstACPU3Handler = 0xffd011c0; +XpbrRstACPUxHandler = 0xffd01070; +XpbrRstApuHandler = 0xffd01d48; +XpbrRstDisplayPortHandler = 0xffd0131c; +XpbrRstFpdHandler = 0xffd014e8; +XpbrRstGem0Handler = 0xffd013b8; +XpbrRstGem1Handler = 0xffd013e4; +XpbrRstGem2Handler = 0xffd01410; +XpbrRstGem3Handler = 0xffd0143c; +XpbrRstGpuHandler = 0xffd011f4; +XpbrRstLsRpuHandler = 0xffd01dac; +XpbrRstPCIeHandler = 0xffd012b4; +XpbrRstPp0Handler = 0xffd0123c; +XpbrRstPp1Handler = 0xffd01278; +XpbrRstPsOnlyHandler = 0xffd014c0; +XpbrRstR50Handler = 0xffd01350; +XpbrRstR51Handler = 0xffd01384; +XpbrRstSataHandler = 0xffd012e8; +XpbrRstUsb0Handler = 0xffd01468; +XpbrRstUsb1Handler = 0xffd01494; +XpbrRtcAlarmHandler = 0xffd00d14; +XpbrServiceHandler = 0xffd03dfc; +XpbrServiceMode = 0xffd01b70; +XpbrSwExceptionHandler = 0xffd03d7c; +XpbrSwRstReqRouter = 0xffd03c54; +XpbrTMRFaultDetectionHandler = 0xffd00cec; +XpbrUsb0WakeHandler = 0xffd00e24; +XpbrUsb1WakeHandler = 0xffd00e40; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_api.c b/lib/sw_apps/zynqmp_pmufw/src/pm_api.c new file mode 100644 index 00000000..3a6c68c2 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_api.c @@ -0,0 +1,298 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * PM API calls definitions: api ids, arguments and functions used for + * checking correctness of API calls received through IPI. + * Every implemented PM API must have its entry in pm_api_table. + * Whenever a PM request is made, PMU PM compares the arguments read + * from IPI buffer, against the definition in PM API table defined in + * this file. + *********************************************************************/ + +#include "pm_api.h" +#include "pm_defs.h" + +static const PmApiEntry pmApiTable[] = { + { + .apiId = PM_SELF_SUSPEND, + .argTypes = { ARG_NODE, ARG_LATENCY, ARG_STATE, ARG_UNDEF } + }, { + .apiId = PM_REQUEST_SUSPEND, + .argTypes = { ARG_NODE, ARG_ACK, ARG_LATENCY, ARG_STATE } + }, { + .apiId = PM_FORCE_POWERDOWN, + .argTypes = { ARG_NODE, ARG_ACK, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_ABORT_SUSPEND, + .argTypes = { ARG_ABORT_REASON, ARG_NODE, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_REQUEST_WAKEUP, + .argTypes = { ARG_NODE, ARG_ACK, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_SET_WAKEUP_SOURCE, + .argTypes = { ARG_NODE, ARG_NODE, ARG_ENABLE, ARG_UNDEF } + }, { + .apiId = PM_SYSTEM_SHUTDOWN, + .argTypes = { ARG_RESTART, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_REQUEST_NODE, + .argTypes = { ARG_NODE, ARG_CAPABILITIES, ARG_QOS, ARG_ACK } + }, { + .apiId = PM_RELEASE_NODE, + .argTypes = { ARG_NODE, ARG_LATENCY, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_SET_REQUIREMENT, + .argTypes = {ARG_NODE, ARG_CAPABILITIES, ARG_QOS, ARG_ACK } + }, { + .apiId = PM_SET_MAX_LATENCY, + .argTypes = {ARG_NODE, ARG_LATENCY, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_GET_API_VERSION, + .argTypes = { ARG_UNDEF, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_SET_CONFIGURATION, + .argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_GET_NODE_STATUS, + .argTypes = { ARG_NODE, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_GET_OP_CHARACTERISTIC, + .argTypes = { ARG_NODE, ARG_OP_CH_TYPE, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_REGISTER_NOTIFIER, + .argTypes = { ARG_NODE, ARG_EVENT_ID, ARG_WAKE, ARG_ENABLE } + }, { + .apiId = PM_CLOCK_REQUEST, + .argTypes = { ARG_UINT32, ARG_UINT32, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_CLOCK_RELEASE, + .argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_CLOCK_GET_RATE, + .argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_RESET_ASSERT, + .argTypes = { ARG_UINT32, ARG_UINT32, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_RESET_GET_STATUS, + .argTypes = { ARG_UINT32, ARG_UNDEF, ARG_UNDEF, ARG_UNDEF } + }, { + .apiId = PM_MMIO_WRITE, + .argTypes = { ARG_UINT32, ARG_UINT32, ARG_UINT32, ARG_UNDEF } + }, { + .apiId = PM_MMIO_READ, + .argTypes = { ARG_UINT32, ARG_UINT32, ARG_UNDEF, ARG_UNDEF } + }, +}; + +/** + * PmIsApiIdValid() - Check whether the given api id is within regular range + * @api PM API call id + * + * @return True if api id is within supported api ids range, false otherwise + */ +bool PmIsApiIdValid(const u32 api) +{ + return (api >= PM_API_MIN) && (api <= PM_API_MAX); +} + +/** + * PmCheckArgument() - API argument checking + * @argType Argument type + * @arg Argument to be checked + * + * @return Status, either OK or ERR_ + */ +static PmPayloadStatus PmCheckArgument(const u8 argType, + const u32 arg) +{ + PmPayloadStatus status = PM_PAYLOAD_OK; + + switch (argType) { + case ARG_NODE: + if ((arg < NODE_MIN) || (arg > NODE_MAX)) { + status = PM_PAYLOAD_ERR_NODE; + } + break; + case ARG_ACK: + if ((arg < REQUEST_ACK_MIN) || (arg > REQUEST_ACK_MAX)) { + status = PM_PAYLOAD_ERR_ACK; + } + break; + case ARG_ABORT_REASON: + if ((arg < ABORT_REASON_MIN) || (arg > ABORT_REASON_MAX)) { + status = PM_PAYLOAD_ERR_ABORT_REASON; + } + break; + case ARG_SUSPEND_REASON: + if ((arg < SUSPEND_REASON_MIN) || (arg > SUSPEND_REASON_MAX)) { + status = PM_PAYLOAD_ERR_SUSPEND_REASON; + } + break; + case ARG_QOS: + if (arg > MAX_QOS) { + status = PM_PAYLOAD_ERR_QOS; + } + break; + case ARG_WAKE: + if (arg != 1 && arg != 0) { + status = PM_PAYLOAD_ERR_WAKE; + } + break; + case ARG_ENABLE: + if (arg != 1 && arg != 0) { + status = PM_PAYLOAD_ERR_ENABLE; + } + break; + case ARG_CAPABILITIES: + case ARG_OP_CH_TYPE: + case ARG_STATE: + case ARG_EVENT_ID: + case ARG_CLOCK: + case ARG_RESET: + case ARG_LATENCY: + case ARG_UINT32: + break; + default: + status = PM_PAYLOAD_ERR_UNKNOWN; + break; + } + + return status; +} + +/** + * PmCheckPayloadArgs() - Check for payload correctness (are provided values + * within expected range) + * @entry PM API call entry with the expected argument definitions + * @args PM API call arguments + * + * @return Status, either OK or ERR_ + */ +static PmPayloadStatus PmCheckPayloadArgs(const PmApiEntry* entry, + const u32 args[PAYLOAD_API_ARGS_CNT]) +{ + u8 i; + PmPayloadStatus status = PM_PAYLOAD_OK; + + for (i = 0U; i < PAYLOAD_API_ARGS_CNT; i++) { + /* if not an argument don't check anymore, return ok */ + if (ARG_UNDEF == entry->argTypes[i]) { + status = PM_PAYLOAD_OK; + goto done; + } + + /* check i-th argument */ + status = PmCheckArgument(entry->argTypes[i], args[i]); + if (PM_PAYLOAD_OK != status) { + /* return when argument is invalid */ + goto done; + } + } + +done: + /* all arguments are ok */ + return status; +} + +/** + * PmCheckPayload() - Check payload read from IPI buffer + * @args Array of argument values read from IPI buffer (the payload) + * + * @return Status of the performed check: OK or ERR_ + */ +PmPayloadStatus PmCheckPayload(const u32 args[PAYLOAD_ELEM_CNT]) +{ + u32 i; + PmPayloadStatus ret; + const PmApiEntry* entry = NULL; + bool status = PmIsApiIdValid(args[0]); + + if (false == status) { + ret = PM_PAYLOAD_ERR_API_ID; + goto done; + } + + for (i = 0U; i < ARRAY_SIZE(pmApiTable); i++) { + if (args[0] == pmApiTable[i].apiId) { + entry = &pmApiTable[i]; + break; + } + } + + if (NULL == entry) { + ret = PM_PAYLOAD_ERR_API_ID; + goto done; + } + + ret = PmCheckPayloadArgs(entry, &args[1]); + +done: + return ret; +} + +/** + * PmRequestAcknowledge() - check whether this API call requires acknowledge + * @args Array of argument values read from IPI buffer (the payload) + * + * @return Extracted acknowledge argument from payload, if payload does not + * contain acknowledge argument (because of APIs call declaration), + * return REQUEST_ACK_NO + */ +u32 PmRequestAcknowledge(const u32 args[PAYLOAD_ELEM_CNT]) +{ + u32 i; + u32 ack = REQUEST_ACK_NO; + const PmApiEntry* entry = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmApiTable); i++) { + if (args[0] == pmApiTable[i].apiId) { + entry = &pmApiTable[i]; + break; + } + } + + if (NULL == entry) { + goto done; + } + + for (i = 1U; i < PAYLOAD_ELEM_CNT; i++) { + if (ARG_ACK == entry->argTypes[i - 1]) { + ack = args[i]; + break; + } + } + +done: + return ack; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_api.h b/lib/sw_apps/zynqmp_pmufw/src/pm_api.h new file mode 100644 index 00000000..1335b437 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_api.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions needed to check correctness of PM API call + * (payload against api id, ranges of arguments, etc.) + * Every new API call must have its pm_api_entry with the definition + * of argument types, otherwise it will be considered irregular. + *********************************************************************/ + +#ifndef PM_API_H_ +#define PM_API_H_ + +#include "pm_common.h" + +/********************************************************************* + * Macro definitions + ********************************************************************/ +/* One (first) u32 is used for API call id coding */ +#define PAYLOAD_API_ID 1U + +/* Each API can have up to 4 arguments */ +#define PAYLOAD_API_ARGS_CNT 4U + +/* Number of payload elements (api id and api's arguments) */ +#define PAYLOAD_ELEM_CNT (PAYLOAD_API_ID + PAYLOAD_API_ARGS_CNT) + +/* Payload element size in bytes */ +#define PAYLOAD_ELEM_SIZE 4U + +#define ARG_UNDEF 0U +#define ARG_NODE 1U +#define ARG_ACK 2U +#define ARG_ABORT_REASON 3U +#define ARG_SUSPEND_REASON 4U +#define ARG_CAPABILITIES 5U +#define ARG_OP_CH_TYPE 6U +#define ARG_STATE 7U +#define ARG_QOS 8U +#define ARG_EVENT_ID 9U +#define ARG_CLOCK 10U +#define ARG_RESET 11U +#define ARG_LATENCY 12U +#define ARG_UINT32 13U +#define ARG_WAKE 14U +#define ARG_ENABLE 15U +#define ARG_RESTART 16U + +/********************************************************************* + * Enum definitions + ********************************************************************/ +typedef enum { + PM_PAYLOAD_OK, + PM_PAYLOAD_ERR_API_ID, + PM_PAYLOAD_ERR_NODE, + PM_PAYLOAD_ERR_ACK, + PM_PAYLOAD_ERR_ABORT_REASON, + PM_PAYLOAD_ERR_SUSPEND_REASON, + PM_PAYLOAD_ERR_CAPABILITIES, + PM_PAYLOAD_ERR_OP_CH_TYPE, + PM_PAYLOAD_ERR_STATE, + PM_PAYLOAD_ERR_QOS, + PM_PAYLOAD_ERR_EVENT_ID, + PM_PAYLOAD_ERR_CLOCK, + PM_PAYLOAD_ERR_RESET, + PM_PAYLOAD_ERR_LATENCY, + PM_PAYLOAD_ERR_WAKE, + PM_PAYLOAD_ERR_ENABLE, + PM_PAYLOAD_ERR_RESTART, + PM_PAYLOAD_ERR_UNKNOWN, +} PmPayloadStatus; + +/********************************************************************* + * Structure definitions + ********************************************************************/ +typedef struct { + const u8 apiId; + const u8 argTypes[PAYLOAD_API_ARGS_CNT]; +} PmApiEntry; + +/********************************************************************* + * Function declarations + ********************************************************************/ +bool PmIsApiIdValid(const u32 api); +u32 PmRequestAcknowledge(const u32 args[PAYLOAD_ELEM_CNT]); +PmPayloadStatus PmCheckPayload(const u32 args[PAYLOAD_ELEM_CNT]); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_binding.c b/lib/sw_apps/zynqmp_pmufw/src/pm_binding.c new file mode 100644 index 00000000..f59265ae --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_binding.c @@ -0,0 +1,216 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Implementations of the functions to be used for integrating power + * management (PM) within PMU firmware. + *********************************************************************/ + +#include "pm_binding.h" +#include "pm_api.h" +#include "pm_defs.h" +#include "pm_common.h" +#include "pm_proc.h" +#include "pm_core.h" +#include "ipi_buffer.h" + +/** + * XPfw_PmInit() - initializes PM firmware + * + * @note Call on startup after XPfw_PmSetConfiguration to initialize PM + * firmware. It is assumed that PMU firmware enables GPI1, GPI2, and + * IPI0 interrupts at the processor level, so PMU only masks/unmasks + * specific events. + */ +void XPfw_PmInit(void) +{ + PmDbg("Power Management Init\n"); + /* Disable all wake requests in GPI1 */ + DISABLE_WAKE(PMU_IOMODULE_GPI1_WAKES_ALL_MASK); + /* Disable all wfi requests in GPI2 */ + DISABLE_WFI(PMU_LOCAL_GPI2_ENABLE_ALL_PWRDN_REQ_MASK); + /* Enable all IPI interrupts so masters' requests can be received */ + PmEnableAllMasterIpis(); +} + +/** + * XPfw_PmIpiHandler() - Call from IPI interrupt handler to process PM API call + * @isrMask IPI's ISR register value. Needed to determine buffer holding the + * payload + * @apiId PM API id that was read from master's IPI buffer and validated as + * existing + * + * @note Call from IPI#0 interrupt routine. IPI's #0 interrupt can be used + * for some other purposes, not only for PM, and in #0 interrupt + * routine must : + * 1. Read ISR register before calling this function + * 2. Determine master requestor and accordingly read first 32b + * argument from master's IPI buffer. Determine is it PM API. + * If yes, this function is called. + * 3. Write into ISR register after this function returns. + * Write to ISR clears interrupt in IPI peripheral. Interrupt must + * be cleared after this function returns to make PM API call + * atomic. + */ +void XPfw_PmIpiHandler(const u32 isrMask, + const u32 apiId) +{ + u32 i; + u32 payload[PAYLOAD_ELEM_CNT]; + u32 bufferBase; + u32 offset = 0U; + const PmMaster* master = PmGetMasterByIpiMask(isrMask); + + if (NULL == master) { + /* Never happens if IPI interrupt routine is implemented correctly */ + PmDbg("%s ERROR: IPI source not supported %d\n", __func__, isrMask); + goto done; + } + + /* Already have first argument (apiId) */ + payload[0] = apiId; + bufferBase = master->buffer + IPI_BUFFER_REQ_OFFSET; + for (i = 1U; i < PAYLOAD_ELEM_CNT; i++) { + offset += PAYLOAD_ELEM_SIZE; + payload[i] = XPfw_Read32(bufferBase + offset); + } + + PmProcessRequest(master, payload); + +done: + return; +} + +/** + * XPfw_PmWfiHandler() - Call from GPI2 interrupt handler to process sleep req + * @srcMask Value read from GPI2 register which determines master requestor + * + * @note Call from GPI2 interrupt routine to process sleep request. Must not + * clear GPI2 interrupt before this function returns. + */ +void XPfw_PmWfiHandler(const u32 srcMask) +{ + PmProc *proc = PmGetProcByWfiStatus(srcMask); + + if (NULL == proc) { + PmDbg("%s ERROR: Unknown processor %d\n", __func__, srcMask); + goto done; + } + + PmProcFsm(proc, PM_PROC_EVENT_SLEEP); + if ((true == proc->isPrimary) && (true == IS_OFF(&proc->node))) { + /* + * We've just powered down a primary processor, now use opportunistic + * suspend to power down its parent(s) + */ + PmOpportunisticSuspend(proc->node.parent); + } + +done: + return; +} + +/** + * XPfw_PmWakeHandler() - Call from GPI1 interrupt to process wake request + * @srcMask Value read from GPI1 register which determines interrupt source + * + * @note Call from GPI1 interrupt routine to process wake request. Must not + * clear GPI1 interrupt before this function returns. + * If the wake source is one of GIC wakes, source of the interrupt + * (peripheral that actually generated interrupt to GIC) cannot be + * determined, and target should be immediately woken-up (target is + * processor whose GIC wake bit is set in srcMask). If not a GIC wake, + * source can be determined, either from GPI1 register (if interrupt + * line is routed directly), or from FPD GIC Proxy registers. When the + * source is determined, based on master requirements for the source + * slave it is determined which processor should be woken-up (always + * wake the primary processor, owner of the master channel). + */ +u32 XPfw_PmWakeHandler(const u32 srcMask) +{ + u32 status = PM_RET_SUCCESS; + + if (PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK & srcMask) { + /* Processor GIC wake */ + PmProc* proc = PmGetProcByWakeStatus(srcMask); + if (NULL != proc) { + PmProcFsm(proc, PM_PROC_EVENT_WAKE); + } else { + status = PM_RET_ERROR_PROC; + } + } else { + /* Slave wake */ + PmSlaveProcessWake(srcMask); + } + + return status; +} + +/** + * XPfw_PmCheckIpiRequest() - Check whether the IPI interrupt is a PM call + * @isrVal IPI's ISR register value + * @apiId Pointer to a variable where api id can be returned + * + * @return Check result + * + * @note Call from IPI interrupt routine to check is interrupt a PM call. + * Function reads first argument of payload in IPI buffer of + * requestor master to determine whether first argument is within + * PM API regular ids. + */ +XPfw_PmIpiStatus XPfw_PmCheckIpiRequest(const u32 isrVal, + u32* const apiId) +{ + u32 status; + bool isValid; + const PmMaster *master = PmGetMasterByIpiMask(isrVal); + + if (NULL == master) { + /* IPI is not generated by one of the PM supported PUs */ + status = XPFW_PM_IPI_SRC_UNKNOWN; + goto done; + } + + /* Api id is first argument in payload */ + *apiId = XPfw_Read32(master->buffer); + isValid = PmIsApiIdValid(*apiId); + if (true == isValid) { + /* Api id is within valid range */ + status = XPFW_PM_IPI_IS_PM_CALL; + } else { + /* This IPI was not a PM call */ + status = XPFW_PM_IPI_NOT_PM_CALL; + } + +done: + return status; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_binding.h b/lib/sw_apps/zynqmp_pmufw/src/pm_binding.h new file mode 100644 index 00000000..3c2cab21 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_binding.h @@ -0,0 +1,70 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/********************************************************************* + * Function declarations to be used for integrating + * power management within PMU firmware. + *********************************************************************/ + +#ifndef PM_BINDING_H_ +#define PM_BINDING_H_ + +#include "xil_types.h" + +/********************************************************************* + * Enum definitions + ********************************************************************/ +/* Return status for checking whether IPI interrupt is a PM API call */ +typedef enum { + XPFW_PM_IPI_NOT_PM_CALL, + XPFW_PM_IPI_IS_PM_CALL, + XPFW_PM_IPI_SRC_UNKNOWN, +} XPfw_PmIpiStatus; + +/********************************************************************* + * Function declarations + ********************************************************************/ +/* Initialize power management firmware */ +void XPfw_PmInit(void); + +/* Check whether the ipi is power management related */ +XPfw_PmIpiStatus XPfw_PmCheckIpiRequest(const u32 isrVal, u32* const apiId); + +/* Call from IPI interrupt routine to handle PM API request */ +void XPfw_PmIpiHandler(const u32 isrMask, const u32 apiId); + +/* Call from GPI2 interrupt routine to handle processor sleep request */ +void XPfw_PmWfiHandler(const u32 srcMask); + +/* Call from GPI1 interrupt routine to handle wake request */ +u32 XPfw_PmWakeHandler(const u32 srcMask); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.c b/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.c new file mode 100644 index 00000000..82985481 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.c @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * PM callbacks interface. + * Used by the power management to send a message to the PM master and + * optionally generate interrupt using IPI. + *********************************************************************/ + +#include "pm_callbacks.h" +#include "pm_defs.h" +#include "pm_api.h" +#include "ipi_buffer.h" + +/** + * PmAcknowledgeCb() - sends acknowledge via callback + * @master Master who is blocked and waiting for the acknowledge + * @nodeId Node id of the node in question + * @status Status of the PM operation + * @oppoint Operating point of the node in question + * + * @note Master is not blocked waiting for this acknowledge. Master + * acknowledge through the IPI interrupt and registered callback. + */ +void PmAcknowledgeCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 status, const u32 oppoint) +{ + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_ACKNOWLEDGE_CB); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE, + nodeId); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE, + status); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE, + oppoint); + XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask); +} + +/** + * PmNotifyCb() - notifies a master about an event occurance + * @nodeId Node id regarding which the event is triggered + * @event Event to informa master about + * @oppoint Optionally event is related to some operating point change + */ +void PmNotifyCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 event, const u32 oppoint) +{ + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_NOTIFY_CB); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE, + nodeId); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE, + event); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE, + oppoint); + XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask); +} + +/** + * PmInitSuspendCb() - request a master to suspend itself + * @nodeId Node within the master to be suspended + * @reason The reason of initiating the suspend + * @latency Not supported + * @state State to which the master should suspend + * @timeout How much time the master has to respond + */ +void PmInitSuspendCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 reason, const u32 latency, const u32 state, + const u32 timeout) +{ + PmDbg("%s(%s, %d, %d, %d, %d)\n", __func__, PmStrNode(nodeId), reason, + latency, state, timeout); + + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_INIT_SUSPEND_CB); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE, + nodeId); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 2 * PAYLOAD_ELEM_SIZE, + reason); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 3 * PAYLOAD_ELEM_SIZE, + latency); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 4 * PAYLOAD_ELEM_SIZE, + state); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + 5 * PAYLOAD_ELEM_SIZE, + timeout); + XPfw_Write32(IPI_PMU_0_TRIG, master->ipiTrigMask); +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.h b/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.h new file mode 100644 index 00000000..3688223f --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_callbacks.h @@ -0,0 +1,55 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * PM callbacks interface. + * Used by the power management to send a message to the PM master and + * generate interrupt using IPI. + *********************************************************************/ + +#ifndef PM_CALLBACKS_H_ +#define PM_CALLBACKS_H_ + +#include "pm_master.h" +#include "xil_types.h" + +void PmAcknowledgeCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 status, const u32 oppoint); + +void PmNotifyCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 event, const u32 oppoint); + +void PmInitSuspendCb(const PmMaster* const master, const PmNodeId nodeId, + const u32 reason, const u32 latency, const u32 state, + const u32 timeout); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_common.c b/lib/sw_apps/zynqmp_pmufw/src/pm_common.c new file mode 100644 index 00000000..d3853802 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_common.c @@ -0,0 +1,147 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of commonly used functions for debugging PMU Power + * Management (PM). + *********************************************************************/ + +#include "pm_common.h" +#include "pm_defs.h" +#include "pm_master.h" + +#ifdef DEBUG_PM +const char* PmStrMaster(const u32 master) +{ + switch (master) { + case PM_MASTER_APU: + return "MASTER_APU"; + case PM_MASTER_RPU_0: + return "MASTER_RPU0"; + case PM_MASTER_RPU_1: + return "MASTER_RPU1"; + default: + return "ERROR_MASTER"; + } +} + +const char* PmStrNode(const u32 node) +{ + switch (node) { + case NODE_APU: + return "NODE_APU"; + case NODE_APU_0: + return "NODE_APU_0"; + case NODE_APU_1: + return "NODE_APU_1"; + case NODE_APU_2: + return "NODE_APU_2"; + case NODE_APU_3: + return "NODE_APU_3"; + case NODE_RPU: + return "NODE_RPU"; + case NODE_RPU_0: + return "NODE_RPU_0"; + case NODE_RPU_1: + return "NODE_RPU_1"; + case NODE_PL: + return "NODE_PL"; + case NODE_FPD: + return "NODE_FPD"; + case NODE_OCM_BANK_0: + return "NODE_OCM_BANK_0"; + case NODE_OCM_BANK_1: + return "NODE_OCM_BANK_1"; + case NODE_OCM_BANK_2: + return "NODE_OCM_BANK_2"; + case NODE_OCM_BANK_3: + return "NODE_OCM_BANK_3"; + case NODE_TCM_0_A: + return "NODE_TCM_0_A"; + case NODE_TCM_0_B: + return "NODE_TCM_0_B"; + case NODE_TCM_1_A: + return "NODE_TCM_1_A"; + case NODE_TCM_1_B: + return "NODE_TCM_1_B"; + case NODE_L2: + return "NODE_L2"; + case NODE_GPU_PP_0: + return "NODE_GPU_PP_0"; + case NODE_GPU_PP_1: + return "NODE_GPU_PP_1"; + case NODE_USB_0: + return "NODE_USB_0"; + case NODE_USB_1: + return "NODE_USB_1"; + case NODE_TTC_0: + return "NODE_TTC_0"; + case NODE_SATA: + return "NODE_SATA"; + default: + return "ERROR_NODE"; + } +} + +const char* PmStrAck(const u32 ack) +{ + switch (ack) { + case REQUEST_ACK_NO: + return "REQUEST_ACK_NO"; + case REQUEST_ACK_BLOCKING: + return "REQUEST_ACK_BLOCKING"; + case REQUEST_ACK_CB_STANDARD: + return "REQUEST_ACK_CB_STANDARD"; + case REQUEST_ACK_CB_ERROR: + return "REQUEST_ACK_CB_ERROR"; + default: + return "ERROR_ACK"; + } +} + +const char* PmStrReason(const u32 reason) +{ + switch (reason) { + case ABORT_REASON_WKUP_EVENT: + return "ABORT_REASON_WKUP_EVENT"; + case ABORT_REASON_PU_BUSY: + return "ABORT_REASON_PU_BUSY"; + case ABORT_REASON_NO_PWRDN: + return "ABORT_REASON_NO_PWRDN"; + case ABORT_REASON_UNKNOWN: + return "ABORT_REASON_UNKNOWN"; + default: + return "ERROR_REASON"; + } +} + +#endif /* DEBUG_PM */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_common.h b/lib/sw_apps/zynqmp_pmufw/src/pm_common.h new file mode 100644 index 00000000..e61c8e55 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_common.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of commonly used macros and enums in PMU Power + * Management (PM). + *********************************************************************/ + +#ifndef PM_COMMON_H_ +#define PM_COMMON_H_ + +#include "pmu_local.h" +#include "xpfw_default.h" +#include "xil_types.h" + +/********************************************************************* + * Typedefs (common use in PMU Power Management) + ********************************************************************/ +/* + * stdint.h is not available, and pmu-fw framework defined similar + * macros but as 0 and 1 (signed). PM, as in general, uses unsigned. + */ +#ifndef bool + typedef u8 bool; + #define true 1U + #define false 0U +#endif + +typedef u32 (*const PmTranHandler)(void); + +/********************************************************************* + * Macros + ********************************************************************/ +/* + * Undefine DEBUG_PM macro to disable power management prints + */ +#ifdef DEBUG_MODE + #define DEBUG_PM +#endif +/* + * Conditional debugging prints used for PM. PM prints should never + * appear if pmu-fw has disabled debug prints, however even when pmu-fw + * has enabled debug prints, power management prints should be configurable. + */ +#ifdef DEBUG_PM + #define PmDbg(MSG, ...) fw_printf("PMU-PM: " MSG, ##__VA_ARGS__) +#else + #define PmDbg(MSG, ...) {} +#endif + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define BIT0(x) (x & 1U) + +/* All WFI bitfields in GPI2 */ +#define PMU_LOCAL_GPI2_ENABLE_ALL_PWRDN_REQ_MASK \ + (PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_MASK | \ + PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_MASK | \ + PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_MASK | \ + PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_MASK | \ + PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_MASK | \ + PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_MASK) + +/* All GIC wakes in GPI1 */ +#define PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK \ + (PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK | \ + PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK | \ + PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK | \ + PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK | \ + PMU_IOMODULE_GPI1_R5_0_WAKE_MASK | \ + PMU_IOMODULE_GPI1_R5_1_WAKE_MASK) + +/* + * Macro for all wake events in GPI1 that PM handles. + * Used for initialization to avoid looping through all slaves array. + */ +#define PMU_IOMODULE_GPI1_WAKES_ALL_MASK \ + (PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK | \ + PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK | \ + PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_MASK | \ + PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_MASK | \ + PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_MASK) + +/* Enable/disable macros for wake events in GPI1 register */ +#define ENABLE_WAKE(mask) XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, mask, mask); +#define DISABLE_WAKE(mask) XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, mask, ~(mask)); + +/********************************************************************* + * Function declarations + ********************************************************************/ +#ifdef DEBUG_PM +const char* PmStrNode(const u32 node); +const char* PmStrMaster(const u32 master); +const char* PmStrAck(const u32 ack); +const char* PmStrReason(const u32 reason); +#endif + +#endif /* PM_COMMON_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_core.c b/lib/sw_apps/zynqmp_pmufw/src/pm_core.c new file mode 100644 index 00000000..e58cf6f9 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_core.c @@ -0,0 +1,722 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * This file contains implementation of the PM API functions, which + * should be used directly only by power management itself. + *********************************************************************/ + +#include "pm_core.h" +#include "pm_node.h" +#include "pm_proc.h" +#include "pm_defs.h" +#include "pm_common.h" +#include "pm_callbacks.h" +#include "ipi_buffer.h" + +/** + * PmProcessAckRequest() -Returns appropriate acknowledge if required + * @ack Ack argument as requested by the master + * @master IPI channel to use + * @nodeId Node ID of requesting PU + * @status Status of PM's operation + * @oppoint Operating point of node in question + */ +static void PmProcessAckRequest(const u32 ack, + const PmMaster* const master, + const PmNodeId nodeId, + const u32 status, + const u32 oppoint) +{ + if (status != PM_RET_SUCCESS) { + PmDbg("ERROR PM operation failed - code %d\n", status); + } + + if (REQUEST_ACK_BLOCKING == ack) { + /* Return status immediately */ + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, status); + } else if ((REQUEST_ACK_CB_STANDARD == ack) || + ((REQUEST_ACK_CB_ERROR == ack) && (PM_RET_SUCCESS != status))) { + /* Return acknowledge through callback */ + PmAcknowledgeCb(master, nodeId, status, oppoint); + } else { + /* No returning of the acknowledge */ + } +} + +/** + * PmSelfSuspend() - Requested self suspend for a processor + * @master Master who initiated the request + * @node Processor or subsystem node to be suspended + * @latency Not supported + * @state Not supported + * + * @note Used to announce starting of self suspend procedure. Node will be + * put to sleep when server handles corresponding processor's WFI + * interrupt. + */ +static void PmSelfSuspend(const PmMaster *const master, + const u32 node, + const u32 latency, + const u32 state) +{ + /* the node ID must refer to a processor belonging to this master */ + PmProc* proc = PmGetProcOfThisMaster(master, node); + + PmDbg("%s(%s, %d, %d)\n", __func__, PmStrNode(node), latency, state); + + if (NULL == proc) { + PmDbg("%s ERROR node ID %s(=%d) does not refer to a processor of this master channel\n", + __func__, PmStrNode(node), node); + goto done; + } + + PmProcFsm(proc, PM_PROC_EVENT_SELF_SUSPEND); + +done: + return; +} + +/** + * PmRequestSuspend() - Requested suspend by a PU for another processor + * @master PU from which the request is initiated + * @node Processor or subsystem node to be suspended + * @ack Acknowledge request + * @latency Desired wakeup latency - Not supported + * @state Desired power status - Not supported + */ +static void PmRequestSuspend(const PmMaster *const master, + const u32 node, + const u32 ack, + const u32 latency, + const u32 state) +{ + PmProc* proc = PmGetProcOfOtherMaster(master, node); + + PmDbg("%s(%s, %s, %d, %d)\n", __func__, PmStrNode(node), PmStrAck(ack), + latency, state); + + if (NULL == proc) { + PmDbg("%s ERROR processor not found by node %d\n", __func__, node); + PmProcessAckRequest(ack, master, node, PM_RET_ERROR_ARGS, 0); + goto done; + } + + PmInitSuspendCb(proc->master, node, 0, 0, 0, 0); + +done: + return; +} + +/** + * PmForcePowerdown() - Powerdown a PU or domain forcefully + * @master Master who initiated the request + * @node Processor, subsystem or domain node to be powered down + * @ack Acknowledge request + * + * @note The affected PUs are not notified about the upcoming powerdown, + * and PMU does not wait for their WFI interrupt. + * Admissible nodes are : + * 1. Processor nodes (RPU0..1, APU0..3, and in future: PL Procs) + * 2. Parent nodes (APU, RPU, FPD, and in future PL) + */ +static void PmForcePowerdown(const PmMaster *const master, + const u32 node, + const u32 ack) +{ + u32 status; + u32 oppoint = 0; + PmNode* nodePtr = PmGetNodeById(node); + + PmDbg("%s(%s, %s)\n", __func__, PmStrNode(node), PmStrAck(ack)); + + if (NULL == nodePtr) { + status = PM_RET_ERROR_ARGS; + goto done; + } + + switch (nodePtr->typeId) { + case PM_TYPE_PROC: + status = PmProcFsm((PmProc*)nodePtr->derived, PM_PROC_EVENT_FORCE_PWRDN); + break; + case PM_TYPE_PWR_ISLAND: + case PM_TYPE_PWR_DOMAIN: + status = PmForceDownTree((PmPower*)nodePtr->derived); + break; + default: + status = PM_RET_ERROR_OTHER; + break; + } + + oppoint = nodePtr->currState; + + /* + * Successfully powered down a node, now trigger opportunistic + * suspend to power down its parent(s) if possible + */ + if (PM_RET_SUCCESS == status && NULL != nodePtr->parent) { + PmOpportunisticSuspend(nodePtr->parent); + } + +done: + PmProcessAckRequest(ack, master, node, status, oppoint); +} + +/** + * PmAbortSuspend() - Abort previously requested suspend + * @master Master who initiated the request + * @reason Reason of aborting suspend + * @node Node ID of processor node to abort suspend for + * + * @note Only processor within the master can initiate its own abortion of + * suspend. + */ +static void PmAbortSuspend(const PmMaster *const master, + const u32 reason, + const u32 node) +{ + PmProc* proc = PmGetProcOfThisMaster(master, node); + + PmDbg("%s(%s, %s)\n", __func__, PmStrNode(node), PmStrReason(reason)); + + if (NULL == proc) { + PmDbg("%s ERROR processor access for node #%d not allowed\n", + __func__, node); + goto done; + } + + PmProcFsm(proc, PM_PROC_EVENT_ABORT_SUSPEND); + +done: + return; +} + +/** + * PmRequestWakeup() - Power-up processor or subsystem + * @master Master who initiated the request + * @node Processor or subsystem node to be powered up + * @ack Acknowledge request + */ +static void PmRequestWakeup(const PmMaster *const master, const u32 node, + const u32 ack) +{ + u32 status; + u32 oppoint = 0; + PmProc* proc = PmGetProcByNodeId(node); + + PmDbg("%s(%s, %s)\n", __func__, PmStrNode(node), PmStrAck(ack)); + + if (NULL == proc) { + status = PM_RET_ERROR_PROC; + goto done; + } + + status = PmProcFsm(proc, PM_PROC_EVENT_WAKE); + oppoint = proc->node.currState; + +done: + PmProcessAckRequest(ack, master, node, status, oppoint); +} + +/** + * PmReleaseNode() - Release a slave node + * @master Master who initiated the request + * @node Node to be released + * + * @note Node to be released must have been requested before + */ +static void PmReleaseNode(const PmMaster *master, + const u32 node, + const u32 latency) +{ + u32 status; + PmRequirement* masterReq = PmGetRequirementForSlave(master, node); + + if (NULL == masterReq) { + PmDbg("ERROR Can't find requirement for slave %s of master %s\n", + PmStrNode(node), PmStrNode(master->procs[0].node.nodeId)); + goto done; + } + + /* Release requirements */ + status = PmRequirementUpdate(masterReq, 0); + masterReq->info &= ~PM_MASTER_USING_SLAVE_MASK; + if (PM_RET_SUCCESS != status) { + PmDbg("%s: ERROR PmRequirementUpdate status = %d (should be 0!!)\n", + __func__, status); + goto done; + } + + /* after releasing a node, try power down whole island/domain */ + PmPower* powerParent = masterReq->slave->node.parent; + if (NULL != powerParent) { + PmOpportunisticSuspend(powerParent); + } + +done: + PmDbg("%s (%s, %d)\n", __func__, PmStrNode(node), latency); +} + +/** + * PmRequestNode() - Request to use a slave node + * @master Master who initiated the request + * @node Node requested + * @capabilities Requested capabilities + * @qos Requested quality of service - Not supported + * @ack Acknowledge request + */ +static void PmRequestNode(const PmMaster *master, + const u32 node, + const u32 capabilities, + const u32 qos, + const u32 ack) +{ + u32 status; + u32 oppoint = 0; + PmRequirement* masterReq = PmGetRequirementForSlave(master, node); + + PmDbg("%s(%s, %d, %d, %s)\n", __func__, PmStrNode(node), capabilities, + qos, PmStrAck(ack)); + + if (NULL == masterReq) { + /* Master is not allowed to use the slave with given node */ + PmDbg("ERROR Master can't use the slave\n"); + status = PM_RET_ERROR_ACCESS; + goto done; + } + + if (PM_MASTER_USING_SLAVE_MASK & masterReq->info) { + status = PM_RET_ERROR_DOUBLEREQ; + goto done; + } + + if (PM_PROC_STATE_ACTIVE != master->procs->node.currState) { + PmDbg("ERROR Master isn't active!\n"); + status = PM_RET_ERROR_ACCESS; + goto done; + } + + /* Set requested capabilities if they are valid */ + masterReq->info |= PM_MASTER_USING_SLAVE_MASK; + status = PmRequirementUpdate(masterReq, capabilities); + +done: + PmProcessAckRequest(ack, master, node, status, oppoint); +} + +/** + * PmSetRequirement() - Setting requement for a slave + * @master Master who initiated the request + * @node Node whose requirements setting is requested + * @capabilities Requested capabilities + * @qos Not supported + * @ack Acknowledge request + * + * @note If processor which initiated request is in suspending state, + * requirement will be set once PMU handles processor's WFI + * interrupt. If processor is active, setting is done + * immidiately (if possible). + */ +static void PmSetRequirement(const PmMaster *master, + const u32 node, + const u32 capabilities, + const u32 qos, + const u32 ack) +{ + u32 status; + u32 oppoint = 0; + PmRequirement* masterReq = PmGetRequirementForSlave(master, node); + + PmDbg("%s(%s, %d, %d, %s)\n", __func__, PmStrNode(node), capabilities, + qos, PmStrAck(ack)); + + /* Is there a provision for the master to use the given slave node */ + if (NULL == masterReq) { + status = PM_RET_ERROR_ACCESS; + goto done; + } + + /* Does master have the privilege to request settings for the node? */ + if (!(PM_MASTER_USING_SLAVE_MASK & masterReq->info)) { + status = PM_RET_ERROR_ACCESS; + goto done; + } + + /* Master is using slave (previously has requested node) */ + switch (master->procs->node.currState) { + case (PM_PROC_STATE_SUSPENDING): + /* Schedule setting the requirement */ + status = PmRequirementSchedule(masterReq, capabilities); + break; + case PM_PROC_STATE_ACTIVE: + /* Set capabilities now - if they are valid */ + status = PmRequirementUpdate(masterReq, capabilities); + break; + default: + /* Should never happen */ + status = PM_RET_ERROR_COMMUNIC; + break; + } + +done: + PmProcessAckRequest(ack, master, node, status, oppoint); +} + +/** + * PmGetApiVersion() - Provides API version number to the caller + * @master Master who initiated the request + */ +static void PmGetApiVersion(const PmMaster *const master) +{ + u32 version = (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR; + + PmDbg("%s version %d.%d\n", __func__, PM_VERSION_MAJOR, PM_VERSION_MINOR); + + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_RET_SUCCESS); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE, + version); +} + +/** + * PmMmioWrite() - Perform write to protected mmio + * @master Master who initiated the request + * @address Address to write to + * @mask Mask to apply + * @value Value to write + * + * @note This function provides access to PM-related control registers + * that may not be directly accessible by a particular PU. + */ +static void PmMmioWrite(const PmMaster *const master, const u32 address, + const u32 mask, const u32 value) +{ + PmDbg("%s (0x%x, 0x%x, 0x%x)\n", __func__, address, mask, value); + + XPfw_Write32(address, mask & value); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_RET_SUCCESS); +} + +/** + * PmMmioRead() - Read value from protected mmio + * @master Master who initiated the request + * @address Address to write to + * @mask Mask to apply + * + * @note This function provides access to PM-related control registers + * that may not be directly accessible by a particular PU. + */ +static void PmMmioRead(const PmMaster *const master, const u32 address, + const u32 mask) +{ + u32 value; + + PmDbg("%s addr=0x%x, mask=0x%x\n", __func__, address, mask); + + value = XPfw_Read32(address) & mask; + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET, PM_RET_SUCCESS); + XPfw_Write32(master->buffer + IPI_BUFFER_RESP_OFFSET + PAYLOAD_ELEM_SIZE, + value); +} + +/** + * PmSetWakeupSource() - Master requests to be woken-up by the slaves interrupt + * @master Initiator of the request + * @targetNode Master node to be woken-up (currently must be same as initiator) + * @sourceNode Source of the wake-up (slave that generates interrupt) + * @enable Flag stating should event be enabled or disabled + * + * @note GIC wake interrupt is automatically enabled when a processor + * goes to sleep. + */ +static void PmSetWakeupSource(const PmMaster *const master, + const u32 targetNode, + const u32 sourceNode, + const u32 enable) +{ + PmRequirement* req = PmGetRequirementForSlave(master, sourceNode); + + if ((NULL == req) || (NULL == req->slave->wake)) { + goto done; + } + + if (0U == enable) { + req->info &= ~PM_MASTER_WAKEUP_REQ_MASK; + } else { + req->info |= PM_MASTER_WAKEUP_REQ_MASK; + } + +done: + PmDbg("%s(%s, %s, %d)\n", __func__, PmStrNode(master->procs->node.nodeId), + PmStrNode(sourceNode), enable); +} + +/** + * PmSystemShutdown() - Request system shutdown or restart + * @master Master requesting system shutdown + * @restart Flag, 0 is for shutdown, 1 for restart + */ +static void PmSystemShutdown(const PmMaster *const master, const u32 restart) +{ + PmDbg("%s(%d) not implemented\n", __func__, restart); +} + +/** + * PmSetMaxLatency() - set maximum allowed latency for the node + * @master Initiator of the request who must previously requested the node + * @node Node whose latency, and consequently deepest possible state, is + * specified + * @latency Maximum allowed latency + */ +static void PmSetMaxLatency(const PmMaster *const master, const u32 node, + const u32 latency) +{ + PmDbg("%s(%s, %d) not implemented\n", __func__, PmStrNode(node), latency); +} + +/** + * PmSetConfiguration() - Load the configuration + * @master Master who initiated the loading of configuration + * @address Address at which the configuration object is placed + */ +static void PmSetConfiguration(const PmMaster *const master, const u32 address) +{ + PmDbg("%s(0x%x) not implemented\n", __func__, address); +} + +/** + * PmGetNodeStatus() - Get the status of the node + * @master Initiator of the request + * @node Node whose status should be returned + */ +static void PmGetNodeStatus(const PmMaster *const master, const u32 node) +{ + PmDbg("%s(%s) not implemented\n", __func__, PmStrNode(node)); +} + +/** + * PmGetOpCharacteristics() - Get operating characteristics of a node + * @master Initiator of the request + * @node Node in question + * @type Type of the operating characteristics (power, temperature) + */ +static void PmGetOpCharacteristics(const PmMaster *const master, const u32 node, + const u32 type) +{ + PmDbg("%s(%s, %d) not implemented\n", __func__, PmStrNode(node), type); +} + +/** + * PmRegisterNotifier() - Register a master to be notified about the event + * @master Master to be notified + * @node Node to which the event is related + * @event Event in question + * @wake Wake master upon capturing the event if value 1, do not wake if 0 + * @enable Enable the registration for value 1, disable for value 0 + */ +static void PmRegisterNotifier(const PmMaster *const master, const u32 node, + const u32 event, const u32 wake, + const u32 enable) +{ + PmDbg("%s(%s, %d, %d, %d) not implemented\n", __func__, PmStrNode(node), + event, wake, enable); +} + +/** + * PmClockRequest() - Request the clock at some frequency + * @master Initiator of the request + * @clock The clock in question + * @rate Frequency to be set + */ +static void PmClockRequest(const PmMaster *const master, const u32 clock, + const u32 rate) +{ + PmDbg("%s(%d, %d) not implemented\n", __func__, clock, rate); +} + +/** + * PmClockRelease() - Release the clock + * @master Initiator of the request + * @clock The clock in question + */ +static void PmClockRelease(const PmMaster *const master, const u32 clock) +{ + PmDbg("%s(%d) not implemented\n", __func__, clock); +} + +/** + * PmGetClockRate() - Get current frequency of the clock + * @master Initiator of the request + * @clock Clock whose frequency should be returned + */ +static void PmGetClockRate(const PmMaster *const master, const u32 clock) +{ + PmDbg("%s(%d) not implemented\n", __func__, clock); +} + +/** + * PmResetAssert() - Request setting of reset (1 - assert, 0 - release) + * @master Initiator of the request + * @reset Reset to be configured + * @assertFlag Flag stating should reset be asserted (1) or released (0) + */ +static void PmResetAssert(const PmMaster *const master, const u32 reset, + const u32 assertFlag) +{ + PmDbg("%s(%d, %d) not implemented\n", __func__, reset, assertFlag); +} + +/** + * PmResetGetStatus() - Get status of the reset + * @master Initiator of the request + * @reset Reset whose status should be returned + */ +static void PmResetGetStatus(const PmMaster *const master, const u32 reset) +{ + PmDbg("%s(%d) not implemented\n", __func__, reset); +} + +/** + * PmProcessApiCall() - Called to process PM API call + * @master Pointer to a requesting master structure + * @pload Array of integers with the information about the pm call (api id + + * arguments of the api) + * + * @note Payload arguments are checked and validated before calling this. + */ +void PmProcessApiCall(const PmMaster *const master, + const u32 pload[PAYLOAD_ELEM_CNT]) +{ + switch (pload[0]) { + case PM_SELF_SUSPEND: + PmSelfSuspend(master, pload[1], pload[2], pload[3]); + break; + case PM_REQUEST_SUSPEND: + PmRequestSuspend(master, pload[1], pload[2], pload[3], pload[4]); + break; + case PM_FORCE_POWERDOWN: + PmForcePowerdown(master, pload[1], pload[2]); + break; + case PM_ABORT_SUSPEND: + PmAbortSuspend(master, pload[1], pload[2]); + break; + case PM_REQUEST_WAKEUP: + PmRequestWakeup(master, pload[1], pload[2]); + break; + case PM_SET_WAKEUP_SOURCE: + PmSetWakeupSource(master, pload[1], pload[2], pload[3]); + break; + case PM_SYSTEM_SHUTDOWN: + PmSystemShutdown(master, pload[1]); + break; + case PM_REQUEST_NODE: + PmRequestNode(master, pload[1], pload[2], pload[3], pload[4]); + break; + case PM_RELEASE_NODE: + PmReleaseNode(master, pload[1], pload[2]); + break; + case PM_SET_REQUIREMENT: + PmSetRequirement(master, pload[1], pload[2], pload[3], pload[4]); + break; + case PM_SET_MAX_LATENCY: + PmSetMaxLatency(master, pload[1], pload[2]); + break; + case PM_GET_API_VERSION: + PmGetApiVersion(master); + break; + case PM_SET_CONFIGURATION: + PmSetConfiguration(master, pload[1]); + break; + case PM_GET_NODE_STATUS: + PmGetNodeStatus(master, pload[1]); + break; + case PM_GET_OP_CHARACTERISTIC: + PmGetOpCharacteristics(master, pload[1], pload[2]); + break; + case PM_REGISTER_NOTIFIER: + PmRegisterNotifier(master, pload[1], pload[2], pload[3], pload[4]); + break; + case PM_CLOCK_REQUEST: + PmClockRequest(master, pload[1], pload[2]); + break; + case PM_CLOCK_RELEASE: + PmClockRelease(master, pload[1]); + break; + case PM_CLOCK_GET_RATE: + PmGetClockRate(master, pload[1]); + break; + case PM_RESET_ASSERT: + PmResetAssert(master, pload[1], pload[2]); + break; + case PM_RESET_GET_STATUS: + PmResetGetStatus(master, pload[1]); + break; + case PM_MMIO_WRITE: + PmMmioWrite(master, pload[1], pload[2], pload[3]); + break; + case PM_MMIO_READ: + PmMmioRead(master, pload[1], pload[2]); + break; + default: + PmDbg("%s ERROR unsupported PM API #%d\n", __func__, pload[0]); + PmProcessAckRequest(PmRequestAcknowledge(pload), master, + NODE_UNKNOWN, PM_RET_ERROR_NOTSUPPORTED, 0); + break; + } +} + +/** + * PmProcessRequest() - Process PM API call + * @master Pointer to a requesting master structure + * @pload Array of integers with the information about the pm call (api id + + * arguments of the api) + * + * @note Called to process PM API call. If specific PM API receives less + * than 4 arguments, extra arguments are ignored. + */ +void PmProcessRequest(const PmMaster *const master, + const u32 pload[PAYLOAD_ELEM_CNT]) +{ + PmPayloadStatus status = PmCheckPayload(pload); + + if (PM_PAYLOAD_OK == status) { + PmProcessApiCall(master, pload); + } else { + PmDbg("%s ERROR invalid payload, status #%d\n", __func__, status); + /* Acknowledge if possible */ + if (PM_PAYLOAD_ERR_API_ID != status) { + u32 ack = PmRequestAcknowledge(pload); + if (REQUEST_ACK_NO != ack) { + PmAcknowledgeCb(master, NODE_UNKNOWN, PM_RET_ERROR_API_ID, 0); + } + } + } +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_core.h b/lib/sw_apps/zynqmp_pmufw/src/pm_core.h new file mode 100644 index 00000000..8cc2f808 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_core.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Contains the function to call for processing a PM API call. + * The function (PmProcessRequest) is called from interrupt handler + * stubs, implemented in pm_binding files. The request is further + * proccessed according to the master that initiated request and + * API call's payload read from master's IPI buffer. + ********************************************************************/ + +#ifndef PM_CORE_H_ +#define PM_CORE_H_ + +#include "pm_api.h" +#include "pm_master.h" +#include "xil_types.h" + +/********************************************************************* + * Function declarations + ********************************************************************/ +void PmProcessRequest(const PmMaster *const master, + const u32 payload[PAYLOAD_ELEM_CNT]); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h b/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h new file mode 100644 index 00000000..b14212bc --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_defs.h @@ -0,0 +1,175 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of commonly used enums that have to match definitions + * that all software layer in the system use. + *********************************************************************/ + +#ifndef PM_DEFS_H_ +#define PM_DEFS_H_ + +/********************************************************************* + * Macro definitions + ********************************************************************/ + +/* + * Version number is a 32bit value, like: + * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR + */ +#define PM_VERSION_MAJOR 0U +#define PM_VERSION_MINOR 1U + +#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR) + +/* Capabilities common for all slave nodes */ +#define PM_CAP_ACCESS 0x1U +#define PM_CAP_CONTEXT 0x2U +#define PM_CAP_WAKEUP 0x4U + +#define MAX_LATENCY (~0U) +#define MAX_QOS 100U + +/* PM API ids */ +#define PM_GET_API_VERSION 1U +#define PM_SET_CONFIGURATION 2U +#define PM_GET_NODE_STATUS 3U +#define PM_GET_OP_CHARACTERISTIC 4U +#define PM_REGISTER_NOTIFIER 5U + +#define PM_REQUEST_SUSPEND 6U +#define PM_SELF_SUSPEND 7U +#define PM_FORCE_POWERDOWN 8U +#define PM_ABORT_SUSPEND 9U +#define PM_REQUEST_WAKEUP 10U +#define PM_SET_WAKEUP_SOURCE 11U +#define PM_SYSTEM_SHUTDOWN 12U + +#define PM_REQUEST_NODE 13U +#define PM_RELEASE_NODE 14U +#define PM_SET_REQUIREMENT 15U +#define PM_SET_MAX_LATENCY 16U + +#define PM_CLOCK_REQUEST 17U +#define PM_CLOCK_RELEASE 18U +#define PM_CLOCK_SET_RATE 19U +#define PM_CLOCK_GET_RATE 20U +#define PM_CLOCK_GET_RATE_INFO 21U +#define PM_RESET_ASSERT 22U +#define PM_RESET_GET_STATUS 23U +#define PM_MMIO_WRITE 24U +#define PM_MMIO_READ 25U + +#define PM_API_MIN PM_GET_API_VERSION +#define PM_API_MAX PM_MMIO_READ + +/* PM API callback ids */ +#define PM_INIT_SUSPEND_CB 30U +#define PM_ACKNOWLEDGE_CB 31U +#define PM_NOTIFY_CB 32U + +/* Nodes */ +#define NODE_UNKNOWN 0U +#define NODE_APU 1U +#define NODE_APU_0 2U +#define NODE_APU_1 3U +#define NODE_APU_2 4U +#define NODE_APU_3 5U +#define NODE_RPU 6U +#define NODE_RPU_0 7U +#define NODE_RPU_1 8U +#define NODE_PL 9U +#define NODE_FPD 10U +#define NODE_OCM_BANK_0 11U +#define NODE_OCM_BANK_1 12U +#define NODE_OCM_BANK_2 13U +#define NODE_OCM_BANK_3 14U +#define NODE_TCM_0_A 15U +#define NODE_TCM_0_B 16U +#define NODE_TCM_1_A 17U +#define NODE_TCM_1_B 18U +#define NODE_L2 19U +#define NODE_GPU_PP_0 20U +#define NODE_GPU_PP_1 21U +#define NODE_USB_0 22U +#define NODE_USB_1 23U +#define NODE_TTC_0 24U +#define NODE_SATA 25U + +#define NODE_MIN NODE_APU +#define NODE_MAX NODE_SATA + +/* Request acknowledge argument values */ +#define REQUEST_ACK_NO 1U +#define REQUEST_ACK_BLOCKING 2U +#define REQUEST_ACK_CB_STANDARD 3U +#define REQUEST_ACK_CB_ERROR 4U +#define REQUEST_ACK_MIN REQUEST_ACK_NO +#define REQUEST_ACK_MAX REQUEST_ACK_CB_ERROR + +/* Abort reason argument */ +#define ABORT_REASON_WKUP_EVENT 100U +#define ABORT_REASON_PU_BUSY 101U +#define ABORT_REASON_NO_PWRDN 102U +#define ABORT_REASON_UNKNOWN 103U + +#define ABORT_REASON_MIN ABORT_REASON_WKUP_EVENT +#define ABORT_REASON_MAX ABORT_REASON_UNKNOWN + +/* Suspend reason argument */ +#define SUSPEND_REASON_PU_REQ 201U +#define SUSPEND_REASON_ALERT 202U +#define SUSPEND_REASON_SYS_SHUTDOWN 203U + +#define SUSPEND_REASON_MIN SUSPEND_REASON_PU_REQ +#define SUSPEND_REASON_MAX SUSPEND_REASON_SYS_SHUTDOWN + +/* Operating characteristics type */ +#define PM_OPCHAR_TYPE_POWER 1U +#define PM_OPCHAR_TYPE_ENERGY 2U +#define PM_OPCHAR_TYPE_TEMP 3U + +/* PM API call return status */ +#define PM_RET_SUCCESS 0U +#define PM_RET_ERROR_ARGS 1U +#define PM_RET_ERROR_ACCESS 2U +#define PM_RET_ERROR_TIMEOUT 3U +#define PM_RET_ERROR_NOTSUPPORTED 4U +#define PM_RET_ERROR_PROC 5U +#define PM_RET_ERROR_API_ID 6U +#define PM_RET_ERROR_FAILURE 7U +#define PM_RET_ERROR_COMMUNIC 8U +#define PM_RET_ERROR_DOUBLEREQ 9U +#define PM_RET_ERROR_INTERNAL 24U +#define PM_RET_ERROR_OTHER 25U + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_master.c b/lib/sw_apps/zynqmp_pmufw/src/pm_master.c new file mode 100644 index 00000000..e1d076c6 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_master.c @@ -0,0 +1,721 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Master related data and function definitions: + * 1. Data structures for masters and array of their requirements for + * slaves capabilities + * 2. Functions for managing requirements and accessing master data + *********************************************************************/ + +#include "pm_master.h" +#include "pm_proc.h" +#include "pm_defs.h" +#include "pm_sram.h" +#include "pm_usb.h" +#include "pm_periph.h" +#include "ipi_buffer.h" + +/* Requirement of APU master */ +PmRequirement pmApuReq_g[PM_MASTER_APU_SLAVE_MAX] = { + [PM_MASTER_APU_SLAVE_OCM0] = { + .slave = &pmSlaveOcm0_g.slv, + .requestor = &pmMasterApu_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_OCM1] = { + .slave = &pmSlaveOcm1_g.slv, + .requestor = &pmMasterApu_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_OCM2] = { + .slave = &pmSlaveOcm2_g.slv, + .requestor = &pmMasterApu_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_OCM3] = { + .slave = &pmSlaveOcm3_g.slv, + .requestor = &pmMasterApu_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_L2] = { + .slave = &pmSlaveL2_g.slv, + .requestor = &pmMasterApu_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_USB0] = { + .slave = &pmSlaveUsb0_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_USB1] = { + .slave = &pmSlaveUsb1_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_TTC0] = { + .slave = &pmSlaveTtc0_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_SATA] = { + .slave = &pmSlaveSata_g.slv, + .requestor = &pmMasterApu_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, +}; + +/* Requirement of RPU_0 master */ +PmRequirement pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_MAX] = { + [PM_MASTER_RPU_0_SLAVE_OCM0] = { + .slave = &pmSlaveOcm0_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_RPU_0_SLAVE_OCM1] = { + .slave = &pmSlaveOcm1_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_RPU_0_SLAVE_OCM2] = { + .slave = &pmSlaveOcm2_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_RPU_0_SLAVE_OCM3] = { + .slave = &pmSlaveOcm3_g.slv, + .requestor = &pmMasterRpu0_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_RPU_0_SLAVE_TCM0A] = { + .slave = &pmSlaveTcm0A_g.slv, + .requestor = &pmMasterRpu0_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_RPU_0_SLAVE_TCM0B] = { + .slave = &pmSlaveTcm0B_g.slv, + .requestor = &pmMasterRpu0_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_RPU_0_SLAVE_TCM1A] = { + .slave = &pmSlaveTcm1A_g.slv, + .requestor = &pmMasterRpu0_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_RPU_0_SLAVE_TCM1B] = { + .slave = &pmSlaveTcm1B_g.slv, + .requestor = &pmMasterRpu0_g, + .info = PM_MASTER_USING_SLAVE_MASK, + .currReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + .nextReq = PM_CAP_ACCESS | PM_CAP_CONTEXT, + }, + [PM_MASTER_APU_SLAVE_USB0] = { + .slave = &pmSlaveUsb0_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_APU_SLAVE_USB1] = { + .slave = &pmSlaveUsb1_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_RPU_0_SLAVE_TTC0] = { + .slave = &pmSlaveTtc0_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, + [PM_MASTER_RPU_0_SLAVE_SATA] = { + .slave = &pmSlaveSata_g.slv, + .requestor = &pmMasterRpu0_g, + .info = 0U, + .currReq = 0U, + .nextReq = 0U, + }, +}; + +PmMaster pmMasterApu_g = { + .procs = pmApuProcs_g, + .procsCnt = PM_PROC_APU_MAX, + .ipiMask = IPI_PMU_0_IER_APU_MASK, + .ipiTrigMask = IPI_PMU_0_TRIG_APU_MASK, + .pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_APU_OFFSET, + .buffer = IPI_BUFFER_APU_BASE + IPI_BUFFER_TARGET_PMU_OFFSET, + .reqs = pmApuReq_g, + .reqsCnt = ARRAY_SIZE(pmApuReq_g), +}; + +PmMaster pmMasterRpu0_g = { + .procs = &pmRpuProcs_g[PM_PROC_RPU_0], + .procsCnt = 1, + .ipiMask = IPI_PMU_0_IER_RPU_0_MASK, + .ipiTrigMask = IPI_PMU_0_TRIG_RPU_0_MASK, + .pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_RPU_0_OFFSET, + .buffer = IPI_BUFFER_RPU_0_BASE + IPI_BUFFER_TARGET_PMU_OFFSET, + .reqs = pmRpu0Req_g, + .reqsCnt = ARRAY_SIZE(pmRpu0Req_g), +}; + +PmMaster pmMasterRpu1_g = { + .procs = &pmRpuProcs_g[PM_PROC_RPU_1], + .procsCnt = 1, + .ipiMask = IPI_PMU_0_IER_RPU_1_MASK, + .ipiTrigMask = IPI_PMU_0_TRIG_RPU_1_MASK, + .pmuBuffer = IPI_BUFFER_PMU_BASE + IPI_BUFFER_TARGET_RPU_1_OFFSET, + .buffer = IPI_BUFFER_RPU_1_BASE + IPI_BUFFER_TARGET_PMU_OFFSET, + .reqs = NULL, /* lockstep mode is assumed for now */ + .reqsCnt = 0, +}; + +static const PmMaster *const pmAllMasters[PM_MASTER_MAX] = { + [PM_MASTER_APU] = &pmMasterApu_g, + [PM_MASTER_RPU_0] = &pmMasterRpu0_g, + [PM_MASTER_RPU_1] = &pmMasterRpu1_g, +}; + +/** + * PmRequirementSchedule() - Schedule requirements of the master for slave. + * Slave state will be updated according to the + * requirement once primary processor goes to sleep. + * @masterReq Pointer to master requirement structure (for a slave) + * @caps Required capabilities of slave to be set once primary core + * goes to sleep. + * + * @return Status of the operation + */ +u32 PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps) +{ + u32 status; + + /* Check if slave has a state with requested capabilities */ + status = PmCheckCapabilities(masterReq->slave, caps); + if (PM_RET_SUCCESS != status) { + status = PM_RET_ERROR_NOTSUPPORTED; + goto done; + } + + /* Schedule setting of the requirement for later */ + masterReq->nextReq = caps; + +done: + return status; +} + +/** + * PmRequirementUpdate() - Set slaves capabilities according to the master's + * requirements + * @masterReq Pointer to structure keeping informations about the + * master's requirement + * @caps Capabilities of a slave requested by the master + * + * @return Status of the operation + */ +u32 PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps) +{ + u32 status; + u32 tmpCaps; + + PmDbg("%s\n", __func__); + /* Check if slave has a state with requested capabilities */ + status = PmCheckCapabilities(masterReq->slave, caps); + + PmDbg("PmCheckCapabilities status=%d\n", status); + if (PM_RET_SUCCESS != status) { + goto done; + } + + /* Configure requested capabilities */ + tmpCaps = masterReq->currReq; + masterReq->currReq = caps; + status = PmUpdateSlave(masterReq->slave); + + PmDbg("PmUpdateSlave status=%d\n", status); + + if (PM_RET_SUCCESS == status) { + /* All capabilities requested in active state are constant */ + masterReq->nextReq = masterReq->currReq; + } else { + /* Remember the last setting, will report an error */ + masterReq->currReq = tmpCaps; + } + +done: + return status; +} + +/** + * PmRequirementUpdateScheduled() - Triggers the setting for scheduled requirements + * @master Master which changed the state and whose scheduled requirements are + * triggered + * @swap Flag stating should current requirement be saved as next + * + * a) swap=false + * Set scheduled requirements of a master without swapping current and + * next requirements - means the current requirements will be dropped. + * Upon every self suspend, master has to explicitly re-request + * slave requirements. + * b) swap=true + * Set scheduled requirements of a master with swapping current and + * next requirements (swapping means the current requirements will be + * saved as next, and will be configured once master wakes-up) + */ +void PmRequirementUpdateScheduled(const PmMaster* const master, const bool swap) +{ + u32 status; + PmRequirementId i; + + PmDbg("%s master %s\n", __func__, PmStrNode(master->procs[0].node.nodeId)); + + for (i = 0; i < master->reqsCnt; i++) { + if (master->reqs[i].currReq != master->reqs[i].nextReq) { + u32 tmpReq = master->reqs[i].nextReq; + + if (true == swap) { + /* Swap current and next requirements */ + master->reqs[i].nextReq = master->reqs[i].currReq; + } + + master->reqs[i].currReq = tmpReq; + + /* Update slave setting */ + status = PmUpdateSlave(master->reqs[i].slave); + /* if rom works correctly, status should be always ok */ + if (PM_RET_SUCCESS != status) { + PmDbg("%s ERROR setting slave node %s\n", + __func__, PmStrNode(master->reqs[i].slave->node.nodeId)); + } + } + } +} + +/** + * PmRequirementCancelScheduled() - Called when master aborts suspend, to cancel + * scheduled requirements (slave capabilities requests) + * @master Master whose scheduled requests should be cancelled + */ +void PmRequirementCancelScheduled(const PmMaster* const master) +{ + PmRequirementId i; + + for (i = 0; i < master->reqsCnt; i++) { + if (master->reqs[i].currReq != master->reqs[i].nextReq) { + /* Drop the scheduled request by making it constant */ + PmDbg("%s %s\n", + __func__, PmStrNode(master->reqs[i].slave->node.nodeId)); + master->reqs[i].nextReq = master->reqs[i].currReq; + } + } +} + +/** + * PmRequirementReleaseAll() - Called when master primary processor is forced to + * power down, so all requirements of the processor + * are automatically released. + * @master Master whose primary processor was forced to power down + */ +void PmRequirementReleaseAll(const PmMaster* const master) +{ + u32 status; + PmRequirementId i; + + for (i = 0; i < master->reqsCnt; i++) { + master->reqs[i].currReq = 0U; + master->reqs[i].nextReq = 0U; + /* Update slave setting */ + status = PmUpdateSlave(master->reqs[i].slave); + /* if pmu rom works correctly, status should be always ok */ + if (PM_RET_SUCCESS != status) { + PmDbg("%s ERROR setting slave node %s\n", + __func__, PmStrNode(master->reqs[i].slave->node.nodeId)); + } + } +} + +/** + * PmGetRequirementForSlave() - Get pointer to the master's request structure for + * a given slave + * @master Master whose request structure should be found + * @nodeId Slave nodeId + * + * @return Pointer to the master's request structure dedicated to a slave with + * given node. If such structure is not found, it means the master is + * not allowed to use the slave. + */ +PmRequirement* PmGetRequirementForSlave(const PmMaster* const master, + const PmNodeId nodeId) +{ + u32 i; + PmRequirement *req = NULL; + + for (i = 0; i < master->reqsCnt; i++) { + if (master->reqs[i].slave->node.nodeId == nodeId) { + req = &master->reqs[i]; + break; + } + } + + return req; +} + +/** + * PmEnableAllMasterIpis() - Iterate through all masters and enable their IPI + * interrupt + */ +void PmEnableAllMasterIpis(void) +{ + u8 i; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + XPfw_RMW32(IPI_PMU_0_IER, + pmAllMasters[i]->ipiMask, + pmAllMasters[i]->ipiMask); + } +} + +/** + * PmGetMasterByIpiMask() - Use to get pointer to master structure by ipi mask + * @mask IPI Mask of a master (requestor) in IPI registers + * + * @return Pointer to a PmMaster structure or NULL if master is not found + */ +const PmMaster* PmGetMasterByIpiMask(const u32 mask) +{ + u32 i; + const PmMaster *mst = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + if (mask == pmAllMasters[i]->ipiMask) { + mst = pmAllMasters[i]; + break; + } + } + + return mst; +} + +/** + * PmGetProcOfThisMaster() - Get processor pointer with given node id, if + * such processor exist within the master + * @master Master within which the search is performed + * @nodeId Node of the processor to be found + * + * @return Pointer to processor with the given node id (which is within the + * master), or NULL if such processor is not found. + */ +PmProc* PmGetProcOfThisMaster(const PmMaster* const master, + const PmNodeId nodeId) +{ + u32 i; + PmProc *proc = NULL; + + for (i = 0U; i < master->procsCnt; i++) { + if (nodeId == master->procs[i].node.nodeId) { + proc = &master->procs[i]; + } + } + + return proc; +} + +/** + * PmGetProcOfOtherMaster() - Get pointer to the processor with given node id, + * by excluding given master from the search + * @master Master to be excluded from search + * @nodeId Node id of the processor to be found + * + * @return Pointer to processor that is not within the master and which has + * given node id, or NULL if such processor is not found + */ +PmProc* PmGetProcOfOtherMaster(const PmMaster* const master, + const PmNodeId nodeId) +{ + u32 i; + PmProc *proc = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + u32 p; + + if (master == pmAllMasters[i]) { + continue; + } + + for (p = 0; p < pmAllMasters[i]->procsCnt; p++) { + if (nodeId == pmAllMasters[i]->procs[p].node.nodeId) { + proc = &pmAllMasters[i]->procs[p]; + goto done; + } + } + } + +done: + return proc; +} + +/** + * PmGetProcByNodeId() - Get a pointer to processor structure by the node id + * @nodeId Node of the processor to be found + * + * @return Pointer to a processor structure whose node is provided, or + * NULL if processor is not found + */ +PmProc* PmGetProcByNodeId(const PmNodeId nodeId) +{ + u32 i; + PmProc *proc = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + u32 p; + for (p = 0U; p < pmAllMasters[i]->procsCnt; p++) { + if (nodeId == pmAllMasters[i]->procs[p].node.nodeId) { + proc = &pmAllMasters[i]->procs[p]; + goto done; + } + } + } + +done: + return proc; +} + +/** + * PmGetProcByWfiStatus() - Get processor struct by wfi interrupt status + * @mask WFI interrupt mask read from GPI2 register + * + * @return Pointer to a processor structure whose wfi mask is provided, or + * NULL if processor is not found + */ +PmProc* PmGetProcByWfiStatus(const u32 mask) +{ + u32 i; + PmProc *proc = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + u32 p; + + for (p = 0U; p < pmAllMasters[i]->procsCnt; p++) { + if (mask & pmAllMasters[i]->procs[p].wfiStatusMask) { + proc = &pmAllMasters[i]->procs[p]; + goto done; + } + } + } + +done: + return proc; +} + +/** + * PmGetProcByWakeStatus() - Get proc struct by wake interrupt status + * @mask GIC wake mask read from GPI1 register + * + * @return Pointer to a processor structure whose wake mask is provided + */ +PmProc* PmGetProcByWakeStatus(const u32 mask) +{ + u32 i; + PmProc *proc = NULL; + + for (i = 0U; i < ARRAY_SIZE(pmAllMasters); i++) { + u32 p; + + for (p = 0U; p < pmAllMasters[i]->procsCnt; p++) { + if (mask & pmAllMasters[i]->procs[p].wakeStatusMask) { + proc = &pmAllMasters[i]->procs[p]; + goto done; + } + } + } + +done: + return proc; +} + +/** + * PmMasterGetAwakeProcCnt() - count how many processors within master are not + * in sleep state + * processor + * @master Pointer to the master whose awake processors are to be counted + * + * @return Number of awake processors within a master + */ +u32 PmMasterGetAwakeProcCnt(const PmMaster* const master) +{ + u32 i; + u32 activeCnt = 0U; + + for (i = 0U; i < master->procsCnt; i++) { + if (PM_PROC_STATE_ACTIVE == master->procs[i].node.currState) { + activeCnt++; + } + } + + return activeCnt; +} + +/** + * PmEnableProxyWake() - Enable scheduled wake-up sources in GIC Proxy + * @master Pointer to master whose scheduled wake-up sources should be enabled + * + * When FPD is powered down, wake-up sources are enabled in GIC Proxy + */ +void PmEnableProxyWake(PmMaster* const master) +{ + u32 i; + + PmDbg("%s %s\n", __func__, PmStrNode(master->procs->node.nodeId)); + + for (i = 0; i < master->reqsCnt; i++) { + if (master->reqs[i].info & PM_MASTER_WAKEUP_REQ_MASK) { + PmSlaveWakeEnable(master->reqs[i].slave); + } + } +} + +/** + * PmWakeUpCancelScheduled() - Cancel scheduled wake-up sources of the master + * @master Pointer to a master whose scheduled wake-up sources should be + * cancelled + */ +static void PmWakeUpCancelScheduled(PmMaster* const master) +{ + u32 i; + + PmDbg("%s %s\n", __func__, PmStrNode(master->procs->node.nodeId)); + + for (i = 0; i < master->reqsCnt; i++) { + master->reqs[i].info &= ~PM_MASTER_WAKEUP_REQ_MASK; + } +} + +/** + * PmWakeUpDisableAll() - Disable all wake-up sources of this master + * @master Pointer to a master whose wake-up sources are to be disabled + */ +static void PmWakeUpDisableAll(PmMaster* const master) +{ + u32 i; + + PmDbg("%s for %s\n", __func__, PmStrNode(master->procs->node.nodeId)); + + for (i = 0; i < master->reqsCnt; i++) { + PmMasterId r; + bool hasOtherReq = false; + + if (0U == (master->reqs[i].info & PM_MASTER_WAKEUP_REQ_MASK)) { + continue; + } + + master->reqs[i].info &= ~PM_MASTER_WAKEUP_REQ_MASK; + /* Check if there are other masters waiting for slave's wake-up */ + for (r = 0U; r < master->reqs[i].slave->reqsCnt; r++) { + if (0U != (master->reqs[i].slave->reqs[r]->info & + PM_MASTER_WAKEUP_REQ_MASK)) { + hasOtherReq = true; + break; + } + } + + if (false == hasOtherReq) { + /* No other masters waiting for wake, disable wake event */ + PmSlaveWakeDisable(master->reqs[i].slave); + } + } +} + +/** + * PmMasterNotify() - Notify master channel of a state change in its primary processor + * @master Pointer to master object which needs to be notified + * @event Processor Event to notify the master about + * + * Primary processor has changed its state, notify master to update its requirements + * accordingly. + */ +void PmMasterNotify(PmMaster* const master, const PmProcEvent event) +{ + switch (event) { + case PM_PROC_EVENT_SLEEP: + PmRequirementUpdateScheduled(master, true); + break; + case PM_PROC_EVENT_ABORT_SUSPEND: + PmRequirementCancelScheduled(master); + PmWakeUpCancelScheduled(master); + break; + case PM_PROC_EVENT_WAKE: + PmRequirementUpdateScheduled(master, false); + PmWakeUpDisableAll(master); + break; + case PM_PROC_EVENT_FORCE_PWRDN: + PmRequirementReleaseAll(master); + PmWakeUpCancelScheduled(master); + break; + default: + PmDbg("%s undefined event #%d\n", __func__, event); + break; + } +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_master.h b/lib/sw_apps/zynqmp_pmufw/src/pm_master.h new file mode 100644 index 00000000..5c6d0aa5 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_master.h @@ -0,0 +1,202 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * This file contains PM master related data structures and + * functions for accessing them. Also, each PM masters have defined + * data structures used for tracking it's requests for each slave's + * capabilities/states. + *********************************************************************/ + +#ifndef PM_MASTER_H_ +#define PM_MASTER_H_ + +#include "pm_slave.h" +#include "pm_common.h" +#include "pm_proc.h" +#include "pm_node.h" +#include "pm_power.h" +#include "xil_types.h" + +typedef u8 PmMasterId; +typedef u8 PmRequirementId; +typedef u8 PmMasterEvent; + +typedef struct PmMaster PmMaster; + +/********************************************************************* + * Macros + ********************************************************************/ +/* Supported masters (macros are used as indexes in array of all masters) */ +#define PM_MASTER_APU 0U +#define PM_MASTER_RPU_0 1U +#define PM_MASTER_RPU_1 2U +#define PM_MASTER_MAX 3U + +/* Master states */ +/* All processors within the master are sleeping */ +#define PM_MASTER_STATE_SLEEP 0U + +/* At least one processor within master is not sleeping */ +#define PM_MASTER_STATE_ACTIVE 1U + +/* Master FSM events */ +/* Triggered after a processor within the master goes to sleep */ +#define PM_MASTER_EVENT_SLEEP 1U + +/* Triggered before a processor within the master wakes-up */ +#define PM_MASTER_EVENT_WAKE 2U + +/* Triggered by abort suspend */ +#define PM_MASTER_EVENT_ABORT 3U + +/* Apu slaves */ +#define PM_MASTER_APU_SLAVE_OCM0 0U +#define PM_MASTER_APU_SLAVE_OCM1 1U +#define PM_MASTER_APU_SLAVE_OCM2 2U +#define PM_MASTER_APU_SLAVE_OCM3 3U +#define PM_MASTER_APU_SLAVE_L2 4U +#define PM_MASTER_APU_SLAVE_USB0 5U +#define PM_MASTER_APU_SLAVE_USB1 6U +#define PM_MASTER_APU_SLAVE_TTC0 7U +#define PM_MASTER_APU_SLAVE_SATA 8U +#define PM_MASTER_APU_SLAVE_MAX 9U + +/* Rpu0 slaves */ +#define PM_MASTER_RPU_0_SLAVE_TCM0A 0U +#define PM_MASTER_RPU_0_SLAVE_TCM0B 1U +#define PM_MASTER_RPU_0_SLAVE_TCM1A 2U +#define PM_MASTER_RPU_0_SLAVE_TCM1B 3U +#define PM_MASTER_RPU_0_SLAVE_OCM0 4U +#define PM_MASTER_RPU_0_SLAVE_OCM1 5U +#define PM_MASTER_RPU_0_SLAVE_OCM2 6U +#define PM_MASTER_RPU_0_SLAVE_OCM3 7U +#define PM_MASTER_RPU_0_SLAVE_USB0 8U +#define PM_MASTER_RPU_0_SLAVE_USB1 9U +#define PM_MASTER_RPU_0_SLAVE_TTC0 10U +#define PM_MASTER_RPU_0_SLAVE_SATA 11U +#define PM_MASTER_RPU_0_SLAVE_MAX 12U + +/* Pm Master request info masks */ +#define PM_MASTER_WAKEUP_REQ_MASK 0x40U +#define PM_MASTER_USING_SLAVE_MASK 0x80U +#define PM_MASTER_INDEX_MASK 0x3FU + +/********************************************************************* + * Structure definitions + ********************************************************************/ +/** + * PmRequirement - structure for tracking requirements of a master for the slave + * setting. One structure should be statically assigned for each + * possible combination of master/slave, because dynamic memory + * allocation cannot be used. + * @info Contains information about master's request - a bit for + * encoding has master requested or released node, other bits + * are used to encode master index in array of all masters. + * PM_MASTER_USING_SLAVE_MASK - extracts a bitfield for usage flag + * @slave Pointer to the slave structure + * @master Pointer to the master structure. Can be removed if need to + * optimize for space instead performance + * @currReq Currently holding requirements of a master for this slave + * @nextReq Requirements of a master to be configured when it changes the + * state (after it goes to sleep or before it gets awake) + */ +typedef struct PmRequirement { + PmSlave* const slave; + PmMaster* const requestor; + u8 info; + u32 currReq; + u32 nextReq; +} PmRequirement; + +/** + * PmMaster - contains PM master related informations + * @procs Pointer to the array of processors within the master + * @procsCnt Number of processors within the master + * @ipiMask Mask dedicated to the master in IPI registers + * @ipiTrigMask Trigger mask dedicated to the master in IPI registers + * @pmuBuffer IPI buffer address into which PMU can write (PMU's buffer) + * @buffer IPI buffer address into which this master can write + * (master's buffer) + * @reqs Pointer to the masters array of requirements for slave + * capabilities + * @reqsCnt Number of requirement elements (= worst case for number of + * used slaves) + */ +typedef struct PmMaster { + PmProc* const procs; + const u8 procsCnt; + const u32 ipiMask; + const u32 ipiTrigMask; + const u32 pmuBuffer; + const u32 buffer; + PmRequirement* const reqs; + const PmRequirementId reqsCnt; +} PmMaster; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmMaster pmMasterApu_g; +extern PmMaster pmMasterRpu0_g; +extern PmMaster pmMasterRpu1_g; + +extern PmRequirement pmApuReq_g[PM_MASTER_APU_SLAVE_MAX]; +extern PmRequirement pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_MAX]; + +/********************************************************************* + * Function declarations + ********************************************************************/ +/* Get functions */ +const PmMaster* PmGetMasterByIpiMask(const u32 mask); +PmProc* PmGetProcByWfiStatus(const u32 mask); +PmProc* PmGetProcByWakeStatus(const u32 mask); +PmProc* PmGetProcByNodeId(const PmNodeId nodeId); +PmProc* PmGetProcOfThisMaster(const PmMaster* const master, + const PmNodeId nodeId); +PmProc* PmGetProcOfOtherMaster(const PmMaster* const master, + const PmNodeId nodeId); +PmRequirement* PmGetRequirementForSlave(const PmMaster* const master, + const PmNodeId nodeId); +u32 PmMasterGetAwakeProcCnt(const PmMaster* const master); + +/* Requirements related functions */ +u32 PmRequirementSchedule(PmRequirement* const masterReq, const u32 caps); +u32 PmRequirementUpdate(PmRequirement* const masterReq, const u32 caps); +void PmRequirementUpdateScheduled(const PmMaster* const master, const bool swap); +void PmRequirementCancelScheduled(const PmMaster* const master); + +void PmEnableAllMasterIpis(void); +void PmMasterNotify(PmMaster* const master, const PmProcEvent event); +void PmEnableProxyWake(PmMaster* const master); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_node.c b/lib/sw_apps/zynqmp_pmufw/src/pm_node.c new file mode 100644 index 00000000..171fcc36 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_node.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Global array of all nodes, and GetbyId function + *********************************************************************/ + +#include "pm_node.h" +#include "pm_power.h" +#include "pm_proc.h" +#include "pm_slave.h" +#include "pm_sram.h" +#include "pm_usb.h" +#include "pm_periph.h" + +static PmNode* const pmNodes[NODE_MAX] = { + &pmApuProcs_g[PM_PROC_APU_0].node, + &pmApuProcs_g[PM_PROC_APU_1].node, + &pmApuProcs_g[PM_PROC_APU_2].node, + &pmApuProcs_g[PM_PROC_APU_3].node, + &pmRpuProcs_g[PM_PROC_RPU_0].node, + &pmRpuProcs_g[PM_PROC_RPU_1].node, + &pmPowerIslandRpu_g.node, + &pmPowerIslandApu_g.node, + &pmPowerDomainFpd_g.node, + &pmSlaveL2_g.slv.node, + &pmSlaveOcm0_g.slv.node, + &pmSlaveOcm1_g.slv.node, + &pmSlaveOcm2_g.slv.node, + &pmSlaveOcm3_g.slv.node, + &pmSlaveTcm0A_g.slv.node, + &pmSlaveTcm0B_g.slv.node, + &pmSlaveTcm1A_g.slv.node, + &pmSlaveTcm1B_g.slv.node, + &pmSlaveUsb0_g.slv.node, + &pmSlaveUsb1_g.slv.node, + &pmSlaveTtc0_g.slv.node, + &pmSlaveSata_g.slv.node, +}; + +/** + * PmGetNodeById() - Find node that matches a given node ID + * @nodeId ID of the node to find + * + * @returns Pointer to PmNode structure (or NULL if not found) + */ +PmNode* PmGetNodeById(const u32 nodeId) +{ + u32 i; + PmNode* node = NULL; + + for (i=0; i < NODE_MAX; i++) { + if (pmNodes[i]->nodeId == nodeId) { + node = pmNodes[i]; + break; + } + } + + return node; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_node.h b/lib/sw_apps/zynqmp_pmufw/src/pm_node.h new file mode 100644 index 00000000..ebba1892 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_node.h @@ -0,0 +1,134 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Pm Node related structures and definitions + *********************************************************************/ + +#ifndef PM_NODE_H_ +#define PM_NODE_H_ + +#include "pm_defs.h" +#include "pm_common.h" +#include "xil_types.h" + +typedef u8 PmNodeId; +typedef u8 PmStateId; +typedef u8 PmTransitionId; +typedef u8 PmNodeTypeId; +typedef u8 PmWakeEventId; + +/* Forward declaration */ +typedef struct PmPower PmPower; +typedef struct PmNode PmNode; + +/* Function pointer for wake/sleep transition functions */ +typedef u32 (*const PmNodeTranHandler)(PmNode* const nodePtr); + +/********************************************************************* + * Macros + ********************************************************************/ +/* Node types */ +#define PM_TYPE_PROC 1U +#define PM_TYPE_PWR_ISLAND 2U +#define PM_TYPE_PWR_DOMAIN 3U +#define PM_TYPE_SLAVE 4U +#define PM_TYPE_SRAM (PM_TYPE_SLAVE + 0U) +#define PM_TYPE_USB (PM_TYPE_SLAVE + 1U) +#define PM_TYPE_GPU_PP (PM_TYPE_SLAVE + 2U) +#define PM_TYPE_TTC (PM_TYPE_SLAVE + 3U) +#define PM_TYPE_SATA (PM_TYPE_SLAVE + 4U) + +#define IS_PROC(type) (PM_TYPE_PROC == type) + +#define IS_POWER(type) ((PM_TYPE_PWR_ISLAND == type) || \ + (PM_TYPE_PWR_DOMAIN == type)) + +#define IS_SLAVE(type) (type >= PM_TYPE_SLAVE) + +#define IS_OFF(nodePtr) (0U == BIT0((nodePtr)->currState)) + +#define HAS_SLEEP(opsPtr) ((NULL != opsPtr) && (NULL != (opsPtr)->sleep)) + +/* Wake events */ +#define PM_WAKE_EVENT_GPI1_APU0_GIC 0U +#define PM_WAKE_EVENT_GPI1_APU1_GIC 1U +#define PM_WAKE_EVENT_GPI1_APU2_GIC 2U +#define PM_WAKE_EVENT_GPI1_APU3_GIC 3U +#define PM_WAKE_EVENT_GPI1_RPU0_GIC 4U +#define PM_WAKE_EVENT_GPI1_RPU1_GIC 5U +#define PM_WAKE_EVENT_GPI1_USB0 6U +#define PM_WAKE_EVENT_GPI1_USB1 7U +#define PM_WAKE_EVENT_GPI1_FPD_PROX 8U +#define PM_WAKE_EVENT_GPI1_MAX 9U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +/** + * PmNodeOps - Node operations + * @sleep Put node into sleep (what the sleep is depends on node's type) + * @wake Wake up this node (procedure depends on node type) + */ +typedef struct PmNodeOps { + PmNodeTranHandler sleep; + PmNodeTranHandler wake; +} PmNodeOps; + +/** + * PmNode - Structure common for all entities that have node id + * @derived Pointer to a derived node type structure + * @nodeId Node id defined in pm_defs.h + * @typeId Type id, used to distinguish the nodes + * @parent Pointer to power parent node + * @currState Id of the node's current state. Interpretation depends on type + * of the node, bit 0 value is reserved for on/off states where + * 0=off and 1=on, so for any other on-state bit 0 must also be 1 + * and any other off-state bit 0 must be 0 + * (e.g. 0x2 for off with retention/saved context) + * @ops Pointer to the operations structure + */ +typedef struct PmNode { + void* const derived; + const PmNodeId nodeId; + const PmNodeTypeId typeId; + PmPower* const parent; + PmStateId currState; + const PmNodeOps* const ops; +} PmNode; + +/********************************************************************* + * Function declarations + ********************************************************************/ +PmNode* PmGetNodeById(const u32 nodeId); + +#endif /* PM_NODE_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c new file mode 100644 index 00000000..0e907c24 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.c @@ -0,0 +1,137 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "pm_periph.h" +#include "pm_common.h" +#include "pm_node.h" +#include "pm_master.h" + +/* + * Without clock/reset control, from PM perspective ttc has only one state. + * It is in LPD, which is never turned off, does not sit in power island, + * therefore has no off state. + */ +const u32 pmAonFsmStates[] = { + [PM_AON_SLAVE_STATE] = PM_CAP_WAKEUP | PM_CAP_ACCESS | PM_CAP_CONTEXT, +}; + +static const PmSlaveFsm slaveAonFsm = { + .states = pmAonFsmStates, + .statesCnt = ARRAY_SIZE(pmAonFsmStates), + .trans = NULL, + .transCnt = 0U, + .actions = NULL, +}; + +static PmWakeProperties pmTtc0Wake = { + .proxyIrqMask = FPD_GICP_TTC0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP1], +}; + +static PmRequirement* const pmTtc0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_TTC0], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_TTC0], +}; + +PmSlaveTtc pmSlaveTtc0_g = { + .slv = { + .node = { + .derived = &pmSlaveTtc0_g, + .nodeId = NODE_TTC_0, + .typeId = PM_TYPE_TTC, + .parent = NULL, + .currState = PM_AON_SLAVE_STATE, + .ops = NULL, + }, + .instId = 0U, + .reqs = pmTtc0Reqs, + .reqsCnt = ARRAY_SIZE(pmTtc0Reqs), + .wake = &pmTtc0Wake, + .slvFsm = &slaveAonFsm, + }, +}; + +/* + * Standard slave with no private PM properties to be controlled. + * It can be powered down with the power parent. + */ +const u32 pmStdStates_g[] = { + [PM_STD_SLAVE_STATE_OFF] = 0U, + [PM_STD_SLAVE_STATE_ON] = PM_CAP_WAKEUP | PM_CAP_ACCESS | PM_CAP_CONTEXT, +}; + +/* Standard slave transitions (from which to which state Std slave transits) */ +const PmStateTran pmStdTransitions_g[] = { + { + .fromState = PM_STD_SLAVE_STATE_ON, + .toState = PM_STD_SLAVE_STATE_OFF, + }, { + .fromState = PM_STD_SLAVE_STATE_OFF, + .toState = PM_STD_SLAVE_STATE_ON, + }, +}; + +static const PmSlaveFsm slaveStdFsm = { + .states = pmStdStates_g, + .statesCnt = ARRAY_SIZE(pmStdStates_g), + .trans = pmStdTransitions_g, + .transCnt = ARRAY_SIZE(pmStdTransitions_g), + .actions = NULL, +}; + +static PmWakeProperties pmSataWake = { + .proxyIrqMask = FPD_GICP_SATA_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP4], +}; + +static PmRequirement* const pmSataReqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_SATA], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_SATA], +}; + +PmSlaveSata pmSlaveSata_g = { + .slv = { + .node = { + .derived = &pmSlaveSata_g, + .nodeId = NODE_SATA, + .typeId = PM_TYPE_SATA, + .parent = &pmPowerDomainFpd_g, + .currState = PM_STD_SLAVE_STATE_ON, + .ops = NULL, + }, + .instId = 0U, + .reqs = pmSataReqs, + .reqsCnt = ARRAY_SIZE(pmSataReqs), + .wake = &pmSataWake, + .slvFsm = &slaveStdFsm, + }, +}; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h new file mode 100644 index 00000000..33c24a6a --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_periph.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef PM_PERIPH_H_ +#define PM_PERIPH_H_ + +#include "pm_slave.h" + +/********************************************************************* + * Macros + ********************************************************************/ +/* + * Standard slave states (used for generic slaves with trivial on/off) + * These slaves have no machanisms for controlling their own state, and their + * off state is controlled by the power parent state. + */ +#define PM_STD_SLAVE_STATE_OFF 0U +#define PM_STD_SLAVE_STATE_ON 1U + +/* Always-on slaves, have only one state */ +#define PM_AON_SLAVE_STATE 0U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +typedef struct PmSlaveTtc { + PmSlave slv; +} PmSlaveTtc; + +typedef struct PmSlaveSata { + PmSlave slv; +} PmSlaveSata; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmSlaveTtc pmSlaveTtc0_g; +extern PmSlaveSata pmSlaveSata_g; + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_power.c b/lib/sw_apps/zynqmp_pmufw/src/pm_power.c new file mode 100644 index 00000000..d023b3ce --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_power.c @@ -0,0 +1,507 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Power nodes (power islands and power domains) related structures, + * transition actions, and FSM definition. + *********************************************************************/ + +#include "pm_power.h" +#include "pm_common.h" +#include "pm_proc.h" +#include "pm_master.h" +#include "pm_sram.h" +#include "pm_periph.h" +#include "xpfw_rom_interface.h" + +/** + * PmPwrDnHandler() - Power down island/domain + * @nodePtr Pointer to node-structure of power island/dom to be powered off + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + */ +static u32 PmPwrDnHandler(PmNode* const nodePtr) +{ + u32 ret = PM_RET_ERROR_FAILURE; + + if (NULL == nodePtr) { + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + /* Call proper PMU-ROM handler as needed */ + switch (nodePtr->nodeId) { + case NODE_FPD: + ret = XpbrRstFpdHandler(); + if (ret == XST_SUCCESS) { + ret = XpbrPwrDnFpdHandler(); + /* + * When FPD is powered off, the APU-GIC will be affected too. + * GIC Proxy has to take over for all wake-up sources for + * the APU. + */ + PmEnableProxyWake(&pmMasterApu_g); + } + break; + case NODE_APU: + ret = XST_SUCCESS; + break; + case NODE_RPU: + ret = XpbrPwrDnRpuHandler(); + break; + default: + PmDbg("%s - unsupported node %s(%d)\n", __func__, + PmStrNode(nodePtr->nodeId), nodePtr->nodeId); + break; + } + + if (XST_SUCCESS != ret) { + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + nodePtr->currState = PM_PWR_STATE_OFF; + ret = PM_RET_SUCCESS; + +done: + PmDbg("%s %s\n", __func__, PmStrNode(nodePtr->nodeId)); + return ret; +} + +/** + * PmPwrUpHandler() - Power up island/domain + * @nodePtr Pointer to node-structure of power island/dom to be powered on + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + */ +static u32 PmPwrUpHandler(PmNode* const nodePtr) +{ + u32 ret = PM_RET_ERROR_FAILURE; + + PmDbg("%s %s\n", __func__, PmStrNode(nodePtr->nodeId)); + + if (NULL == nodePtr) { + goto done; + } + + /* Call proper PMU-ROM handler as needed */ + switch (nodePtr->nodeId) { + case NODE_FPD: + ret = XpbrPwrUpFpdHandler(); + PmDbg("%s XpbrPwrUpFpdHandler return code #%d\n", __func__, ret); + /* FIXME workaround for old version of pmu-rom */ + PmDbg("%s ignoring error\n", __func__); + ret = XST_SUCCESS; + break; + case NODE_APU: + ret = XST_SUCCESS; + break; + case NODE_RPU: + ret = XpbrPwrUpRpuHandler(); + break; + default: + PmDbg("%s ERROR - unsupported node %s(%d)\n", __func__, + PmStrNode(nodePtr->nodeId), nodePtr->nodeId); + break; + } + + if (XST_SUCCESS != ret) { + PmDbg("%s failed to power up %s PBR ERROR #%d\n", __func__, + PmStrNode(nodePtr->nodeId), ret); + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + nodePtr->currState = PM_PWR_STATE_ON; + ret = PM_RET_SUCCESS; + +done: + return ret; +} + +/* Children array definitions */ +static PmNode* pmApuChildren[] = { + &pmApuProcs_g[PM_PROC_APU_0].node, + &pmApuProcs_g[PM_PROC_APU_1].node, + &pmApuProcs_g[PM_PROC_APU_2].node, + &pmApuProcs_g[PM_PROC_APU_3].node, +}; + +static PmNode* pmRpuChildren[] = { + &pmRpuProcs_g[PM_PROC_RPU_0].node, + &pmRpuProcs_g[PM_PROC_RPU_1].node, +}; + +static PmNode* pmFpdChildren[] = { + &pmPowerIslandApu_g.node, + &pmSlaveL2_g.slv.node, + &pmSlaveSata_g.slv.node, +}; + +/* Operations for the Rpu power island */ +static const PmNodeOps pmRpuNodeOps = { + .sleep = PmPwrDnHandler, + .wake = PmPwrUpHandler, +}; + +/* Operations for the Apu dummy power island */ +static const PmNodeOps pmApuNodeOps = { + .sleep = PmPwrDnHandler, + .wake = PmPwrUpHandler, +}; + +/* Operations for the Fpd power domain */ +static const PmNodeOps pmFpdNodeOps = { + .sleep = PmPwrDnHandler, + .wake = PmPwrUpHandler, +}; + +/* + * Power Island and Power Domain definitions + * + * We only define those islands and domains containing more than 1 node. + * For optimization reasons private power islands, such as APU0-island or + * USB0-island are modeled as a feature of the node itself and are therefore + * not described here. + */ +PmPower pmPowerIslandRpu_g = { + .node = { + .derived = &pmPowerIslandRpu_g, + .nodeId = NODE_RPU, + .typeId = PM_TYPE_PWR_ISLAND, + .parent = NULL, + .currState = PM_PWR_STATE_ON, + .ops = &pmRpuNodeOps, + }, + .children = pmRpuChildren, + .childCnt = ARRAY_SIZE(pmRpuChildren), +}; + +/* Apu power island does not physically exist, therefore it has no operations */ +PmPower pmPowerIslandApu_g = { + .node = { + .derived = &pmPowerIslandApu_g, + .nodeId = NODE_APU, + .typeId = PM_TYPE_PWR_ISLAND, + .parent = &pmPowerDomainFpd_g, + .currState = PM_PWR_STATE_ON, + .ops = &pmApuNodeOps, + }, + .children = pmApuChildren, + .childCnt = ARRAY_SIZE(pmApuChildren), +}; + +PmPower pmPowerDomainFpd_g = { + .node = { + .derived = &pmPowerDomainFpd_g, + .nodeId = NODE_FPD, + .typeId = PM_TYPE_PWR_DOMAIN, + .parent = NULL, + .currState = PM_PWR_STATE_ON, + .ops = &pmFpdNodeOps, + }, + .children = pmFpdChildren, + .childCnt = ARRAY_SIZE(pmFpdChildren), +}; + +/** + * PmChildIsInLowestPowerState() - Checked whether the child node is in lowest + * power state + * @nodePtr Pointer to a node whose state should be checked + */ +static bool PmChildIsInLowestPowerState(const PmNode* const nodePtr) +{ + bool status = false; + + if ((true == IS_PROC(nodePtr->typeId)) || + (true == IS_POWER(nodePtr->typeId))) { + if (true == IS_OFF(nodePtr)) { + status = true; + } + } else { + /* Node is a slave */ + if (false == PmSlaveHasCapRequests((PmSlave*)nodePtr->derived)) { + status = true; + } + } + + return status; +} + +/** + * PmHasAwakeChild() - Check whether power node has awake children + * @power Pointer to PmPower object to be checked + * + * Function checks whether any child of the power provided as argument stops + * power from being turned off. In the case of processor or power child, that + * can be checked by inspecting currState value. For slaves, that is not the + * case, as slave can be in non-off state just because the off state is entered + * when power is turned off. This is the case when power parent is common for + * multiple nodes. Therefore, slave does not block power from turning off if + * it is unused and not in lowest power state. + * + * @return True if it has a child that is not off + */ +static bool PmHasAwakeChild(const PmPower* const power) +{ + u32 i; + bool hasAwakeChild = false; + + for (i = 0U; i < power->childCnt; i++) { + if (false == PmChildIsInLowestPowerState(power->children[i])) { + hasAwakeChild = true; + PmDbg("%s %s\n", __func__, + PmStrNode(power->children[i]->nodeId)); + break; + } + } + + return hasAwakeChild; +} + +/** + * PmOpportunisticSuspend() - After a node goes to sleep, try to power off + * parents + * @powerParent Pointer to the power node which should try to suspend, as well + * its parents. + */ +void PmOpportunisticSuspend(PmPower* const powerParent) +{ + PmPower* power = powerParent; + + if (NULL == powerParent) { + goto done; + } + + do { + PmDbg("Opportunistic suspend attempt for %s\n", + PmStrNode(power->node.nodeId)); + + if ((false == PmHasAwakeChild(power)) && + (true == HAS_SLEEP(power->node.ops))) { + /* Call sleep function of this power node */ + power->node.ops->sleep(&power->node); + power = power->node.parent; + } else { + power = NULL; + } + } while (NULL != power); + +done: + return; +} + +/** + * PmPowerUpTopParent() - Power up top parent in hierarchy that's currently off + * @powerChild Power child whose power parent has to be powered up + * + * @return Status of the power up operation (always PM_RET_SUCCESS if all + * power parents are already powered on) + * + * This function turns on exactly one power parent, starting with the highest + * level parent that's currently off. If all power parents are on, it will + * turn on "powerChild", which was passed as an argument. + * + * Since MISRA-C doesn't allow recursion, there's an iterative algorithm in + * PmTriggerPowerUp that calls this function iteratively until all power + * nodes in the hierarchy are powered up. + */ +static u32 PmPowerUpTopParent(PmPower* const powerChild) +{ + u32 status = PM_RET_SUCCESS; + PmPower* powerParent = powerChild; + + if (NULL == powerParent) { + status = PM_RET_ERROR_INTERNAL; + goto done; + } + + /* + * Powering up needs to happen from the top down, so find the highest + * level parent that's currently still off and turn it on. + */ + while ((NULL != powerParent->node.parent) && + (true == IS_OFF(&powerParent->node.parent->node))) { + powerParent = powerChild->node.parent; + } + + status = powerParent->node.ops->wake(&powerParent->node); + +done: + return status; +} + +/** + * PmTriggerPowerUp() - Triggered by child node (processor or slave) when it + * needs its power islands/domains to be powered up + * @power Power node that needs to be powered up + * + * @return Status of the power up operation. + */ +u32 PmTriggerPowerUp(PmPower* const power) +{ + u32 status = PM_RET_SUCCESS; + + if (NULL == power) { + goto done; + } + + /* + * Multiple hierarchy levels of power islands/domains may need to be + * turned on (always top-down). + * Use iterative approach for MISRA-C compliance + */ + while ((true == IS_OFF(&power->node)) && (PM_RET_SUCCESS == status)) { + status = PmPowerUpTopParent(power); + } + +done: + if (PM_RET_SUCCESS != status) { + PmDbg("%s failed to power up: ERROR #%d\n", __func__, status); + } + + return status; +} + +/** + * PmGetLowestParent() - Returns the first leaf parent with active children + * @root Pointer to a power object of which the leafs should be found + * + * In a parent-child tree, a leaf parent is a parent that has one or more + * children, where none of the children are parents. + * (Any state != 0 is considered an active state) + * + * Iterative algorithm for MISRA-C compliance + * + * @return Pointer to an active leaf or root itself if no leafs exist + */ +static PmPower* PmGetLowestParent(PmPower* const root) +{ + PmPower* prevParent; + PmPower* currParent = root; + + if (NULL == currParent) { + goto done; + } + + do { + u32 i; + prevParent = currParent; + + for (i = 0U; i < currParent->childCnt; i++) { + if ((true != IS_POWER(currParent->children[i]->typeId)) || + (false != IS_OFF(currParent->children[i]))) { + continue; + } + + /* Active power child found */ + currParent = (PmPower*)currParent->children[i]->derived; + break; + } + } while (currParent != prevParent); + +done: + return currParent; +} + +/** + * PmForcePowerDownChildren() - Forces power down for child nodes + * @parent pointer to power object whose children are to be turned off + */ +static void PmForcePowerDownChildren(const PmPower* const parent) +{ + u32 i; + PmNode* child; + PmProc* proc; + + for (i = 0U; i < parent->childCnt; i++) { + child = parent->children[i]; + + if ((false != PmChildIsInLowestPowerState(child)) || + (true != HAS_SLEEP(child->ops))) { + continue; + } + + PmDbg("Powering OFF child node %s\n", PmStrNode(child->nodeId)); + + /* Force the child's state to 0, which is its lowest power state */ + child->ops->sleep(child); + child->currState = 0U; + + /* Special case: node is a processor, release slave-requirements */ + if (PM_TYPE_PROC == child->typeId) { + proc = (PmProc*)child->derived; + + if ((NULL !=proc) && (true == proc->isPrimary)) { + /* Notify master so it can release all requirements */ + PmMasterNotify(proc->master, PM_PROC_EVENT_FORCE_PWRDN); + } + } + } + + return; +} + +/** + * PmForceDownTree() - Force power down node and all its children + * @root power node (island/domain) to turn off + * + * This is a power island or power domain, power it off from the bottom up: + * find out if this parent has children which themselves have children. + * Note: using iterative algorithm for MISRA-C compliance + * (instead of recursion) + * + */ +u32 PmForceDownTree(PmPower* const root) +{ + PmPower* lowestParent; + u32 status = PM_RET_SUCCESS; + + if (NULL == root) { + goto done; + } + + do { + lowestParent = PmGetLowestParent(root); + PmForcePowerDownChildren(lowestParent); + if (true == HAS_SLEEP(lowestParent->node.ops)) { + status = lowestParent->node.ops->sleep(&lowestParent->node); + } + } while ((lowestParent != root) && (status == PM_RET_SUCCESS)); + +done: + return status; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_power.h b/lib/sw_apps/zynqmp_pmufw/src/pm_power.h new file mode 100644 index 00000000..e0ece3d4 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_power.h @@ -0,0 +1,85 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Power nodes (power islands and power domains) related structures + * and functions + *********************************************************************/ + +#ifndef PM_POWER_H_ +#define PM_POWER_H_ + +#include "pm_common.h" +#include "pm_node.h" + +/********************************************************************* + * Macros + ********************************************************************/ +/* States of power island/domain */ +#define PM_PWR_STATE_OFF 0U +#define PM_PWR_STATE_ON 1U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +/** + * PmPower - Structure for power related nodes + * Basically an abstraction of power islands and power domains. + * Not all power entities in the system have this struct. If a node has + * its own power, which does not depend to other nodes, its power is + * controlled within its transition actions. Otherwise, this power + * structure must exist. + * @node Node structure of this power entity + * @children Pointer to the array of children + * @childCnt Number of childs in children array + */ +typedef struct PmPower { + PmNode node; + PmNode** const children; + const PmNodeId childCnt; +} PmPower; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmPower pmPowerIslandRpu_g; +extern PmPower pmPowerIslandApu_g; +extern PmPower pmPowerDomainFpd_g; + +/********************************************************************* + * Function declarations + ********************************************************************/ +void PmOpportunisticSuspend(PmPower* const power); +u32 PmTriggerPowerUp(PmPower* const power); +u32 PmForceDownTree(PmPower* const root); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_proc.c b/lib/sw_apps/zynqmp_pmufw/src/pm_proc.c new file mode 100644 index 00000000..b3c88693 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_proc.c @@ -0,0 +1,518 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of processors and finite state machine + * used for managing processor's power states. + * Every processor must have: + * 1. Entry in GPI1 register for wfi interrupt (wfi enable and status + * masks) + * 2. Entry in GPI2 register for GIC wake interrupt (wake enable and + * status masks) + * 3. Operations structure in node definition with: + * - wake function pointer, that is always releasing reset and + * might include some more actions regarding the processor's + * state setting. + * - sleep function might exist but doesn't have to. For example, + * APU processors have sleep that powers down processor island, + * but RPU processors have no private objects whose state can + * be changed at this point. In future, every processor should + * have sleep function in which its clock will be gated. + *********************************************************************/ + +#include "pm_defs.h" +#include "pm_proc.h" +#include "pm_master.h" +#include "xpfw_rom_interface.h" + +/** + * PmProcSleep() - Put a processor to sleep + * @nodePtr Pointer to node-structure of processor to be put to sleep + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + */ +u32 PmProcSleep(PmNode* const nodePtr) +{ + u32 ret; + + if (NULL == nodePtr) { + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + /* Call proper PMU-ROM handler as needed */ + switch (nodePtr->nodeId) { + case NODE_APU_0: + ret = XpbrACPU0SleepHandler(); + break; + case NODE_APU_1: + ret = XpbrACPU1SleepHandler(); + break; + case NODE_APU_2: + ret = XpbrACPU2SleepHandler(); + break; + case NODE_APU_3: + ret = XpbrACPU3SleepHandler(); + break; + default: + ret = XST_SUCCESS; + break; + } + + if (XST_SUCCESS != ret) { + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + nodePtr->currState = PM_PROC_STATE_SLEEP; + ret = PM_RET_SUCCESS; + +done: + return ret; +} + +/** + * PmProcWake() - Wake up a processor node + * @nodePtr Pointer to node-structure of processor to be woken-up + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + */ +u32 PmProcWake(PmNode* const nodePtr) +{ + u32 ret = PM_RET_SUCCESS; + + if (NULL == nodePtr) { + ret = PM_RET_ERROR_INTERNAL; + goto done; + } + + if (PM_PWR_STATE_OFF == nodePtr->parent->node.currState) { + /* Power parent is down, trigger its powering up */ + ret = PmTriggerPowerUp(nodePtr->parent); + } + + if (PM_RET_SUCCESS != ret) { + goto done; + } + + /* Call proper PMU-ROM handler as needed */ + switch (nodePtr->nodeId) { + case NODE_APU_0: + ret = XpbrACPU0WakeHandler(); + break; + case NODE_APU_1: + ret = XpbrACPU1WakeHandler(); + break; + case NODE_APU_2: + ret = XpbrACPU2WakeHandler(); + break; + case NODE_APU_3: + ret = XpbrACPU3WakeHandler(); + break; + case NODE_RPU_0: + ret = XpbrRstR50Handler(); + break; + case NODE_RPU_1: + ret = XpbrRstR51Handler(); + break; + default: + ret = XST_SUCCESS; + break; + } + + if (XST_SUCCESS != ret) { + ret = PM_RET_ERROR_FAILURE; + goto done; + } + + nodePtr->currState = PM_PROC_STATE_ACTIVE; + ret = PM_RET_SUCCESS; + +done: + return ret; +} + +/** + * PmProcTrActiveToSuspend() - FSM transition from active to suspend state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS is always returned as this transition cannot fail + * + * @note Executes when processor's request for self suspend gets processed. + */ +static u32 PmProcTrActiveToSuspend(PmProc* const proc) +{ + PmDbg("ACTIVE->SUSPENDING %s\n", PmStrNode(proc->node.nodeId)); + + ENABLE_WFI(proc->wfiEnableMask); + proc->node.currState = PM_PROC_STATE_SUSPENDING; + + return PM_RET_SUCCESS; +} + +/** + * PmProcTrToForcedOff() - FSM transition from active to force powerdown + * state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + * - PM_RET_ERROR_INTERNAL if processor structures are incorrectly + * initialized + * + * @note Executes when some other processor authorized to do so requests + * through PM API the PMU to powered down this processor. This + * processor is not informed about the following power down and + * therefore PMU does not wait for it to execute wfi. If processor has + * no implemented sleep function it will continue executing + * instructions. + */ +static u32 PmProcTrToForcedOff(PmProc* const proc) +{ + u32 status; + + PmDbg("ACTIVE->FORCED_PWRDN %s\n", PmStrNode(proc->node.nodeId)); + + status = PmProcSleep(&proc->node); + /* Override the state set in PmProcSleep to indicate FORCED OFF */ + proc->node.currState = PM_PROC_STATE_FORCEDOFF; + if (true == proc->isPrimary) { + /* Notify master to release all requirements of this processor */ + PmMasterNotify(proc->master, PM_PROC_EVENT_FORCE_PWRDN); + } + + return status; +} + +/** + * PmProcTrSuspendToActive() - FSM transition from suspend to active state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS is always returned as this transition cannot fail + * + * @note Executes when processor requests abort suspend through PM API. + */ +static u32 PmProcTrSuspendToActive(PmProc* const proc) +{ + PmDbg("SUSPENDING->ACTIVE %s\n", PmStrNode(proc->node.nodeId)); + + DISABLE_WFI(proc->wfiEnableMask); + DISABLE_WAKE(proc->wakeEnableMask); + + /* Notify master to cancel scheduled requests */ + PmMasterNotify(proc->master, PM_PROC_EVENT_ABORT_SUSPEND); + proc->node.currState = PM_PROC_STATE_ACTIVE; + + return PM_RET_SUCCESS; +} + +/** + * PmProcTrSuspendToSleep() - FSM transition from suspend to sleep state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + * - PM_RET_ERROR_INTERNAL if processor structures are incorrectly + * initialized + * + * @note Processor had previously called self suspend and now PMU has + * received processor's wfi interrupt. + */ +static u32 PmProcTrSuspendToSleep(PmProc* const proc) +{ + u32 status; + + PmDbg("SUSPENDING->SLEEP %s\n", PmStrNode(proc->node.nodeId)); + + status = PmProcSleep(&proc->node); + if (true == proc->isPrimary) { + /* + * Notify master to update slave capabilities according to the + * scheduled requests for after primary processor goes to sleep. + */ + PmMasterNotify(proc->master, PM_PROC_EVENT_SLEEP); + } + DISABLE_WFI(proc->wfiEnableMask); + ENABLE_WAKE(proc->wakeEnableMask); + + return status; +} + +/** + * PmProcTrSleepToActive() - FSM transition from sleep to active state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + * - PM_RET_ERROR_INTERNAL if processor structures are incorrectly + * initialized + * + * @note Processor had previously called self suspend and before it had + * executed wfi PMU has received PM API request to force power down + * of this processor. Therefore, PMU does not wait for wfi interrupt + * from this processor to come, but puts it to sleep. + */ +static u32 PmProcTrSleepToActive(PmProc* const proc) +{ + u32 status; + + if (true == proc->isPrimary) { + /* + * Notify master to update slave capabilities according to the + * scheduled requests for before the primary processor + * gets woken-up. + */ + PmMasterNotify(proc->master, PM_PROC_EVENT_WAKE); + } + + PmDbg("SLEEP->ACTIVE %s\n", PmStrNode(proc->node.nodeId)); + + status = PmProcWake(&proc->node); + + /* Keep wfi interrupt disabled while processor is active */ + DISABLE_WFI(proc->wfiEnableMask); + DISABLE_WAKE(proc->wakeEnableMask); + + return status; +} + +/** + * PmProcTrForcePwrdnToActive() - FSM transition from forced powerdown to active + * state + * @proc Pointer to processor whose FSM is changing state + * + * @return Operation status + * - PM_RET_SUCCESS if transition succeeded + * - PM_RET_ERROR_FAILURE if pmu rom failed to set the state + * - PM_RET_ERROR_INTERNAL if processor does not have wake function + * + * @note Processor had previously called self suspend and before it had + * executed wfi PMU has received PM API request to force power down + * of this processor. Therefore, PMU does not wait for wfi interrupt + * from this processor to come, but puts it to sleep. + */ +static u32 PmProcTrForcePwrdnToActive(PmProc* const proc) +{ + u32 status; + + PmDbg("FORCED_PWRDN->ACTIVE %s\n", PmStrNode(proc->node.nodeId)); + + status = PmProcWake(&proc->node); + + return status; +} + +/** + * PmProcFsm() - Implements finite state machine (FSM) for a processor + * @proc Pointer to the processor the event is for + * @event Processor-specific event to act upon + * + * @note This FSM coordinates the state transitions for an individual + * processor. + */ +u32 PmProcFsm(PmProc* const proc, const PmProcEvent event) +{ + u32 status = PM_RET_SUCCESS; + u32 currState = proc->node.currState; + + switch (event) { + case PM_PROC_EVENT_SELF_SUSPEND: + if (PM_PROC_STATE_ACTIVE == currState) { + status = PmProcTrActiveToSuspend(proc); + } else { + PmDbg("%s illegal state %d for SUSPND event\n", + __func__, currState); + status = PM_RET_ERROR_INTERNAL; + } + break; + case PM_PROC_EVENT_FORCE_PWRDN: + if (PM_PROC_STATE_SUSPENDING == currState) { + DISABLE_WFI(proc->wfiEnableMask); + } + status = PmProcTrToForcedOff(proc); + break; + case PM_PROC_EVENT_ABORT_SUSPEND: + if (PM_PROC_STATE_SUSPENDING == currState) { + status = PmProcTrSuspendToActive(proc); + } else { + PmDbg("%s illegal state %d for ABORT event\n", + __func__, currState); + status = PM_RET_ERROR_INTERNAL; + } + break; + case PM_PROC_EVENT_SLEEP: + if (PM_PROC_STATE_SUSPENDING == currState) { + status = PmProcTrSuspendToSleep(proc); + } else { + PmDbg("%s illegal state %d for SLEEP event\n", + __func__, currState); + status = PM_RET_ERROR_INTERNAL; + } + break; + case PM_PROC_EVENT_WAKE: + if (PM_PROC_STATE_SLEEP == currState) { + status = PmProcTrSleepToActive(proc); + } else if (PM_PROC_STATE_FORCEDOFF == currState) { + status = PmProcTrForcePwrdnToActive(proc); + } else { + PmDbg("%s illegal state %d for WAKE event\n", + __func__, currState); + status = PM_RET_ERROR_INTERNAL; + } + break; + default: + PmDbg("%s unrecognized event\n", __func__, event); + status = PM_RET_ERROR_INTERNAL; + break; + } + + return status; +} + +/* NodeOps for all processors */ +static const PmNodeOps pmProcOps = { + .sleep = PmProcSleep, + .wake = PmProcWake, +}; + +/* Apu processors */ +PmProc pmApuProcs_g[PM_PROC_APU_MAX] = { + [PM_PROC_APU_0] = { + .node = { + .derived = &pmApuProcs_g[PM_PROC_APU_0], + .nodeId = NODE_APU_0, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandApu_g, + .currState = PM_PROC_STATE_ACTIVE, + .ops = &pmProcOps, + }, + .master = &pmMasterApu_g, + .isPrimary = true, + .wfiStatusMask = PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_MASK, + }, + [PM_PROC_APU_1] = { + .node = { + .derived = &pmApuProcs_g[PM_PROC_APU_1], + .nodeId = NODE_APU_1, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandApu_g, + .currState = PM_PROC_STATE_SLEEP, + .ops = &pmProcOps, + }, + .master = &pmMasterApu_g, + .isPrimary = false, + .wfiStatusMask = PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_MASK, + }, + [PM_PROC_APU_2] = { + .node = { + .derived = &pmApuProcs_g[PM_PROC_APU_2], + .nodeId = NODE_APU_2, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandApu_g, + .currState = PM_PROC_STATE_SLEEP, + .ops = &pmProcOps, + }, + .master = &pmMasterApu_g, + .isPrimary = false, + .wfiStatusMask = PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_MASK, + }, + [PM_PROC_APU_3] = { + .node = { + .derived = &pmApuProcs_g[PM_PROC_APU_3], + .nodeId = NODE_APU_3, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandApu_g, + .currState = PM_PROC_STATE_SLEEP, + .ops = &pmProcOps, + }, + .master = &pmMasterApu_g, + .isPrimary = false, + .wfiStatusMask = PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_MASK, + } +}; + +/* Rpu processors */ +PmProc pmRpuProcs_g[PM_PROC_RPU_MAX] = { + [PM_PROC_RPU_0] = { + .node = { + .derived = &pmRpuProcs_g[PM_PROC_RPU_0], + .nodeId = NODE_RPU_0, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandRpu_g, + .currState = PM_PROC_STATE_ACTIVE, + .ops = &pmProcOps, + }, + .master = &pmMasterRpu0_g, + .isPrimary = true, + .wfiStatusMask = PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_R5_0_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_MASK, + }, + [PM_PROC_RPU_1] = { + .node = { + .derived = &pmRpuProcs_g[PM_PROC_RPU_1], + .nodeId = NODE_RPU_1, + .typeId = PM_TYPE_PROC, + .parent = &pmPowerIslandRpu_g, + .currState = PM_PROC_STATE_SLEEP, + .ops = &pmProcOps, + }, + .master = &pmMasterRpu1_g, + .isPrimary = false, + .wfiStatusMask = PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK, + .wakeStatusMask = PMU_IOMODULE_GPI1_R5_1_WAKE_MASK, + .wfiEnableMask = PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_MASK, + .wakeEnableMask = PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_MASK, + }, +}; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_proc.h b/lib/sw_apps/zynqmp_pmufw/src/pm_proc.h new file mode 100644 index 00000000..72ae89a0 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_proc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Contains all functions, datas and definitions needed for + * managing processor's states. + *********************************************************************/ + +#ifndef PM_PROC_H_ +#define PM_PROC_H_ + +#include "pm_common.h" +#include "pm_node.h" + +typedef u8 PmProcEvent; + +/********************************************************************* + * Macros + ********************************************************************/ +/* Used for designated initialization */ +#define PM_PROC_APU_0 0U +#define PM_PROC_APU_1 1U +#define PM_PROC_APU_2 2U +#define PM_PROC_APU_3 3U +#define PM_PROC_APU_MAX 4U + +#define PM_PROC_RPU_0 0U +#define PM_PROC_RPU_1 1U +#define PM_PROC_RPU_MAX 2U + +/* Enable/disable macros for processor's wfi event in GPI2 register */ +#define ENABLE_WFI(mask) XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, mask, mask); +#define DISABLE_WFI(mask) XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, mask, ~(mask)); + +/* + * Processor is powered down as requested by a master which is priviledged + * to request so. Processor has not saved its context. + */ +#define PM_PROC_STATE_FORCEDOFF 0U + +/* + * Processor sleep state (specific for the processor implementation, + * if processor has its own power domain it is powered down) + */ +#define PM_PROC_STATE_SLEEP 2U + +/* + * Processor active state. If it executes WFI without previously requesting + * suspend through PM API it is considered active. + */ +#define PM_PROC_STATE_ACTIVE 1U + +/* + * Processor suspending state. It has called pm_self_suspend but WFI + * interrupt from this processor is not yet received. + */ +#define PM_PROC_STATE_SUSPENDING 3U + +/* Triggered when pm_self_suspend call is received for a processor */ +#define PM_PROC_EVENT_SELF_SUSPEND 1U + +/* + * Triggered by pm_abort_suspend call made by a processor to cancel its + * own suspend. + */ +#define PM_PROC_EVENT_ABORT_SUSPEND 2U + +/* Triggered when processor has executed wfi instruction */ +#define PM_PROC_EVENT_SLEEP 3U + +/* Triggered when a master requested force powerdown for this processor */ +#define PM_PROC_EVENT_FORCE_PWRDN 4U + +/* Triggered when PMU receives wake interrupt targeted to the processor */ +#define PM_PROC_EVENT_WAKE 5U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +typedef struct PmMaster PmMaster; +/** + * PmProc - Processor node's structure + * @node Processor's node structure + * @master Master channel used by this processor + * @isPrimary True if this is a primary core (owner of Master channel) + * @wfiStatusMask Mask in PM_IOMODULE_GPI2 register (WFI interrupt) + * @wakeStatusMask Mask in PM_IOMODULE_GPI1 register (GIC wake interrupt) + * @wfiEnableMask Mask in PM_LOCAL_GPI2_ENABLE register (WFI interrupt) + * @wakeEnableMask mask in PM_LOCAL_GPI1_ENABLE register (GIC wake interrupt) + */ +typedef struct { + PmNode node; + PmMaster* const master; + bool isPrimary; + const u32 wfiStatusMask; + const u32 wakeStatusMask; + const u32 wfiEnableMask; + const u32 wakeEnableMask; +} PmProc; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmProc pmApuProcs_g[PM_PROC_APU_MAX]; +extern PmProc pmRpuProcs_g[PM_PROC_RPU_MAX]; + +/********************************************************************* + * Function declarations + ********************************************************************/ +u32 PmProcFsm(PmProc* const proc, const PmProcEvent event); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c new file mode 100644 index 00000000..00db9bad --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.c @@ -0,0 +1,381 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/************************************************************************* + * PM slave structures definitions and code for handling states of slaves. + ************************************************************************/ + +#include "pm_slave.h" +#include "pm_master.h" +#include "pm_defs.h" +#include "pm_common.h" +#include "pm_node.h" +#include "pm_sram.h" +#include "pm_usb.h" +#include "pm_periph.h" +#include "pm_power.h" + +/* Used for tracking number of enabled interrupts in each GIC Proxy group */ +PmGicProxyProperties gicProxyGroups_g[FPD_GICP_GROUP_MAX] = { + [FPD_GICP_GROUP0] = { + .baseAddr = FPD_GICP_GROUP0_BASE_ADDR, + .pmuIrqBit = FPD_GICP_PMU_IRQ_GROUP0, + }, + [FPD_GICP_GROUP1] = { + .baseAddr = FPD_GICP_GROUP1_BASE_ADDR, + .pmuIrqBit = FPD_GICP_PMU_IRQ_GROUP1, + }, + [FPD_GICP_GROUP2] = { + .baseAddr = FPD_GICP_GROUP2_BASE_ADDR, + .pmuIrqBit = FPD_GICP_PMU_IRQ_GROUP2, + }, + [FPD_GICP_GROUP3] = { + .baseAddr = FPD_GICP_GROUP3_BASE_ADDR, + .pmuIrqBit = FPD_GICP_PMU_IRQ_GROUP3, + }, + [FPD_GICP_GROUP4] = { + .baseAddr = FPD_GICP_GROUP4_BASE_ADDR, + .pmuIrqBit = FPD_GICP_PMU_IRQ_GROUP4, + }, +}; + +/* All slaves array */ +static PmSlave* const pmSlaves[] = { + &pmSlaveL2_g.slv, + &pmSlaveOcm0_g.slv, + &pmSlaveOcm1_g.slv, + &pmSlaveOcm2_g.slv, + &pmSlaveOcm3_g.slv, + &pmSlaveTcm0A_g.slv, + &pmSlaveTcm0B_g.slv, + &pmSlaveTcm1A_g.slv, + &pmSlaveTcm1B_g.slv, + &pmSlaveUsb0_g.slv, + &pmSlaveUsb1_g.slv, + &pmSlaveTtc0_g.slv, + &pmSlaveSata_g.slv, +}; + +/** + * PmSlaveHasCapRequests() - Check whether slave has any request for any + * capability + * @slave Pointer to a slave whose requests are to be checked + * + * @note Check all master requests and return : + * - true if there is at least one master requesting a capability + * - false if no master is requesting anything from this slave + */ +bool PmSlaveHasCapRequests(const PmSlave* const slave) +{ + u32 i; + bool hasReq = false; + + for (i = 0U; i < slave->reqsCnt; i++) { + if ((0U != (PM_MASTER_USING_SLAVE_MASK & slave->reqs[i]->info)) && + (0U != slave->reqs[i]->currReq)) { + /* Slave is used by this master and has current request for caps */ + hasReq = true; + break; + } + } + + return hasReq; +} + +/** + * PmGetMaxCapabilities()- Get maximum of all requested capabilities of slave + * @slave Slave whose maximum required capabilities should be determined + * + * @return 32bit value encoding the capabilities + */ +static u32 PmGetMaxCapabilities(const PmSlave* const slave) +{ + u32 i; + u32 maxCaps = 0U; + + for (i = 0U; i < slave->reqsCnt; i++) { + if (0U != (PM_MASTER_USING_SLAVE_MASK & slave->reqs[i]->info)) { + maxCaps |= slave->reqs[i]->currReq; + } + } + + return maxCaps; +} + +/** + * PmCheckCapabilities() - Check whether the slave has given capabilities + * @slave Slave pointer whose capabilities/states should be checked + * @cap Check for these capabilities + * + * @return Status does slave have a state with given capabilities. + * - PM_RET_SUCCESS - slave has state with given capabilities + * - PM_RET_ERROR_NOTSUPPORTED - slave does not have such state + */ +u32 PmCheckCapabilities(PmSlave* const slave, const u32 cap) +{ + PmStateId i; + u32 status = PM_RET_ERROR_NOTSUPPORTED; + + for (i = 0; i < slave->slvFsm->statesCnt; i++) { + /* Find the first state that contains all capabilities */ + if ((cap & slave->slvFsm->states[i]) == cap) { + return PM_RET_SUCCESS; + } + } + + return status; +} + +/** + * PmSlaveChangeState() - Change state of a slave + * @slave Slave pointer whose state should be changed + * @state New state + * + * @return PM_RET_SUCCESS if transition was performed successfully + * error otherwise + */ +u32 PmSlaveChangeState(PmSlave* const slave, const PmStateId state) +{ + u32 t; + u32 status = PM_RET_ERROR_FAILURE; + const PmSlaveFsm* fsm = slave->slvFsm; + + for (t = 0U; t < fsm->transCnt; t++) { + /* Find transition from current state to state to be set */ + if ((fsm->trans[t].fromState != slave->node.currState) || + (fsm->trans[t].toState != state)) { + continue; + } + + if (NULL != fsm->actions) { + /* Execute transition action */ + u32 ret = fsm->actions[(slave->instId * fsm->transCnt) + t](); + + /* Check the status of transition handler */ + if (ret == XST_SUCCESS) { + slave->node.currState = state; + status = PM_RET_SUCCESS; + } else { + status = PM_RET_ERROR_FAILURE; + } + } else { + /* + * Slave's FSM has no actions, because it has no private + * properties to be controlled here. + */ + status = PM_RET_SUCCESS; + } + + break; + } + return status; +} + +/** + * PmUpdateSlave() - Update the slave's state according to the current + * requirements from all masters + * @slave Slave whose state is about to be updated + * + * @return Status of operation + */ +u32 PmUpdateSlave(PmSlave* const slave) +{ + PmStateId s; + const PmSlaveFsm* fsm = slave->slvFsm; + u32 status = PM_RET_ERROR_NOTSUPPORTED; + u32 capsToSet = PmGetMaxCapabilities(slave); + + if (capsToSet == slave->slvFsm->states[slave->node.currState]) { + /* Slave is already in right state */ + status = PM_RET_SUCCESS; + goto done; + } + + if (0U != capsToSet) { + for (s = 0U; s < fsm->statesCnt; s++) { + /* Find the first state with all required capabilities */ + if ((capsToSet & fsm->states[s]) == capsToSet) { + status = PmSlaveChangeState(slave, s); + break; + } + } + } else { + /* + * Set the lowest power state, no capabilities are required. This + * check has to exist because some slaves have no state with 0 + * capabilities. Therefore, they are always placed in first, lowest + * power state when their capabilities are not required. + */ + status = PmSlaveChangeState(slave, 0U); + } + +done: + return status; +} + +/** + * PmSlaveWakeMasters() - Called when slave has to wake-up it's masters + * @slave Pointer to a slave whose masters has to be woken-up (if master has + * requested this slave as wake-up source before going to sleep) + * + * @note: Wake event of this slave is disabled together with all other slaves + * as part of the wake-up sequence. + */ +static void PmSlaveWakeMasters(PmSlave* const slave) +{ + PmMasterId i; + + for (i = 0U; i < slave->reqsCnt; i++) { + if (slave->reqs[i]->info & PM_MASTER_WAKEUP_REQ_MASK) { + slave->reqs[i]->info &= ~PM_MASTER_WAKEUP_REQ_MASK; + PmDbg("%s %s->%s\n", __func__, PmStrNode(slave->node.nodeId), + PmStrNode(slave->reqs[i]->requestor->procs->node.nodeId)); + PmProcFsm(slave->reqs[i]->requestor->procs, PM_PROC_EVENT_WAKE); + } + } + + PmSlaveWakeDisable(slave); +} + +/** + * PmSlaveProcessWake() - Slave has generated wake-up interrupt, find both slave + * source and master targets to and trigger wake-up. + * @wakeMask Mask read from GPI1 register, based on which slave source that + * generated interrupt will be determined. Master targets are + * determined based on requirements for slave's wake-up capability. + * + * @note If multiple slaves has simultaneously generated interrupts (wake + * events), they will be all processed in this function). For FPD + * GIC Proxy this is a must because reading 32-bit status register + * clears the interrupt, meaning that there could be up to 31 irqs + * that would be lost if not handled immediately. + */ +void PmSlaveProcessWake(const u32 wakeMask) +{ + u32 g; + + if (!(PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK & wakeMask)) { + goto done; + } + + for (g = 0U; g < ARRAY_SIZE(gicProxyGroups_g); g++) { + /* Reading status register clears interrupts */ + u32 s; + u32 irqStatus = XPfw_Read32(gicProxyGroups_g[g].baseAddr + + FPD_GICP_STATUS_OFFSET); + + for (s = 0U; (0U != irqStatus) && (s < ARRAY_SIZE(pmSlaves)); s++) { + if ((NULL != pmSlaves[s]->wake) && + (pmSlaves[s]->wake->proxyIrqMask & irqStatus)) { + PmSlaveWakeMasters(pmSlaves[s]); + irqStatus &= ~pmSlaves[s]->wake->proxyIrqMask; + } + } + } + +done: + return; +} + +/** + * PmWaitingForGicProxyWake() - Check is any Fpd wake is unmasked + * @return True if there are some wake events unmasked, false otherwise + */ +static bool PmWaitingForGicProxyWake(void) +{ + u32 i; + bool waitingForWake = false; + + for (i = 0; i < ARRAY_SIZE(gicProxyGroups_g); i++) { + u32 reg = XPfw_Read32(gicProxyGroups_g[i].baseAddr + FPD_GICP_MASK_OFFSET); + + if (FPD_GICP_ALL_IRQ_MASKED_IN_GROUP != reg) { + waitingForWake = true; + break; + } + } + + return waitingForWake; +} + +/** + * PmSlaveWakeEnable() - Enable wake interrupt of this slave + * @slave Slave whose wake should be enabled + */ +void PmSlaveWakeEnable(PmSlave* const slave) +{ + PmDbg("%s %s\n", __func__, PmStrNode(slave->node.nodeId)); + + if (NULL == slave->wake) { + goto done; + } + + /* Enable GIC Proxy IRQ */ + XPfw_Write32(slave->wake->proxyGroup->baseAddr + FPD_GICP_IRQ_ENABLE_OFFSET, + slave->wake->proxyIrqMask); + /* Enable GIC Proxy group */ + XPfw_Write32(FPD_GICP_PMU_IRQ_ENABLE, slave->wake->proxyGroup->pmuIrqBit); + + /* Enable GPI1 FPD GIC Proxy wake event */ + ENABLE_WAKE(PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK); + +done: + return; +} + +/** + * PmSlaveWakeDisable() - Disable wake interrupt of this slave + * @slave Slave whose wake should be disabled + */ +void PmSlaveWakeDisable(PmSlave* const slave) +{ + PmDbg("%s %s\n", __func__, PmStrNode(slave->node.nodeId)); + + if (NULL == slave->wake) { + goto done; + } + + XPfw_Write32(slave->wake->proxyGroup->baseAddr + FPD_GICP_IRQ_DISABLE_OFFSET, + slave->wake->proxyIrqMask); + if (FPD_GICP_ALL_IRQ_MASKED_IN_GROUP == + XPfw_Read32(slave->wake->proxyGroup->baseAddr + FPD_GICP_MASK_OFFSET)) { + /* Disable group */ + XPfw_Write32(FPD_GICP_PMU_IRQ_DISABLE, slave->wake->proxyGroup->pmuIrqBit); + if (false == PmWaitingForGicProxyWake()) { + /* Disable FPD GPI1 wake event */ + DISABLE_WAKE(PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK); + } + } + +done: + return; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h new file mode 100644 index 00000000..b2cb80a2 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_slave.h @@ -0,0 +1,179 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * All functions, data and definitions needed for + * managing PM slaves' states. + *********************************************************************/ + +#ifndef PM_SLAVE_H_ +#define PM_SLAVE_H_ + +#include "pm_defs.h" +#include "pm_common.h" +#include "pm_node.h" + +typedef u8 PmSlaveInstanceId; +typedef struct PmMaster PmMaster; +typedef struct PmRequirement PmRequirement; + +/********************************************************************* + * Macros + ********************************************************************/ +/* FPD GIC Proxy group base addresses */ +#define FPD_GICP_GROUP0_BASE_ADDR 0xFF418000U +#define FPD_GICP_GROUP1_BASE_ADDR 0xFF418014U +#define FPD_GICP_GROUP2_BASE_ADDR 0xFF418028U +#define FPD_GICP_GROUP3_BASE_ADDR 0xFF41803CU +#define FPD_GICP_GROUP4_BASE_ADDR 0xFF418050U + +/* FPD GIC Proxy register offsets */ +#define FPD_GICP_STATUS_OFFSET 0x0U +#define FPD_GICP_MASK_OFFSET 0x4U +#define FPD_GICP_IRQ_ENABLE_OFFSET 0x8U +#define FPD_GICP_IRQ_DISABLE_OFFSET 0xCU + +/* FPD GIC Proxy pmu registers */ +#define FPD_GICP_PMU_IRQ_ENABLE 0xFF4180A8U +#define FPD_GICP_PMU_IRQ_DISABLE 0xFF4180ACU + +/* FPD GIC Proxy group indentifiers */ +#define FPD_GICP_GROUP0 0U +#define FPD_GICP_GROUP1 1U +#define FPD_GICP_GROUP2 2U +#define FPD_GICP_GROUP3 3U +#define FPD_GICP_GROUP4 4U +#define FPD_GICP_GROUP_MAX 5U + +#define FPD_GICP_ALL_IRQ_MASKED_IN_GROUP 0xFFFFFFFFU + +/* FPD GIC Proxy pmu irq masks */ +#define FPD_GICP_PMU_IRQ_GROUP0 0x1U +#define FPD_GICP_PMU_IRQ_GROUP1 0x2U +#define FPD_GICP_PMU_IRQ_GROUP2 0x4U +#define FPD_GICP_PMU_IRQ_GROUP3 0x8U +#define FPD_GICP_PMU_IRQ_GROUP4 0x10U + +/* FPD GIC Proxy irq masks */ +#define FPD_GICP_USB0_WAKE_IRQ_MASK 0x400U +#define FPD_GICP_USB1_WAKE_IRQ_MASK 0x800U +#define FPD_GICP_TTC0_WAKE_IRQ_MASK 0x10U +#define FPD_GICP_SATA_WAKE_IRQ_MASK 0x20U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +/** + * PmStateTran - Transition for a state in finite state machine + * @fromState From which state the transition is taken + * @toState To which state the transition is taken + */ +typedef struct { + PmStateId fromState; + PmStateId toState; +} PmStateTran; + +/** + * PmSlaveFsm - Finite state machine data for slaves + * @state Pointer to states array. Index in array is a state id, elements + * of array are power values in that state. For power island values + * are 0 and 1, for power domains values are in mV + * @statesCnt Number of states in state array + * @trans Pointer to array of transitions of the FSM + * @transCnt Number of elements in transition array + * @actions Array of transition actions (function pointers) for all + * instances of this class + */ +typedef struct { + const u32* const states; + const PmStateId statesCnt; + const PmStateTran* const trans; + const PmTransitionId transCnt; + const PmTranHandler* const actions; +} PmSlaveFsm; + +/** + * PmGicProxyProperties - Information about FPD GIC Proxy groups + */ +typedef struct { + const u32 baseAddr; + const u32 pmuIrqBit; +} PmGicProxyProperties; + +/** + * PmWakeEvent - Wake-up event + * @proxyIrqMask As most of the interrupt routes go through FPD GIC Proxy, + * this is the interrupt mask in GIC Proxy registers. + * @proxyGroup Group in FPD GIC Proxy + */ +typedef struct { + const u32 proxyIrqMask; + PmGicProxyProperties *proxyGroup; +} PmWakeProperties; + +/** + * PmSlave - Slave structure used for managing slave's states + * @node Pointer to the node structure of this slave + * @classId Class of the slave. Slaves of the same class have the same state + * definitions + * @instId Index into array of all instances of slave's class + * @reqs Pointer to array of master requirements related to this slave + * @reqsCnt Size of masterReq array + * @wake Wake event this slave can generate + */ +typedef struct PmSlave { + PmNode node; + const PmSlaveInstanceId instId; + PmRequirement* const* reqs; + u8 reqsCnt; + const PmWakeProperties* wake; + const PmSlaveFsm* slvFsm; +} PmSlave; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmGicProxyProperties gicProxyGroups_g[FPD_GICP_GROUP_MAX]; + +/********************************************************************* + * Function declarations + ********************************************************************/ +u32 PmUpdateSlave(PmSlave* const slave); +u32 PmCheckCapabilities(PmSlave* const slave, const u32 capabilities); + +bool PmSlaveHasCapRequests(const PmSlave* const slave); + +void PmSlaveProcessWake(const u32 wakeMask); +void PmSlaveWakeEnable(PmSlave* const slave); +void PmSlaveWakeDisable(PmSlave* const slave); + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_sram.c b/lib/sw_apps/zynqmp_pmufw/src/pm_sram.c new file mode 100644 index 00000000..488e7c4f --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_sram.c @@ -0,0 +1,529 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of PM slave SRAM structures and state transitions. + *********************************************************************/ + +#include "pm_sram.h" +#include "pm_common.h" +#include "pm_master.h" +#include "xpfw_rom_interface.h" + +#define DEFTR(INST, TRAN) ((INST * PM_SRAM_TR_MAX) + TRAN) + +/* Ocm bank 0 */ +static u32 PmOcm0RetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK0_MASK, + PMU_LOCAL_OCM_RET_CNTRL_BANK0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmOcm0RetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK0_MASK, + ~PMU_LOCAL_OCM_RET_CNTRL_BANK0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +/* Ocm bank 1 */ +static u32 PmOcm1RetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK1_MASK, + PMU_LOCAL_OCM_RET_CNTRL_BANK1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmOcm1RetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK1_MASK, + ~PMU_LOCAL_OCM_RET_CNTRL_BANK1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +/* Ocm bank 2 */ +static u32 PmOcm2RetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK2_MASK, + PMU_LOCAL_OCM_RET_CNTRL_BANK2_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmOcm2RetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK2_MASK, + ~PMU_LOCAL_OCM_RET_CNTRL_BANK2_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +/* Ocm bank 3 */ +static u32 PmOcm3RetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK3_MASK, + PMU_LOCAL_OCM_RET_CNTRL_BANK3_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmOcm3RetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_OCM_RET_CNTRL, + PMU_LOCAL_OCM_RET_CNTRL_BANK3_MASK, + ~PMU_LOCAL_OCM_RET_CNTRL_BANK3_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm0ARetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMA0_MASK, + PMU_LOCAL_TCM_RET_CNTRL_TCMA0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm0ARetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMA0_MASK, + ~PMU_LOCAL_TCM_RET_CNTRL_TCMA0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm0BRetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMB0_MASK, + PMU_LOCAL_TCM_RET_CNTRL_TCMB0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm0BRetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMB0_MASK, + ~PMU_LOCAL_TCM_RET_CNTRL_TCMB0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm1ARetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMA1_MASK, + PMU_LOCAL_TCM_RET_CNTRL_TCMA1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm1ARetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMA1_MASK, + ~PMU_LOCAL_TCM_RET_CNTRL_TCMA1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm1BRetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMB1_MASK, + PMU_LOCAL_TCM_RET_CNTRL_TCMB1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmTcm1BRetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_TCM_RET_CNTRL, + PMU_LOCAL_TCM_RET_CNTRL_TCMB1_MASK, + ~PMU_LOCAL_TCM_RET_CNTRL_TCMB1_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmL2RetEntry(void) +{ + XPfw_RMW32(PMU_LOCAL_L2_RET_CNTRL, + PMU_LOCAL_L2_RET_CNTRL_BANK0_MASK, + PMU_LOCAL_L2_RET_CNTRL_BANK0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static u32 PmL2RetExit(void) +{ + XPfw_RMW32(PMU_LOCAL_L2_RET_CNTRL, + PMU_LOCAL_L2_RET_CNTRL_BANK0_MASK, + ~PMU_LOCAL_L2_RET_CNTRL_BANK0_MASK); + + PmDbg("%s\n", __func__); + + return XST_SUCCESS; +} + +static const PmTranHandler pmSramActions_g[PM_SRAM_INST_MAX * PM_SRAM_TR_MAX] = { + [ DEFTR(PM_SRAM_OCM0, PM_SRAM_TR_ON_TO_RET) ] = PmOcm0RetEntry, + [ DEFTR(PM_SRAM_OCM0, PM_SRAM_TR_RET_TO_ON) ] = PmOcm0RetExit, + [ DEFTR(PM_SRAM_OCM0, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnOcmBank0Handler, + [ DEFTR(PM_SRAM_OCM0, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpOcmBank0Handler, + + [ DEFTR(PM_SRAM_OCM1, PM_SRAM_TR_ON_TO_RET) ] = PmOcm1RetEntry, + [ DEFTR(PM_SRAM_OCM1, PM_SRAM_TR_RET_TO_ON) ] = PmOcm1RetExit, + [ DEFTR(PM_SRAM_OCM1, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnOcmBank1Handler, + [ DEFTR(PM_SRAM_OCM1, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpOcmBank1Handler, + + [ DEFTR(PM_SRAM_OCM2, PM_SRAM_TR_ON_TO_RET) ] = PmOcm2RetEntry, + [ DEFTR(PM_SRAM_OCM2, PM_SRAM_TR_RET_TO_ON) ] = PmOcm2RetExit, + [ DEFTR(PM_SRAM_OCM2, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnOcmBank2Handler, + [ DEFTR(PM_SRAM_OCM2, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpOcmBank2Handler, + + [ DEFTR(PM_SRAM_OCM3, PM_SRAM_TR_ON_TO_RET) ] = PmOcm3RetEntry, + [ DEFTR(PM_SRAM_OCM3, PM_SRAM_TR_RET_TO_ON) ] = PmOcm3RetExit, + [ DEFTR(PM_SRAM_OCM3, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnOcmBank3Handler, + [ DEFTR(PM_SRAM_OCM3, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpOcmBank3Handler, + + [ DEFTR(PM_SRAM_TCM0A, PM_SRAM_TR_ON_TO_RET) ] = PmTcm0ARetEntry, + [ DEFTR(PM_SRAM_TCM0A, PM_SRAM_TR_RET_TO_ON) ] = PmTcm0ARetExit, + [ DEFTR(PM_SRAM_TCM0A, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnTcm0AHandler, + [ DEFTR(PM_SRAM_TCM0A, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpTcm0AHandler, + + [ DEFTR(PM_SRAM_TCM0B, PM_SRAM_TR_ON_TO_RET) ] = PmTcm0BRetEntry, + [ DEFTR(PM_SRAM_TCM0B, PM_SRAM_TR_RET_TO_ON) ] = PmTcm0BRetExit, + [ DEFTR(PM_SRAM_TCM0B, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnTcm0BHandler, + [ DEFTR(PM_SRAM_TCM0B, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpTcm0BHandler, + + [ DEFTR(PM_SRAM_TCM1A, PM_SRAM_TR_ON_TO_RET) ] = PmTcm1ARetEntry, + [ DEFTR(PM_SRAM_TCM1A, PM_SRAM_TR_RET_TO_ON) ] = PmTcm1ARetExit, + [ DEFTR(PM_SRAM_TCM1A, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnTcm1AHandler, + [ DEFTR(PM_SRAM_TCM1A, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpTcm1AHandler, + + [ DEFTR(PM_SRAM_TCM1B, PM_SRAM_TR_ON_TO_RET) ] = PmTcm1BRetEntry, + [ DEFTR(PM_SRAM_TCM1B, PM_SRAM_TR_RET_TO_ON) ] = PmTcm1BRetExit, + [ DEFTR(PM_SRAM_TCM1B, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnTcm1BHandler, + [ DEFTR(PM_SRAM_TCM1B, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpTcm1BHandler, + + [ DEFTR(PM_SRAM_L2, PM_SRAM_TR_ON_TO_RET) ] = PmL2RetEntry, + [ DEFTR(PM_SRAM_L2, PM_SRAM_TR_RET_TO_ON) ] = PmL2RetExit, + [ DEFTR(PM_SRAM_L2, PM_SRAM_TR_ON_TO_OFF) ] = XpbrPwrDnL2Bank0Handler, + [ DEFTR(PM_SRAM_L2, PM_SRAM_TR_OFF_TO_ON) ] = XpbrPwrUpL2Bank0Handler, +}; + +/* Sram states */ +static const u32 pmSramStates_g[PM_SRAM_STATE_MAX] = { + [PM_SRAM_STATE_OFF] = 0U, + [PM_SRAM_STATE_RET] = PM_CAP_CONTEXT, + [PM_SRAM_STATE_ON] = PM_CAP_ACCESS | PM_CAP_CONTEXT, +}; + +/* Sram transition table (from which to which state sram can transit) */ +static const PmStateTran pmSramTransitions_g[PM_SRAM_TR_MAX] = { + [PM_SRAM_TR_ON_TO_RET] = { + .fromState = PM_SRAM_STATE_ON, + .toState = PM_SRAM_STATE_RET, + }, + [PM_SRAM_TR_RET_TO_ON] = { + .fromState = PM_SRAM_STATE_RET, + .toState = PM_SRAM_STATE_ON, + }, + [PM_SRAM_TR_ON_TO_OFF] = { + .fromState = PM_SRAM_STATE_ON, + .toState = PM_SRAM_STATE_OFF, + }, + [PM_SRAM_TR_OFF_TO_ON] = { + .fromState = PM_SRAM_STATE_OFF, + .toState = PM_SRAM_STATE_ON, + }, +}; + +/* Sram FSM */ +static const PmSlaveFsm slaveSramFsm = { + .states = pmSramStates_g, + .statesCnt = PM_SRAM_STATE_MAX, + .trans = pmSramTransitions_g, + .transCnt = PM_SRAM_TR_MAX, + .actions = pmSramActions_g, +}; + +static PmRequirement* const pmL2Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_L2], +}; + +PmSlaveSram pmSlaveL2_g = { + .slv = { + .node = { + .derived = &pmSlaveL2_g, + .nodeId = NODE_L2, + .typeId = PM_TYPE_SRAM, + .parent = &pmPowerDomainFpd_g, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_L2, + .reqs = pmL2Reqs, + .reqsCnt = ARRAY_SIZE(pmL2Reqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmOcm0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_OCM0], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_OCM0], +}; + +PmSlaveSram pmSlaveOcm0_g = { + .slv = { + .node = { + .derived = &pmSlaveOcm0_g, + .nodeId = NODE_OCM_BANK_0, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_OCM0, + .reqs = pmOcm0Reqs, + .reqsCnt = ARRAY_SIZE(pmOcm0Reqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmOcm1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_OCM1], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_OCM1], +}; + +PmSlaveSram pmSlaveOcm1_g = { + .slv = { + .node = { + .derived = &pmSlaveOcm1_g, + .nodeId = NODE_OCM_BANK_1, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_OCM1, + .reqs = pmOcm1Reqs, + .reqsCnt = ARRAY_SIZE(pmOcm1Reqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmOcm2Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_OCM2], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_OCM2], +}; + +PmSlaveSram pmSlaveOcm2_g = { + .slv = { + .node = { + .derived = &pmSlaveOcm2_g, + .nodeId = NODE_OCM_BANK_2, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_OCM2, + .reqs = pmOcm2Reqs, + .reqsCnt = ARRAY_SIZE(pmOcm2Reqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmOcm3Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_OCM3], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_OCM3], +}; + +PmSlaveSram pmSlaveOcm3_g = { + .slv = { + .node = { + .derived = &pmSlaveOcm3_g, + .nodeId = NODE_OCM_BANK_3, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_OCM3, + .reqs = pmOcm3Reqs, + .reqsCnt = ARRAY_SIZE(pmOcm3Reqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmTcm0AReqs[] = { + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_TCM0A], +}; + +PmSlaveSram pmSlaveTcm0A_g = { + .slv = { + .node = { + .derived = &pmSlaveTcm0A_g, + .nodeId = NODE_TCM_0_A, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_TCM0A, + .reqs = pmTcm0AReqs, + .reqsCnt = ARRAY_SIZE(pmTcm0AReqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmTcm0BReqs[] = { + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_TCM0B], +}; + +PmSlaveSram pmSlaveTcm0B_g = { + .slv = { + .node = { + .derived = &pmSlaveTcm0B_g, + .nodeId = NODE_TCM_0_B, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_TCM0B, + .reqs = pmTcm0BReqs, + .reqsCnt = ARRAY_SIZE(pmTcm0BReqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmTcm1AReqs[] = { + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_TCM1A], +}; + +PmSlaveSram pmSlaveTcm1A_g = { + .slv = { + .node = { + .derived = &pmSlaveTcm1A_g, + .nodeId = NODE_TCM_1_A, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_TCM1A, + .reqs = pmTcm1AReqs, + .reqsCnt = ARRAY_SIZE(pmTcm1AReqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; + +static PmRequirement* const pmTcm1BReqs[] = { + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_TCM1B], +}; + +PmSlaveSram pmSlaveTcm1B_g = { + .slv = { + .node = { + .derived = &pmSlaveTcm1B_g, + .nodeId = NODE_TCM_1_B, + .typeId = PM_TYPE_SRAM, + .parent = NULL, + .currState = PM_SRAM_STATE_ON, + .ops = NULL, + }, + .instId = PM_SRAM_TCM1B, + .reqs = pmTcm1BReqs, + .reqsCnt = ARRAY_SIZE(pmTcm1BReqs), + .wake = NULL, + .slvFsm = &slaveSramFsm, + }, +}; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_sram.h b/lib/sw_apps/zynqmp_pmufw/src/pm_sram.h new file mode 100644 index 00000000..81c9d891 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_sram.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * SRAM memories slaves definitions and data structures + *********************************************************************/ + +#ifndef PM_SRAM_H_ +#define PM_SRAM_H_ + +#include "pm_slave.h" + +/********************************************************************* + * Macros + ********************************************************************/ +/* Instances of SRAM */ +#define PM_SRAM_OCM0 0U +#define PM_SRAM_OCM1 1U +#define PM_SRAM_OCM2 2U +#define PM_SRAM_OCM3 3U +#define PM_SRAM_TCM0A 4U +#define PM_SRAM_TCM0B 5U +#define PM_SRAM_TCM1A 6U +#define PM_SRAM_TCM1B 7U +#define PM_SRAM_L2 8U +#define PM_SRAM_INST_MAX 9U + +/* Power states of SRAM */ +#define PM_SRAM_STATE_OFF 0U +#define PM_SRAM_STATE_RET 1U +#define PM_SRAM_STATE_ON 2U +#define PM_SRAM_STATE_MAX 3U + +/* Transitions of sram */ +#define PM_SRAM_TR_ON_TO_RET 0U +#define PM_SRAM_TR_RET_TO_ON 1U +#define PM_SRAM_TR_ON_TO_OFF 2U +#define PM_SRAM_TR_OFF_TO_ON 3U +#define PM_SRAM_TR_MAX 4U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +typedef struct PmSlaveSram { + PmSlave slv; +} PmSlaveSram; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmSlaveSram pmSlaveOcm0_g; +extern PmSlaveSram pmSlaveOcm1_g; +extern PmSlaveSram pmSlaveOcm2_g; +extern PmSlaveSram pmSlaveOcm3_g; +extern PmSlaveSram pmSlaveL2_g; +extern PmSlaveSram pmSlaveTcm0A_g; +extern PmSlaveSram pmSlaveTcm0B_g; +extern PmSlaveSram pmSlaveTcm1A_g; +extern PmSlaveSram pmSlaveTcm1B_g; + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_usb.c b/lib/sw_apps/zynqmp_pmufw/src/pm_usb.c new file mode 100644 index 00000000..531c7cb5 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_usb.c @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * Definitions of PM slave USB structures and state transitions. + *********************************************************************/ + +#include "pm_usb.h" +#include "pm_common.h" +#include "pm_master.h" +#include "xpfw_rom_interface.h" + +#define DEFTR(INST, TRAN) ((INST * PM_USB_TR_MAX) + TRAN) + +static const PmTranHandler pmUsbActions_g[PM_USB_INST_MAX * PM_USB_TR_MAX] = { + [ DEFTR(PM_USB_0, PM_USB_TR_ON_TO_OFF) ] = XpbrPwrDnUsb0Handler, + [ DEFTR(PM_USB_0, PM_USB_TR_OFF_TO_ON) ] = XpbrPwrUpUsb0Handler, + + [ DEFTR(PM_USB_1, PM_USB_TR_ON_TO_OFF) ] = XpbrPwrDnUsb1Handler, + [ DEFTR(PM_USB_1, PM_USB_TR_OFF_TO_ON) ] = XpbrPwrUpUsb1Handler, +}; + +/* USB states */ +static const u32 pmUsbStates_g[PM_USB_STATE_MAX] = { + [PM_USB_STATE_OFF] = PM_CAP_WAKEUP, + [PM_USB_STATE_ON] = PM_CAP_WAKEUP | PM_CAP_ACCESS | PM_CAP_CONTEXT, +}; + +/* USB transition table (from which to which state USB can transit) */ +static const PmStateTran pmUsbTransitions_g[PM_USB_TR_MAX] = { + [PM_USB_TR_ON_TO_OFF] = { + .fromState = PM_USB_STATE_ON, + .toState = PM_USB_STATE_OFF, + }, + [PM_USB_TR_OFF_TO_ON] = { + .fromState = PM_USB_STATE_OFF, + .toState = PM_USB_STATE_ON, + }, +}; + +/* USB FSM */ +static const PmSlaveFsm slaveUsbFsm = { + .states = pmUsbStates_g, + .statesCnt = PM_USB_STATE_MAX, + .trans = pmUsbTransitions_g, + .transCnt = PM_USB_TR_MAX, + .actions = pmUsbActions_g, +}; + +static PmRequirement* const pmUsb0Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_USB0], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_USB0], +}; + +static PmWakeProperties pmUsb0Wake = { + .proxyIrqMask = FPD_GICP_USB0_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP2], +}; + +PmSlaveUsb pmSlaveUsb0_g = { + .slv = { + .node = { + .nodeId = NODE_USB_0, + .typeId = PM_TYPE_USB, + .currState = PM_USB_STATE_ON, + .derived = &pmSlaveUsb0_g, + .ops = NULL, + }, + .instId = PM_USB_0, + .reqs = pmUsb0Reqs, + .reqsCnt = ARRAY_SIZE(pmUsb0Reqs), + .wake = &pmUsb0Wake, + .slvFsm = &slaveUsbFsm, + }, +}; + +static PmRequirement* const pmUsb1Reqs[] = { + &pmApuReq_g[PM_MASTER_APU_SLAVE_USB1], + &pmRpu0Req_g[PM_MASTER_RPU_0_SLAVE_USB1], +}; + +static PmWakeProperties pmUsb1Wake = { + .proxyIrqMask = FPD_GICP_USB1_WAKE_IRQ_MASK, + .proxyGroup = &gicProxyGroups_g[FPD_GICP_GROUP2], +}; + +PmSlaveUsb pmSlaveUsb1_g = { + .slv = { + .node = { + .nodeId = NODE_USB_1, + .typeId = PM_TYPE_USB, + .currState = PM_USB_STATE_ON, + .derived = &pmSlaveUsb1_g, + .ops = NULL, + }, + .instId = PM_USB_1, + .reqs = pmUsb1Reqs, + .reqsCnt = ARRAY_SIZE(pmUsb1Reqs), + .wake = &pmUsb1Wake, + .slvFsm = &slaveUsbFsm, + }, +}; diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_usb.h b/lib/sw_apps/zynqmp_pmufw/src/pm_usb.h new file mode 100644 index 00000000..144229ea --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pm_usb.h @@ -0,0 +1,73 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/********************************************************************* + * USB slaves data structures + *********************************************************************/ + +#ifndef PM_USB_H_ +#define PM_USB_H_ + +#include "pm_slave.h" + +/********************************************************************* + * Macros + ********************************************************************/ +/* Instances of USB */ +#define PM_USB_0 0U +#define PM_USB_1 1U +#define PM_USB_INST_MAX 2U + +/* Power states of USB */ +#define PM_USB_STATE_OFF 0U +#define PM_USB_STATE_ON 1U +#define PM_USB_STATE_MAX 2U + +/* Transitions of USB */ +#define PM_USB_TR_ON_TO_OFF 0U +#define PM_USB_TR_OFF_TO_ON 1U +#define PM_USB_TR_MAX 2U + +/********************************************************************* + * Structure definitions + ********************************************************************/ +typedef struct PmSlaveUsb { + PmSlave slv; +} PmSlaveUsb; + +/********************************************************************* + * Global data declarations + ********************************************************************/ +extern PmSlaveUsb pmSlaveUsb0_g; +extern PmSlaveUsb pmSlaveUsb1_g; + +#endif diff --git a/lib/sw_apps/zynqmp_pmufw/src/pmu_global.h b/lib/sw_apps/zynqmp_pmufw/src/pmu_global.h new file mode 100644 index 00000000..f533bfac --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pmu_global.h @@ -0,0 +1,4299 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef _PMU_GLOBAL_H_ +#define _PMU_GLOBAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * PMU_GLOBAL Base Address + */ +#define PMU_GLOBAL_BASEADDR ((u32)0XFFD80000U) + +/** + * Register: PMU_GLOBAL_GLOBAL_CNTRL + */ +#define PMU_GLOBAL_GLOBAL_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000000U) ) + +#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_SHIFT 16 +#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_SHIFT 12 +#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_WIDTH 4 +#define PMU_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_MASK ((u32)0X0000F000U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_SHIFT 8 +#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_WIDTH 4 +#define PMU_GLOBAL_GLOBAL_CNTRL_READ_QOS_MASK ((u32)0X00000F00U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_SHIFT 4 +#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_SHIFT 2 +#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_COHERENT_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_SHIFT 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_PS_CNTRL + */ +#define PMU_GLOBAL_PS_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000004U) ) + +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_SHIFT 16 +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_WIDTH 1 +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_STATUS_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_SHIFT 1 +#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_WIDTH 1 +#define PMU_GLOBAL_PS_CNTRL_PROG_ENABLE_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_SHIFT 0 +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_WIDTH 1 +#define PMU_GLOBAL_PS_CNTRL_PROG_GATE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_APU_PWR_STATUS_INIT + */ +#define PMU_GLOBAL_APU_PWR_STATUS_INIT ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000008U) ) + +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_SHIFT 3 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_WIDTH 1 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_SHIFT 2 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_WIDTH 1 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_SHIFT 1 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_WIDTH 1 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_SHIFT 0 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_WIDTH 1 +#define PMU_GLOBAL_APU_PWR_STATUS_INIT_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_MEM_CNTRL + */ +#define PMU_GLOBAL_MEM_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000000CU) ) + +#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_SHIFT 23 +#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_WIDTH 1 +#define PMU_GLOBAL_MEM_CNTRL_ROM1_KEN_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_SHIFT 20 +#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_WIDTH 3 +#define PMU_GLOBAL_MEM_CNTRL_ROM1_EMA_MASK ((u32)0X00700000U) + +#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_SHIFT 19 +#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_WIDTH 1 +#define PMU_GLOBAL_MEM_CNTRL_ROM0_KEN_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_SHIFT 16 +#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_WIDTH 3 +#define PMU_GLOBAL_MEM_CNTRL_ROM0_EMA_MASK ((u32)0X00070000U) + +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_SHIFT 11 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_WIDTH 1 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAS_MASK ((u32)0X00000800U) + +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_SHIFT 9 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_WIDTH 2 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMAW_MASK ((u32)0X00000600U) + +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_SHIFT 6 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_WIDTH 3 +#define PMU_GLOBAL_MEM_CNTRL_ECC_RAM_EMA_MASK ((u32)0X000001C0U) + +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_SHIFT 5 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_WIDTH 1 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAS_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_SHIFT 3 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_WIDTH 2 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMAW_MASK ((u32)0X00000018U) + +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_SHIFT 0 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_WIDTH 3 +#define PMU_GLOBAL_MEM_CNTRL_DATA_RAM_EMA_MASK ((u32)0X00000007U) + +/** + * Register: PMU_GLOBAL_ADDR_ERROR_STATUS + */ +#define PMU_GLOBAL_ADDR_ERROR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000010U) ) + +#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_SHIFT 0 +#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_WIDTH 1 +#define PMU_GLOBAL_ADDR_ERROR_STATUS_STATUS_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ADDR_ERROR_INT_MASK + */ +#define PMU_GLOBAL_ADDR_ERROR_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000014U) ) + +#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_SHIFT 0 +#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_WIDTH 1 +#define PMU_GLOBAL_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ADDR_ERROR_INT_EN + */ +#define PMU_GLOBAL_ADDR_ERROR_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000018U) ) + +#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_SHIFT 0 +#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_WIDTH 1 +#define PMU_GLOBAL_ADDR_ERROR_INT_EN_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ADDR_ERROR_INT_DIS + */ +#define PMU_GLOBAL_ADDR_ERROR_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000001CU) ) + +#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_SHIFT 0 +#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_WIDTH 1 +#define PMU_GLOBAL_ADDR_ERROR_INT_DIS_DISABLE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE0 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000030U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE1 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000034U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE2 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000038U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE3 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000003CU) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE4 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000040U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE4_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE5 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000044U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE5_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE6 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000048U) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE6_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_GLOBAL_GEN_STORAGE7 + */ +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000004CU) ) + +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_SHIFT 0 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_WIDTH 32 +#define PMU_GLOBAL_GLOBAL_GEN_STORAGE7_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000050U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000054U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000058U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000005CU) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000060U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE4_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000064U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE5_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000068U) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE6_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7 + */ +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000006CU) ) + +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_SHIFT 0 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_WIDTH 32 +#define PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_DDR_CNTRL + */ +#define PMU_GLOBAL_DDR_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000070U) ) + +#define PMU_GLOBAL_DDR_CNTRL_RET_SHIFT 0 +#define PMU_GLOBAL_DDR_CNTRL_RET_WIDTH 1 +#define PMU_GLOBAL_DDR_CNTRL_RET_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_PWR_STATE + */ +#define PMU_GLOBAL_PWR_STATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000100U) ) + +#define PMU_GLOBAL_PWR_STATE_PL_SHIFT 23 +#define PMU_GLOBAL_PWR_STATE_PL_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_PWR_STATE_FP_SHIFT 22 +#define PMU_GLOBAL_PWR_STATE_FP_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_PWR_STATE_USB1_SHIFT 21 +#define PMU_GLOBAL_PWR_STATE_USB1_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_PWR_STATE_USB0_SHIFT 20 +#define PMU_GLOBAL_PWR_STATE_USB0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_PWR_STATE_TCM1B_SHIFT 15 +#define PMU_GLOBAL_PWR_STATE_TCM1B_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_PWR_STATE_TCM1A_SHIFT 14 +#define PMU_GLOBAL_PWR_STATE_TCM1A_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_PWR_STATE_TCM0B_SHIFT 13 +#define PMU_GLOBAL_PWR_STATE_TCM0B_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_PWR_STATE_TCM0A_SHIFT 12 +#define PMU_GLOBAL_PWR_STATE_TCM0A_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_PWR_STATE_R5_1_SHIFT 11 +#define PMU_GLOBAL_PWR_STATE_R5_1_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_R5_1_MASK ((u32)0X00000800U) + +#define PMU_GLOBAL_PWR_STATE_R5_0_SHIFT 10 +#define PMU_GLOBAL_PWR_STATE_R5_0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_R5_0_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_PWR_STATE_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_PWR_STATE_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_PWR_STATE_PP1_SHIFT 5 +#define PMU_GLOBAL_PWR_STATE_PP1_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_PWR_STATE_PP0_SHIFT 4 +#define PMU_GLOBAL_PWR_STATE_PP0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_PWR_STATE_ACPU3_SHIFT 3 +#define PMU_GLOBAL_PWR_STATE_ACPU3_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_PWR_STATE_ACPU2_SHIFT 2 +#define PMU_GLOBAL_PWR_STATE_ACPU2_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_PWR_STATE_ACPU1_SHIFT 1 +#define PMU_GLOBAL_PWR_STATE_ACPU1_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_PWR_STATE_ACPU0_SHIFT 0 +#define PMU_GLOBAL_PWR_STATE_ACPU0_WIDTH 1 +#define PMU_GLOBAL_PWR_STATE_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_AUX_PWR_STATE + */ +#define PMU_GLOBAL_AUX_PWR_STATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000104U) ) + +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_SHIFT 31 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU3_EMULATION_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_SHIFT 30 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU2_EMULATION_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_SHIFT 29 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU1_EMULATION_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_SHIFT 28 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_ACPU0_EMULATION_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_SHIFT 27 +#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_RPU_EMULATION_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_SHIFT 15 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_SHIFT 14 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_SHIFT 13 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_SHIFT 12 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_AUX_PWR_STATE_L2_BANK0_MASK ((u32)0X00000080U) + +/** + * Register: PMU_GLOBAL_RAM_RET_CNTRL + */ +#define PMU_GLOBAL_RAM_RET_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000108U) ) + +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_SHIFT 15 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_SHIFT 14 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_SHIFT 13 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_SHIFT 12 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_RAM_RET_CNTRL_L2_BANK0_MASK ((u32)0X00000080U) + +/** + * Register: PMU_GLOBAL_PWR_SUPPLY_STATUS + */ +#define PMU_GLOBAL_PWR_SUPPLY_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000010CU) ) + +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_SHIFT 2 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_WIDTH 1 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSAUX_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_SHIFT 1 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_WIDTH 1 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_INT_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_SHIFT 0 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_WIDTH 1 +#define PMU_GLOBAL_PWR_SUPPLY_STATUS_VCC_PSINTFP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRUP_STATUS + */ +#define PMU_GLOBAL_REQ_PWRUP_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000110U) ) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRUP_INT_MASK + */ +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000114U) ) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_MASK_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRUP_INT_EN + */ +#define PMU_GLOBAL_REQ_PWRUP_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000118U) ) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRUP_INT_DIS + */ +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000011CU) ) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_INT_DIS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRUP_TRIG + */ +#define PMU_GLOBAL_REQ_PWRUP_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000120U) ) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRDWN_STATUS + */ +#define PMU_GLOBAL_REQ_PWRDWN_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000210U) ) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_STATUS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRDWN_INT_MASK + */ +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000214U) ) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_MASK_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRDWN_INT_EN + */ +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000218U) ) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRDWN_INT_DIS + */ +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000021CU) ) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_INT_DIS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_PWRDWN_TRIG + */ +#define PMU_GLOBAL_REQ_PWRDWN_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000220U) ) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PL_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_SHIFT 22 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_FP_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_SHIFT 21 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_SHIFT 20 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_USB0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_SHIFT 19 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_SHIFT 18 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_SHIFT 17 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_SHIFT 16 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_SHIFT 15 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_SHIFT 14 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_SHIFT 13 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_SHIFT 12 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_SHIFT 7 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_L2_BANK0_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_SHIFT 5 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_SHIFT 4 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_ISO_STATUS + */ +#define PMU_GLOBAL_REQ_ISO_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000310U) ) + +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_SHIFT 4 +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_LOCKED_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_SHIFT 2 +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_NONPCAP_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_SHIFT 1 +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_STATUS_PL_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_SHIFT 0 +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_STATUS_FP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_ISO_INT_MASK + */ +#define PMU_GLOBAL_REQ_ISO_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000314U) ) + +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_SHIFT 4 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_LOCKED_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_SHIFT 2 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_NONPCAP_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_SHIFT 1 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_PL_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_SHIFT 0 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_MASK_FP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_ISO_INT_EN + */ +#define PMU_GLOBAL_REQ_ISO_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000318U) ) + +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_SHIFT 4 +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_LOCKED_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_SHIFT 2 +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_SHIFT 1 +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_EN_PL_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_SHIFT 0 +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_EN_FP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_ISO_INT_DIS + */ +#define PMU_GLOBAL_REQ_ISO_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000031CU) ) + +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_SHIFT 4 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_LOCKED_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_SHIFT 2 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_NONPCAP_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_SHIFT 1 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_PL_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_SHIFT 0 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_INT_DIS_FP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_ISO_TRIG + */ +#define PMU_GLOBAL_REQ_ISO_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000320U) ) + +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_SHIFT 4 +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_LOCKED_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_SHIFT 2 +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_NONPCAP_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_SHIFT 1 +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_TRIG_PL_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_SHIFT 0 +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_ISO_TRIG_FP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_SWRST_STATUS + */ +#define PMU_GLOBAL_REQ_SWRST_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000410U) ) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_SHIFT 31 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PL_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_SHIFT 30 +#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_FP_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_SHIFT 29 +#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_LP_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_SHIFT 28 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_SHIFT 27 +#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_IOU_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_SHIFT 25 +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB1_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_SHIFT 24 +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_USB0_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_SHIFT 23 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM3_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_SHIFT 22 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM2_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_SHIFT 21 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_SHIFT 20 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GEM0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_SHIFT 18 +#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_RPU_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_SHIFT 17 +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_SHIFT 16 +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_R5_0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_SHIFT 12 +#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_DISPLAY_PORT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_SHIFT 10 +#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_SATA_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_SHIFT 9 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PCIE_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_SHIFT 8 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_GPU_MASK ((u32)0X00000100U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_SHIFT 4 +#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_APU_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_STATUS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_SWRST_INT_MASK + */ +#define PMU_GLOBAL_REQ_SWRST_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000414U) ) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_SHIFT 31 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PL_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_SHIFT 30 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_FP_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_SHIFT 29 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LP_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_SHIFT 28 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_SHIFT 27 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_IOU_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_SHIFT 25 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB1_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_SHIFT 24 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_USB0_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_SHIFT 23 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM3_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_SHIFT 22 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM2_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_SHIFT 21 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_SHIFT 20 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GEM0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_SHIFT 18 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_LS_R5_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_SHIFT 17 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_SHIFT 16 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_R5_0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_SHIFT 12 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_DISPLAY_PORT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_SHIFT 10 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_SATA_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_SHIFT 9 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PCIE_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_SHIFT 8 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_GPU_MASK ((u32)0X00000100U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_SHIFT 4 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_APU_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_MASK_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_SWRST_INT_EN + */ +#define PMU_GLOBAL_REQ_SWRST_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000418U) ) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_SHIFT 31 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PL_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_SHIFT 30 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_FP_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_SHIFT 29 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LP_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_SHIFT 28 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_SHIFT 27 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_IOU_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_SHIFT 25 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB1_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_SHIFT 24 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_USB0_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_SHIFT 23 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM3_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_SHIFT 22 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM2_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_SHIFT 21 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_SHIFT 20 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GEM0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_SHIFT 18 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_LS_R5_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_SHIFT 17 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_SHIFT 16 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_R5_0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_SHIFT 12 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_DISPLAY_PORT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_SHIFT 10 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_SATA_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_SHIFT 9 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PCIE_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_SHIFT 8 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_GPU_MASK ((u32)0X00000100U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_SHIFT 4 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_APU_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_EN_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_SWRST_INT_DIS + */ +#define PMU_GLOBAL_REQ_SWRST_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000041CU) ) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_SHIFT 31 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PL_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_SHIFT 30 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_FP_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_SHIFT 29 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LP_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_SHIFT 28 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_SHIFT 27 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_IOU_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_SHIFT 25 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB1_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_SHIFT 24 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_USB0_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_SHIFT 23 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM3_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_SHIFT 22 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM2_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_SHIFT 21 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_SHIFT 20 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GEM0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_SHIFT 18 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_LS_R5_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_SHIFT 17 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_SHIFT 16 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_R5_0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_SHIFT 12 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_DISPLAY_PORT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_SHIFT 10 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_SATA_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_SHIFT 9 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PCIE_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_SHIFT 8 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_GPU_MASK ((u32)0X00000100U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_SHIFT 4 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_APU_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_INT_DIS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_SWRST_TRIG + */ +#define PMU_GLOBAL_REQ_SWRST_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000420U) ) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_SHIFT 31 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PL_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_SHIFT 30 +#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_FP_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_SHIFT 29 +#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_LP_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_SHIFT 28 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_SHIFT 27 +#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_IOU_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_SHIFT 25 +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB1_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_SHIFT 24 +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_USB0_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_SHIFT 23 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM3_MASK ((u32)0X00800000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_SHIFT 22 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM2_MASK ((u32)0X00400000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_SHIFT 21 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM1_MASK ((u32)0X00200000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_SHIFT 20 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GEM0_MASK ((u32)0X00100000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_SHIFT 18 +#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_LS_R5_MASK ((u32)0X00040000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_SHIFT 17 +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_1_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_SHIFT 16 +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_R5_0_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_SHIFT 12 +#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_DISPLAY_PORT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_SHIFT 10 +#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_SATA_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_SHIFT 9 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PCIE_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_SHIFT 8 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_GPU_MASK ((u32)0X00000100U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_SHIFT 4 +#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_APU_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_SWRST_TRIG_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_LOGCLR_STATUS + */ +#define PMU_GLOBAL_REQ_LOGCLR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000510U) ) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_SHIFT 17 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_SHIFT 16 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_SHIFT 13 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_SHIFT 12 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_STATUS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_LOGCLR_INT_MASK + */ +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000514U) ) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_SHIFT 17 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_SHIFT 16 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_SHIFT 13 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_SHIFT 12 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_MASK_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_LOGCLR_INT_EN + */ +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000518U) ) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_SHIFT 17 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_SHIFT 16 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_SHIFT 13 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_SHIFT 12 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_EN_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_LOGCLR_INT_DIS + */ +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000051CU) ) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_SHIFT 17 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_SHIFT 16 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_SHIFT 13 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_SHIFT 12 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_INT_DIS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_REQ_LOGCLR_TRIG + */ +#define PMU_GLOBAL_REQ_LOGCLR_TRIG ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000520U) ) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_SHIFT 17 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_SHIFT 16 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_SHIFT 13 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_SHIFT 12 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_SHIFT 10 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_SHIFT 7 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_SHIFT 6 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_SHIFT 3 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_SHIFT 2 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_SHIFT 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_SHIFT 0 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_WIDTH 1 +#define PMU_GLOBAL_REQ_LOGCLR_TRIG_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_LOGCLR_STATUS + */ +#define PMU_GLOBAL_LOGCLR_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000524U) ) + +#define PMU_GLOBAL_LOGCLR_STATUS_FP_SHIFT 17 +#define PMU_GLOBAL_LOGCLR_STATUS_FP_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_FP_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_LOGCLR_STATUS_LP_SHIFT 16 +#define PMU_GLOBAL_LOGCLR_STATUS_LP_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_LP_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_LOGCLR_STATUS_USB1_SHIFT 13 +#define PMU_GLOBAL_LOGCLR_STATUS_USB1_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_USB1_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_LOGCLR_STATUS_USB0_SHIFT 12 +#define PMU_GLOBAL_LOGCLR_STATUS_USB0_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_USB0_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_LOGCLR_STATUS_RPU_SHIFT 10 +#define PMU_GLOBAL_LOGCLR_STATUS_RPU_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_RPU_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_LOGCLR_STATUS_PP1_SHIFT 7 +#define PMU_GLOBAL_LOGCLR_STATUS_PP1_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_PP1_MASK ((u32)0X00000080U) + +#define PMU_GLOBAL_LOGCLR_STATUS_PP0_SHIFT 6 +#define PMU_GLOBAL_LOGCLR_STATUS_PP0_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_PP0_MASK ((u32)0X00000040U) + +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_SHIFT 3 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_SHIFT 2 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_SHIFT 1 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_SHIFT 0 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_WIDTH 1 +#define PMU_GLOBAL_LOGCLR_STATUS_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_CSU_BR_ERROR + */ +#define PMU_GLOBAL_CSU_BR_ERROR ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000528U) ) + +#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_SHIFT 31 +#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_WIDTH 1 +#define PMU_GLOBAL_CSU_BR_ERROR_BR_ERROR_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_SHIFT 0 +#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_WIDTH 16 +#define PMU_GLOBAL_CSU_BR_ERROR_ERR_TYPE_MASK ((u32)0X0000FFFFU) + +/** + * Register: PMU_GLOBAL_MB_FAULT_STATUS + */ +#define PMU_GLOBAL_MB_FAULT_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000052CU) ) + +#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_SHIFT 24 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_WIDTH 8 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_FFAIL_MASK ((u32)0XFF000000U) + +#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_SHIFT 19 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_WIDTH 1 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_SLEEP_RST_MASK ((u32)0X00080000U) + +#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_SHIFT 16 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_WIDTH 3 +#define PMU_GLOBAL_MB_FAULT_STATUS_R_LSFAIL_MASK ((u32)0X00070000U) + +#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_SHIFT 8 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_WIDTH 8 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_FFAIL_MASK ((u32)0X0000FF00U) + +#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_SHIFT 3 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_WIDTH 1 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_SLEEP_RST_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_SHIFT 0 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_WIDTH 3 +#define PMU_GLOBAL_MB_FAULT_STATUS_N_LSFAIL_MASK ((u32)0X00000007U) + +/** + * Register: PMU_GLOBAL_ERROR_STATUS_1 + */ +#define PMU_GLOBAL_ERROR_STATUS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000530U) ) + +#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_STATUS_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_STATUS_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_MASK_1 + */ +#define PMU_GLOBAL_ERROR_INT_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000534U) ) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_INT_MASK_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_MASK_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_INT_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_EN_1 + */ +#define PMU_GLOBAL_ERROR_INT_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000538U) ) + +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_INT_EN_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_EN_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_DIS_1 + */ +#define PMU_GLOBAL_ERROR_INT_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000053CU) ) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_INT_DIS_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_DIS_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_INT_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_STATUS_2 + */ +#define PMU_GLOBAL_ERROR_STATUS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000540U) ) + +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_STATUS_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_STATUS_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_STATUS_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_STATUS_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_STATUS_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_STATUS_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_STATUS_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_MASK_2 + */ +#define PMU_GLOBAL_ERROR_INT_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000544U) ) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_MASK_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_MASK_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_MASK_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_EN_2 + */ +#define PMU_GLOBAL_ERROR_INT_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000548U) ) + +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_EN_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_INT_EN_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_EN_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_EN_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_INT_EN_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_EN_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_EN_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_INT_DIS_2 + */ +#define PMU_GLOBAL_ERROR_INT_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000054CU) ) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_INT_DIS_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_INT_DIS_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_INT_DIS_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_MASK_1 + */ +#define PMU_GLOBAL_ERROR_POR_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000550U) ) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_POR_MASK_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_MASK_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_POR_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_EN_1 + */ +#define PMU_GLOBAL_ERROR_POR_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000554U) ) + +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_POR_EN_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_EN_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_POR_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_DIS_1 + */ +#define PMU_GLOBAL_ERROR_POR_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000558U) ) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_POR_DIS_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_DIS_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_POR_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_MASK_2 + */ +#define PMU_GLOBAL_ERROR_POR_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000055CU) ) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_MASK_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_MASK_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_MASK_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_EN_2 + */ +#define PMU_GLOBAL_ERROR_POR_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000560U) ) + +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_EN_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_POR_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_POR_EN_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_EN_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_EN_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_POR_EN_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_EN_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_EN_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_POR_DIS_2 + */ +#define PMU_GLOBAL_ERROR_POR_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000564U) ) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_POR_DIS_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_POR_DIS_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_POR_DIS_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_MASK_1 + */ +#define PMU_GLOBAL_ERROR_SRST_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000568U) ) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_EN_1 + */ +#define PMU_GLOBAL_ERROR_SRST_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000056CU) ) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SRST_EN_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_EN_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SRST_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_DIS_1 + */ +#define PMU_GLOBAL_ERROR_SRST_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000570U) ) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_MASK_2 + */ +#define PMU_GLOBAL_ERROR_SRST_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000574U) ) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_MASK_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_EN_2 + */ +#define PMU_GLOBAL_ERROR_SRST_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000578U) ) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_EN_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_EN_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_EN_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SRST_DIS_2 + */ +#define PMU_GLOBAL_ERROR_SRST_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000057CU) ) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SRST_DIS_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_MASK_1 + */ +#define PMU_GLOBAL_ERROR_SIG_MASK_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000580U) ) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_EN_1 + */ +#define PMU_GLOBAL_ERROR_SIG_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000584U) ) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SIG_EN_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_EN_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SIG_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_DIS_1 + */ +#define PMU_GLOBAL_ERROR_SIG_DIS_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000588U) ) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_MASK_2 + */ +#define PMU_GLOBAL_ERROR_SIG_MASK_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000058CU) ) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_MASK_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_EN_2 + */ +#define PMU_GLOBAL_ERROR_SIG_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000590U) ) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_EN_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_EN_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_EN_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_SIG_DIS_2 + */ +#define PMU_GLOBAL_ERROR_SIG_DIS_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000594U) ) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_SIG_DIS_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_ERROR_EN_1 + */ +#define PMU_GLOBAL_ERROR_EN_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X000005A0U) ) + +#define PMU_GLOBAL_ERROR_EN_1_AUX3_SHIFT 31 +#define PMU_GLOBAL_ERROR_EN_1_AUX3_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_AUX3_MASK ((u32)0X80000000U) + +#define PMU_GLOBAL_ERROR_EN_1_AUX2_SHIFT 30 +#define PMU_GLOBAL_ERROR_EN_1_AUX2_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_AUX2_MASK ((u32)0X40000000U) + +#define PMU_GLOBAL_ERROR_EN_1_AUX1_SHIFT 29 +#define PMU_GLOBAL_ERROR_EN_1_AUX1_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_AUX1_MASK ((u32)0X20000000U) + +#define PMU_GLOBAL_ERROR_EN_1_AUX0_SHIFT 28 +#define PMU_GLOBAL_ERROR_EN_1_AUX0_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_AUX0_MASK ((u32)0X10000000U) + +#define PMU_GLOBAL_ERROR_EN_1_DFT_SHIFT 27 +#define PMU_GLOBAL_ERROR_EN_1_DFT_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_DFT_MASK ((u32)0X08000000U) + +#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_SHIFT 26 +#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_CLK_MON_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_EN_1_XMPU_SHIFT 24 +#define PMU_GLOBAL_ERROR_EN_1_XMPU_WIDTH 2 +#define PMU_GLOBAL_ERROR_EN_1_XMPU_MASK ((u32)0X03000000U) + +#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_SHIFT 16 +#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_WIDTH 8 +#define PMU_GLOBAL_ERROR_EN_1_PWR_SUPPLY_MASK ((u32)0X00FF0000U) + +#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_SHIFT 13 +#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_FPD_SWDT_MASK ((u32)0X00002000U) + +#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_SHIFT 12 +#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_LPD_SWDT_MASK ((u32)0X00001000U) + +#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_SHIFT 9 +#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_RPU_CCF_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_SHIFT 6 +#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_WIDTH 2 +#define PMU_GLOBAL_ERROR_EN_1_RPU_LS_MASK ((u32)0X000000C0U) + +#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_SHIFT 5 +#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_FPD_TEMP_MASK ((u32)0X00000020U) + +#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_SHIFT 4 +#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_LPD_TEMP_MASK ((u32)0X00000010U) + +#define PMU_GLOBAL_ERROR_EN_1_RPU1_SHIFT 3 +#define PMU_GLOBAL_ERROR_EN_1_RPU1_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_RPU1_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_ERROR_EN_1_RPU0_SHIFT 2 +#define PMU_GLOBAL_ERROR_EN_1_RPU0_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_RPU0_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_SHIFT 1 +#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_OCM_ECC_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_SHIFT 0 +#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_1_DDR_ECC_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ERROR_EN_2 + */ +#define PMU_GLOBAL_ERROR_EN_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X000005A4U) ) + +#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_SHIFT 26 +#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_2_CSU_ROM_MASK ((u32)0X04000000U) + +#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_SHIFT 25 +#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_2_PMU_PB_MASK ((u32)0X02000000U) + +#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_SHIFT 24 +#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_2_PMU_SERVICE_MASK ((u32)0X01000000U) + +#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_SHIFT 18 +#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_WIDTH 4 +#define PMU_GLOBAL_ERROR_EN_2_PMU_FW_MASK ((u32)0X003C0000U) + +#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_SHIFT 17 +#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_2_PMU_UC_MASK ((u32)0X00020000U) + +#define PMU_GLOBAL_ERROR_EN_2_CSU_SHIFT 16 +#define PMU_GLOBAL_ERROR_EN_2_CSU_WIDTH 1 +#define PMU_GLOBAL_ERROR_EN_2_CSU_MASK ((u32)0X00010000U) + +#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_SHIFT 8 +#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_WIDTH 5 +#define PMU_GLOBAL_ERROR_EN_2_PLL_LOCK_MASK ((u32)0X00001F00U) + +#define PMU_GLOBAL_ERROR_EN_2_PL_SHIFT 2 +#define PMU_GLOBAL_ERROR_EN_2_PL_WIDTH 4 +#define PMU_GLOBAL_ERROR_EN_2_PL_MASK ((u32)0X0000003CU) + +#define PMU_GLOBAL_ERROR_EN_2_TO_SHIFT 0 +#define PMU_GLOBAL_ERROR_EN_2_TO_WIDTH 2 +#define PMU_GLOBAL_ERROR_EN_2_TO_MASK ((u32)0X00000003U) + +/** + * Register: PMU_GLOBAL_AIB_CNTRL + */ +#define PMU_GLOBAL_AIB_CNTRL ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000600U) ) + +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_SHIFT 3 +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_WIDTH 1 +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_SHIFT 2 +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_WIDTH 1 +#define PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_SHIFT 1 +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_WIDTH 1 +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_SHIFT 0 +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_WIDTH 1 +#define PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_AIB_STATUS + */ +#define PMU_GLOBAL_AIB_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000604U) ) + +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_SHIFT 3 +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_WIDTH 1 +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_MASK ((u32)0X00000008U) + +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_SHIFT 2 +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_WIDTH 1 +#define PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_SHIFT 1 +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_WIDTH 1 +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_SHIFT 0 +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_WIDTH 1 +#define PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_GLOBAL_RESET + */ +#define PMU_GLOBAL_GLOBAL_RESET ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000608U) ) + +#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_SHIFT 10 +#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_MASK ((u32)0X00000400U) + +#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_SHIFT 9 +#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_RESET_FPD_RST_MASK ((u32)0X00000200U) + +#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_SHIFT 8 +#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_WIDTH 1 +#define PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK ((u32)0X00000100U) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_STATUS + */ +#define PMU_GLOBAL_ROM_VALIDATION_STATUS ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000610U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_SHIFT 1 +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_WIDTH 1 +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_PASS_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_WIDTH 1 +#define PMU_GLOBAL_ROM_VALIDATION_STATUS_DONE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_0 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000614U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_1 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000618U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_2 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000061CU) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_3 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000620U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_4 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000624U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_5 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000628U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_6 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000062CU) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_7 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000630U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_8 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000634U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_9 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000638U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_10 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X0000063CU) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ROM_VALIDATION_DIGEST_11 + */ +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000640U) ) + +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_SHIFT 0 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_WIDTH 32 +#define PMU_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_SAFETY_GATE + */ +#define PMU_GLOBAL_SAFETY_GATE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000650U) ) + +#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_SHIFT 2 +#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_WIDTH 1 +#define PMU_GLOBAL_SAFETY_GATE_PMU_LOGCLR_ENABLE_MASK ((u32)0X00000004U) + +#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_SHIFT 1 +#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_WIDTH 1 +#define PMU_GLOBAL_SAFETY_GATE_LBIST_ENABLE_MASK ((u32)0X00000002U) + +#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_SHIFT 0 +#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_WIDTH 1 +#define PMU_GLOBAL_SAFETY_GATE_SCAN_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_GLOBAL_MBIST_RST + */ +#define PMU_GLOBAL_MBIST_RST ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000700U) ) + +#define PMU_GLOBAL_MBIST_RST_REG_SHIFT 0 +#define PMU_GLOBAL_MBIST_RST_REG_WIDTH 32 +#define PMU_GLOBAL_MBIST_RST_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_MBIST_PG_EN + */ +#define PMU_GLOBAL_MBIST_PG_EN ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000704U) ) + +#define PMU_GLOBAL_MBIST_PG_EN_REG_SHIFT 0 +#define PMU_GLOBAL_MBIST_PG_EN_REG_WIDTH 32 +#define PMU_GLOBAL_MBIST_PG_EN_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_MBIST_SETUP + */ +#define PMU_GLOBAL_MBIST_SETUP ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000708U) ) + +#define PMU_GLOBAL_MBIST_SETUP_REG_SHIFT 0 +#define PMU_GLOBAL_MBIST_SETUP_REG_WIDTH 32 +#define PMU_GLOBAL_MBIST_SETUP_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_MBIST_DONE + */ +#define PMU_GLOBAL_MBIST_DONE ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000710U) ) + +#define PMU_GLOBAL_MBIST_DONE_WORD_SHIFT 0 +#define PMU_GLOBAL_MBIST_DONE_WORD_WIDTH 32 +#define PMU_GLOBAL_MBIST_DONE_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_MBIST_GOOD + */ +#define PMU_GLOBAL_MBIST_GOOD ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000714U) ) + +#define PMU_GLOBAL_MBIST_GOOD_WORD_SHIFT 0 +#define PMU_GLOBAL_MBIST_GOOD_WORD_WIDTH 32 +#define PMU_GLOBAL_MBIST_GOOD_WORD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_SAFETY_CHK + */ +#define PMU_GLOBAL_SAFETY_CHK ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000800U) ) + +#define PMU_GLOBAL_SAFETY_CHK_REG_SHIFT 0 +#define PMU_GLOBAL_SAFETY_CHK_REG_WIDTH 32 +#define PMU_GLOBAL_SAFETY_CHK_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ECO_1 + */ +#define PMU_GLOBAL_ECO_1 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000804U) ) + +#define PMU_GLOBAL_ECO_1_REG_SHIFT 0 +#define PMU_GLOBAL_ECO_1_REG_WIDTH 32 +#define PMU_GLOBAL_ECO_1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_GLOBAL_ECO_2 + */ +#define PMU_GLOBAL_ECO_2 ( ( PMU_GLOBAL_BASEADDR ) + ((u32)0X00000808U) ) + +#define PMU_GLOBAL_ECO_2_REG_SHIFT 0 +#define PMU_GLOBAL_ECO_2_REG_WIDTH 32 +#define PMU_GLOBAL_ECO_2_REG_MASK ((u32)0XFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + + +#endif /* _PMU_GLOBAL_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pmu_iomodule.h b/lib/sw_apps/zynqmp_pmufw/src/pmu_iomodule.h new file mode 100644 index 00000000..152b4170 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pmu_iomodule.h @@ -0,0 +1,1257 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _PMU_IOMODULE_H_ +#define _PMU_IOMODULE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * PMU_IOMODULE Base Address + */ +#define PMU_IOMODULE_BASEADDR ((u32)0XFFD40000U) + +/** + * Register: PMU_IOMODULE_IRQ_MODE + */ +#define PMU_IOMODULE_IRQ_MODE ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000000CU) ) + +/** + * Register: PMU_IOMODULE_GPO0 + */ +#define PMU_IOMODULE_GPO0 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000010U) ) + +#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_SHIFT 24 +#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_WIDTH 8 +#define PMU_IOMODULE_GPO0_MAGIC_WORD_1_MASK ((u32)0XFF000000U) + +#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_SHIFT 16 +#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_WIDTH 8 +#define PMU_IOMODULE_GPO0_MAGIC_WORD_2_MASK ((u32)0X00FF0000U) + +#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_SHIFT 13 +#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_WIDTH 3 +#define PMU_IOMODULE_GPO0_FT_INJECT_FAILURE_MASK ((u32)0X0000E000U) + +#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_SHIFT 12 +#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_WIDTH 1 +#define PMU_IOMODULE_GPO0_DISABLE_RST_FTSM_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_GPO0_RST_FTSM_SHIFT 11 +#define PMU_IOMODULE_GPO0_RST_FTSM_WIDTH 1 +#define PMU_IOMODULE_GPO0_RST_FTSM_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_GPO0_CLR_FTSTS_SHIFT 10 +#define PMU_IOMODULE_GPO0_CLR_FTSTS_WIDTH 1 +#define PMU_IOMODULE_GPO0_CLR_FTSTS_MASK ((u32)0X00000400U) + +#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_SHIFT 9 +#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPO0_RST_ON_SLEEP_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_SHIFT 8 +#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_WIDTH 1 +#define PMU_IOMODULE_GPO0_DISABLE_TRACE_COMP_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_SHIFT 7 +#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_WIDTH 1 +#define PMU_IOMODULE_GPO0_PIT3_PRESCALE_MASK ((u32)0X00000080U) + +#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_SHIFT 5 +#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_WIDTH 2 +#define PMU_IOMODULE_GPO0_PIT2_PRESCALE_MASK ((u32)0X00000060U) + +#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_SHIFT 3 +#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_WIDTH 2 +#define PMU_IOMODULE_GPO0_PIT1_PRESCALE_MASK ((u32)0X00000018U) + +#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_SHIFT 1 +#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_WIDTH 2 +#define PMU_IOMODULE_GPO0_PIT0_PRESCALE_MASK ((u32)0X00000006U) + +#define PMU_IOMODULE_GPO0_DEBUG_REMAP_SHIFT 0 +#define PMU_IOMODULE_GPO0_DEBUG_REMAP_WIDTH 1 +#define PMU_IOMODULE_GPO0_DEBUG_REMAP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPO1 + */ +#define PMU_IOMODULE_GPO1 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000014U) ) + +#define PMU_IOMODULE_GPO1_MIO_5_SHIFT 5 +#define PMU_IOMODULE_GPO1_MIO_5_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_5_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_GPO1_MIO_4_SHIFT 4 +#define PMU_IOMODULE_GPO1_MIO_4_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_4_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_GPO1_MIO_3_SHIFT 3 +#define PMU_IOMODULE_GPO1_MIO_3_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_3_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPO1_MIO_2_SHIFT 2 +#define PMU_IOMODULE_GPO1_MIO_2_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_2_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPO1_MIO_1_SHIFT 1 +#define PMU_IOMODULE_GPO1_MIO_1_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_1_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPO1_MIO_0_SHIFT 0 +#define PMU_IOMODULE_GPO1_MIO_0_WIDTH 1 +#define PMU_IOMODULE_GPO1_MIO_0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPO2 + */ +#define PMU_IOMODULE_GPO2 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000018U) ) + +#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_SHIFT 9 +#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_WIDTH 1 +#define PMU_IOMODULE_GPO2_DAP_RPU_WAKE_ACK_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_SHIFT 8 +#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_WIDTH 1 +#define PMU_IOMODULE_GPO2_DAP_FP_WAKE_ACK_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPO2_PS_STATUS_SHIFT 7 +#define PMU_IOMODULE_GPO2_PS_STATUS_WIDTH 1 +#define PMU_IOMODULE_GPO2_PS_STATUS_MASK ((u32)0X00000080U) + +/** + * Register: PMU_IOMODULE_GPO3 + */ +#define PMU_IOMODULE_GPO3 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000001CU) ) + +#define PMU_IOMODULE_GPO3_PL_GPO_31_SHIFT 31 +#define PMU_IOMODULE_GPO3_PL_GPO_31_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_31_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_30_SHIFT 30 +#define PMU_IOMODULE_GPO3_PL_GPO_30_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_30_MASK ((u32)0X40000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_29_SHIFT 29 +#define PMU_IOMODULE_GPO3_PL_GPO_29_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_29_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_28_SHIFT 28 +#define PMU_IOMODULE_GPO3_PL_GPO_28_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_28_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_27_SHIFT 27 +#define PMU_IOMODULE_GPO3_PL_GPO_27_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_27_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_26_SHIFT 26 +#define PMU_IOMODULE_GPO3_PL_GPO_26_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_26_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_25_SHIFT 25 +#define PMU_IOMODULE_GPO3_PL_GPO_25_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_25_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_24_SHIFT 24 +#define PMU_IOMODULE_GPO3_PL_GPO_24_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_24_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_23_SHIFT 23 +#define PMU_IOMODULE_GPO3_PL_GPO_23_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_23_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_22_SHIFT 22 +#define PMU_IOMODULE_GPO3_PL_GPO_22_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_22_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_21_SHIFT 21 +#define PMU_IOMODULE_GPO3_PL_GPO_21_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_21_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_20_SHIFT 20 +#define PMU_IOMODULE_GPO3_PL_GPO_20_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_20_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_19_SHIFT 19 +#define PMU_IOMODULE_GPO3_PL_GPO_19_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_19_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_18_SHIFT 18 +#define PMU_IOMODULE_GPO3_PL_GPO_18_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_18_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_17_SHIFT 17 +#define PMU_IOMODULE_GPO3_PL_GPO_17_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_17_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_16_SHIFT 16 +#define PMU_IOMODULE_GPO3_PL_GPO_16_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_16_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_15_SHIFT 15 +#define PMU_IOMODULE_GPO3_PL_GPO_15_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_15_MASK ((u32)0X00008000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_14_SHIFT 14 +#define PMU_IOMODULE_GPO3_PL_GPO_14_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_14_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_13_SHIFT 13 +#define PMU_IOMODULE_GPO3_PL_GPO_13_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_13_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_12_SHIFT 12 +#define PMU_IOMODULE_GPO3_PL_GPO_12_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_12_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_GPO3_PL_GPO_11_SHIFT 11 +#define PMU_IOMODULE_GPO3_PL_GPO_11_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_11_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_GPO3_PL_GPO_10_SHIFT 10 +#define PMU_IOMODULE_GPO3_PL_GPO_10_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_10_MASK ((u32)0X00000400U) + +#define PMU_IOMODULE_GPO3_PL_GPO_9_SHIFT 9 +#define PMU_IOMODULE_GPO3_PL_GPO_9_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_9_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPO3_PL_GPO_8_SHIFT 8 +#define PMU_IOMODULE_GPO3_PL_GPO_8_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_8_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPO3_PL_GPO_7_SHIFT 7 +#define PMU_IOMODULE_GPO3_PL_GPO_7_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_7_MASK ((u32)0X00000080U) + +#define PMU_IOMODULE_GPO3_PL_GPO_6_SHIFT 6 +#define PMU_IOMODULE_GPO3_PL_GPO_6_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_6_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_GPO3_PL_GPO_5_SHIFT 5 +#define PMU_IOMODULE_GPO3_PL_GPO_5_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_5_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_GPO3_PL_GPO_4_SHIFT 4 +#define PMU_IOMODULE_GPO3_PL_GPO_4_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_4_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_GPO3_PL_GPO_3_SHIFT 3 +#define PMU_IOMODULE_GPO3_PL_GPO_3_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_3_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPO3_PL_GPO_2_SHIFT 2 +#define PMU_IOMODULE_GPO3_PL_GPO_2_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_2_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPO3_PL_GPO_1_SHIFT 1 +#define PMU_IOMODULE_GPO3_PL_GPO_1_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_1_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPO3_PL_GPO_0_SHIFT 0 +#define PMU_IOMODULE_GPO3_PL_GPO_0_WIDTH 1 +#define PMU_IOMODULE_GPO3_PL_GPO_0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPI0 + */ +#define PMU_IOMODULE_GPI0 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000020U) ) + +#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_SHIFT 31 +#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_ECC_FATAL_ERR_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_SHIFT 30 +#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_VOTER_ERR_MASK ((u32)0X40000000U) + +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_SHIFT 29 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_23_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_SHIFT 28 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_13_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_SHIFT 27 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_COMPARE_ERR_12_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_SHIFT 26 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_B_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_SHIFT 25 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_B_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_SHIFT 24 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_B_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_SHIFT 23 +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_STATE_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_SHIFT 22 +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_MISMATCH_CPU_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_SHIFT 19 +#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_SLEEP_RESET_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_SHIFT 18 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_23_A_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_SHIFT 17 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_13_A_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_SHIFT 16 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_RFT_LS_MISMATCH_12_A_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_SHIFT 15 +#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_ECC_FATAL_ERR_MASK ((u32)0X00008000U) + +#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_SHIFT 14 +#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_VOTER_ERR_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_SHIFT 13 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_23_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_SHIFT 12 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_13_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_SHIFT 11 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_COMPARE_ERR_12_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_SHIFT 10 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_B_MASK ((u32)0X00000400U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_SHIFT 9 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_B_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_SHIFT 8 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_B_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_SHIFT 7 +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_STATE_MASK ((u32)0X00000080U) + +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_SHIFT 6 +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_MISMATCH_CPU_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_SHIFT 3 +#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_SLEEP_RESET_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_SHIFT 2 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_23_A_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_SHIFT 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_13_A_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_SHIFT 0 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_WIDTH 1 +#define PMU_IOMODULE_GPI0_NFT_LS_MISMATCH_12_A_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPI1 + */ +#define PMU_IOMODULE_GPI1 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000024U) ) + +#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_SHIFT 31 +#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_WIDTH 1 +#define PMU_IOMODULE_GPI1_APB_AIB_ERROR_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_SHIFT 30 +#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_WIDTH 1 +#define PMU_IOMODULE_GPI1_AXI_AIB_ERROR_MASK ((u32)0X40000000U) + +#define PMU_IOMODULE_GPI1_ERROR_2_SHIFT 29 +#define PMU_IOMODULE_GPI1_ERROR_2_WIDTH 1 +#define PMU_IOMODULE_GPI1_ERROR_2_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_GPI1_ERROR_1_SHIFT 28 +#define PMU_IOMODULE_GPI1_ERROR_1_WIDTH 1 +#define PMU_IOMODULE_GPI1_ERROR_1_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_SHIFT 23 +#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_SHIFT 22 +#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_SHIFT 21 +#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_SHIFT 20 +#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_SHIFT 16 +#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_WIDTH 1 +#define PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_5_SHIFT 15 +#define PMU_IOMODULE_GPI1_MIO_WAKE_5_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK ((u32)0X00008000U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_4_SHIFT 14 +#define PMU_IOMODULE_GPI1_MIO_WAKE_4_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_3_SHIFT 13 +#define PMU_IOMODULE_GPI1_MIO_WAKE_3_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_2_SHIFT 12 +#define PMU_IOMODULE_GPI1_MIO_WAKE_2_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_1_SHIFT 11 +#define PMU_IOMODULE_GPI1_MIO_WAKE_1_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_GPI1_MIO_WAKE_0_SHIFT 10 +#define PMU_IOMODULE_GPI1_MIO_WAKE_0_WIDTH 1 +#define PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK ((u32)0X00000400U) + +#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_SHIFT 9 +#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_DAP_RPU_WAKE_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_SHIFT 8 +#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_DAP_FPD_WAKE_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPI1_USB_1_WAKE_SHIFT 7 +#define PMU_IOMODULE_GPI1_USB_1_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_USB_1_WAKE_MASK ((u32)0X00000080U) + +#define PMU_IOMODULE_GPI1_USB_0_WAKE_SHIFT 6 +#define PMU_IOMODULE_GPI1_USB_0_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_USB_0_WAKE_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_GPI1_R5_1_WAKE_SHIFT 5 +#define PMU_IOMODULE_GPI1_R5_1_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_R5_1_WAKE_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_GPI1_R5_0_WAKE_SHIFT 4 +#define PMU_IOMODULE_GPI1_R5_0_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_R5_0_WAKE_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_SHIFT 3 +#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_SHIFT 2 +#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_SHIFT 1 +#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_SHIFT 0 +#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_WIDTH 1 +#define PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPI2 + */ +#define PMU_IOMODULE_GPI2 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000028U) ) + +#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_SHIFT 31 +#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_WIDTH 1 +#define PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_SHIFT 30 +#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_WIDTH 1 +#define PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_MASK ((u32)0X40000000U) + +#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_SHIFT 29 +#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_WIDTH 1 +#define PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_SHIFT 23 +#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_SHIFT 22 +#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_SHIFT 21 +#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_SHIFT 20 +#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_SHIFT 19 +#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_SHIFT 18 +#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_SHIFT 17 +#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_SHIFT 16 +#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_SHIFT 9 +#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_SHIFT 8 +#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPI2_R5_1_SLEEP_SHIFT 5 +#define PMU_IOMODULE_GPI2_R5_1_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_GPI2_R5_0_SLEEP_SHIFT 4 +#define PMU_IOMODULE_GPI2_R5_0_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_SHIFT 3 +#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_SHIFT 2 +#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_SHIFT 1 +#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_SHIFT 0 +#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_WIDTH 1 +#define PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_GPI3 + */ +#define PMU_IOMODULE_GPI3 ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000002CU) ) + +#define PMU_IOMODULE_GPI3_PL_GPI_31_SHIFT 31 +#define PMU_IOMODULE_GPI3_PL_GPI_31_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_31_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_30_SHIFT 30 +#define PMU_IOMODULE_GPI3_PL_GPI_30_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_30_MASK ((u32)0X40000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_29_SHIFT 29 +#define PMU_IOMODULE_GPI3_PL_GPI_29_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_29_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_28_SHIFT 28 +#define PMU_IOMODULE_GPI3_PL_GPI_28_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_28_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_27_SHIFT 27 +#define PMU_IOMODULE_GPI3_PL_GPI_27_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_27_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_26_SHIFT 26 +#define PMU_IOMODULE_GPI3_PL_GPI_26_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_26_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_25_SHIFT 25 +#define PMU_IOMODULE_GPI3_PL_GPI_25_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_25_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_24_SHIFT 24 +#define PMU_IOMODULE_GPI3_PL_GPI_24_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_24_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_23_SHIFT 23 +#define PMU_IOMODULE_GPI3_PL_GPI_23_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_23_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_22_SHIFT 22 +#define PMU_IOMODULE_GPI3_PL_GPI_22_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_22_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_21_SHIFT 21 +#define PMU_IOMODULE_GPI3_PL_GPI_21_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_21_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_20_SHIFT 20 +#define PMU_IOMODULE_GPI3_PL_GPI_20_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_20_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_19_SHIFT 19 +#define PMU_IOMODULE_GPI3_PL_GPI_19_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_19_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_18_SHIFT 18 +#define PMU_IOMODULE_GPI3_PL_GPI_18_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_18_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_17_SHIFT 17 +#define PMU_IOMODULE_GPI3_PL_GPI_17_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_17_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_16_SHIFT 16 +#define PMU_IOMODULE_GPI3_PL_GPI_16_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_16_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_15_SHIFT 15 +#define PMU_IOMODULE_GPI3_PL_GPI_15_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_15_MASK ((u32)0X00008000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_14_SHIFT 14 +#define PMU_IOMODULE_GPI3_PL_GPI_14_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_14_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_13_SHIFT 13 +#define PMU_IOMODULE_GPI3_PL_GPI_13_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_13_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_12_SHIFT 12 +#define PMU_IOMODULE_GPI3_PL_GPI_12_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_12_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_GPI3_PL_GPI_11_SHIFT 11 +#define PMU_IOMODULE_GPI3_PL_GPI_11_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_11_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_GPI3_PL_GPI_10_SHIFT 10 +#define PMU_IOMODULE_GPI3_PL_GPI_10_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_10_MASK ((u32)0X00000400U) + +#define PMU_IOMODULE_GPI3_PL_GPI_9_SHIFT 9 +#define PMU_IOMODULE_GPI3_PL_GPI_9_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_9_MASK ((u32)0X00000200U) + +#define PMU_IOMODULE_GPI3_PL_GPI_8_SHIFT 8 +#define PMU_IOMODULE_GPI3_PL_GPI_8_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_8_MASK ((u32)0X00000100U) + +#define PMU_IOMODULE_GPI3_PL_GPI_7_SHIFT 7 +#define PMU_IOMODULE_GPI3_PL_GPI_7_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_7_MASK ((u32)0X00000080U) + +#define PMU_IOMODULE_GPI3_PL_GPI_6_SHIFT 6 +#define PMU_IOMODULE_GPI3_PL_GPI_6_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_6_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_GPI3_PL_GPI_5_SHIFT 5 +#define PMU_IOMODULE_GPI3_PL_GPI_5_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_5_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_GPI3_PL_GPI_4_SHIFT 4 +#define PMU_IOMODULE_GPI3_PL_GPI_4_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_4_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_GPI3_PL_GPI_3_SHIFT 3 +#define PMU_IOMODULE_GPI3_PL_GPI_3_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_3_MASK ((u32)0X00000008U) + +#define PMU_IOMODULE_GPI3_PL_GPI_2_SHIFT 2 +#define PMU_IOMODULE_GPI3_PL_GPI_2_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_2_MASK ((u32)0X00000004U) + +#define PMU_IOMODULE_GPI3_PL_GPI_1_SHIFT 1 +#define PMU_IOMODULE_GPI3_PL_GPI_1_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_1_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_GPI3_PL_GPI_0_SHIFT 0 +#define PMU_IOMODULE_GPI3_PL_GPI_0_WIDTH 1 +#define PMU_IOMODULE_GPI3_PL_GPI_0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_IRQ_STATUS + */ +#define PMU_IOMODULE_IRQ_STATUS ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000030U) ) + +#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_SHIFT 31 +#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_SHIFT 29 +#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_INV_ADDR_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_SHIFT 28 +#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PWR_DN_REQ_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_SHIFT 27 +#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PWR_UP_REQ_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_SHIFT 26 +#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_SW_RST_REQ_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_SHIFT 25 +#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_HW_RST_REQ_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_SHIFT 24 +#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_ISO_REQ_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_SHIFT 23 +#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_LOGCLR_REQ_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_IRQ_STATUS_IPI3_SHIFT 22 +#define PMU_IOMODULE_IRQ_STATUS_IPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_IPI3_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_IRQ_STATUS_IPI2_SHIFT 21 +#define PMU_IOMODULE_IRQ_STATUS_IPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_IPI2_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_IRQ_STATUS_IPI1_SHIFT 20 +#define PMU_IOMODULE_IRQ_STATUS_IPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_IPI1_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_IRQ_STATUS_IPI0_SHIFT 19 +#define PMU_IOMODULE_IRQ_STATUS_IPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_IPI0_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_SHIFT 18 +#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_RTC_ALARM_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_SHIFT 17 +#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_RTC_EVERY_SECOND_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_SHIFT 16 +#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_CORRECTABLE_ECC_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_IRQ_STATUS_GPI3_SHIFT 14 +#define PMU_IOMODULE_IRQ_STATUS_GPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_GPI3_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_IRQ_STATUS_GPI2_SHIFT 13 +#define PMU_IOMODULE_IRQ_STATUS_GPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_GPI2_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_IRQ_STATUS_GPI1_SHIFT 12 +#define PMU_IOMODULE_IRQ_STATUS_GPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_GPI1_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_IRQ_STATUS_GPI0_SHIFT 11 +#define PMU_IOMODULE_IRQ_STATUS_GPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_GPI0_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_IRQ_STATUS_PIT3_SHIFT 6 +#define PMU_IOMODULE_IRQ_STATUS_PIT3_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PIT3_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_IRQ_STATUS_PIT2_SHIFT 5 +#define PMU_IOMODULE_IRQ_STATUS_PIT2_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PIT2_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_IRQ_STATUS_PIT1_SHIFT 4 +#define PMU_IOMODULE_IRQ_STATUS_PIT1_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PIT1_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_IRQ_STATUS_PIT0_SHIFT 3 +#define PMU_IOMODULE_IRQ_STATUS_PIT0_WIDTH 1 +#define PMU_IOMODULE_IRQ_STATUS_PIT0_MASK ((u32)0X00000008U) + +/** + * Register: PMU_IOMODULE_IRQ_PENDING + */ +#define PMU_IOMODULE_IRQ_PENDING ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000034U) ) + +#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_SHIFT 31 +#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_SHIFT 29 +#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_SHIFT 28 +#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_SHIFT 27 +#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_SHIFT 26 +#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_SHIFT 25 +#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_SHIFT 24 +#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_SHIFT 23 +#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_LOGCLR_REQ_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_IRQ_PENDING_IPI3_SHIFT 22 +#define PMU_IOMODULE_IRQ_PENDING_IPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_IPI3_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_IRQ_PENDING_IPI2_SHIFT 21 +#define PMU_IOMODULE_IRQ_PENDING_IPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_IPI2_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_IRQ_PENDING_IPI1_SHIFT 20 +#define PMU_IOMODULE_IRQ_PENDING_IPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_IPI1_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_IRQ_PENDING_IPI0_SHIFT 19 +#define PMU_IOMODULE_IRQ_PENDING_IPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_IPI0_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_SHIFT 18 +#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_SHIFT 17 +#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_SHIFT 16 +#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_IRQ_PENDING_GPI3_SHIFT 14 +#define PMU_IOMODULE_IRQ_PENDING_GPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_GPI3_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_IRQ_PENDING_GPI2_SHIFT 13 +#define PMU_IOMODULE_IRQ_PENDING_GPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_GPI2_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_IRQ_PENDING_GPI1_SHIFT 12 +#define PMU_IOMODULE_IRQ_PENDING_GPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_GPI1_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_IRQ_PENDING_GPI0_SHIFT 11 +#define PMU_IOMODULE_IRQ_PENDING_GPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_GPI0_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_IRQ_PENDING_PIT3_SHIFT 6 +#define PMU_IOMODULE_IRQ_PENDING_PIT3_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PIT3_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_IRQ_PENDING_PIT2_SHIFT 5 +#define PMU_IOMODULE_IRQ_PENDING_PIT2_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PIT2_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_IRQ_PENDING_PIT1_SHIFT 4 +#define PMU_IOMODULE_IRQ_PENDING_PIT1_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PIT1_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_IRQ_PENDING_PIT0_SHIFT 3 +#define PMU_IOMODULE_IRQ_PENDING_PIT0_WIDTH 1 +#define PMU_IOMODULE_IRQ_PENDING_PIT0_MASK ((u32)0X00000008U) + +/** + * Register: PMU_IOMODULE_IRQ_ENABLE + */ +#define PMU_IOMODULE_IRQ_ENABLE ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000038U) ) + +#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_SHIFT 31 +#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_SHIFT 29 +#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_INV_ADDR_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_SHIFT 28 +#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PWR_DN_REQ_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_SHIFT 27 +#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PWR_UP_REQ_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_SHIFT 26 +#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_SW_RST_REQ_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_SHIFT 25 +#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_HW_RST_REQ_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_SHIFT 24 +#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_ISO_REQ_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_SHIFT 23 +#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_LOGCLR_REQ_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_IRQ_ENABLE_IPI3_SHIFT 22 +#define PMU_IOMODULE_IRQ_ENABLE_IPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_IPI3_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_IRQ_ENABLE_IPI2_SHIFT 21 +#define PMU_IOMODULE_IRQ_ENABLE_IPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_IPI2_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_IRQ_ENABLE_IPI1_SHIFT 20 +#define PMU_IOMODULE_IRQ_ENABLE_IPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_IPI1_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_IRQ_ENABLE_IPI0_SHIFT 19 +#define PMU_IOMODULE_IRQ_ENABLE_IPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_SHIFT 18 +#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_RTC_ALARM_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_SHIFT 17 +#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_RTC_EVERY_SECOND_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_SHIFT 16 +#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_CORRECTABLE_ECC_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_IRQ_ENABLE_GPI3_SHIFT 14 +#define PMU_IOMODULE_IRQ_ENABLE_GPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_GPI3_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_IRQ_ENABLE_GPI2_SHIFT 13 +#define PMU_IOMODULE_IRQ_ENABLE_GPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_GPI2_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_IRQ_ENABLE_GPI1_SHIFT 12 +#define PMU_IOMODULE_IRQ_ENABLE_GPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_GPI1_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_IRQ_ENABLE_GPI0_SHIFT 11 +#define PMU_IOMODULE_IRQ_ENABLE_GPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_GPI0_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_IRQ_ENABLE_PIT3_SHIFT 6 +#define PMU_IOMODULE_IRQ_ENABLE_PIT3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PIT3_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_IRQ_ENABLE_PIT2_SHIFT 5 +#define PMU_IOMODULE_IRQ_ENABLE_PIT2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PIT2_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_IRQ_ENABLE_PIT1_SHIFT 4 +#define PMU_IOMODULE_IRQ_ENABLE_PIT1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_IRQ_ENABLE_PIT0_SHIFT 3 +#define PMU_IOMODULE_IRQ_ENABLE_PIT0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ENABLE_PIT0_MASK ((u32)0X00000008U) + +/** + * Register: PMU_IOMODULE_IRQ_ACK + */ +#define PMU_IOMODULE_IRQ_ACK ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X0000003CU) ) + +#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_SHIFT 31 +#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_CSU_PMU_SEC_LOCK_MASK ((u32)0X80000000U) + +#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_SHIFT 29 +#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_INV_ADDR_MASK ((u32)0X20000000U) + +#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_SHIFT 28 +#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PWR_DN_REQ_MASK ((u32)0X10000000U) + +#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_SHIFT 27 +#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PWR_UP_REQ_MASK ((u32)0X08000000U) + +#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_SHIFT 26 +#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_SW_RST_REQ_MASK ((u32)0X04000000U) + +#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_SHIFT 25 +#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_HW_RST_REQ_MASK ((u32)0X02000000U) + +#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_SHIFT 24 +#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_ISO_REQ_MASK ((u32)0X01000000U) + +#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_SHIFT 23 +#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_LOGCLR_REQ_MASK ((u32)0X00800000U) + +#define PMU_IOMODULE_IRQ_ACK_IPI3_SHIFT 22 +#define PMU_IOMODULE_IRQ_ACK_IPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_IPI3_MASK ((u32)0X00400000U) + +#define PMU_IOMODULE_IRQ_ACK_IPI2_SHIFT 21 +#define PMU_IOMODULE_IRQ_ACK_IPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_IPI2_MASK ((u32)0X00200000U) + +#define PMU_IOMODULE_IRQ_ACK_IPI1_SHIFT 20 +#define PMU_IOMODULE_IRQ_ACK_IPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_IPI1_MASK ((u32)0X00100000U) + +#define PMU_IOMODULE_IRQ_ACK_IPI0_SHIFT 19 +#define PMU_IOMODULE_IRQ_ACK_IPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_IPI0_MASK ((u32)0X00080000U) + +#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_SHIFT 18 +#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_RTC_ALARM_MASK ((u32)0X00040000U) + +#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_SHIFT 17 +#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_RTC_EVERY_SECOND_MASK ((u32)0X00020000U) + +#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_SHIFT 16 +#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_CORRECTABLE_ECC_MASK ((u32)0X00010000U) + +#define PMU_IOMODULE_IRQ_ACK_GPI3_SHIFT 14 +#define PMU_IOMODULE_IRQ_ACK_GPI3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_GPI3_MASK ((u32)0X00004000U) + +#define PMU_IOMODULE_IRQ_ACK_GPI2_SHIFT 13 +#define PMU_IOMODULE_IRQ_ACK_GPI2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_GPI2_MASK ((u32)0X00002000U) + +#define PMU_IOMODULE_IRQ_ACK_GPI1_SHIFT 12 +#define PMU_IOMODULE_IRQ_ACK_GPI1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_GPI1_MASK ((u32)0X00001000U) + +#define PMU_IOMODULE_IRQ_ACK_GPI0_SHIFT 11 +#define PMU_IOMODULE_IRQ_ACK_GPI0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_GPI0_MASK ((u32)0X00000800U) + +#define PMU_IOMODULE_IRQ_ACK_PIT3_SHIFT 6 +#define PMU_IOMODULE_IRQ_ACK_PIT3_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PIT3_MASK ((u32)0X00000040U) + +#define PMU_IOMODULE_IRQ_ACK_PIT2_SHIFT 5 +#define PMU_IOMODULE_IRQ_ACK_PIT2_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PIT2_MASK ((u32)0X00000020U) + +#define PMU_IOMODULE_IRQ_ACK_PIT1_SHIFT 4 +#define PMU_IOMODULE_IRQ_ACK_PIT1_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PIT1_MASK ((u32)0X00000010U) + +#define PMU_IOMODULE_IRQ_ACK_PIT0_SHIFT 3 +#define PMU_IOMODULE_IRQ_ACK_PIT0_WIDTH 1 +#define PMU_IOMODULE_IRQ_ACK_PIT0_MASK ((u32)0X00000008U) + +/** + * Register: PMU_IOMODULE_PIT0_PRELOAD + */ +#define PMU_IOMODULE_PIT0_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000040U) ) + +#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_SHIFT 0 +#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_WIDTH 32 +#define PMU_IOMODULE_PIT0_PRELOAD_PIT0_PRELOAD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT0_COUNTER + */ +#define PMU_IOMODULE_PIT0_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000044U) ) + +#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_SHIFT 0 +#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_WIDTH 32 +#define PMU_IOMODULE_PIT0_COUNTER_PIT0_COUNTER_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT0_CONTROL + */ +#define PMU_IOMODULE_PIT0_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000048U) ) + +#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_SHIFT 1 +#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_WIDTH 1 +#define PMU_IOMODULE_PIT0_CONTROL_PRELOAD_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_PIT0_CONTROL_EN_SHIFT 0 +#define PMU_IOMODULE_PIT0_CONTROL_EN_WIDTH 1 +#define PMU_IOMODULE_PIT0_CONTROL_EN_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_PIT1_PRELOAD + */ +#define PMU_IOMODULE_PIT1_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000050U) ) + +#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_SHIFT 0 +#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_WIDTH 32 +#define PMU_IOMODULE_PIT1_PRELOAD_PIT1_PRELOAD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT1_COUNTER + */ +#define PMU_IOMODULE_PIT1_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000054U) ) + +#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_SHIFT 0 +#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_WIDTH 32 +#define PMU_IOMODULE_PIT1_COUNTER_PIT1_COUNTER_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT1_CONTROL + */ +#define PMU_IOMODULE_PIT1_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000058U) ) + +#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_SHIFT 1 +#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_WIDTH 1 +#define PMU_IOMODULE_PIT1_CONTROL_PRELOAD_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_PIT1_CONTROL_EN_SHIFT 0 +#define PMU_IOMODULE_PIT1_CONTROL_EN_WIDTH 1 +#define PMU_IOMODULE_PIT1_CONTROL_EN_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_PIT2_PRELOAD + */ +#define PMU_IOMODULE_PIT2_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000060U) ) + +#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_SHIFT 0 +#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_WIDTH 32 +#define PMU_IOMODULE_PIT2_PRELOAD_PIT2_PRELOAD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT2_COUNTER + */ +#define PMU_IOMODULE_PIT2_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000064U) ) + +#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_SHIFT 0 +#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_WIDTH 32 +#define PMU_IOMODULE_PIT2_COUNTER_PIT2_COUNTER_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT2_CONTROL + */ +#define PMU_IOMODULE_PIT2_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000068U) ) + +#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_SHIFT 1 +#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_WIDTH 1 +#define PMU_IOMODULE_PIT2_CONTROL_PRELOAD_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_PIT2_CONTROL_EN_SHIFT 0 +#define PMU_IOMODULE_PIT2_CONTROL_EN_WIDTH 1 +#define PMU_IOMODULE_PIT2_CONTROL_EN_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_PIT3_PRELOAD + */ +#define PMU_IOMODULE_PIT3_PRELOAD ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000070U) ) + +#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_SHIFT 0 +#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_WIDTH 32 +#define PMU_IOMODULE_PIT3_PRELOAD_PIT3_PRELOAD_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT3_COUNTER + */ +#define PMU_IOMODULE_PIT3_COUNTER ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000074U) ) + +#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_SHIFT 0 +#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_WIDTH 32 +#define PMU_IOMODULE_PIT3_COUNTER_PIT3_COUNTER_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_PIT3_CONTROL + */ +#define PMU_IOMODULE_PIT3_CONTROL ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00000078U) ) + +#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_SHIFT 1 +#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_WIDTH 1 +#define PMU_IOMODULE_PIT3_CONTROL_PRELOAD_MASK ((u32)0X00000002U) + +#define PMU_IOMODULE_PIT3_CONTROL_EN_SHIFT 0 +#define PMU_IOMODULE_PIT3_CONTROL_EN_WIDTH 1 +#define PMU_IOMODULE_PIT3_CONTROL_EN_MASK ((u32)0X00000001U) + +/** + * Register: PMU_IOMODULE_INSTRUCTION_INJECT_ADDR + */ +#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00001014U) ) + +#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_SHIFT 0 +#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_WIDTH 32 +#define PMU_IOMODULE_INSTRUCTION_INJECT_ADDR_BIT0_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_IOMODULE_INSTRUCTION_INJECT + */ +#define PMU_IOMODULE_INSTRUCTION_INJECT ( ( PMU_IOMODULE_BASEADDR ) + ((u32)0X00001018U) ) + +#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_SHIFT 0 +#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_WIDTH 32 +#define PMU_IOMODULE_INSTRUCTION_INJECT_BIT0_MASK ((u32)0XFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + + +#endif /* _PMU_IOMODULE_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/pmu_local.h b/lib/sw_apps/zynqmp_pmufw/src/pmu_local.h new file mode 100644 index 00000000..104d9781 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/pmu_local.h @@ -0,0 +1,1263 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef _PMU_LOCAL_H_ +#define _PMU_LOCAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * PMU_LOCAL Base Address + */ +#define PMU_LOCAL_BASEADDR ((u32)0XFFD60000U) + +/** + * Register: PMU_LOCAL_ACPU0_PWR_CNTRL + */ +#define PMU_LOCAL_ACPU0_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000000U) ) + +#define PMU_LOCAL_ACPU0_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_ACPU0_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_ACPU0_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_ACPU0_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU0_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU0_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU0_PWR_STATUS + */ +#define PMU_LOCAL_ACPU0_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000004U) ) + +#define PMU_LOCAL_ACPU0_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU0_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU0_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU1_PWR_CNTRL + */ +#define PMU_LOCAL_ACPU1_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000010U) ) + +#define PMU_LOCAL_ACPU1_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_ACPU1_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_ACPU1_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_ACPU1_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU1_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU1_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU1_PWR_STATUS + */ +#define PMU_LOCAL_ACPU1_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000014U) ) + +#define PMU_LOCAL_ACPU1_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU1_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU1_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU2_PWR_CNTRL + */ +#define PMU_LOCAL_ACPU2_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000020U) ) + +#define PMU_LOCAL_ACPU2_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_ACPU2_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_ACPU2_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_ACPU2_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU2_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU2_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU2_PWR_STATUS + */ +#define PMU_LOCAL_ACPU2_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000024U) ) + +#define PMU_LOCAL_ACPU2_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU2_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU2_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU3_PWR_CNTRL + */ +#define PMU_LOCAL_ACPU3_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000030U) ) + +#define PMU_LOCAL_ACPU3_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_ACPU3_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_ACPU3_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_ACPU3_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU3_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU3_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_ACPU3_PWR_STATUS + */ +#define PMU_LOCAL_ACPU3_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000034U) ) + +#define PMU_LOCAL_ACPU3_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_ACPU3_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_ACPU3_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_PP0_PWR_CNTRL + */ +#define PMU_LOCAL_PP0_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000040U) ) + +#define PMU_LOCAL_PP0_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_PP0_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_PP0_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_PP0_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_PP0_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_PP0_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_PP0_PWR_STATUS + */ +#define PMU_LOCAL_PP0_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000044U) ) + +#define PMU_LOCAL_PP0_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_PP0_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_PP0_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_PP1_PWR_CNTRL + */ +#define PMU_LOCAL_PP1_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000048U) ) + +#define PMU_LOCAL_PP1_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_PP1_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_PP1_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_PP1_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_PP1_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_PP1_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_PP1_PWR_STATUS + */ +#define PMU_LOCAL_PP1_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000004CU) ) + +#define PMU_LOCAL_PP1_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_PP1_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_PP1_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_USB0_PWR_CNTRL + */ +#define PMU_LOCAL_USB0_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000060U) ) + +#define PMU_LOCAL_USB0_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_USB0_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_USB0_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_USB0_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_USB0_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_USB0_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_USB0_PWR_STATUS + */ +#define PMU_LOCAL_USB0_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000064U) ) + +#define PMU_LOCAL_USB0_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_USB0_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_USB0_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_USB1_PWR_CNTRL + */ +#define PMU_LOCAL_USB1_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000070U) ) + +#define PMU_LOCAL_USB1_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_USB1_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_USB1_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_USB1_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_USB1_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_USB1_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_USB1_PWR_STATUS + */ +#define PMU_LOCAL_USB1_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000074U) ) + +#define PMU_LOCAL_USB1_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_USB1_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_USB1_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_RPU_PWR_CNTRL + */ +#define PMU_LOCAL_RPU_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000080U) ) + +#define PMU_LOCAL_RPU_PWR_CNTRL_ISOLATION_SHIFT 4 +#define PMU_LOCAL_RPU_PWR_CNTRL_ISOLATION_WIDTH 1 +#define PMU_LOCAL_RPU_PWR_CNTRL_ISOLATION_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_RPU_PWR_CNTRL_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_RPU_PWR_CNTRL_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_RPU_PWR_CNTRL_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_RPU_PWR_STATUS + */ +#define PMU_LOCAL_RPU_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000084U) ) + +#define PMU_LOCAL_RPU_PWR_STATUS_PWR_GATES_SHIFT 0 +#define PMU_LOCAL_RPU_PWR_STATUS_PWR_GATES_WIDTH 4 +#define PMU_LOCAL_RPU_PWR_STATUS_PWR_GATES_MASK ((u32)0X0000000FU) + +/** + * Register: PMU_LOCAL_L2_PWR_CNTRL + */ +#define PMU_LOCAL_L2_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000B0U) ) + +#define PMU_LOCAL_L2_PWR_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_L2_PWR_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_L2_PWR_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_L2_RET_CNTRL + */ +#define PMU_LOCAL_L2_RET_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000B4U) ) + +#define PMU_LOCAL_L2_RET_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_L2_RET_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_L2_RET_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_L2_CE_CNTRL + */ +#define PMU_LOCAL_L2_CE_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000B8U) ) + +#define PMU_LOCAL_L2_CE_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_L2_CE_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_L2_CE_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_L2_PWR_STATUS + */ +#define PMU_LOCAL_L2_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000BCU) ) + +#define PMU_LOCAL_L2_PWR_STATUS_BANK0_SHIFT 0 +#define PMU_LOCAL_L2_PWR_STATUS_BANK0_WIDTH 1 +#define PMU_LOCAL_L2_PWR_STATUS_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_OCM_PWR_CNTRL + */ +#define PMU_LOCAL_OCM_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000C0U) ) + +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK3_SHIFT 24 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK3_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK3_MASK ((u32)0X01000000U) + +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK2_SHIFT 16 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK2_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK2_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK1_SHIFT 8 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK1_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK1_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_OCM_RET_CNTRL + */ +#define PMU_LOCAL_OCM_RET_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000C4U) ) + +#define PMU_LOCAL_OCM_RET_CNTRL_BANK3_SHIFT 3 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK3_WIDTH 1 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK3_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_OCM_RET_CNTRL_BANK2_SHIFT 2 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK2_WIDTH 1 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_OCM_RET_CNTRL_BANK1_SHIFT 1 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK1_WIDTH 1 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_OCM_RET_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_OCM_RET_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_OCM_CE_CNTRL + */ +#define PMU_LOCAL_OCM_CE_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000C8U) ) + +#define PMU_LOCAL_OCM_CE_CNTRL_BANK3_SHIFT 3 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK3_WIDTH 1 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK3_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_OCM_CE_CNTRL_BANK2_SHIFT 2 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK2_WIDTH 1 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_OCM_CE_CNTRL_BANK1_SHIFT 1 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK1_WIDTH 1 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_OCM_CE_CNTRL_BANK0_SHIFT 0 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK0_WIDTH 1 +#define PMU_LOCAL_OCM_CE_CNTRL_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_OCM_PWR_STATUS + */ +#define PMU_LOCAL_OCM_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000CCU) ) + +#define PMU_LOCAL_OCM_PWR_STATUS_BANK3_SHIFT 24 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK3_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK3_MASK ((u32)0X01000000U) + +#define PMU_LOCAL_OCM_PWR_STATUS_BANK2_SHIFT 16 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK2_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK2_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_OCM_PWR_STATUS_BANK1_SHIFT 8 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK1_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK1_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_OCM_PWR_STATUS_BANK0_SHIFT 0 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK0_WIDTH 1 +#define PMU_LOCAL_OCM_PWR_STATUS_BANK0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_TCM_PWR_CNTRL + */ +#define PMU_LOCAL_TCM_PWR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000D0U) ) + +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB1_SHIFT 24 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB1_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB1_MASK ((u32)0X01000000U) + +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA1_SHIFT 16 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA1_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA1_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB0_SHIFT 8 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB0_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMB0_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA0_SHIFT 0 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA0_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_CNTRL_TCMA0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_TCM_RET_CNTRL + */ +#define PMU_LOCAL_TCM_RET_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000D4U) ) + +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB1_SHIFT 3 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB1_WIDTH 1 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB1_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA1_SHIFT 2 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA1_WIDTH 1 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA1_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB0_SHIFT 1 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB0_WIDTH 1 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMB0_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA0_SHIFT 0 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA0_WIDTH 1 +#define PMU_LOCAL_TCM_RET_CNTRL_TCMA0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_TCM_CE_CNTRL + */ +#define PMU_LOCAL_TCM_CE_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000D8U) ) + +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB1_SHIFT 3 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB1_WIDTH 1 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB1_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA1_SHIFT 2 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA1_WIDTH 1 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA1_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB0_SHIFT 1 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB0_WIDTH 1 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMB0_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA0_SHIFT 0 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA0_WIDTH 1 +#define PMU_LOCAL_TCM_CE_CNTRL_TCMA0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_TCM_PWR_STATUS + */ +#define PMU_LOCAL_TCM_PWR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000DCU) ) + +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB1_SHIFT 24 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB1_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB1_MASK ((u32)0X01000000U) + +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA1_SHIFT 16 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA1_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA1_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB0_SHIFT 8 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB0_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMB0_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA0_SHIFT 0 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA0_WIDTH 1 +#define PMU_LOCAL_TCM_PWR_STATUS_TCMA0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_DOMAIN_ISO_CNTRL + */ +#define PMU_LOCAL_DOMAIN_ISO_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X000000F0U) ) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_SHIFT 31 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_LOCKED_MASK ((u32)0X80000000U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_SHIFT 5 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_MASK ((u32)0X00000020U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_SHIFT 4 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_PCAP_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_SHIFT 3 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_PL_NON_PCAP_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_SHIFT 2 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_SHIFT 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_SHIFT 0 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_WIDTH 1 +#define PMU_LOCAL_DOMAIN_ISO_CNTRL_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_LOC_PWR_STATE + */ +#define PMU_LOCAL_LOC_PWR_STATE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000100U) ) + +#define PMU_LOCAL_LOC_PWR_STATE_USB1_SHIFT 21 +#define PMU_LOCAL_LOC_PWR_STATE_USB1_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_USB1_MASK ((u32)0X00200000U) + +#define PMU_LOCAL_LOC_PWR_STATE_USB0_SHIFT 20 +#define PMU_LOCAL_LOC_PWR_STATE_USB0_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_USB0_MASK ((u32)0X00100000U) + +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK3_SHIFT 19 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK3_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK2_SHIFT 18 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK2_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK1_SHIFT 17 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK1_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK0_SHIFT 16 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK0_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_LOC_PWR_STATE_TCM1B_SHIFT 15 +#define PMU_LOCAL_LOC_PWR_STATE_TCM1B_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_LOCAL_LOC_PWR_STATE_TCM1A_SHIFT 14 +#define PMU_LOCAL_LOC_PWR_STATE_TCM1A_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_LOCAL_LOC_PWR_STATE_TCM0B_SHIFT 13 +#define PMU_LOCAL_LOC_PWR_STATE_TCM0B_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_LOCAL_LOC_PWR_STATE_TCM0A_SHIFT 12 +#define PMU_LOCAL_LOC_PWR_STATE_TCM0A_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_LOCAL_LOC_PWR_STATE_R5_1_SHIFT 11 +#define PMU_LOCAL_LOC_PWR_STATE_R5_1_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_R5_1_MASK ((u32)0X00000800U) + +#define PMU_LOCAL_LOC_PWR_STATE_R5_0_SHIFT 10 +#define PMU_LOCAL_LOC_PWR_STATE_R5_0_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_R5_0_MASK ((u32)0X00000400U) + +#define PMU_LOCAL_LOC_PWR_STATE_L2_SHIFT 7 +#define PMU_LOCAL_LOC_PWR_STATE_L2_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_L2_MASK ((u32)0X00000080U) + +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP1_SHIFT 5 +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP1_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP1_MASK ((u32)0X00000020U) + +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP0_SHIFT 4 +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP0_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_GPU_PP0_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_LOC_PWR_STATE_ACPU3_SHIFT 3 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU3_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_LOC_PWR_STATE_ACPU2_SHIFT 2 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU2_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_LOC_PWR_STATE_ACPU1_SHIFT 1 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU1_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_LOC_PWR_STATE_ACPU0_SHIFT 0 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU0_WIDTH 1 +#define PMU_LOCAL_LOC_PWR_STATE_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_LOC_AUX_PWR_STATE + */ +#define PMU_LOCAL_LOC_AUX_PWR_STATE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000104U) ) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU3_EMUL_SHIFT 31 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU3_EMUL_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU3_EMUL_MASK ((u32)0X80000000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU2_EMUL_SHIFT 30 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU2_EMUL_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU2_EMUL_MASK ((u32)0X40000000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU1_EMUL_SHIFT 29 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU1_EMUL_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU1_EMUL_MASK ((u32)0X20000000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU0_EMUL_SHIFT 28 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU0_EMUL_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_ACPU0_EMUL_MASK ((u32)0X10000000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_RPU_EMUL_SHIFT 27 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_RPU_EMUL_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_RPU_EMUL_MASK ((u32)0X08000000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK3_SHIFT 19 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK3_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK3_MASK ((u32)0X00080000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK2_SHIFT 18 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK2_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK2_MASK ((u32)0X00040000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK1_SHIFT 17 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK1_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK1_MASK ((u32)0X00020000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK0_SHIFT 16 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK0_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_OCM_BANK0_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1B_SHIFT 15 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1B_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1B_MASK ((u32)0X00008000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1A_SHIFT 14 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1A_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM1A_MASK ((u32)0X00004000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0B_SHIFT 13 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0B_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0B_MASK ((u32)0X00002000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0A_SHIFT 12 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0A_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_TCM0A_MASK ((u32)0X00001000U) + +#define PMU_LOCAL_LOC_AUX_PWR_STATE_L2_SHIFT 7 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_L2_WIDTH 1 +#define PMU_LOCAL_LOC_AUX_PWR_STATE_L2_MASK ((u32)0X00000080U) + +/** + * Register: PMU_LOCAL_LOCAL_RESET + */ +#define PMU_LOCAL_LOCAL_RESET ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000200U) ) + +#define PMU_LOCAL_LOCAL_RESET_CSU_RST_SHIFT 0 +#define PMU_LOCAL_LOCAL_RESET_CSU_RST_WIDTH 1 +#define PMU_LOCAL_LOCAL_RESET_CSU_RST_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_LOCAL_CNTRL + */ +#define PMU_LOCAL_LOCAL_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000204U) ) + +#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_SHIFT 1 +#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_WIDTH 1 +#define PMU_LOCAL_LOCAL_CNTRL_ROM_VALID_OVRD_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_SHIFT 0 +#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_WIDTH 1 +#define PMU_LOCAL_LOCAL_CNTRL_BUS_CLK_DIS_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_GPO1_READ + */ +#define PMU_LOCAL_GPO1_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000214U) ) + +#define PMU_LOCAL_GPO1_READ_MIO_GPO_SHIFT 0 +#define PMU_LOCAL_GPO1_READ_MIO_GPO_WIDTH 6 +#define PMU_LOCAL_GPO1_READ_MIO_GPO_MASK ((u32)0X0000003FU) + +/** + * Register: PMU_LOCAL_GPO2_READ + */ +#define PMU_LOCAL_GPO2_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000218U) ) + +#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_SHIFT 9 +#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_WIDTH 1 +#define PMU_LOCAL_GPO2_READ_DAP_RPU_WAKE_ACK_MASK ((u32)0X00000200U) + +#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_SHIFT 8 +#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_WIDTH 1 +#define PMU_LOCAL_GPO2_READ_DAP_FP_WAKE_ACK_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_GPO2_READ_PS_STATUS_SHIFT 7 +#define PMU_LOCAL_GPO2_READ_PS_STATUS_WIDTH 1 +#define PMU_LOCAL_GPO2_READ_PS_STATUS_MASK ((u32)0X00000080U) + +#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_SHIFT 6 +#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPO2_READ_FP_LP_PWRDWN_REQ_MASK ((u32)0X00000040U) + +/** + * Register: PMU_LOCAL_GPO3_READ + */ +#define PMU_LOCAL_GPO3_READ ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000021CU) ) + +#define PMU_LOCAL_GPO3_READ_PL_GPO_SHIFT 0 +#define PMU_LOCAL_GPO3_READ_PL_GPO_WIDTH 32 +#define PMU_LOCAL_GPO3_READ_PL_GPO_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_GPI1_ENABLE + */ +#define PMU_LOCAL_GPI1_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000224U) ) + +#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_SHIFT 31 +#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_APB_AIB_ERROR_MASK ((u32)0X80000000U) + +#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_SHIFT 30 +#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_AXI_AIB_ERROR_MASK ((u32)0X40000000U) + +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_SHIFT 29 +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG2_INT_MASK ((u32)0X20000000U) + +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_SHIFT 28 +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ERROR_REG1_INT_MASK ((u32)0X10000000U) + +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_SHIFT 23 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU3_PWRUP_REQ_MASK ((u32)0X00800000U) + +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_SHIFT 22 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU2_PWRUP_REQ_MASK ((u32)0X00400000U) + +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_SHIFT 21 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU1_PWRUP_REQ_MASK ((u32)0X00200000U) + +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_SHIFT 20 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DBG_ACPU0_PWRUP_REQ_MASK ((u32)0X00100000U) + +#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_SHIFT 16 +#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_FPD_WAKE_GIC_PROX_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_SHIFT 10 +#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_WIDTH 6 +#define PMU_LOCAL_GPI1_ENABLE_MIO_WAKE_MASK ((u32)0X0000FC00U) + +#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_SHIFT 9 +#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DAP_RPU_WAKE_MASK ((u32)0X00000200U) + +#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_SHIFT 8 +#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_DAP_FP_WAKE_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_SHIFT 7 +#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_USB1_WAKE_MASK ((u32)0X00000080U) + +#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_SHIFT 6 +#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_USB0_WAKE_MASK ((u32)0X00000040U) + +#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_SHIFT 5 +#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_R5_1_WAKE_MASK ((u32)0X00000020U) + +#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_SHIFT 4 +#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_R5_0_WAKE_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_SHIFT 3 +#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ACPU3_WAKE_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_SHIFT 2 +#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ACPU2_WAKE_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_SHIFT 1 +#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ACPU1_WAKE_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_SHIFT 0 +#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_WIDTH 1 +#define PMU_LOCAL_GPI1_ENABLE_ACPU0_WAKE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_GPI2_ENABLE + */ +#define PMU_LOCAL_GPI2_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000228U) ) + +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_SHIFT 31 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINTFP_ALARM_MASK ((u32)0X80000000U) + +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_SHIFT 30 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSINT_ALARM_MASK ((u32)0X40000000U) + +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_SHIFT 29 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_VCC_PSAUX_ALARM_MASK ((u32)0X20000000U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_SHIFT 23 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU3_RST_REQ_MASK ((u32)0X00800000U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_SHIFT 22 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU2_RST_REQ_MASK ((u32)0X00400000U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_SHIFT 21 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU1_RST_REQ_MASK ((u32)0X00200000U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_SHIFT 20 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_ACPU0_RST_REQ_MASK ((u32)0X00100000U) + +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_SHIFT 19 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU3_RST_REQ_MASK ((u32)0X00080000U) + +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_SHIFT 18 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU2_RST_REQ_MASK ((u32)0X00040000U) + +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_SHIFT 17 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU1_RST_REQ_MASK ((u32)0X00020000U) + +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_SHIFT 16 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_CP_ACPU0_RST_REQ_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_SHIFT 9 +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU1_RST_REQ_MASK ((u32)0X00000200U) + +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_SHIFT 8 +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_DBG_RPU0_RST_REQ_MASK ((u32)0X00000100U) + +#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_SHIFT 6 +#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_FP_LP_PWRDWN_ACK_MASK ((u32)0X00000040U) + +#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_SHIFT 5 +#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_R5_1_PWRDWN_REQ_MASK ((u32)0X00000020U) + +#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_SHIFT 4 +#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_R5_0_PWRDWN_REQ_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_SHIFT 3 +#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_ACPU3_PWRDWN_REQ_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_SHIFT 2 +#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_ACPU2_PWRDWN_REQ_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_SHIFT 1 +#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_ACPU1_PWRDWN_REQ_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_SHIFT 0 +#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_WIDTH 1 +#define PMU_LOCAL_GPI2_ENABLE_ACPU0_PWRDWN_REQ_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_GPI3_ENABLE + */ +#define PMU_LOCAL_GPI3_ENABLE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000022CU) ) + +#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_SHIFT 0 +#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_WIDTH 32 +#define PMU_LOCAL_GPI3_ENABLE_PL_GPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_LOCAL_GEN_STORAGE0 + */ +#define PMU_LOCAL_LOCAL_GEN_STORAGE0 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000300U) ) + +#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_SHIFT 0 +#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_WIDTH 32 +#define PMU_LOCAL_LOCAL_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_LOCAL_GEN_STORAGE1 + */ +#define PMU_LOCAL_LOCAL_GEN_STORAGE1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000304U) ) + +#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_SHIFT 0 +#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_WIDTH 32 +#define PMU_LOCAL_LOCAL_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_LOCAL_GEN_STORAGE2 + */ +#define PMU_LOCAL_LOCAL_GEN_STORAGE2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000308U) ) + +#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_SHIFT 0 +#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_WIDTH 32 +#define PMU_LOCAL_LOCAL_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_LOCAL_GEN_STORAGE3 + */ +#define PMU_LOCAL_LOCAL_GEN_STORAGE3 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000030CU) ) + +#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_SHIFT 0 +#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_WIDTH 32 +#define PMU_LOCAL_LOCAL_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE0 + */ +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000310U) ) + +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_SHIFT 0 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_WIDTH 32 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE0_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE1 + */ +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000314U) ) + +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_SHIFT 0 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_WIDTH 32 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE2 + */ +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000318U) ) + +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_SHIFT 0 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_WIDTH 32 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE2_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_PERS_LOC_GEN_STORAGE3 + */ +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000031CU) ) + +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_SHIFT 0 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_WIDTH 32 +#define PMU_LOCAL_PERS_LOC_GEN_STORAGE3_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_ADDR_ERROR_STATUS + */ +#define PMU_LOCAL_ADDR_ERROR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000320U) ) + +#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_SHIFT 0 +#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_WIDTH 1 +#define PMU_LOCAL_ADDR_ERROR_STATUS_STATUS_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_ADDR_ERROR_INT_MASK + */ +#define PMU_LOCAL_ADDR_ERROR_INT_MASK ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000324U) ) + +#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_SHIFT 0 +#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_WIDTH 1 +#define PMU_LOCAL_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_ADDR_ERROR_INT_EN + */ +#define PMU_LOCAL_ADDR_ERROR_INT_EN ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000328U) ) + +#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_SHIFT 0 +#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_WIDTH 1 +#define PMU_LOCAL_ADDR_ERROR_INT_EN_EN_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_ADDR_ERROR_INT_DIS + */ +#define PMU_LOCAL_ADDR_ERROR_INT_DIS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000032CU) ) + +#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_SHIFT 0 +#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_WIDTH 1 +#define PMU_LOCAL_ADDR_ERROR_INT_DIS_BIT0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBISR_CNTRL + */ +#define PMU_LOCAL_MBISR_CNTRL ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000330U) ) + +#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_SHIFT 5 +#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_WIDTH 1 +#define PMU_LOCAL_MBISR_CNTRL_FPD_GROUP_MASK ((u32)0X00000020U) + +#define PMU_LOCAL_MBISR_CNTRL_ENABLE_SHIFT 0 +#define PMU_LOCAL_MBISR_CNTRL_ENABLE_WIDTH 1 +#define PMU_LOCAL_MBISR_CNTRL_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBISR_STATUS + */ +#define PMU_LOCAL_MBISR_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000334U) ) + +#define PMU_LOCAL_MBISR_STATUS_PASS_SHIFT 4 +#define PMU_LOCAL_MBISR_STATUS_PASS_WIDTH 1 +#define PMU_LOCAL_MBISR_STATUS_PASS_MASK ((u32)0X00000010U) + +#define PMU_LOCAL_MBISR_STATUS_DONE_SHIFT 0 +#define PMU_LOCAL_MBISR_STATUS_DONE_WIDTH 1 +#define PMU_LOCAL_MBISR_STATUS_DONE_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_PMU_PB_ERR + */ +#define PMU_LOCAL_PMU_PB_ERR ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000338U) ) + +#define PMU_LOCAL_PMU_PB_ERR_PBERR_FLAG_SHIFT 31 +#define PMU_LOCAL_PMU_PB_ERR_PBERR_FLAG_WIDTH 1 +#define PMU_LOCAL_PMU_PB_ERR_PBERR_FLAG_MASK ((u32)0X80000000U) + +#define PMU_LOCAL_PMU_PB_ERR_PBERR_DATA_SHIFT 0 +#define PMU_LOCAL_PMU_PB_ERR_PBERR_DATA_WIDTH 31 +#define PMU_LOCAL_PMU_PB_ERR_PBERR_DATA_MASK ((u32)0X7FFFFFFFU) + +/** + * Register: PMU_LOCAL_PMU_SERV_ERR + */ +#define PMU_LOCAL_PMU_SERV_ERR ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000033CU) ) + +#define PMU_LOCAL_PMU_SERV_ERR_FWERR_SHIFT 28 +#define PMU_LOCAL_PMU_SERV_ERR_FWERR_WIDTH 4 +#define PMU_LOCAL_PMU_SERV_ERR_FWERR_MASK ((u32)0XF0000000U) + +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_SHIFT 23 +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_WIDTH 1 +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_FLAG_MASK ((u32)0X00800000U) + +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_SHIFT 0 +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_WIDTH 20 +#define PMU_LOCAL_PMU_SERV_ERR_SERVERR_DATA_MASK ((u32)0X000FFFFFU) + +/** + * Register: PMU_LOCAL_PWR_ACK_ERR_LPD + */ +#define PMU_LOCAL_PWR_ACK_ERR_LPD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000340U) ) + +#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_SHIFT 0 +#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_WIDTH 32 +#define PMU_LOCAL_PWR_ACK_ERR_LPD_ACK_ERROR_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_PWR_ACK_ERR_FPD + */ +#define PMU_LOCAL_PWR_ACK_ERR_FPD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000344U) ) + +#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_SHIFT 0 +#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_WIDTH 32 +#define PMU_LOCAL_PWR_ACK_ERR_FPD_ACK_ERROR_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_SERV_LOGCLR_ERR + */ +#define PMU_LOCAL_SERV_LOGCLR_ERR ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000348U) ) + +#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_SHIFT 0 +#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_WIDTH 32 +#define PMU_LOCAL_SERV_LOGCLR_ERR_LOGCLR_ERROR_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_LOGCLR_TRIG + */ +#define PMU_LOCAL_LOGCLR_TRIG ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000350U) ) + +#define PMU_LOCAL_LOGCLR_TRIG_FP_SHIFT 17 +#define PMU_LOCAL_LOGCLR_TRIG_FP_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_FP_MASK ((u32)0X00020000U) + +#define PMU_LOCAL_LOGCLR_TRIG_LP_SHIFT 16 +#define PMU_LOCAL_LOGCLR_TRIG_LP_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_LP_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_LOGCLR_TRIG_USB1_SHIFT 13 +#define PMU_LOCAL_LOGCLR_TRIG_USB1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_USB1_MASK ((u32)0X00002000U) + +#define PMU_LOCAL_LOGCLR_TRIG_USB0_SHIFT 12 +#define PMU_LOCAL_LOGCLR_TRIG_USB0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_USB0_MASK ((u32)0X00001000U) + +#define PMU_LOCAL_LOGCLR_TRIG_RPU_SHIFT 10 +#define PMU_LOCAL_LOGCLR_TRIG_RPU_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_RPU_MASK ((u32)0X00000400U) + +#define PMU_LOCAL_LOGCLR_TRIG_PP1_SHIFT 7 +#define PMU_LOCAL_LOGCLR_TRIG_PP1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_PP1_MASK ((u32)0X00000080U) + +#define PMU_LOCAL_LOGCLR_TRIG_PP0_SHIFT 6 +#define PMU_LOCAL_LOGCLR_TRIG_PP0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_PP0_MASK ((u32)0X00000040U) + +#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_SHIFT 3 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_SHIFT 2 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_SHIFT 1 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_SHIFT 0 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_TRIG_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_LOGCLR_ACK + */ +#define PMU_LOCAL_LOGCLR_ACK ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000354U) ) + +#define PMU_LOCAL_LOGCLR_ACK_FP_SHIFT 17 +#define PMU_LOCAL_LOGCLR_ACK_FP_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_FP_MASK ((u32)0X00020000U) + +#define PMU_LOCAL_LOGCLR_ACK_LP_SHIFT 16 +#define PMU_LOCAL_LOGCLR_ACK_LP_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_LP_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_LOGCLR_ACK_USB1_SHIFT 13 +#define PMU_LOCAL_LOGCLR_ACK_USB1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_USB1_MASK ((u32)0X00002000U) + +#define PMU_LOCAL_LOGCLR_ACK_USB0_SHIFT 12 +#define PMU_LOCAL_LOGCLR_ACK_USB0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_USB0_MASK ((u32)0X00001000U) + +#define PMU_LOCAL_LOGCLR_ACK_RPU_SHIFT 10 +#define PMU_LOCAL_LOGCLR_ACK_RPU_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_RPU_MASK ((u32)0X00000400U) + +#define PMU_LOCAL_LOGCLR_ACK_PP1_SHIFT 7 +#define PMU_LOCAL_LOGCLR_ACK_PP1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_PP1_MASK ((u32)0X00000080U) + +#define PMU_LOCAL_LOGCLR_ACK_PP0_SHIFT 6 +#define PMU_LOCAL_LOGCLR_ACK_PP0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_PP0_MASK ((u32)0X00000040U) + +#define PMU_LOCAL_LOGCLR_ACK_ACPU3_SHIFT 3 +#define PMU_LOCAL_LOGCLR_ACK_ACPU3_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_ACPU3_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_LOGCLR_ACK_ACPU2_SHIFT 2 +#define PMU_LOCAL_LOGCLR_ACK_ACPU2_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_ACPU2_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_LOGCLR_ACK_ACPU1_SHIFT 1 +#define PMU_LOCAL_LOGCLR_ACK_ACPU1_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_ACPU1_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_LOGCLR_ACK_ACPU0_SHIFT 0 +#define PMU_LOCAL_LOGCLR_ACK_ACPU0_WIDTH 1 +#define PMU_LOCAL_LOGCLR_ACK_ACPU0_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_APU_WFI_STATUS + */ +#define PMU_LOCAL_APU_WFI_STATUS ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000360U) ) + +#define PMU_LOCAL_APU_WFI_STATUS_L2_WFI_SHIFT 16 +#define PMU_LOCAL_APU_WFI_STATUS_L2_WFI_WIDTH 1 +#define PMU_LOCAL_APU_WFI_STATUS_L2_WFI_MASK ((u32)0X00010000U) + +#define PMU_LOCAL_APU_WFI_STATUS_ACPU3_WFI_SHIFT 3 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU3_WFI_WIDTH 1 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU3_WFI_MASK ((u32)0X00000008U) + +#define PMU_LOCAL_APU_WFI_STATUS_ACPU2_WFI_SHIFT 2 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU2_WFI_WIDTH 1 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU2_WFI_MASK ((u32)0X00000004U) + +#define PMU_LOCAL_APU_WFI_STATUS_ACPU1_WFI_SHIFT 1 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU1_WFI_WIDTH 1 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU1_WFI_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_APU_WFI_STATUS_ACPU0_WFI_SHIFT 0 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU0_WFI_WIDTH 1 +#define PMU_LOCAL_APU_WFI_STATUS_ACPU0_WFI_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBIST_RST + */ +#define PMU_LOCAL_MBIST_RST ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000036CU) ) + +#define PMU_LOCAL_MBIST_RST_CSU_SHIFT 1 +#define PMU_LOCAL_MBIST_RST_CSU_WIDTH 1 +#define PMU_LOCAL_MBIST_RST_CSU_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_MBIST_RST_PMU_SHIFT 0 +#define PMU_LOCAL_MBIST_RST_PMU_WIDTH 1 +#define PMU_LOCAL_MBIST_RST_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBIST_PG_EN + */ +#define PMU_LOCAL_MBIST_PG_EN ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000370U) ) + +#define PMU_LOCAL_MBIST_PG_EN_CSU_SHIFT 1 +#define PMU_LOCAL_MBIST_PG_EN_CSU_WIDTH 1 +#define PMU_LOCAL_MBIST_PG_EN_CSU_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_MBIST_PG_EN_PMU_SHIFT 0 +#define PMU_LOCAL_MBIST_PG_EN_PMU_WIDTH 1 +#define PMU_LOCAL_MBIST_PG_EN_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBIST_SETUP + */ +#define PMU_LOCAL_MBIST_SETUP ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000374U) ) + +#define PMU_LOCAL_MBIST_SETUP_CSU_SHIFT 1 +#define PMU_LOCAL_MBIST_SETUP_CSU_WIDTH 1 +#define PMU_LOCAL_MBIST_SETUP_CSU_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_MBIST_SETUP_PMU_SHIFT 0 +#define PMU_LOCAL_MBIST_SETUP_PMU_WIDTH 1 +#define PMU_LOCAL_MBIST_SETUP_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBIST_DONE + */ +#define PMU_LOCAL_MBIST_DONE ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000378U) ) + +#define PMU_LOCAL_MBIST_DONE_CSU_SHIFT 1 +#define PMU_LOCAL_MBIST_DONE_CSU_WIDTH 1 +#define PMU_LOCAL_MBIST_DONE_CSU_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_MBIST_DONE_PMU_SHIFT 0 +#define PMU_LOCAL_MBIST_DONE_PMU_WIDTH 1 +#define PMU_LOCAL_MBIST_DONE_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_MBIST_GOOD + */ +#define PMU_LOCAL_MBIST_GOOD ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X0000037CU) ) + +#define PMU_LOCAL_MBIST_GOOD_CSU_SHIFT 1 +#define PMU_LOCAL_MBIST_GOOD_CSU_WIDTH 1 +#define PMU_LOCAL_MBIST_GOOD_CSU_MASK ((u32)0X00000002U) + +#define PMU_LOCAL_MBIST_GOOD_PMU_SHIFT 0 +#define PMU_LOCAL_MBIST_GOOD_PMU_WIDTH 1 +#define PMU_LOCAL_MBIST_GOOD_PMU_MASK ((u32)0X00000001U) + +/** + * Register: PMU_LOCAL_ECO_1 + */ +#define PMU_LOCAL_ECO_1 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000400U) ) + +#define PMU_LOCAL_ECO_1_REG_SHIFT 0 +#define PMU_LOCAL_ECO_1_REG_WIDTH 32 +#define PMU_LOCAL_ECO_1_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: PMU_LOCAL_ECO_2 + */ +#define PMU_LOCAL_ECO_2 ( ( PMU_LOCAL_BASEADDR ) + ((u32)0X00000404U) ) + +#define PMU_LOCAL_ECO_2_REG_SHIFT 0 +#define PMU_LOCAL_ECO_2_REG_WIDTH 32 +#define PMU_LOCAL_ECO_2_REG_MASK ((u32)0XFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + + +#endif /* _PMU_LOCAL_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/rpu.h b/lib/sw_apps/zynqmp_pmufw/src/rpu.h new file mode 100644 index 00000000..48c788e4 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/rpu.h @@ -0,0 +1,1526 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef _RPU_H_ +#define _RPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * RPU Base Address + */ +#define RPU_BASEADDR ((u32)0XFF9A0000U) + +/** + * Register: RPU_RPU_GLBL_CNTL + */ +#define RPU_RPU_GLBL_CNTL ( ( RPU_BASEADDR ) + ((u32)0X00000000U) ) + +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_SHIFT 10 +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_GIC_AXPROT_MASK ((u32)0X00000400U) + +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_SHIFT 8 +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_CLK_CNTL_MASK ((u32)0X00000100U) + +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_SHIFT 7 +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_WAIT_MASK ((u32)0X00000080U) + +#define RPU_RPU_GLBL_CNTL_TCM_COMB_SHIFT 6 +#define RPU_RPU_GLBL_CNTL_TCM_COMB_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TCM_COMB_MASK ((u32)0X00000040U) + +#define RPU_RPU_GLBL_CNTL_TEINIT_SHIFT 5 +#define RPU_RPU_GLBL_CNTL_TEINIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_TEINIT_MASK ((u32)0X00000020U) + +#define RPU_RPU_GLBL_CNTL_SLCLAMP_SHIFT 4 +#define RPU_RPU_GLBL_CNTL_SLCLAMP_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_SLCLAMP_MASK ((u32)0X00000010U) + +#define RPU_RPU_GLBL_CNTL_SLSPLIT_SHIFT 3 +#define RPU_RPU_GLBL_CNTL_SLSPLIT_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_SLSPLIT_MASK ((u32)0X00000008U) + +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_SHIFT 2 +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_DBGNOCLKSTOP_MASK ((u32)0X00000004U) + +#define RPU_RPU_GLBL_CNTL_CFGIE_SHIFT 1 +#define RPU_RPU_GLBL_CNTL_CFGIE_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_CFGIE_MASK ((u32)0X00000002U) + +#define RPU_RPU_GLBL_CNTL_CFGEE_SHIFT 0 +#define RPU_RPU_GLBL_CNTL_CFGEE_WIDTH 1 +#define RPU_RPU_GLBL_CNTL_CFGEE_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_GLBL_STATUS + */ +#define RPU_RPU_GLBL_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000004U) ) + +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_SHIFT 0 +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_WIDTH 1 +#define RPU_RPU_GLBL_STATUS_DBGNOPWRDWN_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_ERR_CNTL + */ +#define RPU_RPU_ERR_CNTL ( ( RPU_BASEADDR ) + ((u32)0X00000008U) ) + +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_SHIFT 0 +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_WIDTH 1 +#define RPU_RPU_ERR_CNTL_APB_ERR_RES_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_RAM + */ +#define RPU_RPU_RAM ( ( RPU_BASEADDR ) + ((u32)0X0000000CU) ) + +#define RPU_RPU_RAM_RAMCONTROL1_SHIFT 8 +#define RPU_RPU_RAM_RAMCONTROL1_WIDTH 8 +#define RPU_RPU_RAM_RAMCONTROL1_MASK ((u32)0X0000FF00U) + +#define RPU_RPU_RAM_RAMCONTROL0_SHIFT 0 +#define RPU_RPU_RAM_RAMCONTROL0_WIDTH 8 +#define RPU_RPU_RAM_RAMCONTROL0_MASK ((u32)0X000000FFU) + +/** + * Register: RPU_RPU_CACHE_DATA + */ +#define RPU_RPU_CACHE_DATA ( ( RPU_BASEADDR ) + ((u32)0X00000010U) ) + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_SHIFT 29 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAS_MASK ((u32)0X20000000U) + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_SHIFT 27 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMAW_MASK ((u32)0X18000000U) + +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_SHIFT 24 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DDIRTY_EMA_MASK ((u32)0X07000000U) + +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_SHIFT 23 +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DTAG_EMAS_MASK ((u32)0X00800000U) + +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_SHIFT 21 +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DTAG_EMAW_MASK ((u32)0X00600000U) + +#define RPU_RPU_CACHE_DATA_DTAG_EMA_SHIFT 18 +#define RPU_RPU_CACHE_DATA_DTAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DTAG_EMA_MASK ((u32)0X001C0000U) + +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_SHIFT 17 +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_DDATA_EMAS_MASK ((u32)0X00020000U) + +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_SHIFT 15 +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_DDATA_EMAW_MASK ((u32)0X00018000U) + +#define RPU_RPU_CACHE_DATA_DDATA_EMA_SHIFT 12 +#define RPU_RPU_CACHE_DATA_DDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_DDATA_EMA_MASK ((u32)0X00007000U) + +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_SHIFT 11 +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_ITAG_EMAS_MASK ((u32)0X00000800U) + +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_SHIFT 9 +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_ITAG_EMAW_MASK ((u32)0X00000600U) + +#define RPU_RPU_CACHE_DATA_ITAG_EMA_SHIFT 6 +#define RPU_RPU_CACHE_DATA_ITAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_ITAG_EMA_MASK ((u32)0X000001C0U) + +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_SHIFT 5 +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_DATA_IDATA_EMAS_MASK ((u32)0X00000020U) + +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_SHIFT 3 +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_DATA_IDATA_EMAW_MASK ((u32)0X00000018U) + +#define RPU_RPU_CACHE_DATA_IDATA_EMA_SHIFT 0 +#define RPU_RPU_CACHE_DATA_IDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_DATA_IDATA_EMA_MASK ((u32)0X00000007U) + +/** + * Register: RPU_RPU_CACHE_SYN + */ +#define RPU_RPU_CACHE_SYN ( ( RPU_BASEADDR ) + ((u32)0X00000014U) ) + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_SHIFT 29 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAS_MASK ((u32)0X20000000U) + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_SHIFT 27 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMAW_MASK ((u32)0X18000000U) + +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_SHIFT 24 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DDIRTY_EMA_MASK ((u32)0X07000000U) + +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_SHIFT 23 +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DTAG_EMAS_MASK ((u32)0X00800000U) + +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_SHIFT 21 +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DTAG_EMAW_MASK ((u32)0X00600000U) + +#define RPU_RPU_CACHE_SYN_DTAG_EMA_SHIFT 18 +#define RPU_RPU_CACHE_SYN_DTAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DTAG_EMA_MASK ((u32)0X001C0000U) + +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_SHIFT 17 +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_DDATA_EMAS_MASK ((u32)0X00020000U) + +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_SHIFT 15 +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_DDATA_EMAW_MASK ((u32)0X00018000U) + +#define RPU_RPU_CACHE_SYN_DDATA_EMA_SHIFT 12 +#define RPU_RPU_CACHE_SYN_DDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_DDATA_EMA_MASK ((u32)0X00007000U) + +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_SHIFT 11 +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_ITAG_EMAS_MASK ((u32)0X00000800U) + +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_SHIFT 9 +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_ITAG_EMAW_MASK ((u32)0X00000600U) + +#define RPU_RPU_CACHE_SYN_ITAG_EMA_SHIFT 6 +#define RPU_RPU_CACHE_SYN_ITAG_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_ITAG_EMA_MASK ((u32)0X000001C0U) + +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_SHIFT 5 +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_WIDTH 1 +#define RPU_RPU_CACHE_SYN_IDATA_EMAS_MASK ((u32)0X00000020U) + +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_SHIFT 3 +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_WIDTH 2 +#define RPU_RPU_CACHE_SYN_IDATA_EMAW_MASK ((u32)0X00000018U) + +#define RPU_RPU_CACHE_SYN_IDATA_EMA_SHIFT 0 +#define RPU_RPU_CACHE_SYN_IDATA_EMA_WIDTH 3 +#define RPU_RPU_CACHE_SYN_IDATA_EMA_MASK ((u32)0X00000007U) + +/** + * Register: RPU_RPU_TCM_DATA + */ +#define RPU_RPU_TCM_DATA ( ( RPU_BASEADDR ) + ((u32)0X00000018U) ) + +#define RPU_RPU_TCM_DATA_B_EMAS_SHIFT 17 +#define RPU_RPU_TCM_DATA_B_EMAS_WIDTH 1 +#define RPU_RPU_TCM_DATA_B_EMAS_MASK ((u32)0X00020000U) + +#define RPU_RPU_TCM_DATA_B_EMAW_SHIFT 15 +#define RPU_RPU_TCM_DATA_B_EMAW_WIDTH 2 +#define RPU_RPU_TCM_DATA_B_EMAW_MASK ((u32)0X00018000U) + +#define RPU_RPU_TCM_DATA_B_EMA_SHIFT 12 +#define RPU_RPU_TCM_DATA_B_EMA_WIDTH 3 +#define RPU_RPU_TCM_DATA_B_EMA_MASK ((u32)0X00007000U) + +#define RPU_RPU_TCM_DATA_A_EMAS_SHIFT 5 +#define RPU_RPU_TCM_DATA_A_EMAS_WIDTH 1 +#define RPU_RPU_TCM_DATA_A_EMAS_MASK ((u32)0X00000020U) + +#define RPU_RPU_TCM_DATA_A_EMAW_SHIFT 3 +#define RPU_RPU_TCM_DATA_A_EMAW_WIDTH 2 +#define RPU_RPU_TCM_DATA_A_EMAW_MASK ((u32)0X00000018U) + +#define RPU_RPU_TCM_DATA_A_EMA_SHIFT 0 +#define RPU_RPU_TCM_DATA_A_EMA_WIDTH 3 +#define RPU_RPU_TCM_DATA_A_EMA_MASK ((u32)0X00000007U) + +/** + * Register: RPU_RPU_TCM_SYN + */ +#define RPU_RPU_TCM_SYN ( ( RPU_BASEADDR ) + ((u32)0X0000001CU) ) + +#define RPU_RPU_TCM_SYN_B_EMAS_SHIFT 23 +#define RPU_RPU_TCM_SYN_B_EMAS_WIDTH 1 +#define RPU_RPU_TCM_SYN_B_EMAS_MASK ((u32)0X00800000U) + +#define RPU_RPU_TCM_SYN_B_EMAW_SHIFT 21 +#define RPU_RPU_TCM_SYN_B_EMAW_WIDTH 2 +#define RPU_RPU_TCM_SYN_B_EMAW_MASK ((u32)0X00600000U) + +#define RPU_RPU_TCM_SYN_B_EMA_SHIFT 18 +#define RPU_RPU_TCM_SYN_B_EMA_WIDTH 3 +#define RPU_RPU_TCM_SYN_B_EMA_MASK ((u32)0X001C0000U) + +#define RPU_RPU_TCM_SYN_A_EMAS_SHIFT 11 +#define RPU_RPU_TCM_SYN_A_EMAS_WIDTH 1 +#define RPU_RPU_TCM_SYN_A_EMAS_MASK ((u32)0X00000800U) + +#define RPU_RPU_TCM_SYN_A_EMAW_SHIFT 9 +#define RPU_RPU_TCM_SYN_A_EMAW_WIDTH 2 +#define RPU_RPU_TCM_SYN_A_EMAW_MASK ((u32)0X00000600U) + +#define RPU_RPU_TCM_SYN_A_EMA_SHIFT 6 +#define RPU_RPU_TCM_SYN_A_EMA_WIDTH 3 +#define RPU_RPU_TCM_SYN_A_EMA_MASK ((u32)0X000001C0U) + +/** + * Register: RPU_RPU_ERR_INJ + */ +#define RPU_RPU_ERR_INJ ( ( RPU_BASEADDR ) + ((u32)0X00000020U) ) + +#define RPU_RPU_ERR_INJ_DCCMINP2_SHIFT 8 +#define RPU_RPU_ERR_INJ_DCCMINP2_WIDTH 8 +#define RPU_RPU_ERR_INJ_DCCMINP2_MASK ((u32)0X0000FF00U) + +#define RPU_RPU_ERR_INJ_DCCMINP_SHIFT 0 +#define RPU_RPU_ERR_INJ_DCCMINP_WIDTH 8 +#define RPU_RPU_ERR_INJ_DCCMINP_MASK ((u32)0X000000FFU) + +/** + * Register: RPU_RPU_CCF_MASK + */ +#define RPU_RPU_CCF_MASK ( ( RPU_BASEADDR ) + ((u32)0X00000024U) ) + +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_SHIFT 7 +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_MBIST_MODE_MASK ((u32)0X00000080U) + +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_SHIFT 6 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_LP_MASK ((u32)0X00000040U) + +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_SHIFT 5 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_WIDTH 1 +#define RPU_RPU_CCF_MASK_TEST_SCAN_MODE_MASK ((u32)0X00000020U) + +#define RPU_RPU_CCF_MASK_ISO_SHIFT 4 +#define RPU_RPU_CCF_MASK_ISO_WIDTH 1 +#define RPU_RPU_CCF_MASK_ISO_MASK ((u32)0X00000010U) + +#define RPU_RPU_CCF_MASK_PGE_SHIFT 3 +#define RPU_RPU_CCF_MASK_PGE_WIDTH 1 +#define RPU_RPU_CCF_MASK_PGE_MASK ((u32)0X00000008U) + +#define RPU_RPU_CCF_MASK_R50_DBG_RST_SHIFT 2 +#define RPU_RPU_CCF_MASK_R50_DBG_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_R50_DBG_RST_MASK ((u32)0X00000004U) + +#define RPU_RPU_CCF_MASK_R50_RST_SHIFT 1 +#define RPU_RPU_CCF_MASK_R50_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_R50_RST_MASK ((u32)0X00000002U) + +#define RPU_RPU_CCF_MASK_PGE_RST_SHIFT 0 +#define RPU_RPU_CCF_MASK_PGE_RST_WIDTH 1 +#define RPU_RPU_CCF_MASK_PGE_RST_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_INTR_0 + */ +#define RPU_RPU_INTR_0 ( ( RPU_BASEADDR ) + ((u32)0X00000028U) ) + +#define RPU_RPU_INTR_0_SPI_SHIFT 0 +#define RPU_RPU_INTR_0_SPI_WIDTH 32 +#define RPU_RPU_INTR_0_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_1 + */ +#define RPU_RPU_INTR_1 ( ( RPU_BASEADDR ) + ((u32)0X0000002CU) ) + +#define RPU_RPU_INTR_1_SPI_SHIFT 0 +#define RPU_RPU_INTR_1_SPI_WIDTH 32 +#define RPU_RPU_INTR_1_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_2 + */ +#define RPU_RPU_INTR_2 ( ( RPU_BASEADDR ) + ((u32)0X00000030U) ) + +#define RPU_RPU_INTR_2_SPI_SHIFT 0 +#define RPU_RPU_INTR_2_SPI_WIDTH 32 +#define RPU_RPU_INTR_2_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_3 + */ +#define RPU_RPU_INTR_3 ( ( RPU_BASEADDR ) + ((u32)0X00000034U) ) + +#define RPU_RPU_INTR_3_SPI_SHIFT 0 +#define RPU_RPU_INTR_3_SPI_WIDTH 32 +#define RPU_RPU_INTR_3_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_4 + */ +#define RPU_RPU_INTR_4 ( ( RPU_BASEADDR ) + ((u32)0X00000038U) ) + +#define RPU_RPU_INTR_4_SPI_SHIFT 0 +#define RPU_RPU_INTR_4_SPI_WIDTH 32 +#define RPU_RPU_INTR_4_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_MASK_0 + */ +#define RPU_RPU_INTR_MASK_0 ( ( RPU_BASEADDR ) + ((u32)0X00000040U) ) + +#define RPU_RPU_INTR_MASK_0_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_0_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_0_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_MASK_1 + */ +#define RPU_RPU_INTR_MASK_1 ( ( RPU_BASEADDR ) + ((u32)0X00000044U) ) + +#define RPU_RPU_INTR_MASK_1_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_1_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_1_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_MASK_2 + */ +#define RPU_RPU_INTR_MASK_2 ( ( RPU_BASEADDR ) + ((u32)0X00000048U) ) + +#define RPU_RPU_INTR_MASK_2_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_2_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_2_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_MASK_3 + */ +#define RPU_RPU_INTR_MASK_3 ( ( RPU_BASEADDR ) + ((u32)0X0000004CU) ) + +#define RPU_RPU_INTR_MASK_3_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_3_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_3_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_INTR_MASK_4 + */ +#define RPU_RPU_INTR_MASK_4 ( ( RPU_BASEADDR ) + ((u32)0X00000050U) ) + +#define RPU_RPU_INTR_MASK_4_SPI_SHIFT 0 +#define RPU_RPU_INTR_MASK_4_SPI_WIDTH 32 +#define RPU_RPU_INTR_MASK_4_SPI_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_CCF_VAL + */ +#define RPU_RPU_CCF_VAL ( ( RPU_BASEADDR ) + ((u32)0X00000054U) ) + +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_SHIFT 7 +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_MBIST_MODE_MASK ((u32)0X00000080U) + +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_SHIFT 6 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_LP_MASK ((u32)0X00000040U) + +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_SHIFT 5 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_WIDTH 1 +#define RPU_RPU_CCF_VAL_TEST_SCAN_MODE_MASK ((u32)0X00000020U) + +#define RPU_RPU_CCF_VAL_ISO_SHIFT 4 +#define RPU_RPU_CCF_VAL_ISO_WIDTH 1 +#define RPU_RPU_CCF_VAL_ISO_MASK ((u32)0X00000010U) + +#define RPU_RPU_CCF_VAL_PGE_SHIFT 3 +#define RPU_RPU_CCF_VAL_PGE_WIDTH 1 +#define RPU_RPU_CCF_VAL_PGE_MASK ((u32)0X00000008U) + +#define RPU_RPU_CCF_VAL_R50_DBG_RST_SHIFT 2 +#define RPU_RPU_CCF_VAL_R50_DBG_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_R50_DBG_RST_MASK ((u32)0X00000004U) + +#define RPU_RPU_CCF_VAL_R50_RST_SHIFT 1 +#define RPU_RPU_CCF_VAL_R50_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_R50_RST_MASK ((u32)0X00000002U) + +#define RPU_RPU_CCF_VAL_PGE_RST_SHIFT 0 +#define RPU_RPU_CCF_VAL_PGE_RST_WIDTH 1 +#define RPU_RPU_CCF_VAL_PGE_RST_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_SAFETY_CHK + */ +#define RPU_RPU_SAFETY_CHK ( ( RPU_BASEADDR ) + ((u32)0X000000F0U) ) + +#define RPU_RPU_SAFETY_CHK_VAL_SHIFT 0 +#define RPU_RPU_SAFETY_CHK_VAL_WIDTH 32 +#define RPU_RPU_SAFETY_CHK_VAL_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU + */ +#define RPU_RPU ( ( RPU_BASEADDR ) + ((u32)0X000000F4U) ) + +#define RPU_RPU_ECO_SHIFT 0 +#define RPU_RPU_ECO_WIDTH 32 +#define RPU_RPU_ECO_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RPU_RPU_0_CFG + */ +#define RPU_RPU_0_CFG ( ( RPU_BASEADDR ) + ((u32)0X00000100U) ) + +#define RPU_RPU_0_CFG_CFGNMFI0_SHIFT 3 +#define RPU_RPU_0_CFG_CFGNMFI0_WIDTH 1 +#define RPU_RPU_0_CFG_CFGNMFI0_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_CFG_VINITHI_SHIFT 2 +#define RPU_RPU_0_CFG_VINITHI_WIDTH 1 +#define RPU_RPU_0_CFG_VINITHI_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_CFG_COHERENT_SHIFT 1 +#define RPU_RPU_0_CFG_COHERENT_WIDTH 1 +#define RPU_RPU_0_CFG_COHERENT_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_CFG_NCPUHALT_SHIFT 0 +#define RPU_RPU_0_CFG_NCPUHALT_WIDTH 1 +#define RPU_RPU_0_CFG_NCPUHALT_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_STATUS + */ +#define RPU_RPU_0_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000104U) ) + +#define RPU_RPU_0_STATUS_NVALRESET_SHIFT 5 +#define RPU_RPU_0_STATUS_NVALRESET_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALRESET_MASK ((u32)0X00000020U) + +#define RPU_RPU_0_STATUS_NVALIRQ_SHIFT 4 +#define RPU_RPU_0_STATUS_NVALIRQ_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALIRQ_MASK ((u32)0X00000010U) + +#define RPU_RPU_0_STATUS_NVALFIQ_SHIFT 3 +#define RPU_RPU_0_STATUS_NVALFIQ_WIDTH 1 +#define RPU_RPU_0_STATUS_NVALFIQ_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_SHIFT 2 +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NWFIPIPESTOPPED_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_SHIFT 1 +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NWFEPIPESTOPPED_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_STATUS_NCLKSTOPPED_SHIFT 0 +#define RPU_RPU_0_STATUS_NCLKSTOPPED_WIDTH 1 +#define RPU_RPU_0_STATUS_NCLKSTOPPED_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_PWRDWN + */ +#define RPU_RPU_0_PWRDWN ( ( RPU_BASEADDR ) + ((u32)0X00000108U) ) + +#define RPU_RPU_0_PWRDWN_EN_SHIFT 0 +#define RPU_RPU_0_PWRDWN_EN_WIDTH 1 +#define RPU_RPU_0_PWRDWN_EN_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_ISR + */ +#define RPU_RPU_0_ISR ( ( RPU_BASEADDR ) + ((u32)0X00000114U) ) + +#define RPU_RPU_0_ISR_FPUFC_SHIFT 24 +#define RPU_RPU_0_ISR_FPUFC_WIDTH 1 +#define RPU_RPU_0_ISR_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_0_ISR_FPOFC_SHIFT 23 +#define RPU_RPU_0_ISR_FPOFC_WIDTH 1 +#define RPU_RPU_0_ISR_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_0_ISR_FPIXC_SHIFT 22 +#define RPU_RPU_0_ISR_FPIXC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_0_ISR_FPIOC_SHIFT 21 +#define RPU_RPU_0_ISR_FPIOC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_0_ISR_FPIDC_SHIFT 20 +#define RPU_RPU_0_ISR_FPIDC_WIDTH 1 +#define RPU_RPU_0_ISR_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_0_ISR_FPDZC_SHIFT 19 +#define RPU_RPU_0_ISR_FPDZC_WIDTH 1 +#define RPU_RPU_0_ISR_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_0_ISR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_ISR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_0_ISR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_ISR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_0_ISR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_ISR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_0_ISR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_ISR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_0_ISR_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_ISR_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_ISR_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_0_ISR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_ISR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_0_ISR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_ISR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_0_ISR_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_ISR_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_ISR_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_0_ISR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_ISR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_0_ISR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_ISR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_ISR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_0_ISR_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_ISR_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_ISR_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_ISR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_ISR_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_ISR_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_ISR_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_ISR_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_ISR_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_ISR_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_ISR_APB_ERR_SHIFT 0 +#define RPU_RPU_0_ISR_APB_ERR_WIDTH 1 +#define RPU_RPU_0_ISR_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_IMR + */ +#define RPU_RPU_0_IMR ( ( RPU_BASEADDR ) + ((u32)0X00000118U) ) + +#define RPU_RPU_0_IMR_FPUFC_SHIFT 24 +#define RPU_RPU_0_IMR_FPUFC_WIDTH 1 +#define RPU_RPU_0_IMR_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_0_IMR_FPOFC_SHIFT 23 +#define RPU_RPU_0_IMR_FPOFC_WIDTH 1 +#define RPU_RPU_0_IMR_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_0_IMR_FPIXC_SHIFT 22 +#define RPU_RPU_0_IMR_FPIXC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_0_IMR_FPIOC_SHIFT 21 +#define RPU_RPU_0_IMR_FPIOC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_0_IMR_FPIDC_SHIFT 20 +#define RPU_RPU_0_IMR_FPIDC_WIDTH 1 +#define RPU_RPU_0_IMR_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_0_IMR_FPDZC_SHIFT 19 +#define RPU_RPU_0_IMR_FPDZC_WIDTH 1 +#define RPU_RPU_0_IMR_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_0_IMR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IMR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_0_IMR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IMR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_0_IMR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IMR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_0_IMR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IMR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_0_IMR_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IMR_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IMR_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_0_IMR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IMR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_0_IMR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IMR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_0_IMR_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IMR_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IMR_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_0_IMR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IMR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_0_IMR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IMR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IMR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_0_IMR_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IMR_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IMR_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IMR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_IMR_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IMR_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IMR_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_IMR_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IMR_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IMR_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_IMR_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IMR_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IMR_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_IEN + */ +#define RPU_RPU_0_IEN ( ( RPU_BASEADDR ) + ((u32)0X0000011CU) ) + +#define RPU_RPU_0_IEN_FPUFC_SHIFT 24 +#define RPU_RPU_0_IEN_FPUFC_WIDTH 1 +#define RPU_RPU_0_IEN_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_0_IEN_FPOFC_SHIFT 23 +#define RPU_RPU_0_IEN_FPOFC_WIDTH 1 +#define RPU_RPU_0_IEN_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_0_IEN_FPIXC_SHIFT 22 +#define RPU_RPU_0_IEN_FPIXC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_0_IEN_FPIOC_SHIFT 21 +#define RPU_RPU_0_IEN_FPIOC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_0_IEN_FPIDC_SHIFT 20 +#define RPU_RPU_0_IEN_FPIDC_WIDTH 1 +#define RPU_RPU_0_IEN_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_0_IEN_FPDZC_SHIFT 19 +#define RPU_RPU_0_IEN_FPDZC_WIDTH 1 +#define RPU_RPU_0_IEN_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_0_IEN_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IEN_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_0_IEN_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IEN_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_0_IEN_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IEN_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_0_IEN_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IEN_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_0_IEN_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IEN_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IEN_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_0_IEN_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IEN_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_0_IEN_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IEN_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_0_IEN_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IEN_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IEN_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_0_IEN_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IEN_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_0_IEN_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IEN_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IEN_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_0_IEN_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IEN_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IEN_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IEN_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_IEN_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IEN_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IEN_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_IEN_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IEN_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IEN_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_IEN_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IEN_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IEN_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_IDS + */ +#define RPU_RPU_0_IDS ( ( RPU_BASEADDR ) + ((u32)0X00000120U) ) + +#define RPU_RPU_0_IDS_FPUFC_SHIFT 24 +#define RPU_RPU_0_IDS_FPUFC_WIDTH 1 +#define RPU_RPU_0_IDS_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_0_IDS_FPOFC_SHIFT 23 +#define RPU_RPU_0_IDS_FPOFC_WIDTH 1 +#define RPU_RPU_0_IDS_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_0_IDS_FPIXC_SHIFT 22 +#define RPU_RPU_0_IDS_FPIXC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_0_IDS_FPIOC_SHIFT 21 +#define RPU_RPU_0_IDS_FPIOC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_0_IDS_FPIDC_SHIFT 20 +#define RPU_RPU_0_IDS_FPIDC_WIDTH 1 +#define RPU_RPU_0_IDS_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_0_IDS_FPDZC_SHIFT 19 +#define RPU_RPU_0_IDS_FPDZC_WIDTH 1 +#define RPU_RPU_0_IDS_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_0_IDS_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_0_IDS_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_0_IDS_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_0_IDS_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_0_IDS_B1TCM_CE_SHIFT 14 +#define RPU_RPU_0_IDS_B1TCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_0_IDS_B0TCM_CE_SHIFT 13 +#define RPU_RPU_0_IDS_B0TCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_0_IDS_ATCM_CE_SHIFT 12 +#define RPU_RPU_0_IDS_ATCM_CE_WIDTH 1 +#define RPU_RPU_0_IDS_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_0_IDS_B1TCM_UE_SHIFT 11 +#define RPU_RPU_0_IDS_B1TCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_0_IDS_B0TCM_UE_SHIFT 10 +#define RPU_RPU_0_IDS_B0TCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_0_IDS_ATCM_UE_SHIFT 9 +#define RPU_RPU_0_IDS_ATCM_UE_WIDTH 1 +#define RPU_RPU_0_IDS_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_0_IDS_DDATA_FAT_SHIFT 7 +#define RPU_RPU_0_IDS_DDATA_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_0_IDS_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_0_IDS_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_0_IDS_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_0_IDS_DDATA_CE_SHIFT 4 +#define RPU_RPU_0_IDS_DDATA_CE_WIDTH 1 +#define RPU_RPU_0_IDS_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_0_IDS_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_0_IDS_IDATA_CE_SHIFT 2 +#define RPU_RPU_0_IDS_IDATA_CE_WIDTH 1 +#define RPU_RPU_0_IDS_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_0_IDS_ITAG_CE_SHIFT 1 +#define RPU_RPU_0_IDS_ITAG_CE_WIDTH 1 +#define RPU_RPU_0_IDS_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_IDS_APB_ERR_SHIFT 0 +#define RPU_RPU_0_IDS_APB_ERR_WIDTH 1 +#define RPU_RPU_0_IDS_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_0_SLV_BASE + */ +#define RPU_RPU_0_SLV_BASE ( ( RPU_BASEADDR ) + ((u32)0X00000124U) ) + +#define RPU_RPU_0_SLV_BASE_ADDR_SHIFT 0 +#define RPU_RPU_0_SLV_BASE_ADDR_WIDTH 8 +#define RPU_RPU_0_SLV_BASE_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: RPU_RPU_0_AXI_OVER + */ +#define RPU_RPU_0_AXI_OVER ( ( RPU_BASEADDR ) + ((u32)0X00000128U) ) + +#define RPU_RPU_0_AXI_OVER_AWCACHE_SHIFT 6 +#define RPU_RPU_0_AXI_OVER_AWCACHE_WIDTH 4 +#define RPU_RPU_0_AXI_OVER_AWCACHE_MASK ((u32)0X000003C0U) + +#define RPU_RPU_0_AXI_OVER_ARCACHE_SHIFT 2 +#define RPU_RPU_0_AXI_OVER_ARCACHE_WIDTH 4 +#define RPU_RPU_0_AXI_OVER_ARCACHE_MASK ((u32)0X0000003CU) + +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_SHIFT 1 +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_WIDTH 1 +#define RPU_RPU_0_AXI_OVER_AWCACHE_EN_MASK ((u32)0X00000002U) + +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_SHIFT 0 +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_WIDTH 1 +#define RPU_RPU_0_AXI_OVER_ARCACHE_EN_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_CFG + */ +#define RPU_RPU_1_CFG ( ( RPU_BASEADDR ) + ((u32)0X00000200U) ) + +#define RPU_RPU_1_CFG_CFGNMFI1_SHIFT 3 +#define RPU_RPU_1_CFG_CFGNMFI1_WIDTH 1 +#define RPU_RPU_1_CFG_CFGNMFI1_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_CFG_VINITHI_SHIFT 2 +#define RPU_RPU_1_CFG_VINITHI_WIDTH 1 +#define RPU_RPU_1_CFG_VINITHI_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_CFG_COHERENT_SHIFT 1 +#define RPU_RPU_1_CFG_COHERENT_WIDTH 1 +#define RPU_RPU_1_CFG_COHERENT_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_CFG_NCPUHALT_SHIFT 0 +#define RPU_RPU_1_CFG_NCPUHALT_WIDTH 1 +#define RPU_RPU_1_CFG_NCPUHALT_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_STATUS + */ +#define RPU_RPU_1_STATUS ( ( RPU_BASEADDR ) + ((u32)0X00000204U) ) + +#define RPU_RPU_1_STATUS_NVALRESET_SHIFT 5 +#define RPU_RPU_1_STATUS_NVALRESET_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALRESET_MASK ((u32)0X00000020U) + +#define RPU_RPU_1_STATUS_NVALIRQ_SHIFT 4 +#define RPU_RPU_1_STATUS_NVALIRQ_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALIRQ_MASK ((u32)0X00000010U) + +#define RPU_RPU_1_STATUS_NVALFIQ_SHIFT 3 +#define RPU_RPU_1_STATUS_NVALFIQ_WIDTH 1 +#define RPU_RPU_1_STATUS_NVALFIQ_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_SHIFT 2 +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NWFIPIPESTOPPED_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_SHIFT 1 +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NWFEPIPESTOPPED_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_STATUS_NCLKSTOPPED_SHIFT 0 +#define RPU_RPU_1_STATUS_NCLKSTOPPED_WIDTH 1 +#define RPU_RPU_1_STATUS_NCLKSTOPPED_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_PWRDWN + */ +#define RPU_RPU_1_PWRDWN ( ( RPU_BASEADDR ) + ((u32)0X00000208U) ) + +#define RPU_RPU_1_PWRDWN_EN_SHIFT 0 +#define RPU_RPU_1_PWRDWN_EN_WIDTH 1 +#define RPU_RPU_1_PWRDWN_EN_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_ISR + */ +#define RPU_RPU_1_ISR ( ( RPU_BASEADDR ) + ((u32)0X00000214U) ) + +#define RPU_RPU_1_ISR_FPUFC_SHIFT 24 +#define RPU_RPU_1_ISR_FPUFC_WIDTH 1 +#define RPU_RPU_1_ISR_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_1_ISR_FPOFC_SHIFT 23 +#define RPU_RPU_1_ISR_FPOFC_WIDTH 1 +#define RPU_RPU_1_ISR_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_1_ISR_FPIXC_SHIFT 22 +#define RPU_RPU_1_ISR_FPIXC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_1_ISR_FPIOC_SHIFT 21 +#define RPU_RPU_1_ISR_FPIOC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_1_ISR_FPIDC_SHIFT 20 +#define RPU_RPU_1_ISR_FPIDC_WIDTH 1 +#define RPU_RPU_1_ISR_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_1_ISR_FPDZC_SHIFT 19 +#define RPU_RPU_1_ISR_FPDZC_WIDTH 1 +#define RPU_RPU_1_ISR_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_1_ISR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_ISR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_1_ISR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_ISR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_1_ISR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_ISR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_1_ISR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_ISR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_1_ISR_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_ISR_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_ISR_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_1_ISR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_ISR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_1_ISR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_ISR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_1_ISR_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_ISR_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_ISR_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_1_ISR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_ISR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_1_ISR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_ISR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_ISR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_1_ISR_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_ISR_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_ISR_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_ISR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_ISR_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_ISR_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_ISR_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_ISR_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_ISR_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_ISR_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_ISR_APB_ERR_SHIFT 0 +#define RPU_RPU_1_ISR_APB_ERR_WIDTH 1 +#define RPU_RPU_1_ISR_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_IMR + */ +#define RPU_RPU_1_IMR ( ( RPU_BASEADDR ) + ((u32)0X00000218U) ) + +#define RPU_RPU_1_IMR_FPUFC_SHIFT 24 +#define RPU_RPU_1_IMR_FPUFC_WIDTH 1 +#define RPU_RPU_1_IMR_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_1_IMR_FPOFC_SHIFT 23 +#define RPU_RPU_1_IMR_FPOFC_WIDTH 1 +#define RPU_RPU_1_IMR_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_1_IMR_FPIXC_SHIFT 22 +#define RPU_RPU_1_IMR_FPIXC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_1_IMR_FPIOC_SHIFT 21 +#define RPU_RPU_1_IMR_FPIOC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_1_IMR_FPIDC_SHIFT 20 +#define RPU_RPU_1_IMR_FPIDC_WIDTH 1 +#define RPU_RPU_1_IMR_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_1_IMR_FPDZC_SHIFT 19 +#define RPU_RPU_1_IMR_FPDZC_WIDTH 1 +#define RPU_RPU_1_IMR_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_1_IMR_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IMR_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_1_IMR_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IMR_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_1_IMR_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IMR_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_1_IMR_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IMR_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_1_IMR_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IMR_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IMR_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_1_IMR_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IMR_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_1_IMR_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IMR_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_1_IMR_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IMR_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IMR_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_1_IMR_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IMR_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_1_IMR_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IMR_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IMR_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_1_IMR_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IMR_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IMR_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IMR_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_IMR_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IMR_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IMR_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_IMR_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IMR_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IMR_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_IMR_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IMR_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IMR_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_IEN + */ +#define RPU_RPU_1_IEN ( ( RPU_BASEADDR ) + ((u32)0X0000021CU) ) + +#define RPU_RPU_1_IEN_FPUFC_SHIFT 24 +#define RPU_RPU_1_IEN_FPUFC_WIDTH 1 +#define RPU_RPU_1_IEN_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_1_IEN_FPOFC_SHIFT 23 +#define RPU_RPU_1_IEN_FPOFC_WIDTH 1 +#define RPU_RPU_1_IEN_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_1_IEN_FPIXC_SHIFT 22 +#define RPU_RPU_1_IEN_FPIXC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_1_IEN_FPIOC_SHIFT 21 +#define RPU_RPU_1_IEN_FPIOC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_1_IEN_FPIDC_SHIFT 20 +#define RPU_RPU_1_IEN_FPIDC_WIDTH 1 +#define RPU_RPU_1_IEN_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_1_IEN_FPDZC_SHIFT 19 +#define RPU_RPU_1_IEN_FPDZC_WIDTH 1 +#define RPU_RPU_1_IEN_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_1_IEN_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IEN_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_1_IEN_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IEN_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_1_IEN_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IEN_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_1_IEN_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IEN_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_1_IEN_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IEN_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IEN_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_1_IEN_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IEN_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_1_IEN_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IEN_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_1_IEN_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IEN_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IEN_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_1_IEN_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IEN_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_1_IEN_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IEN_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IEN_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_1_IEN_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IEN_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IEN_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IEN_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_IEN_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IEN_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IEN_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_IEN_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IEN_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IEN_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_IEN_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IEN_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IEN_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_IDS + */ +#define RPU_RPU_1_IDS ( ( RPU_BASEADDR ) + ((u32)0X00000220U) ) + +#define RPU_RPU_1_IDS_FPUFC_SHIFT 24 +#define RPU_RPU_1_IDS_FPUFC_WIDTH 1 +#define RPU_RPU_1_IDS_FPUFC_MASK ((u32)0X01000000U) + +#define RPU_RPU_1_IDS_FPOFC_SHIFT 23 +#define RPU_RPU_1_IDS_FPOFC_WIDTH 1 +#define RPU_RPU_1_IDS_FPOFC_MASK ((u32)0X00800000U) + +#define RPU_RPU_1_IDS_FPIXC_SHIFT 22 +#define RPU_RPU_1_IDS_FPIXC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIXC_MASK ((u32)0X00400000U) + +#define RPU_RPU_1_IDS_FPIOC_SHIFT 21 +#define RPU_RPU_1_IDS_FPIOC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIOC_MASK ((u32)0X00200000U) + +#define RPU_RPU_1_IDS_FPIDC_SHIFT 20 +#define RPU_RPU_1_IDS_FPIDC_WIDTH 1 +#define RPU_RPU_1_IDS_FPIDC_MASK ((u32)0X00100000U) + +#define RPU_RPU_1_IDS_FPDZC_SHIFT 19 +#define RPU_RPU_1_IDS_FPDZC_WIDTH 1 +#define RPU_RPU_1_IDS_FPDZC_MASK ((u32)0X00080000U) + +#define RPU_RPU_1_IDS_TCM_ASLV_CE_SHIFT 18 +#define RPU_RPU_1_IDS_TCM_ASLV_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_ASLV_CE_MASK ((u32)0X00040000U) + +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_SHIFT 17 +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_ASLV_FAT_MASK ((u32)0X00020000U) + +#define RPU_RPU_1_IDS_TCM_LST_CE_SHIFT 16 +#define RPU_RPU_1_IDS_TCM_LST_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_LST_CE_MASK ((u32)0X00010000U) + +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_SHIFT 15 +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_PREFETCH_CE_MASK ((u32)0X00008000U) + +#define RPU_RPU_1_IDS_B1TCM_CE_SHIFT 14 +#define RPU_RPU_1_IDS_B1TCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_B1TCM_CE_MASK ((u32)0X00004000U) + +#define RPU_RPU_1_IDS_B0TCM_CE_SHIFT 13 +#define RPU_RPU_1_IDS_B0TCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_B0TCM_CE_MASK ((u32)0X00002000U) + +#define RPU_RPU_1_IDS_ATCM_CE_SHIFT 12 +#define RPU_RPU_1_IDS_ATCM_CE_WIDTH 1 +#define RPU_RPU_1_IDS_ATCM_CE_MASK ((u32)0X00001000U) + +#define RPU_RPU_1_IDS_B1TCM_UE_SHIFT 11 +#define RPU_RPU_1_IDS_B1TCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_B1TCM_UE_MASK ((u32)0X00000800U) + +#define RPU_RPU_1_IDS_B0TCM_UE_SHIFT 10 +#define RPU_RPU_1_IDS_B0TCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_B0TCM_UE_MASK ((u32)0X00000400U) + +#define RPU_RPU_1_IDS_ATCM_UE_SHIFT 9 +#define RPU_RPU_1_IDS_ATCM_UE_WIDTH 1 +#define RPU_RPU_1_IDS_ATCM_UE_MASK ((u32)0X00000200U) + +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_SHIFT 8 +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_DTAG_DIRTY_FAT_MASK ((u32)0X00000100U) + +#define RPU_RPU_1_IDS_DDATA_FAT_SHIFT 7 +#define RPU_RPU_1_IDS_DDATA_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_DDATA_FAT_MASK ((u32)0X00000080U) + +#define RPU_RPU_1_IDS_TCM_LST_FAT_SHIFT 6 +#define RPU_RPU_1_IDS_TCM_LST_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_LST_FAT_MASK ((u32)0X00000040U) + +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_SHIFT 5 +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_WIDTH 1 +#define RPU_RPU_1_IDS_TCM_PREFETCH_FAT_MASK ((u32)0X00000020U) + +#define RPU_RPU_1_IDS_DDATA_CE_SHIFT 4 +#define RPU_RPU_1_IDS_DDATA_CE_WIDTH 1 +#define RPU_RPU_1_IDS_DDATA_CE_MASK ((u32)0X00000010U) + +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_SHIFT 3 +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_WIDTH 1 +#define RPU_RPU_1_IDS_DTAG_DIRTY_CE_MASK ((u32)0X00000008U) + +#define RPU_RPU_1_IDS_IDATA_CE_SHIFT 2 +#define RPU_RPU_1_IDS_IDATA_CE_WIDTH 1 +#define RPU_RPU_1_IDS_IDATA_CE_MASK ((u32)0X00000004U) + +#define RPU_RPU_1_IDS_ITAG_CE_SHIFT 1 +#define RPU_RPU_1_IDS_ITAG_CE_WIDTH 1 +#define RPU_RPU_1_IDS_ITAG_CE_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_IDS_APB_ERR_SHIFT 0 +#define RPU_RPU_1_IDS_APB_ERR_WIDTH 1 +#define RPU_RPU_1_IDS_APB_ERR_MASK ((u32)0X00000001U) + +/** + * Register: RPU_RPU_1_SLV_BASE + */ +#define RPU_RPU_1_SLV_BASE ( ( RPU_BASEADDR ) + ((u32)0X00000224U) ) + +#define RPU_RPU_1_SLV_BASE_ADDR_SHIFT 0 +#define RPU_RPU_1_SLV_BASE_ADDR_WIDTH 8 +#define RPU_RPU_1_SLV_BASE_ADDR_MASK ((u32)0X000000FFU) + +/** + * Register: RPU_RPU_1_AXI_OVER + */ +#define RPU_RPU_1_AXI_OVER ( ( RPU_BASEADDR ) + ((u32)0X00000228U) ) + +#define RPU_RPU_1_AXI_OVER_AWCACHE_SHIFT 6 +#define RPU_RPU_1_AXI_OVER_AWCACHE_WIDTH 4 +#define RPU_RPU_1_AXI_OVER_AWCACHE_MASK ((u32)0X000003C0U) + +#define RPU_RPU_1_AXI_OVER_ARCACHE_SHIFT 2 +#define RPU_RPU_1_AXI_OVER_ARCACHE_WIDTH 4 +#define RPU_RPU_1_AXI_OVER_ARCACHE_MASK ((u32)0X0000003CU) + +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_SHIFT 1 +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_WIDTH 1 +#define RPU_RPU_1_AXI_OVER_AWCACHE_EN_MASK ((u32)0X00000002U) + +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_SHIFT 0 +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_WIDTH 1 +#define RPU_RPU_1_AXI_OVER_ARCACHE_EN_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _RPU_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/rtc.h b/lib/sw_apps/zynqmp_pmufw/src/rtc.h new file mode 100644 index 00000000..c4fb005e --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/rtc.h @@ -0,0 +1,252 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _RTC_H_ +#define _RTC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * RTC Base Address + */ +#define RTC_BASEADDR ((u32)0XFFA60000U) + +/** + * Register: RTC_SET_TIME_WRITE + */ +#define RTC_SET_TIME_WRITE ( ( RTC_BASEADDR ) + ((u32)0X00000000U) ) + +#define RTC_SET_TIME_WRITE_VALUE_SHIFT 0 +#define RTC_SET_TIME_WRITE_VALUE_WIDTH 32 +#define RTC_SET_TIME_WRITE_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RTC_SET_TIME_READ + */ +#define RTC_SET_TIME_READ ( ( RTC_BASEADDR ) + ((u32)0X00000004U) ) + +#define RTC_SET_TIME_READ_VALUE_SHIFT 0 +#define RTC_SET_TIME_READ_VALUE_WIDTH 32 +#define RTC_SET_TIME_READ_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RTC_CALIB_WRITE + */ +#define RTC_CALIB_WRITE ( ( RTC_BASEADDR ) + ((u32)0X00000008U) ) + +#define RTC_CALIB_WRITE_FRACTION_EN_SHIFT 20 +#define RTC_CALIB_WRITE_FRACTION_EN_WIDTH 1 +#define RTC_CALIB_WRITE_FRACTION_EN_MASK ((u32)0X00100000U) + +#define RTC_CALIB_WRITE_FRACTION_DATA_SHIFT 16 +#define RTC_CALIB_WRITE_FRACTION_DATA_WIDTH 4 +#define RTC_CALIB_WRITE_FRACTION_DATA_MASK ((u32)0X000F0000U) + +#define RTC_CALIB_WRITE_MAX_TICK_SHIFT 0 +#define RTC_CALIB_WRITE_MAX_TICK_WIDTH 16 +#define RTC_CALIB_WRITE_MAX_TICK_MASK ((u32)0X0000FFFFU) + +/** + * Register: RTC_CALIB_READ + */ +#define RTC_CALIB_READ ( ( RTC_BASEADDR ) + ((u32)0X0000000CU) ) + +#define RTC_CALIB_READ_FRACTION_EN_SHIFT 20 +#define RTC_CALIB_READ_FRACTION_EN_WIDTH 1 +#define RTC_CALIB_READ_FRACTION_EN_MASK ((u32)0X00100000U) + +#define RTC_CALIB_READ_FRACTION_DATA_SHIFT 16 +#define RTC_CALIB_READ_FRACTION_DATA_WIDTH 4 +#define RTC_CALIB_READ_FRACTION_DATA_MASK ((u32)0X000F0000U) + +#define RTC_CALIB_READ_MAX_TICK_SHIFT 0 +#define RTC_CALIB_READ_MAX_TICK_WIDTH 16 +#define RTC_CALIB_READ_MAX_TICK_MASK ((u32)0X0000FFFFU) + +/** + * Register: RTC_CURRENT_TIME + */ +#define RTC_CURRENT_TIME ( ( RTC_BASEADDR ) + ((u32)0X00000010U) ) + +#define RTC_CURRENT_TIME_VALUE_SHIFT 0 +#define RTC_CURRENT_TIME_VALUE_WIDTH 32 +#define RTC_CURRENT_TIME_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RTC_CURRENT_TICK + */ +#define RTC_CURRENT_TICK ( ( RTC_BASEADDR ) + ((u32)0X00000014U) ) + +#define RTC_CURRENT_TICK_VALUE_SHIFT 0 +#define RTC_CURRENT_TICK_VALUE_WIDTH 16 +#define RTC_CURRENT_TICK_VALUE_MASK ((u32)0X0000FFFFU) + +/** + * Register: RTC_ALARM + */ +#define RTC_ALARM ( ( RTC_BASEADDR ) + ((u32)0X00000018U) ) + +#define RTC_ALARM_VALUE_SHIFT 0 +#define RTC_ALARM_VALUE_WIDTH 32 +#define RTC_ALARM_VALUE_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RTC_RTC_INT_STATUS + */ +#define RTC_RTC_INT_STATUS ( ( RTC_BASEADDR ) + ((u32)0X00000020U) ) + +#define RTC_RTC_INT_STATUS_ALARM_SHIFT 1 +#define RTC_RTC_INT_STATUS_ALARM_WIDTH 1 +#define RTC_RTC_INT_STATUS_ALARM_MASK ((u32)0X00000002U) + +#define RTC_RTC_INT_STATUS_SECONDS_SHIFT 0 +#define RTC_RTC_INT_STATUS_SECONDS_WIDTH 1 +#define RTC_RTC_INT_STATUS_SECONDS_MASK ((u32)0X00000001U) + +/** + * Register: RTC_RTC_INT_MASK + */ +#define RTC_RTC_INT_MASK ( ( RTC_BASEADDR ) + ((u32)0X00000024U) ) + +#define RTC_RTC_INT_MASK_ALARM_SHIFT 1 +#define RTC_RTC_INT_MASK_ALARM_WIDTH 1 +#define RTC_RTC_INT_MASK_ALARM_MASK ((u32)0X00000002U) + +#define RTC_RTC_INT_MASK_SECONDS_SHIFT 0 +#define RTC_RTC_INT_MASK_SECONDS_WIDTH 1 +#define RTC_RTC_INT_MASK_SECONDS_MASK ((u32)0X00000001U) + +/** + * Register: RTC_RTC_INT_EN + */ +#define RTC_RTC_INT_EN ( ( RTC_BASEADDR ) + ((u32)0X00000028U) ) + +#define RTC_RTC_INT_EN_ALARM_SHIFT 1 +#define RTC_RTC_INT_EN_ALARM_WIDTH 1 +#define RTC_RTC_INT_EN_ALARM_MASK ((u32)0X00000002U) + +#define RTC_RTC_INT_EN_SECONDS_SHIFT 0 +#define RTC_RTC_INT_EN_SECONDS_WIDTH 1 +#define RTC_RTC_INT_EN_SECONDS_MASK ((u32)0X00000001U) + +/** + * Register: RTC_RTC_INT_DIS + */ +#define RTC_RTC_INT_DIS ( ( RTC_BASEADDR ) + ((u32)0X0000002CU) ) + +#define RTC_RTC_INT_DIS_ALARM_SHIFT 1 +#define RTC_RTC_INT_DIS_ALARM_WIDTH 1 +#define RTC_RTC_INT_DIS_ALARM_MASK ((u32)0X00000002U) + +#define RTC_RTC_INT_DIS_SECONDS_SHIFT 0 +#define RTC_RTC_INT_DIS_SECONDS_WIDTH 1 +#define RTC_RTC_INT_DIS_SECONDS_MASK ((u32)0X00000001U) + +/** + * Register: RTC_ADDR_ERROR + */ +#define RTC_ADDR_ERROR ( ( RTC_BASEADDR ) + ((u32)0X00000030U) ) + +#define RTC_ADDR_ERROR_STATUS_SHIFT 0 +#define RTC_ADDR_ERROR_STATUS_WIDTH 1 +#define RTC_ADDR_ERROR_STATUS_MASK ((u32)0X00000001U) + +/** + * Register: RTC_ADDR_ERROR_INT_MASK + */ +#define RTC_ADDR_ERROR_INT_MASK ( ( RTC_BASEADDR ) + ((u32)0X00000034U) ) + +#define RTC_ADDR_ERROR_INT_MASK_MASK_SHIFT 0 +#define RTC_ADDR_ERROR_INT_MASK_MASK_WIDTH 1 +#define RTC_ADDR_ERROR_INT_MASK_MASK_MASK ((u32)0X00000001U) + +/** + * Register: RTC_ADDR_ERROR_INT_EN + */ +#define RTC_ADDR_ERROR_INT_EN ( ( RTC_BASEADDR ) + ((u32)0X00000038U) ) + +#define RTC_ADDR_ERROR_INT_EN_MASK_SHIFT 0 +#define RTC_ADDR_ERROR_INT_EN_MASK_WIDTH 1 +#define RTC_ADDR_ERROR_INT_EN_MASK_MASK ((u32)0X00000001U) + +/** + * Register: RTC_ADDR_ERROR_INT_DIS + */ +#define RTC_ADDR_ERROR_INT_DIS ( ( RTC_BASEADDR ) + ((u32)0X0000003CU) ) + +#define RTC_ADDR_ERROR_INT_DIS_MASK_SHIFT 0 +#define RTC_ADDR_ERROR_INT_DIS_MASK_WIDTH 1 +#define RTC_ADDR_ERROR_INT_DIS_MASK_MASK ((u32)0X00000001U) + +/** + * Register: RTC_CONTROL + */ +#define RTC_CONTROL ( ( RTC_BASEADDR ) + ((u32)0X00000040U) ) + +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_WIDTH 1 +#define RTC_CONTROL_BATTERY_DISABLE_MASK ((u32)0X80000000U) + +#define RTC_CONTROL_OSC_CNTRL_SHIFT 24 +#define RTC_CONTROL_OSC_CNTRL_WIDTH 4 +#define RTC_CONTROL_OSC_CNTRL_MASK ((u32)0X0F000000U) + +#define RTC_CONTROL_SLVERR_ENABLE_SHIFT 0 +#define RTC_CONTROL_SLVERR_ENABLE_WIDTH 1 +#define RTC_CONTROL_SLVERR_ENABLE_MASK ((u32)0X00000001U) + +/** + * Register: RTC_SAFETY_CHK + */ +#define RTC_SAFETY_CHK ( ( RTC_BASEADDR ) + ((u32)0X00000050U) ) + +#define RTC_SAFETY_CHK_REG_SHIFT 0 +#define RTC_SAFETY_CHK_REG_WIDTH 32 +#define RTC_SAFETY_CHK_REG_MASK ((u32)0XFFFFFFFFU) + +/** + * Register: RTC_ECO + */ +#define RTC_ECO ( ( RTC_BASEADDR ) + ((u32)0X00000060U) ) + +#define RTC_ECO_REG_SHIFT 0 +#define RTC_ECO_REG_WIDTH 32 +#define RTC_ECO_REG_MASK ((u32)0XFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + + +#endif /* _RTC_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/uart0.h b/lib/sw_apps/zynqmp_pmufw/src/uart0.h new file mode 100644 index 00000000..75920cb0 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/uart0.h @@ -0,0 +1,632 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#ifndef _UART0_H_ +#define _UART0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * UART0 Base Address + */ +#define UART0_BASEADDR ((u32)0XFF000000U) + +/** + * Register: UART0_CONTROL_REG0 + */ +#define UART0_CONTROL_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000000U) ) + +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_WIDTH 1 +#define UART0_CONTROL_REG0_STPBRK_MASK ((u32)0X00000100U) + +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_WIDTH 1 +#define UART0_CONTROL_REG0_STTBRK_MASK ((u32)0X00000080U) + +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_WIDTH 1 +#define UART0_CONTROL_REG0_RSTTO_MASK ((u32)0X00000040U) + +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_WIDTH 1 +#define UART0_CONTROL_REG0_TXDIS_MASK ((u32)0X00000020U) + +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_WIDTH 1 +#define UART0_CONTROL_REG0_TXEN_MASK ((u32)0X00000010U) + +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_WIDTH 1 +#define UART0_CONTROL_REG0_RXDIS_MASK ((u32)0X00000008U) + +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_WIDTH 1 +#define UART0_CONTROL_REG0_RXEN_MASK ((u32)0X00000004U) + +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_WIDTH 1 +#define UART0_CONTROL_REG0_TXRES_MASK ((u32)0X00000002U) + +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_WIDTH 1 +#define UART0_CONTROL_REG0_RXRES_MASK ((u32)0X00000001U) + +/** + * Register: UART0_MODE_REG0 + */ +#define UART0_MODE_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000004U) ) + +#define UART0_MODE_REG0_WSIZE_SHIFT 12 +#define UART0_MODE_REG0_WSIZE_WIDTH 2 +#define UART0_MODE_REG0_WSIZE_MASK ((u32)0X00003000U) + +#define UART0_MODE_REG0_IRMODE_SHIFT 11 +#define UART0_MODE_REG0_IRMODE_WIDTH 1 +#define UART0_MODE_REG0_IRMODE_MASK ((u32)0X00000800U) + +#define UART0_MODE_REG0_UCLKEN_SHIFT 10 +#define UART0_MODE_REG0_UCLKEN_WIDTH 1 +#define UART0_MODE_REG0_UCLKEN_MASK ((u32)0X00000400U) + +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_WIDTH 2 +#define UART0_MODE_REG0_CHMODE_MASK ((u32)0X00000300U) + +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_WIDTH 2 +#define UART0_MODE_REG0_NBSTOP_MASK ((u32)0X000000C0U) + +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_WIDTH 3 +#define UART0_MODE_REG0_PAR_MASK ((u32)0X00000038U) + +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_WIDTH 2 +#define UART0_MODE_REG0_CHRL_MASK ((u32)0X00000006U) + +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_WIDTH 1 +#define UART0_MODE_REG0_CLKS_MASK ((u32)0X00000001U) + +/** + * Register: UART0_INTRPT_EN_REG0 + */ +#define UART0_INTRPT_EN_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000008U) ) + +#define UART0_INTRPT_EN_REG0_RBRK_SHIFT 13 +#define UART0_INTRPT_EN_REG0_RBRK_WIDTH 1 +#define UART0_INTRPT_EN_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART0_INTRPT_EN_REG0_TOVR_SHIFT 12 +#define UART0_INTRPT_EN_REG0_TOVR_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART0_INTRPT_EN_REG0_TNFUL_SHIFT 11 +#define UART0_INTRPT_EN_REG0_TNFUL_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART0_INTRPT_EN_REG0_TTRIG_SHIFT 10 +#define UART0_INTRPT_EN_REG0_TTRIG_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART0_INTRPT_EN_REG0_DMSI_SHIFT 9 +#define UART0_INTRPT_EN_REG0_DMSI_WIDTH 1 +#define UART0_INTRPT_EN_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART0_INTRPT_EN_REG0_TIMEOUT_SHIFT 8 +#define UART0_INTRPT_EN_REG0_TIMEOUT_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART0_INTRPT_EN_REG0_PARE_SHIFT 7 +#define UART0_INTRPT_EN_REG0_PARE_WIDTH 1 +#define UART0_INTRPT_EN_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART0_INTRPT_EN_REG0_FRAME_SHIFT 6 +#define UART0_INTRPT_EN_REG0_FRAME_WIDTH 1 +#define UART0_INTRPT_EN_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART0_INTRPT_EN_REG0_ROVR_SHIFT 5 +#define UART0_INTRPT_EN_REG0_ROVR_WIDTH 1 +#define UART0_INTRPT_EN_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART0_INTRPT_EN_REG0_TFUL_SHIFT 4 +#define UART0_INTRPT_EN_REG0_TFUL_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART0_INTRPT_EN_REG0_TEMPTY_SHIFT 3 +#define UART0_INTRPT_EN_REG0_TEMPTY_WIDTH 1 +#define UART0_INTRPT_EN_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART0_INTRPT_EN_REG0_RFUL_SHIFT 2 +#define UART0_INTRPT_EN_REG0_RFUL_WIDTH 1 +#define UART0_INTRPT_EN_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART0_INTRPT_EN_REG0_REMPTY_SHIFT 1 +#define UART0_INTRPT_EN_REG0_REMPTY_WIDTH 1 +#define UART0_INTRPT_EN_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART0_INTRPT_EN_REG0_RTRIG_SHIFT 0 +#define UART0_INTRPT_EN_REG0_RTRIG_WIDTH 1 +#define UART0_INTRPT_EN_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART0_INTRPT_DIS_REG0 + */ +#define UART0_INTRPT_DIS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000000CU) ) + +#define UART0_INTRPT_DIS_REG0_RBRK_SHIFT 13 +#define UART0_INTRPT_DIS_REG0_RBRK_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART0_INTRPT_DIS_REG0_TOVR_SHIFT 12 +#define UART0_INTRPT_DIS_REG0_TOVR_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART0_INTRPT_DIS_REG0_TNFUL_SHIFT 11 +#define UART0_INTRPT_DIS_REG0_TNFUL_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART0_INTRPT_DIS_REG0_TTRIG_SHIFT 10 +#define UART0_INTRPT_DIS_REG0_TTRIG_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART0_INTRPT_DIS_REG0_DMSI_SHIFT 9 +#define UART0_INTRPT_DIS_REG0_DMSI_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART0_INTRPT_DIS_REG0_TIMEOUT_SHIFT 8 +#define UART0_INTRPT_DIS_REG0_TIMEOUT_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART0_INTRPT_DIS_REG0_PARE_SHIFT 7 +#define UART0_INTRPT_DIS_REG0_PARE_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART0_INTRPT_DIS_REG0_FRAME_SHIFT 6 +#define UART0_INTRPT_DIS_REG0_FRAME_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART0_INTRPT_DIS_REG0_ROVR_SHIFT 5 +#define UART0_INTRPT_DIS_REG0_ROVR_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART0_INTRPT_DIS_REG0_TFUL_SHIFT 4 +#define UART0_INTRPT_DIS_REG0_TFUL_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART0_INTRPT_DIS_REG0_TEMPTY_SHIFT 3 +#define UART0_INTRPT_DIS_REG0_TEMPTY_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART0_INTRPT_DIS_REG0_RFUL_SHIFT 2 +#define UART0_INTRPT_DIS_REG0_RFUL_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART0_INTRPT_DIS_REG0_REMPTY_SHIFT 1 +#define UART0_INTRPT_DIS_REG0_REMPTY_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART0_INTRPT_DIS_REG0_RTRIG_SHIFT 0 +#define UART0_INTRPT_DIS_REG0_RTRIG_WIDTH 1 +#define UART0_INTRPT_DIS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART0_INTRPT_MASK_REG0 + */ +#define UART0_INTRPT_MASK_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000010U) ) + +#define UART0_INTRPT_MASK_REG0_RBRK_SHIFT 13 +#define UART0_INTRPT_MASK_REG0_RBRK_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART0_INTRPT_MASK_REG0_TOVR_SHIFT 12 +#define UART0_INTRPT_MASK_REG0_TOVR_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART0_INTRPT_MASK_REG0_TNFUL_SHIFT 11 +#define UART0_INTRPT_MASK_REG0_TNFUL_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART0_INTRPT_MASK_REG0_TTRIG_SHIFT 10 +#define UART0_INTRPT_MASK_REG0_TTRIG_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART0_INTRPT_MASK_REG0_DMSI_SHIFT 9 +#define UART0_INTRPT_MASK_REG0_DMSI_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART0_INTRPT_MASK_REG0_TIMEOUT_SHIFT 8 +#define UART0_INTRPT_MASK_REG0_TIMEOUT_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART0_INTRPT_MASK_REG0_PARE_SHIFT 7 +#define UART0_INTRPT_MASK_REG0_PARE_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART0_INTRPT_MASK_REG0_FRAME_SHIFT 6 +#define UART0_INTRPT_MASK_REG0_FRAME_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART0_INTRPT_MASK_REG0_ROVR_SHIFT 5 +#define UART0_INTRPT_MASK_REG0_ROVR_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART0_INTRPT_MASK_REG0_TFUL_SHIFT 4 +#define UART0_INTRPT_MASK_REG0_TFUL_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART0_INTRPT_MASK_REG0_TEMPTY_SHIFT 3 +#define UART0_INTRPT_MASK_REG0_TEMPTY_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART0_INTRPT_MASK_REG0_RFUL_SHIFT 2 +#define UART0_INTRPT_MASK_REG0_RFUL_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART0_INTRPT_MASK_REG0_REMPTY_SHIFT 1 +#define UART0_INTRPT_MASK_REG0_REMPTY_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART0_INTRPT_MASK_REG0_RTRIG_SHIFT 0 +#define UART0_INTRPT_MASK_REG0_RTRIG_WIDTH 1 +#define UART0_INTRPT_MASK_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART0_CHNL_INT_STS_REG0 + */ +#define UART0_CHNL_INT_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000014U) ) + +#define UART0_CHNL_INT_STS_REG0_RBRK_SHIFT 13 +#define UART0_CHNL_INT_STS_REG0_RBRK_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART0_CHNL_INT_STS_REG0_TOVR_SHIFT 12 +#define UART0_CHNL_INT_STS_REG0_TOVR_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART0_CHNL_INT_STS_REG0_TNFUL_SHIFT 11 +#define UART0_CHNL_INT_STS_REG0_TNFUL_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART0_CHNL_INT_STS_REG0_TTRIG_SHIFT 10 +#define UART0_CHNL_INT_STS_REG0_TTRIG_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART0_CHNL_INT_STS_REG0_DMSI_SHIFT 9 +#define UART0_CHNL_INT_STS_REG0_DMSI_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART0_CHNL_INT_STS_REG0_TIMEOUT_SHIFT 8 +#define UART0_CHNL_INT_STS_REG0_TIMEOUT_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART0_CHNL_INT_STS_REG0_PARE_SHIFT 7 +#define UART0_CHNL_INT_STS_REG0_PARE_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART0_CHNL_INT_STS_REG0_FRAME_SHIFT 6 +#define UART0_CHNL_INT_STS_REG0_FRAME_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART0_CHNL_INT_STS_REG0_ROVR_SHIFT 5 +#define UART0_CHNL_INT_STS_REG0_ROVR_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART0_CHNL_INT_STS_REG0_TFUL_SHIFT 4 +#define UART0_CHNL_INT_STS_REG0_TFUL_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART0_CHNL_INT_STS_REG0_TEMPTY_SHIFT 3 +#define UART0_CHNL_INT_STS_REG0_TEMPTY_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART0_CHNL_INT_STS_REG0_RFUL_SHIFT 2 +#define UART0_CHNL_INT_STS_REG0_RFUL_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART0_CHNL_INT_STS_REG0_REMPTY_SHIFT 1 +#define UART0_CHNL_INT_STS_REG0_REMPTY_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART0_CHNL_INT_STS_REG0_RTRIG_SHIFT 0 +#define UART0_CHNL_INT_STS_REG0_RTRIG_WIDTH 1 +#define UART0_CHNL_INT_STS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART0_BAUD_RATE_GEN_REG0 + */ +#define UART0_BAUD_RATE_GEN_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000018U) ) + +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_WIDTH 16 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK ((u32)0X0000FFFFU) + +/** + * Register: UART0_RCVR_TIMEOUT_REG0 + */ +#define UART0_RCVR_TIMEOUT_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000001CU) ) + +#define UART0_RCVR_TIMEOUT_REG0_RTO_SHIFT 0 +#define UART0_RCVR_TIMEOUT_REG0_RTO_WIDTH 8 +#define UART0_RCVR_TIMEOUT_REG0_RTO_MASK ((u32)0X000000FFU) + +/** + * Register: UART0_RCVR_FIFO_TRIGGER_LEVEL0 + */ +#define UART0_RCVR_FIFO_TRIGGER_LEVEL0 ( ( UART0_BASEADDR ) + ((u32)0X00000020U) ) + +#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_SHIFT 0 +#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_WIDTH 6 +#define UART0_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_MASK ((u32)0X0000003FU) + +/** + * Register: UART0_MODEM_CTRL_REG0 + */ +#define UART0_MODEM_CTRL_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000024U) ) + +#define UART0_MODEM_CTRL_REG0_FCM_SHIFT 5 +#define UART0_MODEM_CTRL_REG0_FCM_WIDTH 1 +#define UART0_MODEM_CTRL_REG0_FCM_MASK ((u32)0X00000020U) + +#define UART0_MODEM_CTRL_REG0_RTS_SHIFT 1 +#define UART0_MODEM_CTRL_REG0_RTS_WIDTH 1 +#define UART0_MODEM_CTRL_REG0_RTS_MASK ((u32)0X00000002U) + +#define UART0_MODEM_CTRL_REG0_DTR_SHIFT 0 +#define UART0_MODEM_CTRL_REG0_DTR_WIDTH 1 +#define UART0_MODEM_CTRL_REG0_DTR_MASK ((u32)0X00000001U) + +/** + * Register: UART0_MODEM_STS_REG0 + */ +#define UART0_MODEM_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000028U) ) + +#define UART0_MODEM_STS_REG0_FCMS_SHIFT 8 +#define UART0_MODEM_STS_REG0_FCMS_WIDTH 1 +#define UART0_MODEM_STS_REG0_FCMS_MASK ((u32)0X00000100U) + +#define UART0_MODEM_STS_REG0_DCD_SHIFT 7 +#define UART0_MODEM_STS_REG0_DCD_WIDTH 1 +#define UART0_MODEM_STS_REG0_DCD_MASK ((u32)0X00000080U) + +#define UART0_MODEM_STS_REG0_RI_SHIFT 6 +#define UART0_MODEM_STS_REG0_RI_WIDTH 1 +#define UART0_MODEM_STS_REG0_RI_MASK ((u32)0X00000040U) + +#define UART0_MODEM_STS_REG0_DSR_SHIFT 5 +#define UART0_MODEM_STS_REG0_DSR_WIDTH 1 +#define UART0_MODEM_STS_REG0_DSR_MASK ((u32)0X00000020U) + +#define UART0_MODEM_STS_REG0_CTS_SHIFT 4 +#define UART0_MODEM_STS_REG0_CTS_WIDTH 1 +#define UART0_MODEM_STS_REG0_CTS_MASK ((u32)0X00000010U) + +#define UART0_MODEM_STS_REG0_DDCD_SHIFT 3 +#define UART0_MODEM_STS_REG0_DDCD_WIDTH 1 +#define UART0_MODEM_STS_REG0_DDCD_MASK ((u32)0X00000008U) + +#define UART0_MODEM_STS_REG0_TERI_SHIFT 2 +#define UART0_MODEM_STS_REG0_TERI_WIDTH 1 +#define UART0_MODEM_STS_REG0_TERI_MASK ((u32)0X00000004U) + +#define UART0_MODEM_STS_REG0_DDSR_SHIFT 1 +#define UART0_MODEM_STS_REG0_DDSR_WIDTH 1 +#define UART0_MODEM_STS_REG0_DDSR_MASK ((u32)0X00000002U) + +#define UART0_MODEM_STS_REG0_DCTS_SHIFT 0 +#define UART0_MODEM_STS_REG0_DCTS_WIDTH 1 +#define UART0_MODEM_STS_REG0_DCTS_MASK ((u32)0X00000001U) + +/** + * Register: UART0_CHANNEL_STS_REG0 + */ +#define UART0_CHANNEL_STS_REG0 ( ( UART0_BASEADDR ) + ((u32)0X0000002CU) ) + +#define UART0_CHANNEL_STS_REG0_RBRK_SHIFT 15 +#define UART0_CHANNEL_STS_REG0_RBRK_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_RBRK_MASK ((u32)0X00008000U) + +#define UART0_CHANNEL_STS_REG0_TNFUL_SHIFT 14 +#define UART0_CHANNEL_STS_REG0_TNFUL_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TNFUL_MASK ((u32)0X00004000U) + +#define UART0_CHANNEL_STS_REG0_TTRIG_SHIFT 13 +#define UART0_CHANNEL_STS_REG0_TTRIG_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TTRIG_MASK ((u32)0X00002000U) + +#define UART0_CHANNEL_STS_REG0_FDELT_SHIFT 12 +#define UART0_CHANNEL_STS_REG0_FDELT_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_FDELT_MASK ((u32)0X00001000U) + +#define UART0_CHANNEL_STS_REG0_TACTIVE_SHIFT 11 +#define UART0_CHANNEL_STS_REG0_TACTIVE_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TACTIVE_MASK ((u32)0X00000800U) + +#define UART0_CHANNEL_STS_REG0_RACTIVE_SHIFT 10 +#define UART0_CHANNEL_STS_REG0_RACTIVE_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_RACTIVE_MASK ((u32)0X00000400U) + +#define UART0_CHANNEL_STS_REG0_DMSI_SHIFT 9 +#define UART0_CHANNEL_STS_REG0_DMSI_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART0_CHANNEL_STS_REG0_TIMEOUT_SHIFT 8 +#define UART0_CHANNEL_STS_REG0_TIMEOUT_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART0_CHANNEL_STS_REG0_PARE_SHIFT 7 +#define UART0_CHANNEL_STS_REG0_PARE_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART0_CHANNEL_STS_REG0_FRAME_SHIFT 6 +#define UART0_CHANNEL_STS_REG0_FRAME_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART0_CHANNEL_STS_REG0_ROVR_SHIFT 5 +#define UART0_CHANNEL_STS_REG0_ROVR_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART0_CHANNEL_STS_REG0_TFUL_SHIFT 4 +#define UART0_CHANNEL_STS_REG0_TFUL_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART0_CHANNEL_STS_REG0_TEMPTY_SHIFT 3 +#define UART0_CHANNEL_STS_REG0_TEMPTY_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART0_CHANNEL_STS_REG0_RFUL_SHIFT 2 +#define UART0_CHANNEL_STS_REG0_RFUL_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART0_CHANNEL_STS_REG0_REMPTY_SHIFT 1 +#define UART0_CHANNEL_STS_REG0_REMPTY_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART0_CHANNEL_STS_REG0_RTRIG_SHIFT 0 +#define UART0_CHANNEL_STS_REG0_RTRIG_WIDTH 1 +#define UART0_CHANNEL_STS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART0_TX_RX_FIFO0 + */ +#define UART0_TX_RX_FIFO0 ( ( UART0_BASEADDR ) + ((u32)0X00000030U) ) + +#define UART0_TX_RX_FIFO0_FIFO_SHIFT 0 +#define UART0_TX_RX_FIFO0_FIFO_WIDTH 8 +#define UART0_TX_RX_FIFO0_FIFO_MASK ((u32)0X000000FFU) + +/** + * Register: UART0_BAUD_RATE_DIVIDER_REG0 + */ +#define UART0_BAUD_RATE_DIVIDER_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000034U) ) + +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_WIDTH 8 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK ((u32)0X000000FFU) + +/** + * Register: UART0_FLOW_DELAY_REG0 + */ +#define UART0_FLOW_DELAY_REG0 ( ( UART0_BASEADDR ) + ((u32)0X00000038U) ) + +#define UART0_FLOW_DELAY_REG0_FDEL_SHIFT 0 +#define UART0_FLOW_DELAY_REG0_FDEL_WIDTH 6 +#define UART0_FLOW_DELAY_REG0_FDEL_MASK ((u32)0X0000003FU) + +/** + * Register: UART0_IR_MIN_RCV_PULSE_WDTH0 + */ +#define UART0_IR_MIN_RCV_PULSE_WDTH0 ( ( UART0_BASEADDR ) + ((u32)0X0000003CU) ) + +#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_SHIFT 0 +#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_WIDTH 16 +#define UART0_IR_MIN_RCV_PULSE_WDTH0_PMN_MASK ((u32)0X0000FFFFU) + +/** + * Register: UART0_IR_TRANSMITTED_PULSE_WDTH0 + */ +#define UART0_IR_TRANSMITTED_PULSE_WDTH0 ( ( UART0_BASEADDR ) + ((u32)0X00000040U) ) + +#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_SHIFT 0 +#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_WIDTH 8 +#define UART0_IR_TRANSMITTED_PULSE_WDTH0_PWID_MASK ((u32)0X000000FFU) + +/** + * Register: UART0_TX_FIFO_TRIGGER_LEVEL0 + */ +#define UART0_TX_FIFO_TRIGGER_LEVEL0 ( ( UART0_BASEADDR ) + ((u32)0X00000044U) ) + +#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_SHIFT 0 +#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_WIDTH 6 +#define UART0_TX_FIFO_TRIGGER_LEVEL0_TTRIG_MASK ((u32)0X0000003FU) + +/** + * Register: UART0_RX_FIFO_BYTE_STATUS + */ +#define UART0_RX_FIFO_BYTE_STATUS ( ( UART0_BASEADDR ) + ((u32)0X00000048U) ) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_SHIFT 11 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_MASK ((u32)0X00000800U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_SHIFT 10 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_MASK ((u32)0X00000400U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_SHIFT 9 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_MASK ((u32)0X00000200U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_SHIFT 8 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_MASK ((u32)0X00000100U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_SHIFT 7 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_MASK ((u32)0X00000080U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_SHIFT 6 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_MASK ((u32)0X00000040U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_SHIFT 5 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_MASK ((u32)0X00000020U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_SHIFT 4 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_MASK ((u32)0X00000010U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_SHIFT 3 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_MASK ((u32)0X00000008U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_SHIFT 2 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_MASK ((u32)0X00000004U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_SHIFT 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_MASK ((u32)0X00000002U) + +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_SHIFT 0 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_WIDTH 1 +#define UART0_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _UART0_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/uart1.h b/lib/sw_apps/zynqmp_pmufw/src/uart1.h new file mode 100644 index 00000000..55e26889 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/uart1.h @@ -0,0 +1,633 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef _UART1_H_ +#define _UART1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * UART1 Base Address + */ +#define UART1_BASEADDR ((u32)0XFF010000U) + +/** + * Register: UART1_CONTROL_REG0 + */ +#define UART1_CONTROL_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000000U) ) + +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_WIDTH 1 +#define UART1_CONTROL_REG0_STPBRK_MASK ((u32)0X00000100U) + +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_WIDTH 1 +#define UART1_CONTROL_REG0_STTBRK_MASK ((u32)0X00000080U) + +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_WIDTH 1 +#define UART1_CONTROL_REG0_RSTTO_MASK ((u32)0X00000040U) + +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_WIDTH 1 +#define UART1_CONTROL_REG0_TXDIS_MASK ((u32)0X00000020U) + +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_WIDTH 1 +#define UART1_CONTROL_REG0_TXEN_MASK ((u32)0X00000010U) + +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_WIDTH 1 +#define UART1_CONTROL_REG0_RXDIS_MASK ((u32)0X00000008U) + +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_WIDTH 1 +#define UART1_CONTROL_REG0_RXEN_MASK ((u32)0X00000004U) + +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_WIDTH 1 +#define UART1_CONTROL_REG0_TXRES_MASK ((u32)0X00000002U) + +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_WIDTH 1 +#define UART1_CONTROL_REG0_RXRES_MASK ((u32)0X00000001U) + +/** + * Register: UART1_MODE_REG0 + */ +#define UART1_MODE_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000004U) ) + +#define UART1_MODE_REG0_WSIZE_SHIFT 12 +#define UART1_MODE_REG0_WSIZE_WIDTH 2 +#define UART1_MODE_REG0_WSIZE_MASK ((u32)0X00003000U) + +#define UART1_MODE_REG0_IRMODE_SHIFT 11 +#define UART1_MODE_REG0_IRMODE_WIDTH 1 +#define UART1_MODE_REG0_IRMODE_MASK ((u32)0X00000800U) + +#define UART1_MODE_REG0_UCLKEN_SHIFT 10 +#define UART1_MODE_REG0_UCLKEN_WIDTH 1 +#define UART1_MODE_REG0_UCLKEN_MASK ((u32)0X00000400U) + +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_WIDTH 2 +#define UART1_MODE_REG0_CHMODE_MASK ((u32)0X00000300U) + +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_WIDTH 2 +#define UART1_MODE_REG0_NBSTOP_MASK ((u32)0X000000C0U) + +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_WIDTH 3 +#define UART1_MODE_REG0_PAR_MASK ((u32)0X00000038U) + +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_WIDTH 2 +#define UART1_MODE_REG0_CHRL_MASK ((u32)0X00000006U) + +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_WIDTH 1 +#define UART1_MODE_REG0_CLKS_MASK ((u32)0X00000001U) + +/** + * Register: UART1_INTRPT_EN_REG0 + */ +#define UART1_INTRPT_EN_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000008U) ) + +#define UART1_INTRPT_EN_REG0_RBRK_SHIFT 13 +#define UART1_INTRPT_EN_REG0_RBRK_WIDTH 1 +#define UART1_INTRPT_EN_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART1_INTRPT_EN_REG0_TOVR_SHIFT 12 +#define UART1_INTRPT_EN_REG0_TOVR_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART1_INTRPT_EN_REG0_TNFUL_SHIFT 11 +#define UART1_INTRPT_EN_REG0_TNFUL_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART1_INTRPT_EN_REG0_TTRIG_SHIFT 10 +#define UART1_INTRPT_EN_REG0_TTRIG_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART1_INTRPT_EN_REG0_DMSI_SHIFT 9 +#define UART1_INTRPT_EN_REG0_DMSI_WIDTH 1 +#define UART1_INTRPT_EN_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART1_INTRPT_EN_REG0_TIMEOUT_SHIFT 8 +#define UART1_INTRPT_EN_REG0_TIMEOUT_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART1_INTRPT_EN_REG0_PARE_SHIFT 7 +#define UART1_INTRPT_EN_REG0_PARE_WIDTH 1 +#define UART1_INTRPT_EN_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART1_INTRPT_EN_REG0_FRAME_SHIFT 6 +#define UART1_INTRPT_EN_REG0_FRAME_WIDTH 1 +#define UART1_INTRPT_EN_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART1_INTRPT_EN_REG0_ROVR_SHIFT 5 +#define UART1_INTRPT_EN_REG0_ROVR_WIDTH 1 +#define UART1_INTRPT_EN_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART1_INTRPT_EN_REG0_TFUL_SHIFT 4 +#define UART1_INTRPT_EN_REG0_TFUL_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART1_INTRPT_EN_REG0_TEMPTY_SHIFT 3 +#define UART1_INTRPT_EN_REG0_TEMPTY_WIDTH 1 +#define UART1_INTRPT_EN_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART1_INTRPT_EN_REG0_RFUL_SHIFT 2 +#define UART1_INTRPT_EN_REG0_RFUL_WIDTH 1 +#define UART1_INTRPT_EN_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART1_INTRPT_EN_REG0_REMPTY_SHIFT 1 +#define UART1_INTRPT_EN_REG0_REMPTY_WIDTH 1 +#define UART1_INTRPT_EN_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART1_INTRPT_EN_REG0_RTRIG_SHIFT 0 +#define UART1_INTRPT_EN_REG0_RTRIG_WIDTH 1 +#define UART1_INTRPT_EN_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART1_INTRPT_DIS_REG0 + */ +#define UART1_INTRPT_DIS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000000CU) ) + +#define UART1_INTRPT_DIS_REG0_RBRK_SHIFT 13 +#define UART1_INTRPT_DIS_REG0_RBRK_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART1_INTRPT_DIS_REG0_TOVR_SHIFT 12 +#define UART1_INTRPT_DIS_REG0_TOVR_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART1_INTRPT_DIS_REG0_TNFUL_SHIFT 11 +#define UART1_INTRPT_DIS_REG0_TNFUL_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART1_INTRPT_DIS_REG0_TTRIG_SHIFT 10 +#define UART1_INTRPT_DIS_REG0_TTRIG_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART1_INTRPT_DIS_REG0_DMSI_SHIFT 9 +#define UART1_INTRPT_DIS_REG0_DMSI_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART1_INTRPT_DIS_REG0_TIMEOUT_SHIFT 8 +#define UART1_INTRPT_DIS_REG0_TIMEOUT_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART1_INTRPT_DIS_REG0_PARE_SHIFT 7 +#define UART1_INTRPT_DIS_REG0_PARE_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART1_INTRPT_DIS_REG0_FRAME_SHIFT 6 +#define UART1_INTRPT_DIS_REG0_FRAME_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART1_INTRPT_DIS_REG0_ROVR_SHIFT 5 +#define UART1_INTRPT_DIS_REG0_ROVR_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART1_INTRPT_DIS_REG0_TFUL_SHIFT 4 +#define UART1_INTRPT_DIS_REG0_TFUL_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART1_INTRPT_DIS_REG0_TEMPTY_SHIFT 3 +#define UART1_INTRPT_DIS_REG0_TEMPTY_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART1_INTRPT_DIS_REG0_RFUL_SHIFT 2 +#define UART1_INTRPT_DIS_REG0_RFUL_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART1_INTRPT_DIS_REG0_REMPTY_SHIFT 1 +#define UART1_INTRPT_DIS_REG0_REMPTY_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART1_INTRPT_DIS_REG0_RTRIG_SHIFT 0 +#define UART1_INTRPT_DIS_REG0_RTRIG_WIDTH 1 +#define UART1_INTRPT_DIS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART1_INTRPT_MASK_REG0 + */ +#define UART1_INTRPT_MASK_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000010U) ) + +#define UART1_INTRPT_MASK_REG0_RBRK_SHIFT 13 +#define UART1_INTRPT_MASK_REG0_RBRK_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART1_INTRPT_MASK_REG0_TOVR_SHIFT 12 +#define UART1_INTRPT_MASK_REG0_TOVR_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART1_INTRPT_MASK_REG0_TNFUL_SHIFT 11 +#define UART1_INTRPT_MASK_REG0_TNFUL_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART1_INTRPT_MASK_REG0_TTRIG_SHIFT 10 +#define UART1_INTRPT_MASK_REG0_TTRIG_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART1_INTRPT_MASK_REG0_DMSI_SHIFT 9 +#define UART1_INTRPT_MASK_REG0_DMSI_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART1_INTRPT_MASK_REG0_TIMEOUT_SHIFT 8 +#define UART1_INTRPT_MASK_REG0_TIMEOUT_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART1_INTRPT_MASK_REG0_PARE_SHIFT 7 +#define UART1_INTRPT_MASK_REG0_PARE_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART1_INTRPT_MASK_REG0_FRAME_SHIFT 6 +#define UART1_INTRPT_MASK_REG0_FRAME_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART1_INTRPT_MASK_REG0_ROVR_SHIFT 5 +#define UART1_INTRPT_MASK_REG0_ROVR_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART1_INTRPT_MASK_REG0_TFUL_SHIFT 4 +#define UART1_INTRPT_MASK_REG0_TFUL_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART1_INTRPT_MASK_REG0_TEMPTY_SHIFT 3 +#define UART1_INTRPT_MASK_REG0_TEMPTY_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART1_INTRPT_MASK_REG0_RFUL_SHIFT 2 +#define UART1_INTRPT_MASK_REG0_RFUL_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART1_INTRPT_MASK_REG0_REMPTY_SHIFT 1 +#define UART1_INTRPT_MASK_REG0_REMPTY_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART1_INTRPT_MASK_REG0_RTRIG_SHIFT 0 +#define UART1_INTRPT_MASK_REG0_RTRIG_WIDTH 1 +#define UART1_INTRPT_MASK_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART1_CHNL_INT_STS_REG0 + */ +#define UART1_CHNL_INT_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000014U) ) + +#define UART1_CHNL_INT_STS_REG0_RBRK_SHIFT 13 +#define UART1_CHNL_INT_STS_REG0_RBRK_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_RBRK_MASK ((u32)0X00002000U) + +#define UART1_CHNL_INT_STS_REG0_TOVR_SHIFT 12 +#define UART1_CHNL_INT_STS_REG0_TOVR_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TOVR_MASK ((u32)0X00001000U) + +#define UART1_CHNL_INT_STS_REG0_TNFUL_SHIFT 11 +#define UART1_CHNL_INT_STS_REG0_TNFUL_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TNFUL_MASK ((u32)0X00000800U) + +#define UART1_CHNL_INT_STS_REG0_TTRIG_SHIFT 10 +#define UART1_CHNL_INT_STS_REG0_TTRIG_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TTRIG_MASK ((u32)0X00000400U) + +#define UART1_CHNL_INT_STS_REG0_DMSI_SHIFT 9 +#define UART1_CHNL_INT_STS_REG0_DMSI_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART1_CHNL_INT_STS_REG0_TIMEOUT_SHIFT 8 +#define UART1_CHNL_INT_STS_REG0_TIMEOUT_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART1_CHNL_INT_STS_REG0_PARE_SHIFT 7 +#define UART1_CHNL_INT_STS_REG0_PARE_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART1_CHNL_INT_STS_REG0_FRAME_SHIFT 6 +#define UART1_CHNL_INT_STS_REG0_FRAME_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART1_CHNL_INT_STS_REG0_ROVR_SHIFT 5 +#define UART1_CHNL_INT_STS_REG0_ROVR_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART1_CHNL_INT_STS_REG0_TFUL_SHIFT 4 +#define UART1_CHNL_INT_STS_REG0_TFUL_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART1_CHNL_INT_STS_REG0_TEMPTY_SHIFT 3 +#define UART1_CHNL_INT_STS_REG0_TEMPTY_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART1_CHNL_INT_STS_REG0_RFUL_SHIFT 2 +#define UART1_CHNL_INT_STS_REG0_RFUL_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART1_CHNL_INT_STS_REG0_REMPTY_SHIFT 1 +#define UART1_CHNL_INT_STS_REG0_REMPTY_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART1_CHNL_INT_STS_REG0_RTRIG_SHIFT 0 +#define UART1_CHNL_INT_STS_REG0_RTRIG_WIDTH 1 +#define UART1_CHNL_INT_STS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART1_BAUD_RATE_GEN_REG0 + */ +#define UART1_BAUD_RATE_GEN_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000018U) ) + +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_WIDTH 16 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK ((u32)0X0000FFFFU) + +/** + * Register: UART1_RCVR_TIMEOUT_REG0 + */ +#define UART1_RCVR_TIMEOUT_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000001CU) ) + +#define UART1_RCVR_TIMEOUT_REG0_RTO_SHIFT 0 +#define UART1_RCVR_TIMEOUT_REG0_RTO_WIDTH 8 +#define UART1_RCVR_TIMEOUT_REG0_RTO_MASK ((u32)0X000000FFU) + +/** + * Register: UART1_RCVR_FIFO_TRIGGER_LEVEL0 + */ +#define UART1_RCVR_FIFO_TRIGGER_LEVEL0 ( ( UART1_BASEADDR ) + ((u32)0X00000020U) ) + +#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_SHIFT 0 +#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_WIDTH 6 +#define UART1_RCVR_FIFO_TRIGGER_LEVEL0_RTRIG_MASK ((u32)0X0000003FU) + +/** + * Register: UART1_MODEM_CTRL_REG0 + */ +#define UART1_MODEM_CTRL_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000024U) ) + +#define UART1_MODEM_CTRL_REG0_FCM_SHIFT 5 +#define UART1_MODEM_CTRL_REG0_FCM_WIDTH 1 +#define UART1_MODEM_CTRL_REG0_FCM_MASK ((u32)0X00000020U) + +#define UART1_MODEM_CTRL_REG0_RTS_SHIFT 1 +#define UART1_MODEM_CTRL_REG0_RTS_WIDTH 1 +#define UART1_MODEM_CTRL_REG0_RTS_MASK ((u32)0X00000002U) + +#define UART1_MODEM_CTRL_REG0_DTR_SHIFT 0 +#define UART1_MODEM_CTRL_REG0_DTR_WIDTH 1 +#define UART1_MODEM_CTRL_REG0_DTR_MASK ((u32)0X00000001U) + +/** + * Register: UART1_MODEM_STS_REG0 + */ +#define UART1_MODEM_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000028U) ) + +#define UART1_MODEM_STS_REG0_FCMS_SHIFT 8 +#define UART1_MODEM_STS_REG0_FCMS_WIDTH 1 +#define UART1_MODEM_STS_REG0_FCMS_MASK ((u32)0X00000100U) + +#define UART1_MODEM_STS_REG0_DCD_SHIFT 7 +#define UART1_MODEM_STS_REG0_DCD_WIDTH 1 +#define UART1_MODEM_STS_REG0_DCD_MASK ((u32)0X00000080U) + +#define UART1_MODEM_STS_REG0_RI_SHIFT 6 +#define UART1_MODEM_STS_REG0_RI_WIDTH 1 +#define UART1_MODEM_STS_REG0_RI_MASK ((u32)0X00000040U) + +#define UART1_MODEM_STS_REG0_DSR_SHIFT 5 +#define UART1_MODEM_STS_REG0_DSR_WIDTH 1 +#define UART1_MODEM_STS_REG0_DSR_MASK ((u32)0X00000020U) + +#define UART1_MODEM_STS_REG0_CTS_SHIFT 4 +#define UART1_MODEM_STS_REG0_CTS_WIDTH 1 +#define UART1_MODEM_STS_REG0_CTS_MASK ((u32)0X00000010U) + +#define UART1_MODEM_STS_REG0_DDCD_SHIFT 3 +#define UART1_MODEM_STS_REG0_DDCD_WIDTH 1 +#define UART1_MODEM_STS_REG0_DDCD_MASK ((u32)0X00000008U) + +#define UART1_MODEM_STS_REG0_TERI_SHIFT 2 +#define UART1_MODEM_STS_REG0_TERI_WIDTH 1 +#define UART1_MODEM_STS_REG0_TERI_MASK ((u32)0X00000004U) + +#define UART1_MODEM_STS_REG0_DDSR_SHIFT 1 +#define UART1_MODEM_STS_REG0_DDSR_WIDTH 1 +#define UART1_MODEM_STS_REG0_DDSR_MASK ((u32)0X00000002U) + +#define UART1_MODEM_STS_REG0_DCTS_SHIFT 0 +#define UART1_MODEM_STS_REG0_DCTS_WIDTH 1 +#define UART1_MODEM_STS_REG0_DCTS_MASK ((u32)0X00000001U) + +/** + * Register: UART1_CHANNEL_STS_REG0 + */ +#define UART1_CHANNEL_STS_REG0 ( ( UART1_BASEADDR ) + ((u32)0X0000002CU) ) + +#define UART1_CHANNEL_STS_REG0_RBRK_SHIFT 15 +#define UART1_CHANNEL_STS_REG0_RBRK_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_RBRK_MASK ((u32)0X00008000U) + +#define UART1_CHANNEL_STS_REG0_TNFUL_SHIFT 14 +#define UART1_CHANNEL_STS_REG0_TNFUL_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TNFUL_MASK ((u32)0X00004000U) + +#define UART1_CHANNEL_STS_REG0_TTRIG_SHIFT 13 +#define UART1_CHANNEL_STS_REG0_TTRIG_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TTRIG_MASK ((u32)0X00002000U) + +#define UART1_CHANNEL_STS_REG0_FDELT_SHIFT 12 +#define UART1_CHANNEL_STS_REG0_FDELT_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_FDELT_MASK ((u32)0X00001000U) + +#define UART1_CHANNEL_STS_REG0_TACTIVE_SHIFT 11 +#define UART1_CHANNEL_STS_REG0_TACTIVE_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TACTIVE_MASK ((u32)0X00000800U) + +#define UART1_CHANNEL_STS_REG0_RACTIVE_SHIFT 10 +#define UART1_CHANNEL_STS_REG0_RACTIVE_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_RACTIVE_MASK ((u32)0X00000400U) + +#define UART1_CHANNEL_STS_REG0_DMSI_SHIFT 9 +#define UART1_CHANNEL_STS_REG0_DMSI_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_DMSI_MASK ((u32)0X00000200U) + +#define UART1_CHANNEL_STS_REG0_TIMEOUT_SHIFT 8 +#define UART1_CHANNEL_STS_REG0_TIMEOUT_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TIMEOUT_MASK ((u32)0X00000100U) + +#define UART1_CHANNEL_STS_REG0_PARE_SHIFT 7 +#define UART1_CHANNEL_STS_REG0_PARE_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_PARE_MASK ((u32)0X00000080U) + +#define UART1_CHANNEL_STS_REG0_FRAME_SHIFT 6 +#define UART1_CHANNEL_STS_REG0_FRAME_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_FRAME_MASK ((u32)0X00000040U) + +#define UART1_CHANNEL_STS_REG0_ROVR_SHIFT 5 +#define UART1_CHANNEL_STS_REG0_ROVR_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_ROVR_MASK ((u32)0X00000020U) + +#define UART1_CHANNEL_STS_REG0_TFUL_SHIFT 4 +#define UART1_CHANNEL_STS_REG0_TFUL_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TFUL_MASK ((u32)0X00000010U) + +#define UART1_CHANNEL_STS_REG0_TEMPTY_SHIFT 3 +#define UART1_CHANNEL_STS_REG0_TEMPTY_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_TEMPTY_MASK ((u32)0X00000008U) + +#define UART1_CHANNEL_STS_REG0_RFUL_SHIFT 2 +#define UART1_CHANNEL_STS_REG0_RFUL_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_RFUL_MASK ((u32)0X00000004U) + +#define UART1_CHANNEL_STS_REG0_REMPTY_SHIFT 1 +#define UART1_CHANNEL_STS_REG0_REMPTY_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_REMPTY_MASK ((u32)0X00000002U) + +#define UART1_CHANNEL_STS_REG0_RTRIG_SHIFT 0 +#define UART1_CHANNEL_STS_REG0_RTRIG_WIDTH 1 +#define UART1_CHANNEL_STS_REG0_RTRIG_MASK ((u32)0X00000001U) + +/** + * Register: UART1_TX_RX_FIFO0 + */ +#define UART1_TX_RX_FIFO0 ( ( UART1_BASEADDR ) + ((u32)0X00000030U) ) + +#define UART1_TX_RX_FIFO0_FIFO_SHIFT 0 +#define UART1_TX_RX_FIFO0_FIFO_WIDTH 8 +#define UART1_TX_RX_FIFO0_FIFO_MASK ((u32)0X000000FFU) + +/** + * Register: UART1_BAUD_RATE_DIVIDER_REG0 + */ +#define UART1_BAUD_RATE_DIVIDER_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000034U) ) + +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_WIDTH 8 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK ((u32)0X000000FFU) + +/** + * Register: UART1_FLOW_DELAY_REG0 + */ +#define UART1_FLOW_DELAY_REG0 ( ( UART1_BASEADDR ) + ((u32)0X00000038U) ) + +#define UART1_FLOW_DELAY_REG0_FDEL_SHIFT 0 +#define UART1_FLOW_DELAY_REG0_FDEL_WIDTH 6 +#define UART1_FLOW_DELAY_REG0_FDEL_MASK ((u32)0X0000003FU) + +/** + * Register: UART1_IR_MIN_RCV_PULSE_WDTH0 + */ +#define UART1_IR_MIN_RCV_PULSE_WDTH0 ( ( UART1_BASEADDR ) + ((u32)0X0000003CU) ) + +#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_SHIFT 0 +#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_WIDTH 16 +#define UART1_IR_MIN_RCV_PULSE_WDTH0_PMN_MASK ((u32)0X0000FFFFU) + +/** + * Register: UART1_IR_TRANSMITTED_PULSE_WDTH0 + */ +#define UART1_IR_TRANSMITTED_PULSE_WDTH0 ( ( UART1_BASEADDR ) + ((u32)0X00000040U) ) + +#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_SHIFT 0 +#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_WIDTH 8 +#define UART1_IR_TRANSMITTED_PULSE_WDTH0_PWID_MASK ((u32)0X000000FFU) + +/** + * Register: UART1_TX_FIFO_TRIGGER_LEVEL0 + */ +#define UART1_TX_FIFO_TRIGGER_LEVEL0 ( ( UART1_BASEADDR ) + ((u32)0X00000044U) ) + +#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_SHIFT 0 +#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_WIDTH 6 +#define UART1_TX_FIFO_TRIGGER_LEVEL0_TTRIG_MASK ((u32)0X0000003FU) + +/** + * Register: UART1_RX_FIFO_BYTE_STATUS + */ +#define UART1_RX_FIFO_BYTE_STATUS ( ( UART1_BASEADDR ) + ((u32)0X00000048U) ) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_SHIFT 11 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_BREAK_MASK ((u32)0X00000800U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_SHIFT 10 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_FRM_ERR_MASK ((u32)0X00000400U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_SHIFT 9 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE3_PAR_ERR_MASK ((u32)0X00000200U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_SHIFT 8 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_BREAK_MASK ((u32)0X00000100U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_SHIFT 7 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_FRM_ERR_MASK ((u32)0X00000080U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_SHIFT 6 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE2_PAR_ERR_MASK ((u32)0X00000040U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_SHIFT 5 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_BREAK_MASK ((u32)0X00000020U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_SHIFT 4 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_FRM_ERR_MASK ((u32)0X00000010U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_SHIFT 3 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE1_PAR_ERR_MASK ((u32)0X00000008U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_SHIFT 2 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_BREAK_MASK ((u32)0X00000004U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_SHIFT 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_FRM_ERR_MASK ((u32)0X00000002U) + +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_SHIFT 0 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_WIDTH 1 +#define UART1_RX_FIFO_BYTE_STATUS_BYTE0_PAR_ERR_MASK ((u32)0X00000001U) + +#ifdef __cplusplus +} +#endif + + +#endif /* _UART1_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_codes.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_codes.h new file mode 100644 index 00000000..2d7f2c6c --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_codes.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_CODES_H_ +#define XPFW_CODES_H_ +/*FIXME: Use Xilinx BSP Codes */ +#define XPFW_STATUS_SUCCESS 0x00000000U +#define XPFW_STATUS_FAIL 0x00000001U +#define XPFW_STATUS_PWRDN_DONE 0x00000002U +#define XPFW_STATUS_PENDING 0x00000003U +#define XPFW_STATUS_PWRUP_DONE 0x00000004U +#define XPFW_STATUS_ACCESS_DENIED 0x00000005U +#define XPFW_STATUS_INVALID_MSG 0x00000006U +#define XPFW_STATUS_INVALID_ACTION 0x00000007U +#define XPFW_STATUS_CURSTATE 0x00000008U + +#endif /* XPFW_CODES_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_config.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_config.h new file mode 100644 index 00000000..ffa885f8 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_config.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_CONFIG_H_ +#define XPFW_CONFIG_H_ + +/************* User Configurable Options ***************/ +/* Define DEBUG_MODE to enable debug prints on PS_UART */ +#define DEBUG_MODE + +/* Let the MB sleep when it is Idle in Main Loop */ +#define SLEEP_WHEN_IDLE + +#ifndef ZYNQMP_XPFW_VERSION +#define ZYNQMP_XPFW_VERSION "--LOCAL COPY--" +#endif +/* Directs the PMU FW to configure UART */ +#define CONFIG_UART + +/* Enable Power Management Module */ +#define ENABLE_PM + +/* + * Disable all other mods + * User can enable Each of the Optional Modules if required + */ +#undef ENABLE_RTC_TEST +#undef ENABLE_EM +#undef ENABLE_SCHEDULER + + +#endif /* XPFW_CONFIG_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c new file mode 100644 index 00000000..284acbe0 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.c @@ -0,0 +1,359 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_default.h" +#include "xpfw_core.h" +#include "xpfw_events.h" +#include "xpfw_interrupts.h" + +#define CORE_IS_READY ((u32)0x5AFEC0DEU) +#define CORE_IS_DEAD ((u32)0xDEADBEAFU) + +static XPfw_Core_t XPfwCore = { .IsReady = CORE_IS_DEAD }; + +/* Declare the Core Pointer as constant, since we don't intend to change it */ +static XPfw_Core_t * const CorePtr = &XPfwCore; + +XStatus XPfw_CoreInit(u32 Options) +{ + u32 Index; + XStatus Status; + if (CorePtr != NULL) { + + XPfw_InterruptInit(); + + + CorePtr->ModCount = (u8)0U; + + for (Index = 0U; Index < ARRAYSIZE(CorePtr->ModList); Index++) { + Status = XPfw_ModuleInit(&CorePtr->ModList[Index], (u8) 0U); + /* If there was an error, then just get out of here */ + if (XST_SUCCESS != Status) { + break; + } + } + /* Got to Scheduler Init only if we were able to init the Mods */ + if (XST_SUCCESS == Status) { + Status = XPfw_SchedulerInit(&CorePtr->Scheduler, + PMU_IOMODULE_PIT1_PRELOAD); + } + + } else { + Status = XST_FAILURE; + } + return Status; +} + +XStatus XPfw_CoreConfigure(void) +{ + u32 Idx; + XStatus Status; + + if (CorePtr != NULL) { + for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) { + + if (CorePtr->ModList[Idx].CfgInitHandler != NULL) { + /* TODO: Pass on configure data based on module type */ + CorePtr->ModList[Idx].CfgInitHandler(&CorePtr->ModList[Idx], + NULL, 0U); + } + } + + /* We are ready to take interrupts now */ + CorePtr->IsReady = CORE_IS_READY; + /* FIXME: Enable IPI0 for PM-> Do it elsewhere */ + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_IPI0_MASK); + XPfw_InterruptStart(); + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + return Status; +} + +XStatus XPfw_CoreDispatchEvent(u32 EventId) +{ + XStatus Status; + u32 Idx; + u32 CallCount = 0U; + if ((CorePtr != NULL) && (EventId < XPFW_EV_MAX)) { + + for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) { + /** + * Check if Mod[Idx] is registered for this event + */ + if ((XPfw_EventGetModMask(EventId) & ((u32) 1U << Idx)) + == ((u32) 1U << Idx)) { + CorePtr->ModList[Idx].EventHandler(&CorePtr->ModList[Idx], + EventId); + CallCount++; + } + } + } + /* fw_printf("%s: Event(%d) dispatched to %d Mods\r\n", __func__, EventId,CallCount); */ + if (CallCount > 0U) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + return Status; +} + +/* + * FIXME: After Integrating IPI Driver, redesign to + * dispatch events based on IPI_ID (first word in msg buffer) Mask + * + */ +XStatus XPfw_CoreDispatchIpi(u32 IpiNum) +{ + XStatus Status; + u32 Idx; + u32 CallCount = 0U; + + if ((CorePtr != NULL) && (IpiNum < 4U)) { + for (Idx = 0U; Idx < CorePtr->ModCount; Idx++) { + /** + * TODO: Check if Mod[Idx] is registered for this Ipi + * TODO: What if it is registered , but Handler is NULL. Report it! + */ + if (NULL != CorePtr->ModList[Idx].IpiHandler) { + CorePtr->ModList[Idx].IpiHandler(&CorePtr->ModList[Idx], IpiNum, + 0U); + CallCount++; + } + } + } + /* fw_printf("%s: IPI-%d dispatched to %d Mods\r\n", __func__, IpiNum, + CallCount); */ + if (CallCount > 0U) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + return Status; +} + + +const XPfw_Module_t *XPfw_CoreCreateMod(void) +{ + const XPfw_Module_t *ModPtr; + + if (CorePtr != NULL) { + if (CorePtr->ModCount < XPFW_MAX_MOD_COUNT) { + CorePtr->ModList[CorePtr->ModCount].ModId = CorePtr->ModCount; + ModPtr = &CorePtr->ModList[CorePtr->ModCount]; + CorePtr->ModCount++; + } else { + ModPtr = NULL; + } + } else { + ModPtr = NULL; + } + + return ModPtr; +} + +XStatus XPfw_CoreScheduleTask(const XPfw_Module_t *ModPtr, u32 Interval, + VoidFunction_t CallbackRef) +{ + XStatus Status; + + if ((ModPtr != NULL) && (CorePtr != NULL)) { + Status = XPfw_SchedulerAddTask(&CorePtr->Scheduler, ModPtr->ModId, + Interval, CallbackRef); + } else { + Status = XST_FAILURE; + } + + return Status; +} + +void XPfw_CoreTickHandler(void) +{ + if(CorePtr != NULL){ + XPfw_SchedulerTickHandler(&CorePtr->Scheduler); + } + else { + fw_printf("ERROR: NULL pointer to Core\r\n"); + } +} + +XStatus XPfw_CoreIsReady(void) +{ + XStatus Status; + + if (CorePtr != NULL) { + if (CORE_IS_READY == CorePtr->IsReady) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + } else { + Status = XST_FAILURE; + } + + return Status; +} + +XStatus XPfw_CoreLoop(void) +{ + + if(CORE_IS_READY == CorePtr->IsReady) + { + + #ifdef ENABLE_SCHEDULER + XPfw_SchedulerStart(&CorePtr->Scheduler); + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK); + #endif + do { + + #ifdef SLEEP_WHEN_IDLE + /*Sleep. Will be waken up when a interrupt occurs*/ + mb_sleep(); + #endif + + #ifdef ENABLE_SCHEDULER + if(TRUE == CorePtr->Scheduler.Enabled){ + (void)XPfw_SchedulerProcess(&CorePtr->Scheduler); + } + #endif + + } while (1); + + } + /* If we reach this point then there was an error */ + return (XStatus)XST_FAILURE; +} + + +void XPfw_CorePrintStats(void) +{ + if(CorePtr != NULL) { + fw_printf("######################################################\r\n"); + fw_printf("Module Count: %d (%d)\r\n", CorePtr->ModCount, XPFW_MAX_MOD_COUNT); + fw_printf("Scheduler State: %s\r\n",((CorePtr->Scheduler.Enabled == TRUE)?"ENABLED":"DISABLED")); + fw_printf("Scheduler Ticks: %d\r\n",CorePtr->Scheduler.Tick); + fw_printf("######################################################\r\n"); + } +} + + +XStatus XPfw_CoreRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId) +{ + XStatus Status; + + if (NULL == ModPtr) { + Status = XST_FAILURE; + } else { + Status = XPfw_EventAddOwner(ModPtr->ModId, EventId); + } + return Status; +} + +XStatus XPfw_CoreDeRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId) +{ + XStatus Status; + + if (NULL == ModPtr) { + Status = XST_FAILURE; + } else { + Status = XPfw_EventRemoveOwner(ModPtr->ModId, EventId); + } + return Status; +} + +XStatus XPfw_CoreStopScheduler(void) +{ + XStatus Status; + if(CorePtr != NULL) { + Status = XPfw_SchedulerStop(&CorePtr->Scheduler); + XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_PIT1_MASK); + } else { + Status = XST_FAILURE; + } + + return Status; +} + +XStatus XPfw_CoreSetCfgHandler(const XPfw_Module_t *ModPtr, XPfwModCfgInitHandler_t CfgHandler) +{ + XStatus Status; + if ((ModPtr != NULL) && (CorePtr != NULL)) { + if (ModPtr->ModId < CorePtr->ModCount) { + CorePtr->ModList[ModPtr->ModId].CfgInitHandler = CfgHandler; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + } else { + Status = XST_FAILURE; + } + + return Status; +} + +XStatus XPfw_CoreSetEventHandler(const XPfw_Module_t *ModPtr, XPfwModEventHandler_t EventHandlerFn) +{ + XStatus Status; + if ((ModPtr != NULL) && (CorePtr != NULL)) { + if (ModPtr->ModId < CorePtr->ModCount) { + CorePtr->ModList[ModPtr->ModId].EventHandler = EventHandlerFn; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + } else { + Status = XST_FAILURE; + } + + return Status; +} + + +XStatus XPfw_CoreSetIpiHandler(const XPfw_Module_t *ModPtr, XPfwModIpiHandler_t IpiHandlerFn, u32 IpiId) +{ + XStatus Status; + if ((ModPtr != NULL) && (CorePtr != NULL)) { + if (ModPtr->ModId < CorePtr->ModCount) { + CorePtr->ModList[ModPtr->ModId].IpiHandler = IpiHandlerFn; + CorePtr->ModList[ModPtr->ModId].IpiId = IpiId; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + } else { + Status = XST_FAILURE; + } + + return Status; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.h new file mode 100644 index 00000000..118b232d --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_core.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_CORE_H_ +#define XPFW_CORE_H_ + + +#include "xpfw_module.h" +#include "xpfw_scheduler.h" + +#define XPFW_MAX_MOD_COUNT 4U + +#define XPFW_CORE_ERR_TASK_MISS +#define XPFW_CORe_ERR_TASK_NULL + + +typedef struct { + XPfw_Module_t ModList[XPFW_MAX_MOD_COUNT]; + XPfw_Scheduler_t Scheduler; + u8 ModCount; + u32 IsReady; + u8 Mode; /**< Mode - Safety Diagnostics Mode / Normal Mode */ +} XPfw_Core_t; + +XStatus XPfw_CoreInit(u32 Options); +XStatus XPfw_CoreConfigure(void); +XStatus XPfw_CoreDispatchEvent( u32 EventId); +const XPfw_Module_t *XPfw_CoreCreateMod(void); +XStatus XPfw_CoreScheduleTask(const XPfw_Module_t *ModPtr, u32 Interval, VoidFunction_t CallbackRef); +XStatus XPfw_CoreStopScheduler(void); +XStatus XPfw_CoreLoop(void); +void XPfw_CorePrintStats(void); +XStatus XPfw_CoreRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId); +XStatus XPfw_CoreDeRegisterEvent(const XPfw_Module_t *ModPtr, u32 EventId); + +XStatus XPfw_CoreDispatchIpi(u32 IpiNum); + +void XPfw_CoreTickHandler(void); +XStatus XPfw_CoreIsReady(void); + +XStatus XPfw_CoreSetCfgHandler(const XPfw_Module_t *ModPtr, XPfwModCfgInitHandler_t CfgHandler); +XStatus XPfw_CoreSetEventHandler(const XPfw_Module_t *ModPtr, XPfwModEventHandler_t EventHandler); +XStatus XPfw_CoreSetIpiHandler(const XPfw_Module_t *ModPtr, XPfwModIpiHandler_t IpiHandler, u32 IpiId); + + +#endif /* XPFW_CORE_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_default.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_default.h new file mode 100644 index 00000000..00f8d9d0 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_default.h @@ -0,0 +1,112 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef XPFW_DEFAULT_H_ +#define XPFW_DEFAULT_H_ + + +#include "xpfw_config.h" +#include "xpfw_codes.h" +#include "xpfw_util.h" + +/* BSP Headers */ +#include "xil_io.h" +#include "xil_types.h" +#include "mb_interface.h" +#include "xstatus.h" +/* REGDB Headers */ +#include "pmu_local.h" +#include "pmu_iomodule.h" +#include "pmu_global.h" +#include "ipi.h" +#include "uart0.h" +#include "uart1.h" +#include "crl_apb.h" +#include "lpd_slcr.h" +#include "rtc.h" + + +/* RAM address used for scrubbing */ +#define PARAM_RAM_LOW_ADDRESS 0Xffdc0000U +#define PARAM_RAM_HIGH_ADDRESS 0Xffdcff00U + +/* RAM base address for general usage */ +#define PMU_RAM_BASE_ADDR 0Xffdc0000U + +/* Register Access Macros */ + +#define XPfw_Write32(Addr, Value) Xil_Out32((Addr), (Value)) + +#define XPfw_Read32(Addr) Xil_In32((Addr)) + +#define XPfw_RMW32 XPfw_UtilRMW + +#define ARRAYSIZE(x) (u32)(sizeof(x)/sizeof(x[0])) +/* Custom Flags */ + +#define MASK_ALL 0XffffffffU +#define ENABLE_ALL 0XffffffffU +#define ALL_HIGH 0XffffffffU +#define FLAG_ALL 0XffffffffU + + +#define MASK32_ALL_HIGH ((u32)0xFFFFFFFFU) +#define MASK32_ALL_LOW ((u32)0x0U) + + +#define YES 0x01U +#define NO 0x00U + + +#define XPFW_ACCESS_ALLOWED 0x01U +#define XPFW_ACCESS_DENIED 0x00U + +/* Handler Table Structure */ +typedef void (*VoidFunction_t)(void); +struct HandlerTable{ + u32 Mask; + VoidFunction_t Handler; +}; + + + +#ifdef DEBUG_MODE +#define fw_printf xil_printf +#define fw_print print +#else +#define fw_printf(MSG, ...) {} +#define fw_print(MSG) {} +#endif + + +#endif /* XPFW_DEFAULT_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.c new file mode 100644 index 00000000..de627cdd --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.c @@ -0,0 +1,261 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_default.h" +#include "xpfw_error_handler.h" +#include "xpfw_resets.h" + +#define ERROR_ONE_EN (PMU_GLOBAL_ERROR_INT_EN_1_DDR_ECC_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_OCM_ECC_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_RPU0_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_RPU1_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_LPD_TEMP_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_FPD_TEMP_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_RPU_LS_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_RPU_CCF_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_LPD_SWDT_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_FPD_SWDT_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_PWR_SUPPLY_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_1_XMPU_MASK) + +#define ERROR_TWO_EN (PMU_GLOBAL_ERROR_INT_EN_2_TO_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_PL_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_PLL_LOCK_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_CSU_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_PMU_UC_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_CSU_ROM_MASK) + +/*Not Enabled : PMU_GLOBAL_ERROR_INT_EN_2_PMU_FW_MASK |\ + PMU_GLOBAL_ERROR_INT_EN_2_PMU_SERVICE_MASK |\ + PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_MASK + */ + +void XPfw_ErrorHandlerInit(void) +{ + /* Enable All in Error-1 */ + XPfw_Write32(PMU_GLOBAL_ERROR_EN_1, ERROR_ONE_EN); + XPfw_Write32(PMU_GLOBAL_ERROR_INT_EN_1, ERROR_ONE_EN); + + /* PMU related errors are not enabled in Error-2*/ + XPfw_Write32(PMU_GLOBAL_ERROR_EN_2, ERROR_TWO_EN); + XPfw_Write32(PMU_GLOBAL_ERROR_INT_EN_2, ERROR_TWO_EN); + + + +} + + +void XPfw_ErrorHandlerOne(void) +{ + u32 l_ErrorOneReg; + + /* Latch the Error Flags */ + l_ErrorOneReg = XPfw_Read32(PMU_GLOBAL_ERROR_STATUS_1); + + /* Clear Error Register so that new errors can trigger an Interrupt */ + XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_1,l_ErrorOneReg); + + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_DDR_ECC_MASK) != 0x00000000U) { + XPfw_ErrorEccDdr(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_OCM_ECC_MASK) != 0x00000000U) { + XPfw_ErrorEccOcm(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_RPU0_MASK) != 0x00000000U) { + XPfw_ErrorRpu0(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_RPU1_MASK) != 0x00000000U) { + XPfw_ErrorRpu1(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_LPD_TEMP_MASK) != 0x00000000U) { + XPfw_ErrorLpdTemp(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_FPD_TEMP_MASK) != 0x00000000U) { + XPfw_ErrorFpdTemp(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_RPU_LS_MASK) != 0x00000000U) { + XPfw_ErrorRpuLockStep(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_RPU_CCF_MASK) != 0x00000000U) { + XPfw_ErrorRpuCcf(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_LPD_SWDT_MASK) != 0x00000000U) { + XPfw_ErrorLpdSwdt(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_FPD_SWDT_MASK) != 0x00000000U) { + XPfw_ErrorFpdSwdt(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_PWR_SUPPLY_MASK) != 0x00000000U) { + XPfw_ErrorPowerSupply(); + } + if( (l_ErrorOneReg & PMU_GLOBAL_ERROR_STATUS_1_XMPU_MASK) != 0x00000000U) { + XPfw_ErrorXmpu(); + } + + /* Clear Error Register so that new errors can trigger an Interrupt */ + + XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_1,l_ErrorOneReg); + +} + + +void XPfw_ErrorHandlerTwo(void) +{ + u32 l_ErrorTwoReg; + + /* Latch the Error Flags */ + l_ErrorTwoReg = XPfw_Read32(PMU_GLOBAL_ERROR_STATUS_2); + + /* Clear Error Register so that new errors can trigger an Interrupt */ + XPfw_Write32(PMU_GLOBAL_ERROR_STATUS_2,l_ErrorTwoReg); + + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_TO_MASK) != 0x00000000U) { + XPfw_ErrorTimeOut(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PL_MASK) != 0x00000000U) { + XPfw_ErrorPL(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK) != 0x00000000U) { + XPfw_ErrorPLL(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_CSU_MASK) != 0x00000000U) { + XPfw_ErrorCsu(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PMU_UC_MASK) != 0x00000000U) { + XPfw_ErrorPmuUncorrectable(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PMU_FW_MASK) != 0x00000000U) { + XPfw_ErrorPmuFw(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PMU_SERVICE_MASK) != 0x00000000U) { + XPfw_ErrorPmuServiceMode(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_PMU_PB_MASK) != 0x00000000U) { + XPfw_ErrorPmuPreBoot(); + } + if( (l_ErrorTwoReg & PMU_GLOBAL_ERROR_STATUS_2_CSU_ROM_MASK) != 0x00000000U) { + XPfw_ErrorCsuRom(); + } + + + + +} + + + + +void XPfw_ErrorEccDdr(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorEccOcm(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorRpu0(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorRpu1(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorLpdTemp(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorFpdTemp(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorRpuLockStep(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); + XPfw_ResetRpu(); +} + +void XPfw_ErrorRpuCcf(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorLpdSwdt(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorFpdSwdt(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPowerSupply(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorXmpu(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorTimeOut(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPL(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPLL(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorCsu(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPmuUncorrectable(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPmuFw(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPmuServiceMode(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} + +void XPfw_ErrorPmuPreBoot(void) +{ + fw_printf( " XPFW: Error Handler Triggered: %s\r\n " ,__func__); +} + +void XPfw_ErrorCsuRom(void) { + fw_printf("XPFW: Error Handler Triggered: %s\r\n",__func__); +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.h new file mode 100644 index 00000000..44d1ebdf --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_error_handler.h @@ -0,0 +1,66 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_ERROR_HANDLER_H_ +#define XPFW_ERROR_HANDLER_H_ + +void XPfw_ErrorHandlerInit(void); + +void XPfw_ErrorHandlerOne(void); +void XPfw_ErrorHandlerTwo(void); + +void XPfw_ErrorEccDdr(void); +void XPfw_ErrorEccOcm(void); +void XPfw_ErrorRpu0(void); +void XPfw_ErrorRpu1(void); +void XPfw_ErrorLpdTemp(void); +void XPfw_ErrorFpdTemp(void); +void XPfw_ErrorRpuLockStep(void); +void XPfw_ErrorRpuCcf(void); +void XPfw_ErrorLpdSwdt(void); +void XPfw_ErrorFpdSwdt(void); +void XPfw_ErrorPowerSupply(void); +void XPfw_ErrorXmpu(void); +void XPfw_ErrorTimeOut(void); +void XPfw_ErrorPL(void); +void XPfw_ErrorPLL(void); +void XPfw_ErrorCsu(void); +void XPfw_ErrorPmuUncorrectable(void); +void XPfw_ErrorPmuFw(void); +void XPfw_ErrorPmuServiceMode(void); +void XPfw_ErrorPmuPreBoot(void); +void XPfw_ErrorCsuRom(void); + + + + +#endif /* XPFW_ERROR_HANDLER_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_events.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_events.c new file mode 100644 index 00000000..4d5390aa --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_events.c @@ -0,0 +1,327 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_events.h" +#include "xpfw_interrupts.h" + + +static struct XPfw_Event_t EventTable[]={ + [0U] = {.Type = (u8)0U, .RegMask = MASK32_ALL_LOW, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MB_FAULT] = { .Type = XPFW_EV_TYPE_GPI0, .RegMask = MASK32_ALL_HIGH, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_APB_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_APB_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_AXI_AIB_ERROR] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_AXI_AIB_ERROR_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ERROR_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_2_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ERROR_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ERROR_1_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_3_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_2_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_1_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_0_DBG_PWRUP] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_DBG_PWRUP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_FPD_WAKE_GIC_PROXY] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_5] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_5_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_4] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_4_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_3] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_3_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_2] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_2_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_1] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_1_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_MIO_WAKE_0] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DAP_RPU_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_RPU_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DAP_FPD_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_DAP_FPD_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_USB_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_USB_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_USB_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_R5_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_R5_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_R5_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_3_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_3_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_2_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_2_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_1_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_1_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_0_WAKE] = { .Type = XPFW_EV_TYPE_GPI1, .RegMask = PMU_IOMODULE_GPI1_ACPU_0_WAKE_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_VCC_INT_FP_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_FP_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_VCC_INT_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_INT_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_VCC_AUX_DISCONNECT] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_VCC_AUX_DISCONNECT_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_CP_ACPU3_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU3_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_CP_ACPU2_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU2_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_CP_ACPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_CP_ACPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_CP_ACPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_RCPU1_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU1_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_DBG_RCPU0_RST_REQ] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_DBG_RCPU0_RST_REQ_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_R5_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_R5_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_R5_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_3_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_3_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_2_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_2_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_1_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_1_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_ACPU_0_SLEEP] = { .Type = XPFW_EV_TYPE_GPI2, .RegMask = PMU_IOMODULE_GPI2_ACPU_0_SLEEP_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_31] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_31_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_30] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_30_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_29] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_29_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_28] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_28_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_27] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_27_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_26] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_26_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_25] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_25_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_24] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_24_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_23] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_23_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_22] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_22_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_21] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_21_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_20] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_20_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_19] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_19_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_18] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_18_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_17] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_17_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_16] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_16_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_15] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_15_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_14] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_14_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_13] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_13_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_12] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_12_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_11] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_11_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_10] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_10_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_9] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_9_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_8] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_8_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_7] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_7_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_6] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_6_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_5] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_5_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_4] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_4_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_3] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_3_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_2] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_2_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_1] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_1_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_PL_GPI_0] = { .Type = XPFW_EV_TYPE_GPI3, .RegMask = PMU_IOMODULE_GPI3_PL_GPI_0_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_RTC_SECONDS] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, .ModMask = MASK32_ALL_LOW }, + [XPFW_EV_RTC_ALARM] = { .Type = XPFW_EV_TYPE_RTC, .RegMask = PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, .ModMask = MASK32_ALL_LOW } + +}; + + +u32 XPfw_EventGetModMask(u32 EventId) +{ + u32 Mask; + if(EventId < XPFW_EV_MAX){ + Mask = EventTable[EventId].ModMask; + } + else{ + Mask = 0U; + } + + return Mask; +} + +u32 XPfw_EventGetRegMask(u32 EventId) +{ + u32 Mask; + if(EventId < XPFW_EV_MAX){ + Mask = EventTable[EventId].RegMask; + } + else{ + Mask = MASK32_ALL_HIGH; + } + + return Mask; +} + +static XStatus XPfw_EventEnable(u32 EventId) +{ + XStatus Status; + + switch(EventTable[EventId].Type){ + + case XPFW_EV_TYPE_GPI0: + /* Nothing to do for GPI0. These are enabled by default */ + /* Enable GPI0 bit in IRQ_ENABLE */ + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_GPI0_MASK); + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI1: + /* Enable the event in GPI1 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, EventTable[EventId].RegMask, EventTable[EventId].RegMask); + /* Enable the GPI1 bit in IRQ ENABLE */ + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_GPI1_MASK); + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI2: + /* Enable the event in GPI2 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, EventTable[EventId].RegMask, EventTable[EventId].RegMask); + /* Enable the GPI2 bit in IRQ ENABLE */ + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_GPI2_MASK); + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI3: + /* Enable the event in GPI3 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI3_ENABLE, EventTable[EventId].RegMask, EventTable[EventId].RegMask); + /* Enable the GPI3 bit in IRQ ENABLE */ + XPfw_InterruptEnable(PMU_IOMODULE_IRQ_ENABLE_GPI3_MASK); + Status = XST_SUCCESS; + break; + case XPFW_EV_TYPE_RTC: + /* Enable RTC in IRQENABLE Register */ + XPfw_InterruptEnable(EventTable[EventId].RegMask); + Status = XST_SUCCESS; + break; + + default: + Status = XST_FAILURE; + break; + + + } + + + + return Status; +} + +static XStatus XPfw_EventDisable(u32 EventId) +{ + XStatus Status; + + switch(EventTable[EventId].Type){ + + case XPFW_EV_TYPE_GPI0: + /* Nothing to do for GPI0. These are enabled by default */ + /* Disable GPI0 bit in IRQ_ENABLE */ + XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI0_MASK); + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI1: + /* Disable the event in GPI1 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI1_ENABLE, EventTable[EventId].RegMask, 0U); + /* Disable the GPI1 bit in IRQ ENABLE */ + if(0U == XPfw_Read32(PMU_LOCAL_GPI1_ENABLE)) { + XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI1_MASK); + } + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI2: + /* Disable the event in GPI2 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, EventTable[EventId].RegMask, 0U); + /* Disable the GPI2 bit in IRQ ENABLE */ + if (0U == XPfw_Read32(PMU_LOCAL_GPI2_ENABLE)) { + XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI2_MASK); + } + Status = XST_SUCCESS; + break; + + case XPFW_EV_TYPE_GPI3: + /* Disable the event in GPI3 ENABLE register */ + XPfw_RMW32(PMU_LOCAL_GPI3_ENABLE, EventTable[EventId].RegMask, 0U); + /* Enable the GPI3 bit in IRQ ENABLE */ + if(0U == XPfw_Read32(PMU_LOCAL_GPI3_ENABLE)) { + XPfw_InterruptDisable(PMU_IOMODULE_IRQ_ENABLE_GPI3_MASK); + } + Status = XST_SUCCESS; + break; + case XPFW_EV_TYPE_RTC: + /* Enable RTC in IRQENABLE Register */ + XPfw_InterruptDisable(EventTable[EventId].RegMask); + Status = XST_SUCCESS; + break; + + default: + Status = XST_FAILURE; + break; + + + } + + + + return Status; +} + +XStatus XPfw_EventAddOwner(u8 ModId, u32 EventId) +{ + XStatus Status; + if((EventId < XPFW_EV_MAX) && (ModId < 32U)){ + + EventTable[EventId].ModMask = EventTable[EventId].ModMask | ((u32)1U< Report Error */ + +static void XPfw_InterruptRtcAlaramHandler(void) +{ + (void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_ALARM); +} + + +static void XPfw_InterruptRtcSecondsmHandler(void) +{ + (void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_SECONDS); +} + +static void XPfw_Pit1Handler(void) +{ + (void)XPfw_CoreTickHandler(); +} + +static void XPfw_Ipi0Handler(void) +{ + XStatus Status; + u32 Mask; + Mask = XPfw_Read32(IPI_PMU_0_ISR); + Status = XPfw_CoreDispatchIpi(0U); + /* If no Mod has registered for IPI, Ack it to prevent re-triggering */ + if(XST_SUCCESS != Status){ + fw_printf("Error: Unhandled IPI received\r\n"); + XPfw_Write32(IPI_PMU_0_ISR, Mask); + } +} + +static void XPfw_Ipi1Handler(void) +{ + XStatus Status; + u32 Mask; + Mask = XPfw_Read32(IPI_PMU_1_ISR); + Status = XPfw_CoreDispatchIpi(1U); + /* If no Mod has registered for IPI, Ack it to prevent re-triggering */ + if(XST_SUCCESS != Status){ + fw_printf("Error: Unhandled IPI received\r\n"); + XPfw_Write32(IPI_PMU_1_ISR, Mask); + } +} + +static void XPfw_Ipi2Handler(void) +{ + XStatus Status; + u32 Mask; + Mask = XPfw_Read32(IPI_PMU_2_ISR); + Status = XPfw_CoreDispatchIpi(2U); + /* If no Mod has registered for IPI, Ack it to prevent re-triggering */ + if(XST_SUCCESS != Status){ + fw_printf("Error: Unhandled IPI received\r\n"); + XPfw_Write32(IPI_PMU_2_ISR, Mask); + } +} + +static void XPfw_Ipi3Handler(void) +{ + XStatus Status; + u32 Mask; + Mask = XPfw_Read32(IPI_PMU_3_ISR); + Status = XPfw_CoreDispatchIpi(3U); + /* If no Mod has registered for IPI, Ack it to prevent re-triggering */ + if(XST_SUCCESS != Status){ + fw_printf("Error: Unhandled IPI received\r\n"); + XPfw_Write32(IPI_PMU_3_ISR, Mask); + } +} + + +static struct HandlerTable g_TopLevelInterruptTable[] ={ + {PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, XPfw_InterruptRtcAlaramHandler}, + {PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, XPfw_InterruptRtcSecondsmHandler}, + {PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_IPI3_MASK, XPfw_Ipi3Handler}, + {PMU_IOMODULE_IRQ_PENDING_IPI2_MASK, XPfw_Ipi2Handler}, + {PMU_IOMODULE_IRQ_PENDING_IPI1_MASK, XPfw_Ipi1Handler}, + {PMU_IOMODULE_IRQ_PENDING_IPI0_MASK, XPfw_Ipi0Handler}, + {PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_GPI3_MASK, XPfw_InterruptGpi3Handler}, + {PMU_IOMODULE_IRQ_PENDING_GPI2_MASK, XPfw_InterruptGpi2Handler}, + {PMU_IOMODULE_IRQ_PENDING_GPI1_MASK, XPfw_InterruptGpi1Handler}, + {PMU_IOMODULE_IRQ_PENDING_GPI0_MASK, XPfw_InterruptGpi0Handler}, + {PMU_IOMODULE_IRQ_PENDING_PIT3_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_PIT2_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_PIT1_MASK, XPfw_Pit1Handler}, + {PMU_IOMODULE_IRQ_PENDING_PIT0_MASK, XPfw_NullHandler}, + {PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK, XPfw_NullHandler} +}; + +void XPfw_InterruptInit(void) +{ + + XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U); + Xil_ExceptionDisable(); + XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU); + InterruptRegsiter = 0U; + +} + +void XPfw_InterruptStart(void) +{ + XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter); + Xil_ExceptionEnable(); +} + +void XPfw_InterruptHandler(void) +{ + u32 l_IrqReg; + u32 l_index; + + if ( XST_SUCCESS == XPfw_CoreIsReady()) { + + /* Latch the IRQ_PENDING register into a local variable */ + l_IrqReg = XPfw_Read32(PMU_IOMODULE_IRQ_PENDING); + + /* Loop through the Handler Table and handle the trigger interrupts */ + for (l_index = 0U; l_index < ARRAYSIZE(g_TopLevelInterruptTable); + l_index++) { + if ((l_IrqReg & g_TopLevelInterruptTable[l_index].Mask) + == g_TopLevelInterruptTable[l_index].Mask) { + /* Call the Handler */ + g_TopLevelInterruptTable[l_index].Handler(); + /* ACK the Interrupt */ + XPfw_Write32(PMU_IOMODULE_IRQ_ACK, + g_TopLevelInterruptTable[l_index].Mask); + } + } + } else { + /* We shouldnt be here before Init, but we are.. So disable the Interrupts */ + /* Init will enable only the required interrupts */ + XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U); + XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU); + } + +} + + + +void XPfw_InterruptDisable(u32 Mask) +{ + InterruptRegsiter = InterruptRegsiter & (~Mask); + XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter); +} + +void XPfw_InterruptEnable(u32 Mask) +{ + InterruptRegsiter = InterruptRegsiter | Mask; + XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter); +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_interrupts.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_interrupts.h new file mode 100644 index 00000000..77bde4cc --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_interrupts.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_INTERRUPTS_H_ +#define XPFW_INTERRUPTS_H_ + +#include "xpfw_default.h" + + +void XPfw_InterruptHandler(void) __attribute__ ((interrupt_handler)); + +void XPfw_InterruptDisable(u32 Mask); + +void XPfw_InterruptEnable(u32 Mask); + +void XPfw_InterruptStart(void); + +void XPfw_InterruptInit(void); + +#endif /* XPFW_INTERRUPTS_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_main.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_main.c index dd208a45..1b339dc2 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/xpfw_main.c +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_main.c @@ -30,15 +30,54 @@ * ******************************************************************************/ -#include "xil_printf.h" +#include "xil_io.h" #include "xstatus.h" -#include "mb_interface.h" +#include "xil_types.h" -void XPfw_Main(void) +#include "xpfw_version.h" +#include "xpfw_default.h" + +#include "xpfw_core.h" +#include "xpfw_user_startup.h" +#include "xpfw_platform.h" + +XStatus XPfw_Main(void) { - xil_printf("PMU Firmware [Build: %s %s ] \r\n",__DATE__, __TIME__); - /* Put Microblaze to Sleep in an infinite loop */ - do{ - mb_sleep(); - } while(1); + XStatus Status; + + /* Start the Init Routine */ + XPfw_PlatformInit(); + fw_printf("PMU Firmware %s\t%s %s\n", + ZYNQMP_XPFW_VERSION, __DATE__, __TIME__); + /* TODO: Print ROM version */ + + /* Initialize the FW Core Object */ + Status = XPfw_CoreInit(0U); + + if (Status != XST_SUCCESS) { + fw_printf("%s: Error! Core Init failed\r\n", __func__); + goto Done; + } + + /* Call the User Start Up Code to add Mods, Handlers and Tasks */ + XPfw_UserStartUp(); + + /* Configure the Modules. Calls CfgInit Handlers of all modules */ + Status = XPfw_CoreConfigure(); + + if (Status != XST_SUCCESS) { + fw_printf("%s: Error! Core Cfg failed\r\n", __func__); + goto Done; + } + + /* Wait to Service the Requests */ + Status = XPfw_CoreLoop(); + + if (Status != XST_SUCCESS) { + fw_printf("%s: Error! Unexpected exit from CoreLoop\r\n", __func__); + goto Done; + } + Done: + /* Control never comes here */ + return Status; } diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.c new file mode 100644 index 00000000..3f5805b6 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +#include "xpfw_module.h" + +XStatus XPfw_ModuleInit(XPfw_Module_t *ModPtr,u8 ModId) +{ + XStatus Status; + + if (ModPtr != NULL) { + ModPtr->ModId = ModId; + ModPtr->CfgInitHandler = NULL; + ModPtr->EventHandler = NULL; + ModPtr->IpiHandler = NULL; + ModPtr->IpiId = 0U; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + return Status; + +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.h new file mode 100644 index 00000000..e4a12ae3 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_module.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ + +#ifndef XPFW_MODULE_H_ +#define XPFW_MODULE_H_ + +#include "xpfw_default.h" + +struct XPfw_Module_s; + +/* Typedefs for Handlers used in Module Struct */ +typedef void (*XPfwModEventHandler_t)(const struct XPfw_Module_s *ModPtr, + u32 EventId); +typedef void (*XPfwModIpiHandler_t)(const struct XPfw_Module_s *ModPtr, + u32 IpiNum, u32 SrcMask); +typedef void (*XPfwModCfgInitHandler_t)(const struct XPfw_Module_s *ModPtr, + const u32 *CfgObject, u32 CfgLen); + +/** + * Module Data Structure + * + * Any functionally isolated set of code targeted for a specific application like + * Power Management, Safety, etc should use an object of this class to interact with Core FW + * + */ +typedef struct XPfw_Module_s { + u8 ModId; /**< Unique Module Id. Assigned by Core */ + XPfwModCfgInitHandler_t CfgInitHandler; /**< Callback when an Event is triggered for this Module */ + XPfwModIpiHandler_t IpiHandler; /**< Callback when an IPI is triggered for this Module */ + XPfwModEventHandler_t EventHandler; /**< Callback during Initialization of Core FW (Post User_StartUp) */ + u32 IpiId; /**< Filter for First Word of IPI Message */ +} XPfw_Module_t; + +/** + * Init the members of Module Object to default values. + * Default values are NULL for pointers and 0 Masks + * + * @param ModPtr is pointer to the Mod + * @param ModId is the value of unique Id assigned to this Mod + * + * @return Always returns XST_SUCCESS + */ +XStatus XPfw_ModuleInit(XPfw_Module_t *ModPtr, u8 ModId); + +#endif /* XPFW_MODULE_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.c new file mode 100644 index 00000000..8cf1774d --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_platform.h" +#include "xparameters.h" +#include "xil_io.h" +#include "xil_types.h" + + +#include "crl_apb.h" + +#include "xpfw_default.h" + +#ifdef STDOUT_BASEADDRESS + +#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) +/* Register definitions for UART0 */ +#define UART_BASE 0XFF000000U +#define R_CRL_APB_REF_CTL CRL_APB_UART0_REF_CTRL +#define IOU_UART_RST_MASK CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK + +#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) + +/* Register definitions for UART1 */ +#define UART_BASE 0XFF010000U +#define R_CRL_APB_REF_CTL CRL_APB_UART1_REF_CTRL +#define IOU_UART_RST_MASK CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK + +#else +#define SKIP_UARTINIT +#endif + +#endif /* STDOUT_BASEADDRESS */ + +#ifndef SKIP_UARTINIT +#define R_UART_CR (UART_BASE) +#define R_UART_MODE (UART_BASE + 0x04) +#define R_UART_IMR (UART_BASE + 0x10) +#define R_UART_BGEN (UART_BASE + 0x18) +#define R_UART_STS (UART_BASE + 0x2C) +#define R_UART_TX (UART_BASE + 0x30) +#define R_UART_BDIV (UART_BASE + 0x34) +#endif + +void XPfw_PlatformInit(void) +{ + +#ifndef SKIP_UARTINIT + /* + * FIXME: This function configures UART to baud 115200 and uses + * hardcoded values. Fix it to use Clock params from xparameters + * Also add MIO configs + */ + + /* Release UART from Reset */ + XPfw_RMW32(CRL_APB_RST_LPD_IOU2, IOU_UART_RST_MASK,0 ); + /* SetUp the Reference Clock for UART*/ + XPfw_Write32(R_CRL_APB_REF_CTL,0X01000500U); + /* RX and TX Enable */ + XPfw_Write32(R_UART_CR, (UART0_CONTROL_REG0_TXEN_MASK|UART0_CONTROL_REG0_RXEN_MASK)); + /* 8bits, 1 stop bit, No Parity, normal mode, uart_ref_clk */ + XPfw_Write32(R_UART_MODE, 0X00000020U); + /* For Baud Rate = 115200 */ + XPfw_Write32(R_UART_BGEN, 0X0000001FU); + /* Baud Rate Divider */ + XPfw_Write32(R_UART_BDIV, 0X00000006U); +#endif + +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.h new file mode 100644 index 00000000..5a1e806a --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_platform.h @@ -0,0 +1,38 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_PLATFORM_H_ +#define XPFW_PLATFORM_H_ + +void XPfw_PlatformInit(void); + +#endif /* XPFW_PLATFORM_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.c new file mode 100644 index 00000000..9b9e48af --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.c @@ -0,0 +1,270 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_default.h" +#include "xpfw_util.h" +#include "xpfw_resets.h" + + + +/** + * Delays or Wait times for HW related actions + */ +#define XPFW_TO_AIB_PS_PL (0xFU) +#define XPFW_RST_PROP_DELAY (0xFU) + +/** + * Macros used for convenience + * Only in this file + */ + +#define AIB_CNTRL_MASK (PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FM_MASK |\ + PMU_GLOBAL_AIB_CNTRL_LPD_AFI_FS_MASK |\ + PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FM_MASK |\ + PMU_GLOBAL_AIB_CNTRL_FPD_AFI_FS_MASK) + +#define AIB_STATUS_MASK (PMU_GLOBAL_AIB_STATUS_LPD_AFI_FM_MASK |\ + PMU_GLOBAL_AIB_STATUS_LPD_AFI_FS_MASK |\ + PMU_GLOBAL_AIB_STATUS_FPD_AFI_FM_MASK |\ + PMU_GLOBAL_AIB_STATUS_FPD_AFI_FS_MASK) + +#define RPU_AIB_MASTER_MASK (LPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK |\ + LPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK ) +#define RPU_AIB_SLAVE_MASK (LPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK |\ + LPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK ) + +/** + * This PS only reset is to gracefully reset PS while PL remains active. + * This reset can be triggered by hardware error signal(s) or + * by software register write. This reset is a subset of + * �System� reset (excluding PL reset). If this PS reset is triggered by + * error signal, then error is transmitted to PL also. + * The sequencing of this reset is described below: +*- [ErrorLogic]Error interrupt is asserted whose action requires PS-only reset + *- This request is sent to PMU as interrupt + *- [PMU-FW] Set PMU Error (=>PS-only reset) to indicate to PL. + *- [PMU-FW] Block FPD=>PL and LPD=>PL interfaces with the help of AIB (in PS). + *- If AIB ack is not received, then PMU should timeout and continue. + *- [PMU-FW] (Optional) Block PL=>FPD (and PL=>LPD if any) interfaces with the + * help of AIB (in PL wrapper). + *-If AIB ack is not received, then PMU should timeout and continue. + *@note It requires PMU to PL-AIB req/ack interface. + *@note PMU to PL-AIB req signals should not be reset by this PS-only reset. + *- [PMU-FW] Initiate PS-only reset by writing to PMU-local register + *- [RstCtrl] Assert PS-only reset + *- [RstCtrl] After some wait, de-assert reset which will result in + * PS-only re-boot + *- [FSBL] Unblock PL => FPD (and PL=>LPD if any) AXI interfaces + * @note: You may never return from this function, since PS resets + * + */ +void XPfw_ResetPsOnly(void) +{ + XStatus l_Status; + + /** + *TODO: Set PMU Error to indicate to PL + * + */ + + fw_printf("Isolating Interfaces....."); + /* + * Block FPD=>PL and LPD=>PL interfaces with the help of AIB (in PS) + */ + + /** + * AIB CNTRL register has only these four interface bits + * And we will be asserting all of them + * So there is no need to do RMW + */ + + Xil_Out32(PMU_GLOBAL_AIB_CNTRL,AIB_CNTRL_MASK); + + + /** + * Wait till we get the AIB ack or Timeout + */ + l_Status = XPfw_UtilPollForMask(PMU_GLOBAL_AIB_STATUS, + AIB_STATUS_MASK,XPFW_TO_AIB_PS_PL); + + if(l_Status == XST_SUCCESS){ + fw_printf("Done\r\n"); + } + else + { + fw_printf("Time Out\r\n"); + } + + /** + * Initiate PS-only reset by writing to PMU-local register + */ + fw_printf("Asserting Reset\r\n"); + XPfw_UtilRMW(PMU_GLOBAL_GLOBAL_RESET, + PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_MASK, + PMU_GLOBAL_GLOBAL_RESET_PS_ONLY_RST_MASK); + /** + * Done + */ + +} + + + +XStatus XPfw_ResetFpd(void) +{ + /* + * Block FPD=>LPD interfaces with the help of AIB (in FPS). + */ + Xil_Out32(PMU_LOCAL_DOMAIN_ISO_CNTRL, + (PMU_LOCAL_DOMAIN_ISO_CNTRL_LP_FP_1_MASK | + PMU_LOCAL_DOMAIN_ISO_CNTRL_FP_PL_MASK)); + + /** + * FIXME: Update with correct delay here for AIB + */ + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + /** + * Initiate FPD reset by writing to PMU-local register + */ + XPfw_UtilRMW(PMU_GLOBAL_GLOBAL_RESET, + PMU_GLOBAL_GLOBAL_RESET_FPD_RST_MASK, + PMU_GLOBAL_GLOBAL_RESET_FPD_RST_MASK); + /** + * Hold in Reset and wait till it propagates + */ + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + /** + * Remove Isolation + */ + Xil_Out32(PMU_LOCAL_DOMAIN_ISO_CNTRL,0U); + /** + * FIXME: Update with correct delay here + */ + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + /** + * Release from Reset and wait till it propagates + */ + XPfw_UtilRMW(PMU_GLOBAL_GLOBAL_RESET, + PMU_GLOBAL_GLOBAL_RESET_FPD_RST_MASK, + 0); + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + + /** + * FIXME: Is there something that we can poll to + * check if we failed somewhere? + */ + return XST_SUCCESS; + +} + + +XStatus XPfw_ResetRpu(void) +{ + + XStatus l_Status; + + /** + * Reference: ZynqMP Arch Spec 2.02 + * + */ + + /** + * - Block R5 Master Interfaces using AIB + */ + XPfw_UtilRMW(LPD_SLCR_ISO_AIBAXI_REQ, RPU_AIB_MASTER_MASK, + RPU_AIB_MASTER_MASK); + + /** + * - Wait for AIB ack, TimeOut If not received + */ + fw_printf("Waiting for AIB Ack (M)....."); + l_Status = XPfw_UtilPollForMask(LPD_SLCR_ISO_AIBAXI_ACK, + RPU_AIB_MASTER_MASK, + XPFW_TO_AIB_PS_PL); + + if (l_Status == XST_SUCCESS) { + fw_printf("Done\r\n"); + } else { + fw_printf("Time Out\r\n"); + } + + /** + * - Block R5 Slave Interfaces using AIB + * + */ + XPfw_UtilRMW(LPD_SLCR_ISO_AIBAXI_REQ, + RPU_AIB_SLAVE_MASK, RPU_AIB_SLAVE_MASK); + /** + * - Wait for AIB ack, Timeout if not received + */ + fw_printf("Waiting for AIB Ack (S)....."); + l_Status = XPfw_UtilPollForMask(LPD_SLCR_ISO_AIBAXI_ACK, RPU_AIB_SLAVE_MASK, + XPFW_TO_AIB_PS_PL); + if (l_Status == XST_SUCCESS) { + fw_printf("Done\r\n"); + } else { + fw_printf("Time Out\r\n"); + } + + /** + * Unblock Master Interfaces + */ + XPfw_UtilRMW(LPD_SLCR_ISO_AIBAXI_REQ, + RPU_AIB_MASTER_MASK, 0U); + + /** + * Initiate R5 LockStep reset by writing to PMU-local register + */ + XPfw_UtilRMW(PMU_GLOBAL_GLOBAL_RESET, + PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK, + PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK); + /** + * FIXME: Update with correct delay here + */ + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + + fw_printf("Releasing RPU out of Reset\r\n"); + + /** + * Release from Reset and wait till it propagates + */ + XPfw_UtilRMW(PMU_GLOBAL_GLOBAL_RESET, + PMU_GLOBAL_GLOBAL_RESET_RPU_LS_RST_MASK, 0U); + XPfw_UtilWait(XPFW_RST_PROP_DELAY); + + /** + * Unblock SLave Interfaces + */ + XPfw_UtilRMW(LPD_SLCR_ISO_AIBAXI_REQ, + RPU_AIB_SLAVE_MASK, 0U); + return XST_SUCCESS; +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.h new file mode 100644 index 00000000..e6df4425 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_resets.h @@ -0,0 +1,55 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xstatus.h" + +/*****************************************************************************/ +/** + * @brief PS-Only Reset Routine + */ +/*****************************************************************************/ +void XPfw_ResetPsOnly(void); + +/*****************************************************************************/ +/** + * @brief FPD Reset Routine + */ +/*****************************************************************************/ + +XStatus XPfw_ResetFpd(void); + +/*****************************************************************************/ +/** + * @brief RPU Reset Routine + */ +/*****************************************************************************/ +XStatus XPfw_ResetRpu(void); diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_rom_interface.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_rom_interface.h new file mode 100644 index 00000000..338049fb --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_rom_interface.h @@ -0,0 +1,113 @@ +u32 XpbrACPU0SleepHandler(void); +u32 XpbrACPU0WakeHandler(void); +u32 XpbrACPU1SleepHandler(void); +u32 XpbrACPU1WakeHandler(void); +u32 XpbrACPU2SleepHandler(void); +u32 XpbrACPU2WakeHandler(void); +u32 XpbrACPU3SleepHandler(void); +u32 XpbrACPU3WakeHandler(void); +u32 XpbrCsuSecureLockdownHandler(void); +u32 XpbrDapFpdWakeHandler(void); +u32 XpbrDapRpuWakeHandler(void); +u32 XpbrDefaultWakeHandler(void); +u32 XpbrFpdGicProxyWakeHandler(void); +u32 XpbrFPIsolationReqHandler(void); +u32 XpbrFPLockIsoHandler(void); +u32 XpbrGpi1Router(void); +u32 XpbrGpi2Router(void); +u32 XpbrGpi3Handler(void); +u32 XpbrHwExceptionHandler(void); +u32 XpbrHwRstReqHandler(void); +u32 XpbrIpi0Handler(void); +u32 XpbrIsoReqRouter(void); +u32 XpbrMio0WakeHandler(void); +u32 XpbrMio1WakeHandler(void); +u32 XpbrMio2WakeHandler(void); +u32 XpbrMio3WakeHandler(void); +u32 XpbrMio4WakeHandler(void); +u32 XpbrMio5WakeHandler(void); +u32 XpbrNullInterruptHandler(void); +u32 XpbrNullServiceHandler(void); +u32 XpbrPLIsolationReqHandler(void); +u32 XpbrPLNonPCAPIsoReqHandler(void); +u32 XpbrPwrDnACPU0Handler(void); +u32 XpbrPwrDnACPU1Handler(void); +u32 XpbrPwrDnACPU2Handler(void); +u32 XpbrPwrDnACPU3Handler(void); +u32 XpbrPwrDnFpdHandler(void); +u32 XpbrPwrDnGpuHandler(void); +u32 XpbrPwrDnL2Bank0Handler(void); +u32 XpbrPwrDnOcmBank0Handler(void); +u32 XpbrPwrDnOcmBank1Handler(void); +u32 XpbrPwrDnOcmBank2Handler(void); +u32 XpbrPwrDnOcmBank3Handler(void); +u32 XpbrPwrDnPldHandler(void); +u32 XpbrPwrDnPp0Handler(void); +u32 XpbrPwrDnPp1Handler(void); +u32 XpbrPwrDnR50Handler(void); +u32 XpbrPwrDnR51Handler(void); +u32 XpbrPwrDnReqRouter(void); +u32 XpbrPwrDnRpuHandler(void); +u32 XpbrPwrDnTcm0AHandler(void); +u32 XpbrPwrDnTcm0BHandler(void); +u32 XpbrPwrDnTcm1AHandler(void); +u32 XpbrPwrDnTcm1BHandler(void); +u32 XpbrPwrDnUsb0Handler(void); +u32 XpbrPwrDnUsb1Handler(void); +u32 XpbrPwrUpACPU0Handler(void); +u32 XpbrPwrUpACPU1Handler(void); +u32 XpbrPwrUpACPU2Handler(void); +u32 XpbrPwrUpACPU3Handler(void); +u32 XpbrPwrUpFpdHandler(void); +u32 XpbrPwrUpL2Bank0Handler(void); +u32 XpbrPwrUpOcmBank0Handler(void); +u32 XpbrPwrUpOcmBank1Handler(void); +u32 XpbrPwrUpOcmBank2Handler(void); +u32 XpbrPwrUpOcmBank3Handler(void); +u32 XpbrPwrUpPldHandler(void); +u32 XpbrPwrUpPp0Handler(void); +u32 XpbrPwrUpPp1Handler(void); +u32 XpbrPwrUpReqRouter(void); +u32 XpbrPwrUpRpuHandler(void); +u32 XpbrPwrUpTcm0AHandler(void); +u32 XpbrPwrUpTcm0BHandler(void); +u32 XpbrPwrUpTcm1AHandler(void); +u32 XpbrPwrUpTcm1BHandler(void); +u32 XpbrPwrUpUsb0Handler(void); +u32 XpbrPwrUpUsb1Handler(void); +u32 XpbrR50SleepHandler(void); +u32 XpbrR50WakeHandler(void); +u32 XpbrR51SleepHandler(void); +u32 XpbrR51WakeHandler(void); +u32 XpbrROMExceptionHandler(void); +u32 XpbrRstACPU0Handler(void); +u32 XpbrRstACPU1Handler(void); +u32 XpbrRstACPU2Handler(void); +u32 XpbrRstACPU3Handler(void); +u32 XpbrRstACPUxHandler(void); +u32 XpbrRstApuHandler(void); +u32 XpbrRstDisplayPortHandler(void); +u32 XpbrRstFpdHandler(void); +u32 XpbrRstGem0Handler(void); +u32 XpbrRstGem1Handler(void); +u32 XpbrRstGem2Handler(void); +u32 XpbrRstGem3Handler(void); +u32 XpbrRstGpuHandler(void); +u32 XpbrRstLsRpuHandler(void); +u32 XpbrRstPCIeHandler(void); +u32 XpbrRstPp0Handler(void); +u32 XpbrRstPp1Handler(void); +u32 XpbrRstPsOnlyHandler(void); +u32 XpbrRstR50Handler(void); +u32 XpbrRstR51Handler(void); +u32 XpbrRstSataHandler(void); +u32 XpbrRstUsb0Handler(void); +u32 XpbrRstUsb1Handler(void); +u32 XpbrRtcAlarmHandler(void); +u32 XpbrServiceHandler(void); +u32 XpbrServiceMode(void); +u32 XpbrSwExceptionHandler(void); +u32 XpbrSwRstReqRouter(void); +u32 XpbrTMRFaultDetectionHandler(void); +u32 XpbrUsb0WakeHandler(void); +u32 XpbrUsb1WakeHandler(void); diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.c new file mode 100644 index 00000000..c612f216 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.c @@ -0,0 +1,192 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xpfw_scheduler.h" + +/** + * PMU PIT Clock Frequency and Tick Calculation + * TODO: Replace with respective CLK_FREQ from xparameters.h + */ +#define PMU_PIT_CLK_FREQ 4000000U +#define TICK_MILLISECONDS 10U +#define COUNT_PER_TICK ((PMU_PIT_CLK_FREQ / 1000U)* TICK_MILLISECONDS ) + +/** + * Microblaze IOModule PIT Register Offsets + * Used internally in this file + */ +#define PIT_PRELOAD_OFFSET 0U +#define PIT_COUNTER_OFFSET 4U +#define PIT_CONTROL_OFFSET 8U + +XStatus XPfw_SchedulerInit(XPfw_Scheduler_t *SchedPtr, u32 PitBaseAddr) +{ + u32 Idx; + XStatus Status; + + if (SchedPtr != NULL) { + /* Disable all the tasks */ + for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) { + SchedPtr->TaskList[Idx].Interval = 0U; + SchedPtr->TaskList[Idx].Callback = NULL; + } + SchedPtr->Enabled = FALSE; + SchedPtr->PitBaseAddr = PitBaseAddr; + SchedPtr->Tick = 0U; + XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U); + /* Successfully completed init */ + Status = XST_SUCCESS; + } else { + /* Failed due to NULL pointer to Scheduler */ + Status = XST_FAILURE; + } + return Status; + +} + +XStatus XPfw_SchedulerStart(XPfw_Scheduler_t *SchedPtr) +{ + + XStatus Status; + + if (SchedPtr != NULL) { + SchedPtr->Enabled = TRUE; + + XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET, + COUNT_PER_TICK); + XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 3U); + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + return Status; +} + + +XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr) +{ + SchedPtr->Enabled =FALSE; + + XPfw_Write32(SchedPtr->PitBaseAddr + PIT_PRELOAD_OFFSET, 0U ); + XPfw_Write32(SchedPtr->PitBaseAddr + PIT_CONTROL_OFFSET, 0U ); + + return XST_SUCCESS; +} + +void XPfw_SchedulerTickHandler(XPfw_Scheduler_t *SchedPtr) +{ + /* TODO: Add check to detect task misses */ + SchedPtr->Tick++; +} + +XStatus XPfw_SchedulerProcess(const XPfw_Scheduler_t *SchedPtr) +{ + u32 Idx; + XStatus Status; + u32 CallCount = 0U; + for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) { + /* Check if it is valid event */ + if ((0U != SchedPtr->TaskList[Idx].Interval) + && (NULL != SchedPtr->TaskList[Idx].Callback)) { + /* Check if it has triggered */ + if (0U == (SchedPtr->Tick % SchedPtr->TaskList[Idx].Interval)) { + /* Execute the Task */ + SchedPtr->TaskList[Idx].Callback(); + CallCount++; + } + } + } + + //fw_printf("%s: %d Tasks were triggered\r\n", __func__, CallCount); + + if (CallCount > 0U) { + Status = XST_SUCCESS; + } else { + /* Failed because non of the tasks were triggered */ + Status = XST_FAILURE; + } + return Status; +} + + + +XStatus XPfw_SchedulerAddTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId,u32 MilliSeconds, XPfw_Callback_t Callback) +{ + u32 Idx; + XStatus Status; + /* Get the Next Free Task Index */ + for(Idx=0U;Idx < XPFW_SCHED_MAX_TASK;Idx++){ + if( 0U == SchedPtr->TaskList[Idx].Interval){ + break; + } + } + /* Check if we have reached Max Task limit */ + if(XPFW_SCHED_MAX_TASK == Idx){ + Status = XST_FAILURE; + } + else{ + /* Add Interval as a factor of TICK_MILLISECONDS */ + SchedPtr->TaskList[Idx].Interval = MilliSeconds/TICK_MILLISECONDS; + SchedPtr->TaskList[Idx].OwnerId = OwnerId; + SchedPtr->TaskList[Idx].Callback = Callback; + Status = XST_SUCCESS; + } + + return Status; +} + + +XStatus XPfw_SchedulerRemoveTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId, u32 MilliSeconds, XPfw_Callback_t Callback) +{ + u32 Idx; + u32 TaskCount = 0; + /*Find the Task Index */ + + for (Idx = 0U; Idx < XPFW_SCHED_MAX_TASK; Idx++) { + + if ((Callback == SchedPtr->TaskList[Idx].Callback) + && (SchedPtr->TaskList[Idx].OwnerId == OwnerId)) { + /* Disable task with given Milliseconds param or ALL if Milliseconds=0 */ + if ((SchedPtr->TaskList[Idx].Interval == MilliSeconds) + || (0U == MilliSeconds)) { + SchedPtr->TaskList[Idx].Interval = 0U; + SchedPtr->TaskList[Idx].OwnerId = 0U; + SchedPtr->TaskList[Idx].Callback = NULL; + TaskCount++; + } + } + } + + fw_printf("$s: Removed %d tasks\r\n", __func__, TaskCount); + + return ((TaskCount > 0) ? XST_SUCCESS : XST_FAILURE); +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.h new file mode 100644 index 00000000..d5f1ffe3 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_scheduler.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_SCHEDULER_H_ +#define XPFW_SCHEDULER_H_ + + +#include "xpfw_default.h" + +#define XPFW_SCHED_MAX_TASK 10U + + +typedef void (*XPfw_Callback_t) (void); + +struct XPfw_Task_t{ + u32 Interval; + u32 OwnerId; + XPfw_Callback_t Callback; +}; + +typedef struct { + struct XPfw_Task_t TaskList[XPFW_SCHED_MAX_TASK]; + u32 TaskCount; + u32 PitBaseAddr; + u32 Tick; + u32 Enabled; +} XPfw_Scheduler_t ; + + +void XPfw_SchedulerTickHandler(XPfw_Scheduler_t *SchedPtr); +XStatus XPfw_SchedulerInit(XPfw_Scheduler_t *SchedPtr, u32 PitBaseAddr); +XStatus XPfw_SchedulerStart(XPfw_Scheduler_t *SchedPtr); +XStatus XPfw_SchedulerStop(XPfw_Scheduler_t *SchedPtr); +XStatus XPfw_SchedulerProcess(const XPfw_Scheduler_t *SchedPtr); +XStatus XPfw_SchedulerAddTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId,u32 MilliSeconds, XPfw_Callback_t Callback); +XStatus XPfw_SchedulerRemoveTask(XPfw_Scheduler_t *SchedPtr, u32 OwnerId, u32 MilliSeconds, XPfw_Callback_t Callback); + +#endif /* XPFW_SCHEDULER_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S b/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S index 4454caa6..be021f39 100644 --- a/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_start.S @@ -29,37 +29,67 @@ * this Software without prior written authorization from Xilinx. * ******************************************************************************/ - .section .vectors.reset, "ax" .align 2 _vector_reset: brai XPfw_Init +/* TBD: Implement SW Exception Handler and update the vector */ + .section .vectors.sw_exception, "ax" + .align 2 - /* FW StartUP Begins Here: Initialization of the Stack and Stack Protection. */ +_vector_sw_exception: + brai XPfw_Exception + + .section .vectors.interrupt, "ax" + .align 2 +_vector_interrupt: + brai XPfw_InterruptHandler + +/* TBD: Implement HW Exception Handler and update the vector */ + .section .vectors.hw_exception, "ax" + .align 2 +_vector_hw_exception: + brai XPfw_Exception + +/* FW StartUP Begins Here: Initialization of the Stack and Stack Protection. */ .section .text .globl XPfw_Init .align 2 .ent XPfw_Init .type XPfw_Init, @function XPfw_Init: - /* PMU Firmware does not reuse the ROM Stack. FW uses a separate stack of 4k (can be changed by user) */ + /* + *PMU Firmware does not reuse the ROM Stack. FW uses a speprate stack of 4k (can be changed by user) + */ /* Stack Initialization */ - addik r1, r0, _stack /* R1 is stack pointer, load Stack's highest address into SP. */ - addik r13, r0, _SDA_BASE_ /* The read-write small data anchor address */ - addik r2, r0, _SDA2_BASE_ /* The read-only small data anchor address */ + addik r1, r0, _stack /* R1 is stack pointer, load Stack's highest address into SP. */ + addik r13, r0, _SDA_BASE_ /* The read-write small data anchor address */ + addik r2, r0, _SDA2_BASE_ /* The read-only small data anchor address */ /* Stack Protection */ - addik r11, r0, _stack /* Load Stack's highest address into temp R11 */ - mts rshr, r11 /* Store Stack's highest address into STACK_HIGH_REGISTER */ - addik r11, r0, _stack_end /* Load Stack's lowest address into temp R11 */ - mts rslr, r11 /* Store Stack's lowest address into STACK_LOW_REGISTER */ + addik r11, r0, _stack /* Load Stack's highest address into temp R11 */ + mts rshr, r11 /* Store Stack's highest address into STACK_HIGH_REGISTER */ + addik r11, r0, _stack_end /* Load Stack's lowest address into temp R11 */ + mts rslr, r11 /* Store Stack's lowest address into STACK_LOW_REGISTER */ - /* Call Main */ + /* Call Main*/ brlid r15, XPfw_Main nop /* Control never comes here */ bri 0 nop .end XPfw_Init + +/* Exception Handler */ + .section .text + .globl XPfw_Exception + .align 2 + .ent XPfw_Exception + .type XPfw_Exception, @function +XPfw_Exception: +/* For now, just keep looping here. Its easier to debug */ + bri 0 + nop + .end XPfw_Exception diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.c new file mode 100644 index 00000000..5c729109 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.c @@ -0,0 +1,282 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#include "xpfw_config.h" + +#include "xpfw_core.h" +#include "xpfw_events.h" +#include "xpfw_module.h" + +#include "xpfw_user_startup.h" + +#include "pm_binding.h" +#include "xpfw_error_handler.h" + +#include "pm_api.h" +#include "ipi_buffer.h" +#include "pm_defs.h" + + +#ifdef ENABLE_SCHEDULER +void PrintMsg1(void) +{ + fw_printf("Task#1\r\n"); +} +void PrintMsg2(void) +{ + fw_printf("Task#2\r\n"); +} +#endif + + +#ifdef ENABLE_PM +static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask) +{ + + + u32 isrVal, apiId; + XPfw_PmIpiStatus ipiStatus; + + switch(IpiNum) { + + case 0: + isrVal = XPfw_Read32(IPI_PMU_0_ISR); + fw_printf("Received IPI Mask:0x%08x\r\n", isrVal); + ipiStatus = XPfw_PmCheckIpiRequest(isrVal, &apiId); + if (XPFW_PM_IPI_IS_PM_CALL == ipiStatus) { + /* Power management API processing */ + XPfw_PmIpiHandler(isrVal, apiId); + } + else { + fw_printf("MOD-%d: Non-PM IPI-%d call received\r\n", ModPtr->ModId, IpiNum); + } + XPfw_Write32(IPI_PMU_0_ISR, isrVal); + break; + + case 1: + isrVal = XPfw_Read32(IPI_PMU_1_ISR); + XPfw_Write32(IPI_PMU_1_ISR, isrVal); + break; + + case 2: + isrVal = XPfw_Read32(IPI_PMU_2_ISR); + XPfw_Write32(IPI_PMU_2_ISR, isrVal); + break; + + case 3: + isrVal = XPfw_Read32(IPI_PMU_3_ISR); + XPfw_Write32(IPI_PMU_3_ISR, isrVal); + break; + + default: + fw_printf("ERROR: Invalid IPI Number: %d\r\n", IpiNum); + + } + + +} + +void PmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId) +{ + u32 EvType, RegValue; + EvType = XPfw_EventGetType(EventId); + + switch (EvType) { + case XPFW_EV_TYPE_GPI1: + RegValue = XPfw_EventGetRegMask(EventId); + XPfw_PmWakeHandler(RegValue); + break; + case XPFW_EV_TYPE_GPI2: + RegValue = XPfw_EventGetRegMask(EventId); + XPfw_PmWfiHandler(RegValue); + break; + default: + fw_printf("Unhandled PM Event: %d\r\n", EventId); + break; + } + +} + +void PmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len) +{ + /* Add Event Handlers for PM */ + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_0_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_1_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_2_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_3_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_0_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_1_WAKE); + + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_0); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_1); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_2); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_3); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_4); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_MIO_WAKE_5); + + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_FPD_WAKE_GIC_PROXY); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_USB_0_WAKE); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_USB_1_WAKE); + + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_0_SLEEP); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_1_SLEEP); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_2_SLEEP); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_ACPU_3_SLEEP); + + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_0_SLEEP); + XPfw_CoreRegisterEvent(ModPtr, XPFW_EV_R5_1_SLEEP); + +/* + * FIXME: PM Init Disables the wakes/sleep interrupts + * and enables them when required. For NOW, it works, but in future + * all modules should use Register/DeRegister Event + */ + XPfw_PmInit(); +} +#endif + +#ifdef ENABLE_EM +void EmEventHandler(const XPfw_Module_t *ModPtr, u32 EventId) +{ + switch (EventId) { + case XPFW_EV_ERROR_1: + XPfw_ErrorHandlerOne(); + break; + case XPFW_EV_ERROR_2: + XPfw_ErrorHandlerTwo(); + break; + default: + fw_printf("EM:Unhandled Event(ID:%d)\r\n", EventId); + break; + } + +} + +void EmCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len) +{ + + (void)XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_ERROR_1); + (void)XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_ERROR_2); + XPfw_ErrorHandlerInit(); + fw_printf("EM (MOD-%d): Initialized.\r\n", ModPtr->ModId); +} + +#endif + +#ifdef ENABLE_RTC_TEST + +void RtcEventHandler(const XPfw_Module_t *ModPtr, u32 EventId) +{ + + fw_printf("MOD%d:EVENTID: %d\r\n", ModPtr->ModId, EventId); + //XPfw_CorePrintStats(); + if(XPFW_EV_RTC_SECONDS == EventId){ + /* Ack the Int in RTC Module */ + Xil_Out32(RTC_RTC_INT_STATUS,1U); + fw_printf("RTC: %d \r\n", Xil_In32(RTC_CURRENT_TIME)); + + } +} + + + +void RtcCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len) +{ + XPfw_CoreRegisterEvent(ModPtr,XPFW_EV_RTC_SECONDS); + /* Enable Seconds Alarm */ + Xil_Out32(RTC_RTC_INT_EN,1U); + Xil_Out32(RTC_RTC_INT_STATUS,1U); + fw_printf("RTC (MOD-%d): Initialized.\r\n", ModPtr->ModId); +} + +#endif + +#ifdef ENABLE_SCHEDULER +void SchCfgInit(const XPfw_Module_t *ModPtr, const u32 *CfgData, u32 Len) +{ + /* Task every 5 seconds - For our convenience in manual testing */ + fw_printf("Adding Task1 - Status: %d\n", XPfw_CoreScheduleTask(ModPtr,5000U, PrintMsg1)); + /* Every 10 seconds */ + fw_printf("Adding Task2 - Status:%d\n", XPfw_CoreScheduleTask(ModPtr,10000U, PrintMsg2)); +} +#endif + + +void XPfw_UserStartUp(void) +{ +#ifdef ENABLE_PM + const XPfw_Module_t *PmModPtr; +#endif + +#ifdef ENABLE_RTC_TEST + const XPfw_Module_t *RtcModPtr; +#endif + +#ifdef ENABLE_EM + const XPfw_Module_t *EmModPtr; +#endif + +#ifdef ENABLE_SCHEDULER + const XPfw_Module_t *SchModPtr; +#endif + +#ifdef ENABLE_RTC_TEST + RtcModPtr = XPfw_CoreCreateMod(); + (void)XPfw_CoreSetCfgHandler(RtcModPtr,RtcCfgInit); + (void)XPfw_CoreSetEventHandler(RtcModPtr,RtcEventHandler); +#endif + +#ifdef ENABLE_EM + EmModPtr = XPfw_CoreCreateMod(); + (void)XPfw_CoreSetCfgHandler(EmModPtr,EmCfgInit); + (void)XPfw_CoreSetEventHandler(EmModPtr,EmEventHandler); +#endif + +#ifdef ENABLE_PM + PmModPtr = XPfw_CoreCreateMod(); + (void)XPfw_CoreSetCfgHandler(PmModPtr,PmCfgInit); + (void)XPfw_CoreSetEventHandler(PmModPtr,PmEventHandler); + (void)XPfw_CoreSetIpiHandler(PmModPtr,PmIpiHandler,0U); + +#endif + + + + +#ifdef ENABLE_SCHEDULER + SchModPtr = XPfw_CoreCreateMod(); + (void)XPfw_CoreSetCfgHandler(SchModPtr,SchCfgInit); +#endif + + +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.h new file mode 100644 index 00000000..0dee4640 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef XPFW_USER_STARTUP_H_ +#define XPFW_USER_STARTUP_H_ + +void XPfw_UserStartUp(void); + +#endif /* XPFW_USER_STARTUP_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.c b/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.c new file mode 100644 index 00000000..28c84ead --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xil_io.h" +#include "xpfw_util.h" + +void XPfw_UtilRMW(u32 RegAddress, u32 Mask, u32 Value) +{ + u32 l_Val; + + l_Val = Xil_In32(RegAddress); + l_Val = (l_Val & (~Mask)) | (Mask & Value); + + Xil_Out32(RegAddress, l_Val); +} + +XStatus XPfw_UtilPollForMask(u32 RegAddress, u32 Mask, u32 TimeOutCount) +{ + u32 l_RegValue; + u32 TimeOut = TimeOutCount; + /** + * Read the Register value + */ + l_RegValue = Xil_In32(RegAddress); + /** + * Loop while the MAsk is not set or we timeout + */ + while(((l_RegValue & Mask) != Mask) && (TimeOut > 0U)){ + /** + * Latch up the Register value again + */ + l_RegValue = Xil_In32(RegAddress); + /** + * Decrement the TimeOut Count + */ + TimeOut--; + } + + return ((TimeOut == 0U) ? XST_FAILURE : XST_SUCCESS); + +} + +XStatus XPfw_UtilPollForZero(u32 RegAddress, u32 Mask, u32 TimeOutCount) +{ + u32 l_RegValue; + u32 TimeOut = TimeOutCount; + + l_RegValue = Xil_In32(RegAddress); + /** + * Loop until all bits defined by mask are cleared + * or we time out + */ + while (((l_RegValue & Mask) != 0U) && (TimeOut > 0U)) { + /** + * Latch up the reg value again + */ + l_RegValue = Xil_In32(RegAddress); + /** + * Decrement the timeout count + */ + TimeOut--; + } + + return ((TimeOut == 0U) ? XST_FAILURE : XST_SUCCESS); + +} + +void XPfw_UtilWait(u32 TimeOutCount) +{ + u32 TimeOut = TimeOutCount; + while (TimeOut > 0U) { + TimeOut--; + } +} diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.h new file mode 100644 index 00000000..9fddcb63 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_util.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef XPFW_UTIL_H_ +#define XPFW_UTIL_H_ + + +#include "xil_types.h" +#include "xstatus.h" + + +/** + * Read Modify Write a register + */ +void XPfw_UtilRMW(u32 RegAddress, u32 Mask, u32 Value); + +/** + * Poll for a set of bits to be set (represented by Mask) + * or until we TimeOut + * @param RegAddress is the Address of the Register to be polled + * @param Mask is the bit mask to poll for in the register value + * @param TimeOutCount is the value to count down before return failure + */ +XStatus XPfw_UtilPollForMask(u32 RegAddress, u32 Mask, u32 TimeOutCount); + +/** + * Poll for a set of bits to be cleared (represented by Mask) + * or until we TimeOut + * + * @param RegAddress is the Address of the Register to be polled + * @param Mask is the bit mask to poll for in the register value + * @param TimeOutCount is the value to count down before return failure + */ +XStatus XPfw_UtilPollForZero(u32 RegAddress, u32 Mask, u32 TimeOutCount); + + +/** + * Wait for a period represented by TimeOut + * FIXME: Make it more meaningful. Clock Cycles or MilliSeconds + * + * @param Timeout is the value to count before we return this function + */ +void XPfw_UtilWait(u32 TimeOutCount); + + +#endif /* XPFW_UTIL_H_ */ diff --git a/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h b/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h new file mode 100644 index 00000000..883a0ce8 --- /dev/null +++ b/lib/sw_apps/zynqmp_pmufw/src/xpfw_version.h @@ -0,0 +1,4 @@ +#ifndef ZYNQMP_XPFW_VERSION__H_ +#define ZYNQMP_XPFW_VERSION__H_ +#define ZYNQMP_XPFW_VERSION "51ced25" +#endif