diff --git a/lib/bsp/standalone/data/standalone.tcl b/lib/bsp/standalone/data/standalone.tcl index e0a13e1a..1f7e3351 100644 --- a/lib/bsp/standalone/data/standalone.tcl +++ b/lib/bsp/standalone/data/standalone.tcl @@ -119,6 +119,7 @@ proc generate {os_handle} { } "psu_cortexr5" { set procdrv [hsi::get_sw_processor] + set includedir "./src/cortexa53/includes_ps" set ccdir "./src/cortexr5/gcc" foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] { file copy -force $entry "./src/" @@ -126,7 +127,7 @@ proc generate {os_handle} { foreach entry [glob -nocomplain [file join $ccdir *]] { file copy -force $entry "./src/" } - + file copy -force $includedir "./src/" file delete -force "./src/gcc" file delete -force "./src/profile" if { $enable_sw_profile == "true" } { diff --git a/lib/bsp/standalone/src/cortexr5/gcc/Makefile b/lib/bsp/standalone/src/cortexr5/gcc/Makefile index 3a5c8c6a..061e96fa 100644 --- a/lib/bsp/standalone/src/cortexr5/gcc/Makefile +++ b/lib/bsp/standalone/src/cortexr5/gcc/Makefile @@ -59,6 +59,7 @@ INCLUDES=-I./. -I${INCLUDEDIR} OUTS = *.o INCLUDEFILES=*.h +INCLUDEFILES+=includes_ps/*.h libs: $(LIBS) diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h deleted file mode 100644 index 9029bead..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu0_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU0_CFG_H__ -#define __XDDR_XMPU0_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu0Cfg Base Address - */ -#define XDDR_XMPU0_CFG_BASEADDR 0xFD000000UL - -/** - * Register: XddrXmpu0CfgCtrl - */ -#define XDDR_XMPU0_CFG_CTRL ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU0_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu0CfgErrSts1 - */ -#define XDDR_XMPU0_CFG_ERR_STS1 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgErrSts2 - */ -#define XDDR_XMPU0_CFG_ERR_STS2 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgPoison - */ -#define XDDR_XMPU0_CFG_POISON ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU0_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU0_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgIsr - */ -#define XDDR_XMPU0_CFG_ISR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU0_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgImr - */ -#define XDDR_XMPU0_CFG_IMR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU0_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu0CfgIen - */ -#define XDDR_XMPU0_CFG_IEN ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU0_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgIds - */ -#define XDDR_XMPU0_CFG_IDS ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU0_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgLock - */ -#define XDDR_XMPU0_CFG_LOCK ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU0_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR00Strt - */ -#define XDDR_XMPU0_CFG_R00_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR00End - */ -#define XDDR_XMPU0_CFG_R00_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU0_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR00Mstr - */ -#define XDDR_XMPU0_CFG_R00_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR00 - */ -#define XDDR_XMPU0_CFG_R00 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU0_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR01Strt - */ -#define XDDR_XMPU0_CFG_R01_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR01End - */ -#define XDDR_XMPU0_CFG_R01_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU0_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR01Mstr - */ -#define XDDR_XMPU0_CFG_R01_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR01 - */ -#define XDDR_XMPU0_CFG_R01 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU0_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR02Strt - */ -#define XDDR_XMPU0_CFG_R02_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR02End - */ -#define XDDR_XMPU0_CFG_R02_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU0_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR02Mstr - */ -#define XDDR_XMPU0_CFG_R02_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR02 - */ -#define XDDR_XMPU0_CFG_R02 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU0_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR03Strt - */ -#define XDDR_XMPU0_CFG_R03_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR03End - */ -#define XDDR_XMPU0_CFG_R03_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU0_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR03Mstr - */ -#define XDDR_XMPU0_CFG_R03_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR03 - */ -#define XDDR_XMPU0_CFG_R03 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU0_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR04Strt - */ -#define XDDR_XMPU0_CFG_R04_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR04End - */ -#define XDDR_XMPU0_CFG_R04_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU0_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR04Mstr - */ -#define XDDR_XMPU0_CFG_R04_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR04 - */ -#define XDDR_XMPU0_CFG_R04 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU0_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR05Strt - */ -#define XDDR_XMPU0_CFG_R05_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR05End - */ -#define XDDR_XMPU0_CFG_R05_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU0_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR05Mstr - */ -#define XDDR_XMPU0_CFG_R05_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR05 - */ -#define XDDR_XMPU0_CFG_R05 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU0_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR06Strt - */ -#define XDDR_XMPU0_CFG_R06_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR06End - */ -#define XDDR_XMPU0_CFG_R06_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU0_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR06Mstr - */ -#define XDDR_XMPU0_CFG_R06_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR06 - */ -#define XDDR_XMPU0_CFG_R06 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU0_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR07Strt - */ -#define XDDR_XMPU0_CFG_R07_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR07End - */ -#define XDDR_XMPU0_CFG_R07_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU0_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR07Mstr - */ -#define XDDR_XMPU0_CFG_R07_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR07 - */ -#define XDDR_XMPU0_CFG_R07 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU0_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR08Strt - */ -#define XDDR_XMPU0_CFG_R08_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR08End - */ -#define XDDR_XMPU0_CFG_R08_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU0_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR08Mstr - */ -#define XDDR_XMPU0_CFG_R08_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR08 - */ -#define XDDR_XMPU0_CFG_R08 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU0_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR09Strt - */ -#define XDDR_XMPU0_CFG_R09_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR09End - */ -#define XDDR_XMPU0_CFG_R09_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU0_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR09Mstr - */ -#define XDDR_XMPU0_CFG_R09_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR09 - */ -#define XDDR_XMPU0_CFG_R09 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU0_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR10Strt - */ -#define XDDR_XMPU0_CFG_R10_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR10End - */ -#define XDDR_XMPU0_CFG_R10_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU0_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR10Mstr - */ -#define XDDR_XMPU0_CFG_R10_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR10 - */ -#define XDDR_XMPU0_CFG_R10 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU0_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR11Strt - */ -#define XDDR_XMPU0_CFG_R11_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR11End - */ -#define XDDR_XMPU0_CFG_R11_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU0_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR11Mstr - */ -#define XDDR_XMPU0_CFG_R11_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR11 - */ -#define XDDR_XMPU0_CFG_R11 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU0_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR12Strt - */ -#define XDDR_XMPU0_CFG_R12_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR12End - */ -#define XDDR_XMPU0_CFG_R12_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU0_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR12Mstr - */ -#define XDDR_XMPU0_CFG_R12_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR12 - */ -#define XDDR_XMPU0_CFG_R12 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU0_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR13Strt - */ -#define XDDR_XMPU0_CFG_R13_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR13End - */ -#define XDDR_XMPU0_CFG_R13_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU0_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR13Mstr - */ -#define XDDR_XMPU0_CFG_R13_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR13 - */ -#define XDDR_XMPU0_CFG_R13 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU0_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR14Strt - */ -#define XDDR_XMPU0_CFG_R14_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR14End - */ -#define XDDR_XMPU0_CFG_R14_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU0_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR14Mstr - */ -#define XDDR_XMPU0_CFG_R14_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR14 - */ -#define XDDR_XMPU0_CFG_R14 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU0_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR15Strt - */ -#define XDDR_XMPU0_CFG_R15_STRT ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR15End - */ -#define XDDR_XMPU0_CFG_R15_END ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU0_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR15Mstr - */ -#define XDDR_XMPU0_CFG_R15_MSTR ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu0CfgR15 - */ -#define XDDR_XMPU0_CFG_R15 ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU0_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU0_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU0_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU0_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU0_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU0_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU0_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU0_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h deleted file mode 100644 index e2fa6d4a..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu1_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU1_CFG_H__ -#define __XDDR_XMPU1_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu1Cfg Base Address - */ -#define XDDR_XMPU1_CFG_BASEADDR 0xFD010000UL - -/** - * Register: XddrXmpu1CfgCtrl - */ -#define XDDR_XMPU1_CFG_CTRL ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU1_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu1CfgErrSts1 - */ -#define XDDR_XMPU1_CFG_ERR_STS1 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgErrSts2 - */ -#define XDDR_XMPU1_CFG_ERR_STS2 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgPoison - */ -#define XDDR_XMPU1_CFG_POISON ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU1_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU1_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgIsr - */ -#define XDDR_XMPU1_CFG_ISR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU1_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgImr - */ -#define XDDR_XMPU1_CFG_IMR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU1_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu1CfgIen - */ -#define XDDR_XMPU1_CFG_IEN ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU1_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgIds - */ -#define XDDR_XMPU1_CFG_IDS ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU1_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgLock - */ -#define XDDR_XMPU1_CFG_LOCK ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU1_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR00Strt - */ -#define XDDR_XMPU1_CFG_R00_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR00End - */ -#define XDDR_XMPU1_CFG_R00_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU1_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR00Mstr - */ -#define XDDR_XMPU1_CFG_R00_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR00 - */ -#define XDDR_XMPU1_CFG_R00 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU1_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR01Strt - */ -#define XDDR_XMPU1_CFG_R01_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR01End - */ -#define XDDR_XMPU1_CFG_R01_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU1_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR01Mstr - */ -#define XDDR_XMPU1_CFG_R01_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR01 - */ -#define XDDR_XMPU1_CFG_R01 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU1_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR02Strt - */ -#define XDDR_XMPU1_CFG_R02_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR02End - */ -#define XDDR_XMPU1_CFG_R02_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU1_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR02Mstr - */ -#define XDDR_XMPU1_CFG_R02_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR02 - */ -#define XDDR_XMPU1_CFG_R02 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU1_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR03Strt - */ -#define XDDR_XMPU1_CFG_R03_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR03End - */ -#define XDDR_XMPU1_CFG_R03_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU1_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR03Mstr - */ -#define XDDR_XMPU1_CFG_R03_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR03 - */ -#define XDDR_XMPU1_CFG_R03 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU1_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR04Strt - */ -#define XDDR_XMPU1_CFG_R04_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR04End - */ -#define XDDR_XMPU1_CFG_R04_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU1_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR04Mstr - */ -#define XDDR_XMPU1_CFG_R04_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR04 - */ -#define XDDR_XMPU1_CFG_R04 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU1_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR05Strt - */ -#define XDDR_XMPU1_CFG_R05_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR05End - */ -#define XDDR_XMPU1_CFG_R05_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU1_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR05Mstr - */ -#define XDDR_XMPU1_CFG_R05_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR05 - */ -#define XDDR_XMPU1_CFG_R05 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU1_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR06Strt - */ -#define XDDR_XMPU1_CFG_R06_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR06End - */ -#define XDDR_XMPU1_CFG_R06_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU1_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR06Mstr - */ -#define XDDR_XMPU1_CFG_R06_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR06 - */ -#define XDDR_XMPU1_CFG_R06 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU1_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR07Strt - */ -#define XDDR_XMPU1_CFG_R07_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR07End - */ -#define XDDR_XMPU1_CFG_R07_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU1_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR07Mstr - */ -#define XDDR_XMPU1_CFG_R07_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR07 - */ -#define XDDR_XMPU1_CFG_R07 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU1_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR08Strt - */ -#define XDDR_XMPU1_CFG_R08_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR08End - */ -#define XDDR_XMPU1_CFG_R08_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU1_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR08Mstr - */ -#define XDDR_XMPU1_CFG_R08_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR08 - */ -#define XDDR_XMPU1_CFG_R08 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU1_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR09Strt - */ -#define XDDR_XMPU1_CFG_R09_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR09End - */ -#define XDDR_XMPU1_CFG_R09_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU1_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR09Mstr - */ -#define XDDR_XMPU1_CFG_R09_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR09 - */ -#define XDDR_XMPU1_CFG_R09 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU1_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR10Strt - */ -#define XDDR_XMPU1_CFG_R10_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR10End - */ -#define XDDR_XMPU1_CFG_R10_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU1_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR10Mstr - */ -#define XDDR_XMPU1_CFG_R10_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR10 - */ -#define XDDR_XMPU1_CFG_R10 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU1_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR11Strt - */ -#define XDDR_XMPU1_CFG_R11_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR11End - */ -#define XDDR_XMPU1_CFG_R11_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU1_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR11Mstr - */ -#define XDDR_XMPU1_CFG_R11_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR11 - */ -#define XDDR_XMPU1_CFG_R11 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU1_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR12Strt - */ -#define XDDR_XMPU1_CFG_R12_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR12End - */ -#define XDDR_XMPU1_CFG_R12_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU1_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR12Mstr - */ -#define XDDR_XMPU1_CFG_R12_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR12 - */ -#define XDDR_XMPU1_CFG_R12 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU1_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR13Strt - */ -#define XDDR_XMPU1_CFG_R13_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR13End - */ -#define XDDR_XMPU1_CFG_R13_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU1_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR13Mstr - */ -#define XDDR_XMPU1_CFG_R13_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR13 - */ -#define XDDR_XMPU1_CFG_R13 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU1_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR14Strt - */ -#define XDDR_XMPU1_CFG_R14_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR14End - */ -#define XDDR_XMPU1_CFG_R14_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU1_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR14Mstr - */ -#define XDDR_XMPU1_CFG_R14_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR14 - */ -#define XDDR_XMPU1_CFG_R14 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU1_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR15Strt - */ -#define XDDR_XMPU1_CFG_R15_STRT ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR15End - */ -#define XDDR_XMPU1_CFG_R15_END ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU1_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR15Mstr - */ -#define XDDR_XMPU1_CFG_R15_MSTR ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu1CfgR15 - */ -#define XDDR_XMPU1_CFG_R15 ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU1_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU1_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU1_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU1_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU1_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU1_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU1_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU1_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h deleted file mode 100644 index 55ea2a7d..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu2_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU2_CFG_H__ -#define __XDDR_XMPU2_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu2Cfg Base Address - */ -#define XDDR_XMPU2_CFG_BASEADDR 0xFD020000UL - -/** - * Register: XddrXmpu2CfgCtrl - */ -#define XDDR_XMPU2_CFG_CTRL ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU2_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu2CfgErrSts1 - */ -#define XDDR_XMPU2_CFG_ERR_STS1 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgErrSts2 - */ -#define XDDR_XMPU2_CFG_ERR_STS2 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgPoison - */ -#define XDDR_XMPU2_CFG_POISON ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU2_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU2_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgIsr - */ -#define XDDR_XMPU2_CFG_ISR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU2_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgImr - */ -#define XDDR_XMPU2_CFG_IMR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU2_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu2CfgIen - */ -#define XDDR_XMPU2_CFG_IEN ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU2_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgIds - */ -#define XDDR_XMPU2_CFG_IDS ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU2_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgLock - */ -#define XDDR_XMPU2_CFG_LOCK ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU2_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR00Strt - */ -#define XDDR_XMPU2_CFG_R00_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR00End - */ -#define XDDR_XMPU2_CFG_R00_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU2_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR00Mstr - */ -#define XDDR_XMPU2_CFG_R00_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR00 - */ -#define XDDR_XMPU2_CFG_R00 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU2_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR01Strt - */ -#define XDDR_XMPU2_CFG_R01_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR01End - */ -#define XDDR_XMPU2_CFG_R01_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU2_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR01Mstr - */ -#define XDDR_XMPU2_CFG_R01_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR01 - */ -#define XDDR_XMPU2_CFG_R01 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU2_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR02Strt - */ -#define XDDR_XMPU2_CFG_R02_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR02End - */ -#define XDDR_XMPU2_CFG_R02_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU2_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR02Mstr - */ -#define XDDR_XMPU2_CFG_R02_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR02 - */ -#define XDDR_XMPU2_CFG_R02 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU2_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR03Strt - */ -#define XDDR_XMPU2_CFG_R03_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR03End - */ -#define XDDR_XMPU2_CFG_R03_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU2_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR03Mstr - */ -#define XDDR_XMPU2_CFG_R03_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR03 - */ -#define XDDR_XMPU2_CFG_R03 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU2_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR04Strt - */ -#define XDDR_XMPU2_CFG_R04_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR04End - */ -#define XDDR_XMPU2_CFG_R04_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU2_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR04Mstr - */ -#define XDDR_XMPU2_CFG_R04_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR04 - */ -#define XDDR_XMPU2_CFG_R04 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU2_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR05Strt - */ -#define XDDR_XMPU2_CFG_R05_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR05End - */ -#define XDDR_XMPU2_CFG_R05_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU2_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR05Mstr - */ -#define XDDR_XMPU2_CFG_R05_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR05 - */ -#define XDDR_XMPU2_CFG_R05 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU2_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR06Strt - */ -#define XDDR_XMPU2_CFG_R06_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR06End - */ -#define XDDR_XMPU2_CFG_R06_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU2_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR06Mstr - */ -#define XDDR_XMPU2_CFG_R06_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR06 - */ -#define XDDR_XMPU2_CFG_R06 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU2_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR07Strt - */ -#define XDDR_XMPU2_CFG_R07_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR07End - */ -#define XDDR_XMPU2_CFG_R07_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU2_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR07Mstr - */ -#define XDDR_XMPU2_CFG_R07_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR07 - */ -#define XDDR_XMPU2_CFG_R07 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU2_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR08Strt - */ -#define XDDR_XMPU2_CFG_R08_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR08End - */ -#define XDDR_XMPU2_CFG_R08_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU2_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR08Mstr - */ -#define XDDR_XMPU2_CFG_R08_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR08 - */ -#define XDDR_XMPU2_CFG_R08 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU2_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR09Strt - */ -#define XDDR_XMPU2_CFG_R09_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR09End - */ -#define XDDR_XMPU2_CFG_R09_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU2_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR09Mstr - */ -#define XDDR_XMPU2_CFG_R09_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR09 - */ -#define XDDR_XMPU2_CFG_R09 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU2_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR10Strt - */ -#define XDDR_XMPU2_CFG_R10_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR10End - */ -#define XDDR_XMPU2_CFG_R10_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU2_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR10Mstr - */ -#define XDDR_XMPU2_CFG_R10_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR10 - */ -#define XDDR_XMPU2_CFG_R10 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU2_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR11Strt - */ -#define XDDR_XMPU2_CFG_R11_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR11End - */ -#define XDDR_XMPU2_CFG_R11_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU2_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR11Mstr - */ -#define XDDR_XMPU2_CFG_R11_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR11 - */ -#define XDDR_XMPU2_CFG_R11 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU2_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR12Strt - */ -#define XDDR_XMPU2_CFG_R12_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR12End - */ -#define XDDR_XMPU2_CFG_R12_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU2_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR12Mstr - */ -#define XDDR_XMPU2_CFG_R12_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR12 - */ -#define XDDR_XMPU2_CFG_R12 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU2_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR13Strt - */ -#define XDDR_XMPU2_CFG_R13_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR13End - */ -#define XDDR_XMPU2_CFG_R13_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU2_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR13Mstr - */ -#define XDDR_XMPU2_CFG_R13_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR13 - */ -#define XDDR_XMPU2_CFG_R13 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU2_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR14Strt - */ -#define XDDR_XMPU2_CFG_R14_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR14End - */ -#define XDDR_XMPU2_CFG_R14_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU2_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR14Mstr - */ -#define XDDR_XMPU2_CFG_R14_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR14 - */ -#define XDDR_XMPU2_CFG_R14 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU2_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR15Strt - */ -#define XDDR_XMPU2_CFG_R15_STRT ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR15End - */ -#define XDDR_XMPU2_CFG_R15_END ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU2_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR15Mstr - */ -#define XDDR_XMPU2_CFG_R15_MSTR ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu2CfgR15 - */ -#define XDDR_XMPU2_CFG_R15 ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU2_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU2_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU2_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU2_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU2_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU2_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU2_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU2_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h deleted file mode 100644 index 41631496..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu3_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU3_CFG_H__ -#define __XDDR_XMPU3_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu3Cfg Base Address - */ -#define XDDR_XMPU3_CFG_BASEADDR 0xFD030000UL - -/** - * Register: XddrXmpu3CfgCtrl - */ -#define XDDR_XMPU3_CFG_CTRL ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU3_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu3CfgErrSts1 - */ -#define XDDR_XMPU3_CFG_ERR_STS1 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgErrSts2 - */ -#define XDDR_XMPU3_CFG_ERR_STS2 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgPoison - */ -#define XDDR_XMPU3_CFG_POISON ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU3_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU3_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgIsr - */ -#define XDDR_XMPU3_CFG_ISR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU3_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgImr - */ -#define XDDR_XMPU3_CFG_IMR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU3_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu3CfgIen - */ -#define XDDR_XMPU3_CFG_IEN ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU3_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgIds - */ -#define XDDR_XMPU3_CFG_IDS ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU3_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgLock - */ -#define XDDR_XMPU3_CFG_LOCK ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU3_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR00Strt - */ -#define XDDR_XMPU3_CFG_R00_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR00End - */ -#define XDDR_XMPU3_CFG_R00_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU3_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR00Mstr - */ -#define XDDR_XMPU3_CFG_R00_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR00 - */ -#define XDDR_XMPU3_CFG_R00 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU3_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR01Strt - */ -#define XDDR_XMPU3_CFG_R01_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR01End - */ -#define XDDR_XMPU3_CFG_R01_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU3_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR01Mstr - */ -#define XDDR_XMPU3_CFG_R01_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR01 - */ -#define XDDR_XMPU3_CFG_R01 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU3_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR02Strt - */ -#define XDDR_XMPU3_CFG_R02_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR02End - */ -#define XDDR_XMPU3_CFG_R02_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU3_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR02Mstr - */ -#define XDDR_XMPU3_CFG_R02_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR02 - */ -#define XDDR_XMPU3_CFG_R02 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU3_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR03Strt - */ -#define XDDR_XMPU3_CFG_R03_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR03End - */ -#define XDDR_XMPU3_CFG_R03_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU3_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR03Mstr - */ -#define XDDR_XMPU3_CFG_R03_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR03 - */ -#define XDDR_XMPU3_CFG_R03 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU3_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR04Strt - */ -#define XDDR_XMPU3_CFG_R04_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR04End - */ -#define XDDR_XMPU3_CFG_R04_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU3_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR04Mstr - */ -#define XDDR_XMPU3_CFG_R04_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR04 - */ -#define XDDR_XMPU3_CFG_R04 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU3_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR05Strt - */ -#define XDDR_XMPU3_CFG_R05_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR05End - */ -#define XDDR_XMPU3_CFG_R05_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU3_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR05Mstr - */ -#define XDDR_XMPU3_CFG_R05_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR05 - */ -#define XDDR_XMPU3_CFG_R05 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU3_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR06Strt - */ -#define XDDR_XMPU3_CFG_R06_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR06End - */ -#define XDDR_XMPU3_CFG_R06_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU3_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR06Mstr - */ -#define XDDR_XMPU3_CFG_R06_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR06 - */ -#define XDDR_XMPU3_CFG_R06 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU3_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR07Strt - */ -#define XDDR_XMPU3_CFG_R07_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR07End - */ -#define XDDR_XMPU3_CFG_R07_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU3_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR07Mstr - */ -#define XDDR_XMPU3_CFG_R07_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR07 - */ -#define XDDR_XMPU3_CFG_R07 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU3_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR08Strt - */ -#define XDDR_XMPU3_CFG_R08_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR08End - */ -#define XDDR_XMPU3_CFG_R08_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU3_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR08Mstr - */ -#define XDDR_XMPU3_CFG_R08_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR08 - */ -#define XDDR_XMPU3_CFG_R08 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU3_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR09Strt - */ -#define XDDR_XMPU3_CFG_R09_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR09End - */ -#define XDDR_XMPU3_CFG_R09_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU3_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR09Mstr - */ -#define XDDR_XMPU3_CFG_R09_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR09 - */ -#define XDDR_XMPU3_CFG_R09 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU3_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR10Strt - */ -#define XDDR_XMPU3_CFG_R10_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR10End - */ -#define XDDR_XMPU3_CFG_R10_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU3_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR10Mstr - */ -#define XDDR_XMPU3_CFG_R10_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR10 - */ -#define XDDR_XMPU3_CFG_R10 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU3_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR11Strt - */ -#define XDDR_XMPU3_CFG_R11_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR11End - */ -#define XDDR_XMPU3_CFG_R11_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU3_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR11Mstr - */ -#define XDDR_XMPU3_CFG_R11_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR11 - */ -#define XDDR_XMPU3_CFG_R11 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU3_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR12Strt - */ -#define XDDR_XMPU3_CFG_R12_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR12End - */ -#define XDDR_XMPU3_CFG_R12_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU3_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR12Mstr - */ -#define XDDR_XMPU3_CFG_R12_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR12 - */ -#define XDDR_XMPU3_CFG_R12 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU3_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR13Strt - */ -#define XDDR_XMPU3_CFG_R13_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR13End - */ -#define XDDR_XMPU3_CFG_R13_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU3_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR13Mstr - */ -#define XDDR_XMPU3_CFG_R13_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR13 - */ -#define XDDR_XMPU3_CFG_R13 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU3_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR14Strt - */ -#define XDDR_XMPU3_CFG_R14_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR14End - */ -#define XDDR_XMPU3_CFG_R14_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU3_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR14Mstr - */ -#define XDDR_XMPU3_CFG_R14_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR14 - */ -#define XDDR_XMPU3_CFG_R14 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU3_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR15Strt - */ -#define XDDR_XMPU3_CFG_R15_STRT ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR15End - */ -#define XDDR_XMPU3_CFG_R15_END ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU3_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR15Mstr - */ -#define XDDR_XMPU3_CFG_R15_MSTR ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu3CfgR15 - */ -#define XDDR_XMPU3_CFG_R15 ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU3_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU3_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU3_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU3_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU3_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU3_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU3_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU3_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h deleted file mode 100644 index 2df81441..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu4_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU4_CFG_H__ -#define __XDDR_XMPU4_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu4Cfg Base Address - */ -#define XDDR_XMPU4_CFG_BASEADDR 0xFD040000UL - -/** - * Register: XddrXmpu4CfgCtrl - */ -#define XDDR_XMPU4_CFG_CTRL ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU4_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu4CfgErrSts1 - */ -#define XDDR_XMPU4_CFG_ERR_STS1 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgErrSts2 - */ -#define XDDR_XMPU4_CFG_ERR_STS2 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgPoison - */ -#define XDDR_XMPU4_CFG_POISON ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU4_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU4_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgIsr - */ -#define XDDR_XMPU4_CFG_ISR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU4_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgImr - */ -#define XDDR_XMPU4_CFG_IMR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU4_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu4CfgIen - */ -#define XDDR_XMPU4_CFG_IEN ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU4_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgIds - */ -#define XDDR_XMPU4_CFG_IDS ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU4_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgLock - */ -#define XDDR_XMPU4_CFG_LOCK ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU4_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR00Strt - */ -#define XDDR_XMPU4_CFG_R00_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR00End - */ -#define XDDR_XMPU4_CFG_R00_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU4_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR00Mstr - */ -#define XDDR_XMPU4_CFG_R00_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR00 - */ -#define XDDR_XMPU4_CFG_R00 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU4_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR01Strt - */ -#define XDDR_XMPU4_CFG_R01_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR01End - */ -#define XDDR_XMPU4_CFG_R01_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU4_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR01Mstr - */ -#define XDDR_XMPU4_CFG_R01_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR01 - */ -#define XDDR_XMPU4_CFG_R01 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU4_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR02Strt - */ -#define XDDR_XMPU4_CFG_R02_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR02End - */ -#define XDDR_XMPU4_CFG_R02_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU4_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR02Mstr - */ -#define XDDR_XMPU4_CFG_R02_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR02 - */ -#define XDDR_XMPU4_CFG_R02 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU4_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR03Strt - */ -#define XDDR_XMPU4_CFG_R03_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR03End - */ -#define XDDR_XMPU4_CFG_R03_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU4_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR03Mstr - */ -#define XDDR_XMPU4_CFG_R03_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR03 - */ -#define XDDR_XMPU4_CFG_R03 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU4_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR04Strt - */ -#define XDDR_XMPU4_CFG_R04_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR04End - */ -#define XDDR_XMPU4_CFG_R04_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU4_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR04Mstr - */ -#define XDDR_XMPU4_CFG_R04_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR04 - */ -#define XDDR_XMPU4_CFG_R04 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU4_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR05Strt - */ -#define XDDR_XMPU4_CFG_R05_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR05End - */ -#define XDDR_XMPU4_CFG_R05_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU4_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR05Mstr - */ -#define XDDR_XMPU4_CFG_R05_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR05 - */ -#define XDDR_XMPU4_CFG_R05 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU4_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR06Strt - */ -#define XDDR_XMPU4_CFG_R06_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR06End - */ -#define XDDR_XMPU4_CFG_R06_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU4_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR06Mstr - */ -#define XDDR_XMPU4_CFG_R06_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR06 - */ -#define XDDR_XMPU4_CFG_R06 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU4_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR07Strt - */ -#define XDDR_XMPU4_CFG_R07_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR07End - */ -#define XDDR_XMPU4_CFG_R07_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU4_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR07Mstr - */ -#define XDDR_XMPU4_CFG_R07_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR07 - */ -#define XDDR_XMPU4_CFG_R07 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU4_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR08Strt - */ -#define XDDR_XMPU4_CFG_R08_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR08End - */ -#define XDDR_XMPU4_CFG_R08_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU4_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR08Mstr - */ -#define XDDR_XMPU4_CFG_R08_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR08 - */ -#define XDDR_XMPU4_CFG_R08 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU4_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR09Strt - */ -#define XDDR_XMPU4_CFG_R09_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR09End - */ -#define XDDR_XMPU4_CFG_R09_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU4_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR09Mstr - */ -#define XDDR_XMPU4_CFG_R09_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR09 - */ -#define XDDR_XMPU4_CFG_R09 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU4_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR10Strt - */ -#define XDDR_XMPU4_CFG_R10_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR10End - */ -#define XDDR_XMPU4_CFG_R10_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU4_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR10Mstr - */ -#define XDDR_XMPU4_CFG_R10_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR10 - */ -#define XDDR_XMPU4_CFG_R10 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU4_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR11Strt - */ -#define XDDR_XMPU4_CFG_R11_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR11End - */ -#define XDDR_XMPU4_CFG_R11_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU4_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR11Mstr - */ -#define XDDR_XMPU4_CFG_R11_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR11 - */ -#define XDDR_XMPU4_CFG_R11 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU4_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR12Strt - */ -#define XDDR_XMPU4_CFG_R12_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR12End - */ -#define XDDR_XMPU4_CFG_R12_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU4_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR12Mstr - */ -#define XDDR_XMPU4_CFG_R12_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR12 - */ -#define XDDR_XMPU4_CFG_R12 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU4_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR13Strt - */ -#define XDDR_XMPU4_CFG_R13_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR13End - */ -#define XDDR_XMPU4_CFG_R13_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU4_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR13Mstr - */ -#define XDDR_XMPU4_CFG_R13_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR13 - */ -#define XDDR_XMPU4_CFG_R13 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU4_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR14Strt - */ -#define XDDR_XMPU4_CFG_R14_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR14End - */ -#define XDDR_XMPU4_CFG_R14_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU4_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR14Mstr - */ -#define XDDR_XMPU4_CFG_R14_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR14 - */ -#define XDDR_XMPU4_CFG_R14 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU4_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR15Strt - */ -#define XDDR_XMPU4_CFG_R15_STRT ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR15End - */ -#define XDDR_XMPU4_CFG_R15_END ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU4_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR15Mstr - */ -#define XDDR_XMPU4_CFG_R15_MSTR ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu4CfgR15 - */ -#define XDDR_XMPU4_CFG_R15 ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU4_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU4_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU4_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU4_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU4_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU4_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU4_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU4_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h b/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h deleted file mode 100644 index 60811718..00000000 --- a/lib/bsp/standalone/src/cortexr5/xddr_xmpu5_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XDDR_XMPU5_CFG_H__ -#define __XDDR_XMPU5_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XddrXmpu5Cfg Base Address - */ -#define XDDR_XMPU5_CFG_BASEADDR 0xFD050000UL - -/** - * Register: XddrXmpu5CfgCtrl - */ -#define XDDR_XMPU5_CFG_CTRL ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL ) -#define XDDR_XMPU5_CFG_CTRL_RSTVAL 0x00000003UL - -#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XddrXmpu5CfgErrSts1 - */ -#define XDDR_XMPU5_CFG_ERR_STS1 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL ) -#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgErrSts2 - */ -#define XDDR_XMPU5_CFG_ERR_STS2 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL ) -#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgPoison - */ -#define XDDR_XMPU5_CFG_POISON ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL ) -#define XDDR_XMPU5_CFG_POISON_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT 20UL -#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH 12UL -#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT 0UL -#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH 20UL -#define XDDR_XMPU5_CFG_POISON_BASE_MASK 0x000fffffUL -#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgIsr - */ -#define XDDR_XMPU5_CFG_ISR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL ) -#define XDDR_XMPU5_CFG_ISR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT 0UL -#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH 1UL -#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgImr - */ -#define XDDR_XMPU5_CFG_IMR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL ) -#define XDDR_XMPU5_CFG_IMR_RSTVAL 0x0000000fUL - -#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT 0UL -#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH 1UL -#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XddrXmpu5CfgIen - */ -#define XDDR_XMPU5_CFG_IEN ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL ) -#define XDDR_XMPU5_CFG_IEN_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT 0UL -#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH 1UL -#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgIds - */ -#define XDDR_XMPU5_CFG_IDS ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL ) -#define XDDR_XMPU5_CFG_IDS_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT 0UL -#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH 1UL -#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgLock - */ -#define XDDR_XMPU5_CFG_LOCK ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL ) -#define XDDR_XMPU5_CFG_LOCK_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR00Strt - */ -#define XDDR_XMPU5_CFG_R00_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL ) -#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR00End - */ -#define XDDR_XMPU5_CFG_R00_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL ) -#define XDDR_XMPU5_CFG_R00_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR00Mstr - */ -#define XDDR_XMPU5_CFG_R00_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL ) -#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR00 - */ -#define XDDR_XMPU5_CFG_R00 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL ) -#define XDDR_XMPU5_CFG_R00_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R00_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R00_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R00_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R00_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R00_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R00_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR01Strt - */ -#define XDDR_XMPU5_CFG_R01_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL ) -#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR01End - */ -#define XDDR_XMPU5_CFG_R01_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL ) -#define XDDR_XMPU5_CFG_R01_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR01Mstr - */ -#define XDDR_XMPU5_CFG_R01_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL ) -#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR01 - */ -#define XDDR_XMPU5_CFG_R01 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL ) -#define XDDR_XMPU5_CFG_R01_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R01_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R01_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R01_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R01_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R01_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R01_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR02Strt - */ -#define XDDR_XMPU5_CFG_R02_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL ) -#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR02End - */ -#define XDDR_XMPU5_CFG_R02_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL ) -#define XDDR_XMPU5_CFG_R02_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR02Mstr - */ -#define XDDR_XMPU5_CFG_R02_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL ) -#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR02 - */ -#define XDDR_XMPU5_CFG_R02 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL ) -#define XDDR_XMPU5_CFG_R02_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R02_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R02_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R02_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R02_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R02_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R02_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR03Strt - */ -#define XDDR_XMPU5_CFG_R03_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL ) -#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR03End - */ -#define XDDR_XMPU5_CFG_R03_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL ) -#define XDDR_XMPU5_CFG_R03_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR03Mstr - */ -#define XDDR_XMPU5_CFG_R03_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL ) -#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR03 - */ -#define XDDR_XMPU5_CFG_R03 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL ) -#define XDDR_XMPU5_CFG_R03_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R03_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R03_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R03_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R03_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R03_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R03_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR04Strt - */ -#define XDDR_XMPU5_CFG_R04_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL ) -#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR04End - */ -#define XDDR_XMPU5_CFG_R04_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL ) -#define XDDR_XMPU5_CFG_R04_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR04Mstr - */ -#define XDDR_XMPU5_CFG_R04_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL ) -#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR04 - */ -#define XDDR_XMPU5_CFG_R04 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL ) -#define XDDR_XMPU5_CFG_R04_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R04_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R04_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R04_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R04_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R04_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R04_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR05Strt - */ -#define XDDR_XMPU5_CFG_R05_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL ) -#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR05End - */ -#define XDDR_XMPU5_CFG_R05_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL ) -#define XDDR_XMPU5_CFG_R05_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR05Mstr - */ -#define XDDR_XMPU5_CFG_R05_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL ) -#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR05 - */ -#define XDDR_XMPU5_CFG_R05 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL ) -#define XDDR_XMPU5_CFG_R05_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R05_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R05_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R05_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R05_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R05_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R05_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR06Strt - */ -#define XDDR_XMPU5_CFG_R06_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL ) -#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR06End - */ -#define XDDR_XMPU5_CFG_R06_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL ) -#define XDDR_XMPU5_CFG_R06_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR06Mstr - */ -#define XDDR_XMPU5_CFG_R06_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL ) -#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR06 - */ -#define XDDR_XMPU5_CFG_R06 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL ) -#define XDDR_XMPU5_CFG_R06_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R06_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R06_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R06_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R06_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R06_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R06_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR07Strt - */ -#define XDDR_XMPU5_CFG_R07_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL ) -#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR07End - */ -#define XDDR_XMPU5_CFG_R07_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL ) -#define XDDR_XMPU5_CFG_R07_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR07Mstr - */ -#define XDDR_XMPU5_CFG_R07_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL ) -#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR07 - */ -#define XDDR_XMPU5_CFG_R07 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL ) -#define XDDR_XMPU5_CFG_R07_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R07_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R07_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R07_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R07_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R07_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R07_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR08Strt - */ -#define XDDR_XMPU5_CFG_R08_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL ) -#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR08End - */ -#define XDDR_XMPU5_CFG_R08_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL ) -#define XDDR_XMPU5_CFG_R08_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR08Mstr - */ -#define XDDR_XMPU5_CFG_R08_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL ) -#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR08 - */ -#define XDDR_XMPU5_CFG_R08 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL ) -#define XDDR_XMPU5_CFG_R08_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R08_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R08_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R08_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R08_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R08_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R08_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR09Strt - */ -#define XDDR_XMPU5_CFG_R09_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL ) -#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR09End - */ -#define XDDR_XMPU5_CFG_R09_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL ) -#define XDDR_XMPU5_CFG_R09_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR09Mstr - */ -#define XDDR_XMPU5_CFG_R09_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL ) -#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR09 - */ -#define XDDR_XMPU5_CFG_R09 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL ) -#define XDDR_XMPU5_CFG_R09_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R09_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R09_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R09_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R09_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R09_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R09_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR10Strt - */ -#define XDDR_XMPU5_CFG_R10_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL ) -#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR10End - */ -#define XDDR_XMPU5_CFG_R10_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL ) -#define XDDR_XMPU5_CFG_R10_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR10Mstr - */ -#define XDDR_XMPU5_CFG_R10_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL ) -#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR10 - */ -#define XDDR_XMPU5_CFG_R10 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL ) -#define XDDR_XMPU5_CFG_R10_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R10_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R10_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R10_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R10_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R10_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R10_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR11Strt - */ -#define XDDR_XMPU5_CFG_R11_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL ) -#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR11End - */ -#define XDDR_XMPU5_CFG_R11_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL ) -#define XDDR_XMPU5_CFG_R11_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR11Mstr - */ -#define XDDR_XMPU5_CFG_R11_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL ) -#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR11 - */ -#define XDDR_XMPU5_CFG_R11 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL ) -#define XDDR_XMPU5_CFG_R11_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R11_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R11_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R11_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R11_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R11_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R11_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR12Strt - */ -#define XDDR_XMPU5_CFG_R12_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL ) -#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR12End - */ -#define XDDR_XMPU5_CFG_R12_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL ) -#define XDDR_XMPU5_CFG_R12_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR12Mstr - */ -#define XDDR_XMPU5_CFG_R12_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL ) -#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR12 - */ -#define XDDR_XMPU5_CFG_R12 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL ) -#define XDDR_XMPU5_CFG_R12_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R12_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R12_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R12_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R12_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R12_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R12_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR13Strt - */ -#define XDDR_XMPU5_CFG_R13_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL ) -#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR13End - */ -#define XDDR_XMPU5_CFG_R13_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL ) -#define XDDR_XMPU5_CFG_R13_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR13Mstr - */ -#define XDDR_XMPU5_CFG_R13_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL ) -#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR13 - */ -#define XDDR_XMPU5_CFG_R13 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL ) -#define XDDR_XMPU5_CFG_R13_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R13_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R13_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R13_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R13_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R13_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R13_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR14Strt - */ -#define XDDR_XMPU5_CFG_R14_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL ) -#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR14End - */ -#define XDDR_XMPU5_CFG_R14_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL ) -#define XDDR_XMPU5_CFG_R14_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR14Mstr - */ -#define XDDR_XMPU5_CFG_R14_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL ) -#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR14 - */ -#define XDDR_XMPU5_CFG_R14 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL ) -#define XDDR_XMPU5_CFG_R14_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R14_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R14_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R14_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R14_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R14_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R14_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR15Strt - */ -#define XDDR_XMPU5_CFG_R15_STRT ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL ) -#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR15End - */ -#define XDDR_XMPU5_CFG_R15_END ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL ) -#define XDDR_XMPU5_CFG_R15_END_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT 0UL -#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH 28UL -#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR15Mstr - */ -#define XDDR_XMPU5_CFG_R15_MSTR ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL ) -#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT 0UL -#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH 16UL -#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XddrXmpu5CfgR15 - */ -#define XDDR_XMPU5_CFG_R15 ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL ) -#define XDDR_XMPU5_CFG_R15_RSTVAL 0x00000008UL - -#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT 3UL -#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH 1UL -#define XDDR_XMPU5_CFG_R15_REGNNS_MASK 0x00000008UL -#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT 2UL -#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R15_WRALWD_MASK 0x00000004UL -#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT 1UL -#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH 1UL -#define XDDR_XMPU5_CFG_R15_RDALWD_MASK 0x00000002UL -#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XDDR_XMPU5_CFG_R15_EN_SHIFT 0UL -#define XDDR_XMPU5_CFG_R15_EN_WIDTH 1UL -#define XDDR_XMPU5_CFG_R15_EN_MASK 0x00000001UL -#define XDDR_XMPU5_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XDDR_XMPU5_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h b/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h deleted file mode 100644 index b565b958..00000000 --- a/lib/bsp/standalone/src/cortexr5/xfpd_slcr.h +++ /dev/null @@ -1,382 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XFPD_SLCR_H__ -#define __XFPD_SLCR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XfpdSlcr Base Address - */ -#define XFPD_SLCR_BASEADDR 0xFD610000UL - -/** - * Register: XfpdSlcrWprot0 - */ -#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL ) -#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL - -#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL -#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL -#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL -#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrCtrl - */ -#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL ) -#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL - -#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL -#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL -#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrIsr - */ -#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL ) -#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrImr - */ -#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL ) -#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL - -#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrIer - */ -#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL ) -#define XFPD_SLCR_IER_RSTVAL 0x00000000UL - -#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrIdr - */ -#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL ) -#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrItr - */ -#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL ) -#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrWdtClkSel - */ -#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL ) -#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL - -#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL -#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL -#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL -#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrIntFpd - */ -#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL ) -#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL - -#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL -#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL -#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL -#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrGpu - */ -#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL ) -#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL - -#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL -#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL -#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL -#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL - -#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL -#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL -#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL -#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL - -#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL -#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL -#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL -#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL - -#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL -#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL -#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL -#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL - -#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL -#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL -#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL -#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrGdmaCfg - */ -#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL ) -#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL - -#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL -#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL -#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL -#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL - -#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL -#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL -#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL -#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL - -/** - * Register: XfpdSlcrGdma - */ -#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL ) -#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL - -#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL -#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL -#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL -#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL - -#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL -#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL -#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL -#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL - -#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL -#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL -#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL -#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL - -#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL -#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL -#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL -#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL - -#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL -#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL -#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL -#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL - -#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL -#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL -#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL -#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL - -/** - * Register: XfpdSlcrAfiFs - */ -#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL ) -#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL - -#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL -#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL -#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL -#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL - -#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL -#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL -#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL -#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL - -/** - * Register: XfpdSlcrErrAtbIsr - */ -#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL ) -#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL -#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrErrAtbImr - */ -#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL ) -#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL - -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL - -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL - -#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL -#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrErrAtbIer - */ -#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL ) -#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL -#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrErrAtbIdr - */ -#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL ) -#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL - -#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL -#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL -#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrAtbCmdstore - */ -#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL ) -#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL - -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL - -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL - -#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL -#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL -#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrAtbRespEn - */ -#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL ) -#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL - -#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL - -#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL - -#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL -#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL -#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrAtbResptype - */ -#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL ) -#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL - -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL - -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL -#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL - -#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL -#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL -#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL -#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrAtbPrescale - */ -#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL ) -#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL - -#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL -#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL -#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL -#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL - -#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL -#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL -#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL -#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XFPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h b/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h deleted file mode 100644 index 6541a4f1..00000000 --- a/lib/bsp/standalone/src/cortexr5/xfpd_slcr_secure.h +++ /dev/null @@ -1,277 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XFPD_SLCR_SECURE_H__ -#define __XFPD_SLCR_SECURE_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XfpdSlcrSecure Base Address - */ -#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL - -/** - * Register: XfpdSlcrSecCtrl - */ -#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) -#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL -#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL -#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecIsr - */ -#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) -#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecImr - */ -#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) -#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL - -#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrSecIer - */ -#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) -#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecIdr - */ -#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) -#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecItr - */ -#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) -#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecSata - */ -#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) -#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL - -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL -#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL -#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL -#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL -#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL - -/** - * Register: XfpdSlcrSecPcie - */ -#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) -#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL - -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL -#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL -#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL -#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL -#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL - -#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL -#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL -#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL -#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrSecDpdma - */ -#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL ) -#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL - -#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL -#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL -#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL -#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL - -/** - * Register: XfpdSlcrSecGdma - */ -#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL ) -#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL - -#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL -#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL -#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL -#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL - -/** - * Register: XfpdSlcrSecGic - */ -#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL ) -#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL - -#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL -#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL -#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL -#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XFPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h deleted file mode 100644 index 75aef19f..00000000 --- a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XFPD_XMPU_CFG_H__ -#define __XFPD_XMPU_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XfpdXmpuCfg Base Address - */ -#define XFPD_XMPU_CFG_BASEADDR 0xFD5D0000UL - -/** - * Register: XfpdXmpuCfgCtrl - */ -#define XFPD_XMPU_CFG_CTRL ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL ) -#define XFPD_XMPU_CFG_CTRL_RSTVAL 0x00000003UL - -#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XfpdXmpuCfgErrSts1 - */ -#define XFPD_XMPU_CFG_ERR_STS1 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL ) -#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgErrSts2 - */ -#define XFPD_XMPU_CFG_ERR_STS2 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL ) -#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgPoison - */ -#define XFPD_XMPU_CFG_POISON ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) -#define XFPD_XMPU_CFG_POISON_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL -#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL -#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_POISON_BASE_SHIFT 0UL -#define XFPD_XMPU_CFG_POISON_BASE_WIDTH 20UL -#define XFPD_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL -#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgIsr - */ -#define XFPD_XMPU_CFG_ISR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL ) -#define XFPD_XMPU_CFG_ISR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT 0UL -#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH 1UL -#define XFPD_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgImr - */ -#define XFPD_XMPU_CFG_IMR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL ) -#define XFPD_XMPU_CFG_IMR_RSTVAL 0x0000000fUL - -#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT 0UL -#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH 1UL -#define XFPD_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XfpdXmpuCfgIen - */ -#define XFPD_XMPU_CFG_IEN ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL ) -#define XFPD_XMPU_CFG_IEN_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT 0UL -#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH 1UL -#define XFPD_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgIds - */ -#define XFPD_XMPU_CFG_IDS ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) -#define XFPD_XMPU_CFG_IDS_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT 0UL -#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH 1UL -#define XFPD_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgLock - */ -#define XFPD_XMPU_CFG_LOCK ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL ) -#define XFPD_XMPU_CFG_LOCK_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR00Strt - */ -#define XFPD_XMPU_CFG_R00_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL ) -#define XFPD_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR00End - */ -#define XFPD_XMPU_CFG_R00_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL ) -#define XFPD_XMPU_CFG_R00_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR00Mstr - */ -#define XFPD_XMPU_CFG_R00_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL ) -#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR00 - */ -#define XFPD_XMPU_CFG_R00 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) -#define XFPD_XMPU_CFG_R00_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R00_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R00_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R00_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR01Strt - */ -#define XFPD_XMPU_CFG_R01_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL ) -#define XFPD_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR01End - */ -#define XFPD_XMPU_CFG_R01_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL ) -#define XFPD_XMPU_CFG_R01_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR01Mstr - */ -#define XFPD_XMPU_CFG_R01_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL ) -#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR01 - */ -#define XFPD_XMPU_CFG_R01 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) -#define XFPD_XMPU_CFG_R01_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R01_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R01_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R01_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR02Strt - */ -#define XFPD_XMPU_CFG_R02_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL ) -#define XFPD_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR02End - */ -#define XFPD_XMPU_CFG_R02_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL ) -#define XFPD_XMPU_CFG_R02_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR02Mstr - */ -#define XFPD_XMPU_CFG_R02_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL ) -#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR02 - */ -#define XFPD_XMPU_CFG_R02 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) -#define XFPD_XMPU_CFG_R02_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R02_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R02_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R02_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR03Strt - */ -#define XFPD_XMPU_CFG_R03_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL ) -#define XFPD_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR03End - */ -#define XFPD_XMPU_CFG_R03_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL ) -#define XFPD_XMPU_CFG_R03_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR03Mstr - */ -#define XFPD_XMPU_CFG_R03_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL ) -#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR03 - */ -#define XFPD_XMPU_CFG_R03 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) -#define XFPD_XMPU_CFG_R03_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R03_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R03_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R03_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR04Strt - */ -#define XFPD_XMPU_CFG_R04_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL ) -#define XFPD_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR04End - */ -#define XFPD_XMPU_CFG_R04_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL ) -#define XFPD_XMPU_CFG_R04_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR04Mstr - */ -#define XFPD_XMPU_CFG_R04_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL ) -#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR04 - */ -#define XFPD_XMPU_CFG_R04 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) -#define XFPD_XMPU_CFG_R04_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R04_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R04_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R04_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR05Strt - */ -#define XFPD_XMPU_CFG_R05_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL ) -#define XFPD_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR05End - */ -#define XFPD_XMPU_CFG_R05_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL ) -#define XFPD_XMPU_CFG_R05_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR05Mstr - */ -#define XFPD_XMPU_CFG_R05_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL ) -#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR05 - */ -#define XFPD_XMPU_CFG_R05 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) -#define XFPD_XMPU_CFG_R05_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R05_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R05_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R05_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR06Strt - */ -#define XFPD_XMPU_CFG_R06_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL ) -#define XFPD_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR06End - */ -#define XFPD_XMPU_CFG_R06_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL ) -#define XFPD_XMPU_CFG_R06_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR06Mstr - */ -#define XFPD_XMPU_CFG_R06_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL ) -#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR06 - */ -#define XFPD_XMPU_CFG_R06 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) -#define XFPD_XMPU_CFG_R06_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R06_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R06_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R06_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR07Strt - */ -#define XFPD_XMPU_CFG_R07_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL ) -#define XFPD_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR07End - */ -#define XFPD_XMPU_CFG_R07_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL ) -#define XFPD_XMPU_CFG_R07_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR07Mstr - */ -#define XFPD_XMPU_CFG_R07_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL ) -#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR07 - */ -#define XFPD_XMPU_CFG_R07 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) -#define XFPD_XMPU_CFG_R07_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R07_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R07_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R07_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR08Strt - */ -#define XFPD_XMPU_CFG_R08_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL ) -#define XFPD_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR08End - */ -#define XFPD_XMPU_CFG_R08_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL ) -#define XFPD_XMPU_CFG_R08_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR08Mstr - */ -#define XFPD_XMPU_CFG_R08_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL ) -#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR08 - */ -#define XFPD_XMPU_CFG_R08 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) -#define XFPD_XMPU_CFG_R08_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R08_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R08_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R08_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR09Strt - */ -#define XFPD_XMPU_CFG_R09_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL ) -#define XFPD_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR09End - */ -#define XFPD_XMPU_CFG_R09_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL ) -#define XFPD_XMPU_CFG_R09_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR09Mstr - */ -#define XFPD_XMPU_CFG_R09_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL ) -#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR09 - */ -#define XFPD_XMPU_CFG_R09 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) -#define XFPD_XMPU_CFG_R09_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R09_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R09_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R09_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR10Strt - */ -#define XFPD_XMPU_CFG_R10_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) -#define XFPD_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR10End - */ -#define XFPD_XMPU_CFG_R10_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) -#define XFPD_XMPU_CFG_R10_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR10Mstr - */ -#define XFPD_XMPU_CFG_R10_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) -#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR10 - */ -#define XFPD_XMPU_CFG_R10 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) -#define XFPD_XMPU_CFG_R10_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R10_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R10_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R10_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR11Strt - */ -#define XFPD_XMPU_CFG_R11_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) -#define XFPD_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR11End - */ -#define XFPD_XMPU_CFG_R11_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) -#define XFPD_XMPU_CFG_R11_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR11Mstr - */ -#define XFPD_XMPU_CFG_R11_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) -#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR11 - */ -#define XFPD_XMPU_CFG_R11 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) -#define XFPD_XMPU_CFG_R11_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R11_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R11_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R11_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR12Strt - */ -#define XFPD_XMPU_CFG_R12_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) -#define XFPD_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR12End - */ -#define XFPD_XMPU_CFG_R12_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) -#define XFPD_XMPU_CFG_R12_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR12Mstr - */ -#define XFPD_XMPU_CFG_R12_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) -#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR12 - */ -#define XFPD_XMPU_CFG_R12 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) -#define XFPD_XMPU_CFG_R12_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R12_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R12_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R12_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR13Strt - */ -#define XFPD_XMPU_CFG_R13_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) -#define XFPD_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR13End - */ -#define XFPD_XMPU_CFG_R13_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) -#define XFPD_XMPU_CFG_R13_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR13Mstr - */ -#define XFPD_XMPU_CFG_R13_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) -#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR13 - */ -#define XFPD_XMPU_CFG_R13 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) -#define XFPD_XMPU_CFG_R13_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R13_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R13_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R13_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR14Strt - */ -#define XFPD_XMPU_CFG_R14_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) -#define XFPD_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR14End - */ -#define XFPD_XMPU_CFG_R14_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) -#define XFPD_XMPU_CFG_R14_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR14Mstr - */ -#define XFPD_XMPU_CFG_R14_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) -#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR14 - */ -#define XFPD_XMPU_CFG_R14 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) -#define XFPD_XMPU_CFG_R14_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R14_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R14_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R14_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR15Strt - */ -#define XFPD_XMPU_CFG_R15_STRT ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) -#define XFPD_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR15End - */ -#define XFPD_XMPU_CFG_R15_END ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) -#define XFPD_XMPU_CFG_R15_END_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT 0UL -#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH 28UL -#define XFPD_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR15Mstr - */ -#define XFPD_XMPU_CFG_R15_MSTR ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) -#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL -#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL -#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuCfgR15 - */ -#define XFPD_XMPU_CFG_R15 ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) -#define XFPD_XMPU_CFG_R15_RSTVAL 0x00000008UL - -#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT 3UL -#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH 1UL -#define XFPD_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL -#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT 2UL -#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL -#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT 1UL -#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH 1UL -#define XFPD_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL -#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XFPD_XMPU_CFG_R15_EN_SHIFT 0UL -#define XFPD_XMPU_CFG_R15_EN_WIDTH 1UL -#define XFPD_XMPU_CFG_R15_EN_MASK 0x00000001UL -#define XFPD_XMPU_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XFPD_XMPU_CFG_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h b/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h deleted file mode 100644 index 39172f1f..00000000 --- a/lib/bsp/standalone/src/cortexr5/xfpd_xmpu_sink.h +++ /dev/null @@ -1,81 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XFPD_XMPU_SINK_H__ -#define __XFPD_XMPU_SINK_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XfpdXmpuSink Base Address - */ -#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL - -/** - * Register: XfpdXmpuSinkErrSts - */ -#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL ) -#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL - -#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL -#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL -#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL -#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL - -#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL -#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL -#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL -#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuSinkIsr - */ -#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL ) -#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL -#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL -#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL -#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuSinkImr - */ -#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL ) -#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL - -#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL -#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL -#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL -#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL - -/** - * Register: XfpdXmpuSinkIer - */ -#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL ) -#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL - -#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL -#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL -#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL -#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL - -/** - * Register: XfpdXmpuSinkIdr - */ -#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL ) -#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL - -#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL -#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL -#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL -#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XFPD_XMPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h b/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h deleted file mode 100644 index cb4ad490..00000000 --- a/lib/bsp/standalone/src/cortexr5/xiou_secure_slcr.h +++ /dev/null @@ -1,174 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XIOU_SECURE_SLCR_H__ -#define __XIOU_SECURE_SLCR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XiouSecureSlcr Base Address - */ -#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL - -/** - * Register: XiouSecSlcrAxiWprtcn - */ -#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL ) -#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL -#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrAxiRprtcn - */ -#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL ) -#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL - -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL -#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrCtrl - */ -#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL ) -#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL -#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL -#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrIsr - */ -#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL ) -#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrImr - */ -#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL ) -#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL - -#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XiouSecSlcrIer - */ -#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL ) -#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrIdr - */ -#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL ) -#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSecSlcrItr - */ -#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL ) -#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL - -#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XIOU_SECURE_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xiou_slcr.h b/lib/bsp/standalone/src/cortexr5/xiou_slcr.h deleted file mode 100644 index d81d178d..00000000 --- a/lib/bsp/standalone/src/cortexr5/xiou_slcr.h +++ /dev/null @@ -1,4029 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XIOU_SLCR_H__ -#define __XIOU_SLCR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XiouSlcr Base Address - */ -#define XIOU_SLCR_BASEADDR 0xFF180000UL - -/** - * Register: XiouSlcrMioPin0 - */ -#define XIOU_SLCR_MIO_PIN_0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL ) -#define XIOU_SLCR_MIO_PIN_0_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin1 - */ -#define XIOU_SLCR_MIO_PIN_1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL ) -#define XIOU_SLCR_MIO_PIN_1_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin2 - */ -#define XIOU_SLCR_MIO_PIN_2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL ) -#define XIOU_SLCR_MIO_PIN_2_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin3 - */ -#define XIOU_SLCR_MIO_PIN_3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL ) -#define XIOU_SLCR_MIO_PIN_3_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin4 - */ -#define XIOU_SLCR_MIO_PIN_4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL ) -#define XIOU_SLCR_MIO_PIN_4_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin5 - */ -#define XIOU_SLCR_MIO_PIN_5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL ) -#define XIOU_SLCR_MIO_PIN_5_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin6 - */ -#define XIOU_SLCR_MIO_PIN_6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL ) -#define XIOU_SLCR_MIO_PIN_6_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin7 - */ -#define XIOU_SLCR_MIO_PIN_7 ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL ) -#define XIOU_SLCR_MIO_PIN_7_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin8 - */ -#define XIOU_SLCR_MIO_PIN_8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL ) -#define XIOU_SLCR_MIO_PIN_8_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin9 - */ -#define XIOU_SLCR_MIO_PIN_9 ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL ) -#define XIOU_SLCR_MIO_PIN_9_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin10 - */ -#define XIOU_SLCR_MIO_PIN_10 ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL ) -#define XIOU_SLCR_MIO_PIN_10_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin11 - */ -#define XIOU_SLCR_MIO_PIN_11 ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL ) -#define XIOU_SLCR_MIO_PIN_11_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin12 - */ -#define XIOU_SLCR_MIO_PIN_12 ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL ) -#define XIOU_SLCR_MIO_PIN_12_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin13 - */ -#define XIOU_SLCR_MIO_PIN_13 ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL ) -#define XIOU_SLCR_MIO_PIN_13_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin14 - */ -#define XIOU_SLCR_MIO_PIN_14 ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL ) -#define XIOU_SLCR_MIO_PIN_14_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin15 - */ -#define XIOU_SLCR_MIO_PIN_15 ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL ) -#define XIOU_SLCR_MIO_PIN_15_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin16 - */ -#define XIOU_SLCR_MIO_PIN_16 ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL ) -#define XIOU_SLCR_MIO_PIN_16_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin17 - */ -#define XIOU_SLCR_MIO_PIN_17 ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL ) -#define XIOU_SLCR_MIO_PIN_17_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin18 - */ -#define XIOU_SLCR_MIO_PIN_18 ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL ) -#define XIOU_SLCR_MIO_PIN_18_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin19 - */ -#define XIOU_SLCR_MIO_PIN_19 ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL ) -#define XIOU_SLCR_MIO_PIN_19_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin20 - */ -#define XIOU_SLCR_MIO_PIN_20 ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL ) -#define XIOU_SLCR_MIO_PIN_20_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin21 - */ -#define XIOU_SLCR_MIO_PIN_21 ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL ) -#define XIOU_SLCR_MIO_PIN_21_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin22 - */ -#define XIOU_SLCR_MIO_PIN_22 ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL ) -#define XIOU_SLCR_MIO_PIN_22_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin23 - */ -#define XIOU_SLCR_MIO_PIN_23 ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL ) -#define XIOU_SLCR_MIO_PIN_23_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin24 - */ -#define XIOU_SLCR_MIO_PIN_24 ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL ) -#define XIOU_SLCR_MIO_PIN_24_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin25 - */ -#define XIOU_SLCR_MIO_PIN_25 ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL ) -#define XIOU_SLCR_MIO_PIN_25_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin26 - */ -#define XIOU_SLCR_MIO_PIN_26 ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL ) -#define XIOU_SLCR_MIO_PIN_26_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin27 - */ -#define XIOU_SLCR_MIO_PIN_27 ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL ) -#define XIOU_SLCR_MIO_PIN_27_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin28 - */ -#define XIOU_SLCR_MIO_PIN_28 ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL ) -#define XIOU_SLCR_MIO_PIN_28_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin29 - */ -#define XIOU_SLCR_MIO_PIN_29 ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL ) -#define XIOU_SLCR_MIO_PIN_29_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin30 - */ -#define XIOU_SLCR_MIO_PIN_30 ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL ) -#define XIOU_SLCR_MIO_PIN_30_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin31 - */ -#define XIOU_SLCR_MIO_PIN_31 ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL ) -#define XIOU_SLCR_MIO_PIN_31_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin32 - */ -#define XIOU_SLCR_MIO_PIN_32 ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL ) -#define XIOU_SLCR_MIO_PIN_32_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin33 - */ -#define XIOU_SLCR_MIO_PIN_33 ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL ) -#define XIOU_SLCR_MIO_PIN_33_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin34 - */ -#define XIOU_SLCR_MIO_PIN_34 ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL ) -#define XIOU_SLCR_MIO_PIN_34_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin35 - */ -#define XIOU_SLCR_MIO_PIN_35 ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL ) -#define XIOU_SLCR_MIO_PIN_35_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin36 - */ -#define XIOU_SLCR_MIO_PIN_36 ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL ) -#define XIOU_SLCR_MIO_PIN_36_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin37 - */ -#define XIOU_SLCR_MIO_PIN_37 ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL ) -#define XIOU_SLCR_MIO_PIN_37_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin38 - */ -#define XIOU_SLCR_MIO_PIN_38 ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL ) -#define XIOU_SLCR_MIO_PIN_38_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin39 - */ -#define XIOU_SLCR_MIO_PIN_39 ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL ) -#define XIOU_SLCR_MIO_PIN_39_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin40 - */ -#define XIOU_SLCR_MIO_PIN_40 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL ) -#define XIOU_SLCR_MIO_PIN_40_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin41 - */ -#define XIOU_SLCR_MIO_PIN_41 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL ) -#define XIOU_SLCR_MIO_PIN_41_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin42 - */ -#define XIOU_SLCR_MIO_PIN_42 ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL ) -#define XIOU_SLCR_MIO_PIN_42_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin43 - */ -#define XIOU_SLCR_MIO_PIN_43 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL ) -#define XIOU_SLCR_MIO_PIN_43_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin44 - */ -#define XIOU_SLCR_MIO_PIN_44 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL ) -#define XIOU_SLCR_MIO_PIN_44_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin45 - */ -#define XIOU_SLCR_MIO_PIN_45 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL ) -#define XIOU_SLCR_MIO_PIN_45_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin46 - */ -#define XIOU_SLCR_MIO_PIN_46 ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL ) -#define XIOU_SLCR_MIO_PIN_46_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin47 - */ -#define XIOU_SLCR_MIO_PIN_47 ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL ) -#define XIOU_SLCR_MIO_PIN_47_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin48 - */ -#define XIOU_SLCR_MIO_PIN_48 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL ) -#define XIOU_SLCR_MIO_PIN_48_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin49 - */ -#define XIOU_SLCR_MIO_PIN_49 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL ) -#define XIOU_SLCR_MIO_PIN_49_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin50 - */ -#define XIOU_SLCR_MIO_PIN_50 ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL ) -#define XIOU_SLCR_MIO_PIN_50_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin51 - */ -#define XIOU_SLCR_MIO_PIN_51 ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL ) -#define XIOU_SLCR_MIO_PIN_51_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin52 - */ -#define XIOU_SLCR_MIO_PIN_52 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL ) -#define XIOU_SLCR_MIO_PIN_52_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin53 - */ -#define XIOU_SLCR_MIO_PIN_53 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL ) -#define XIOU_SLCR_MIO_PIN_53_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin54 - */ -#define XIOU_SLCR_MIO_PIN_54 ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL ) -#define XIOU_SLCR_MIO_PIN_54_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin55 - */ -#define XIOU_SLCR_MIO_PIN_55 ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL ) -#define XIOU_SLCR_MIO_PIN_55_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin56 - */ -#define XIOU_SLCR_MIO_PIN_56 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL ) -#define XIOU_SLCR_MIO_PIN_56_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin57 - */ -#define XIOU_SLCR_MIO_PIN_57 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL ) -#define XIOU_SLCR_MIO_PIN_57_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin58 - */ -#define XIOU_SLCR_MIO_PIN_58 ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL ) -#define XIOU_SLCR_MIO_PIN_58_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin59 - */ -#define XIOU_SLCR_MIO_PIN_59 ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL ) -#define XIOU_SLCR_MIO_PIN_59_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin60 - */ -#define XIOU_SLCR_MIO_PIN_60 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL ) -#define XIOU_SLCR_MIO_PIN_60_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin61 - */ -#define XIOU_SLCR_MIO_PIN_61 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL ) -#define XIOU_SLCR_MIO_PIN_61_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin62 - */ -#define XIOU_SLCR_MIO_PIN_62 ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL ) -#define XIOU_SLCR_MIO_PIN_62_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin63 - */ -#define XIOU_SLCR_MIO_PIN_63 ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL ) -#define XIOU_SLCR_MIO_PIN_63_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin64 - */ -#define XIOU_SLCR_MIO_PIN_64 ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL ) -#define XIOU_SLCR_MIO_PIN_64_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin65 - */ -#define XIOU_SLCR_MIO_PIN_65 ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL ) -#define XIOU_SLCR_MIO_PIN_65_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin66 - */ -#define XIOU_SLCR_MIO_PIN_66 ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL ) -#define XIOU_SLCR_MIO_PIN_66_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin67 - */ -#define XIOU_SLCR_MIO_PIN_67 ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL ) -#define XIOU_SLCR_MIO_PIN_67_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin68 - */ -#define XIOU_SLCR_MIO_PIN_68 ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL ) -#define XIOU_SLCR_MIO_PIN_68_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin69 - */ -#define XIOU_SLCR_MIO_PIN_69 ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL ) -#define XIOU_SLCR_MIO_PIN_69_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin70 - */ -#define XIOU_SLCR_MIO_PIN_70 ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL ) -#define XIOU_SLCR_MIO_PIN_70_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin71 - */ -#define XIOU_SLCR_MIO_PIN_71 ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL ) -#define XIOU_SLCR_MIO_PIN_71_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin72 - */ -#define XIOU_SLCR_MIO_PIN_72 ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL ) -#define XIOU_SLCR_MIO_PIN_72_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin73 - */ -#define XIOU_SLCR_MIO_PIN_73 ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL ) -#define XIOU_SLCR_MIO_PIN_73_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin74 - */ -#define XIOU_SLCR_MIO_PIN_74 ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL ) -#define XIOU_SLCR_MIO_PIN_74_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin75 - */ -#define XIOU_SLCR_MIO_PIN_75 ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL ) -#define XIOU_SLCR_MIO_PIN_75_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin76 - */ -#define XIOU_SLCR_MIO_PIN_76 ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL ) -#define XIOU_SLCR_MIO_PIN_76_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioPin77 - */ -#define XIOU_SLCR_MIO_PIN_77 ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL ) -#define XIOU_SLCR_MIO_PIN_77_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5UL -#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH 3UL -#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000e0UL -#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3UL -#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH 2UL -#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018UL -#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2UL -#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004UL -#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1UL -#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH 1UL -#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002UL -#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank0Ctrl0 - */ -#define XIOU_SLCR_BANK0_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL ) -#define XIOU_SLCR_BANK0_CTRL0_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank0Ctrl1 - */ -#define XIOU_SLCR_BANK0_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL ) -#define XIOU_SLCR_BANK0_CTRL1_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank0Ctrl3 - */ -#define XIOU_SLCR_BANK0_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL ) -#define XIOU_SLCR_BANK0_CTRL3_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank0Ctrl4 - */ -#define XIOU_SLCR_BANK0_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL ) -#define XIOU_SLCR_BANK0_CTRL4_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank0Ctrl5 - */ -#define XIOU_SLCR_BANK0_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL ) -#define XIOU_SLCR_BANK0_CTRL5_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank0Ctrl6 - */ -#define XIOU_SLCR_BANK0_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL ) -#define XIOU_SLCR_BANK0_CTRL6_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL -#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL -#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank0Sts - */ -#define XIOU_SLCR_BANK0_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL ) -#define XIOU_SLCR_BANK0_STS_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT 0UL -#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH 1UL -#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK 0x00000001UL -#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank1Ctrl0 - */ -#define XIOU_SLCR_BANK1_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL ) -#define XIOU_SLCR_BANK1_CTRL0_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank1Ctrl1 - */ -#define XIOU_SLCR_BANK1_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL ) -#define XIOU_SLCR_BANK1_CTRL1_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank1Ctrl3 - */ -#define XIOU_SLCR_BANK1_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL ) -#define XIOU_SLCR_BANK1_CTRL3_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank1Ctrl4 - */ -#define XIOU_SLCR_BANK1_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL ) -#define XIOU_SLCR_BANK1_CTRL4_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank1Ctrl5 - */ -#define XIOU_SLCR_BANK1_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL ) -#define XIOU_SLCR_BANK1_CTRL5_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank1Ctrl6 - */ -#define XIOU_SLCR_BANK1_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL ) -#define XIOU_SLCR_BANK1_CTRL6_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL -#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL -#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank1Sts - */ -#define XIOU_SLCR_BANK1_STS ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL ) -#define XIOU_SLCR_BANK1_STS_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT 0UL -#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH 1UL -#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK 0x00000001UL -#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank2Ctrl0 - */ -#define XIOU_SLCR_BANK2_CTRL0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL ) -#define XIOU_SLCR_BANK2_CTRL0_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank2Ctrl1 - */ -#define XIOU_SLCR_BANK2_CTRL1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL ) -#define XIOU_SLCR_BANK2_CTRL1_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank2Ctrl3 - */ -#define XIOU_SLCR_BANK2_CTRL3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL ) -#define XIOU_SLCR_BANK2_CTRL3_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank2Ctrl4 - */ -#define XIOU_SLCR_BANK2_CTRL4 ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL ) -#define XIOU_SLCR_BANK2_CTRL4_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank2Ctrl5 - */ -#define XIOU_SLCR_BANK2_CTRL5 ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL ) -#define XIOU_SLCR_BANK2_CTRL5_RSTVAL 0x03ffffffUL - -#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL 0x3ffffffUL - -/** - * Register: XiouSlcrBank2Ctrl6 - */ -#define XIOU_SLCR_BANK2_CTRL6 ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL ) -#define XIOU_SLCR_BANK2_CTRL6_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT 0UL -#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH 26UL -#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK 0x03ffffffUL -#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL 0x0UL - -/** - * Register: XiouSlcrBank2Sts - */ -#define XIOU_SLCR_BANK2_STS ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL ) -#define XIOU_SLCR_BANK2_STS_RSTVAL 0x00000000UL - -#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT 0UL -#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH 1UL -#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK 0x00000001UL -#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioLpbck - */ -#define XIOU_SLCR_MIO_LPBCK ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL ) -#define XIOU_SLCR_MIO_LPBCK_RSTVAL 0x00000000UL - -#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT 3UL -#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH 1UL -#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK 0x00000008UL -#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT 2UL -#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH 1UL -#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK 0x00000004UL -#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT 1UL -#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH 1UL -#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK 0x00000002UL -#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL 0x0UL - -#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT 0UL -#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH 1UL -#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK 0x00000001UL -#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL 0x0UL - -/** - * Register: XiouSlcrMioMstTri0 - */ -#define XIOU_SLCR_MIO_MST_TRI0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL ) -#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL 0xffffffffUL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001UL -#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0x1UL - -/** - * Register: XiouSlcrMioMstTri1 - */ -#define XIOU_SLCR_MIO_MST_TRI1 ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL ) -#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL 0xffffffffUL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001UL -#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0x1UL - -/** - * Register: XiouSlcrMioMstTri2 - */ -#define XIOU_SLCR_MIO_MST_TRI2 ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL ) -#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL 0x00003fffUL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x1UL - -#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH 1UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001UL -#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x1UL - -/** - * Register: XiouSlcrWdtClkSel - */ -#define XIOU_SLCR_WDT_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL ) -#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_WDT_CLK_SEL_SHIFT 0UL -#define XIOU_SLCR_WDT_CLK_SEL_WIDTH 1UL -#define XIOU_SLCR_WDT_CLK_SEL_MASK 0x00000001UL -#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrCanMioCtrl - */ -#define XIOU_SLCR_CAN_MIO_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL ) -#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT 23UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH 1UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK 0x00800000UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL 0x0UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT 22UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH 1UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK 0x00400000UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT 15UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH 7UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK 0x003f8000UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL 0x0UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT 8UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH 1UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK 0x00000100UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL 0x0UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT 7UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH 1UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK 0x00000080UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT 0UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH 7UL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK 0x0000007fUL -#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL 0x0UL - -/** - * Register: XiouSlcrGemClkCtrl - */ -#define XIOU_SLCR_GEM_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL ) -#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT 22UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK 0x00400000UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT 20UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH 2UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK 0x00300000UL -#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 18UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00040000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 17UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00020000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 16UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00010000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 15UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00008000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 13UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00002000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 12UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00001000UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 11UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000800UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 10UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000400UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 8UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000100UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 7UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000080UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 6UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000040UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 5UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000020UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT 3UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK 0x00000008UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT 2UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK 0x00000004UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK 0x00000002UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT 0UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK 0x00000001UL -#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdioClkCtrl - */ -#define XIOU_SLCR_SDIO_CLK_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL ) -#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT 18UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH 1UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK 0x00040000UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH 1UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT 2UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH 1UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK 0x00000004UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT 0UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH 2UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK 0x00000003UL -#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrCtrlRegSd - */ -#define XIOU_SLCR_CTRL_REG_SD ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL ) -#define XIOU_SLCR_CTRL_REG_SD_RSTVAL 0x00000000UL - -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 15UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00008000UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT 0UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH 1UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK 0x00000001UL -#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdItapdly - */ -#define XIOU_SLCR_SD_ITAPDLY ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL ) -#define XIOU_SLCR_SD_ITAPDLY_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 25UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x02000000UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 24UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x01000000UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 16UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x00ff0000UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT 9UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH 1UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK 0x00000200UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT 8UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH 1UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK 0x00000100UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT 0UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH 8UL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK 0x000000ffUL -#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdOtapdlysel - */ -#define XIOU_SLCR_SD_OTAPDLYSEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL ) -#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 22UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00400000UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x003f0000UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT 6UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH 1UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK 0x00000040UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH 6UL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK 0x0000003fUL -#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdCfgReg1 - */ -#define XIOU_SLCR_SD_CFG_REG1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL ) -#define XIOU_SLCR_SD_CFG_REG1_RSTVAL 0x32403240UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 23UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x7f800000UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 17UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x007e0000UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 16UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00010000UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT 7UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH 8UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK 0x00007f80UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL 0x64UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT 1UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH 6UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK 0x0000007eUL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL 0x20UL - -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT 0UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK 0x00000001UL -#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdCfgReg2 - */ -#define XIOU_SLCR_SD_CFG_REG2 ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL ) -#define XIOU_SLCR_SD_CFG_REG2_RSTVAL 0x0ffc0ffcUL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 28UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x30000000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 27UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x08000000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 26UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x04000000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 25UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x02000000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 24UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x01000000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 23UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00800000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 22UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00400000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 21UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00200000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 20UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00100000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 19UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00080000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 18UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00040000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 16UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00030000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT 12UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH 2UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK 0x00003000UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT 11UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK 0x00000800UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT 10UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK 0x00000400UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT 9UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK 0x00000200UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT 8UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK 0x00000100UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT 7UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK 0x00000080UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT 6UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK 0x00000040UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT 5UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK 0x00000020UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT 4UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK 0x00000010UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT 3UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK 0x00000008UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT 2UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK 0x00000004UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT 0UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH 2UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK 0x00000003UL -#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdCfgReg3 - */ -#define XIOU_SLCR_SD_CFG_REG3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL ) -#define XIOU_SLCR_SD_CFG_REG3_RSTVAL 0x06070607UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 26UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x04000000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 22UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x03c00000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 21UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00200000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 20UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00100000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 19UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00080000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 18UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00040000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 17UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00020000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 16UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00010000UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT 10UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK 0x00000400UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT 6UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH 4UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK 0x000003c0UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL 0x8UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT 5UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK 0x00000020UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT 4UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK 0x00000010UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT 3UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK 0x00000008UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT 2UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK 0x00000004UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK 0x00000002UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT 0UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH 1UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK 0x00000001UL -#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL 0x1UL - -/** - * Register: XiouSlcrSdInitpreset - */ -#define XIOU_SLCR_SD_INITPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL ) -#define XIOU_SLCR_SD_INITPRESET_RSTVAL 0x01000100UL - -#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL - -#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL 0x100UL - -/** - * Register: XiouSlcrSdDsppreset - */ -#define XIOU_SLCR_SD_DSPPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL ) -#define XIOU_SLCR_SD_DSPPRESET_RSTVAL 0x00040004UL - -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL - -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL 0x4UL - -/** - * Register: XiouSlcrSdHspdpreset - */ -#define XIOU_SLCR_SD_HSPDPRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL ) -#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL 0x00020002UL - -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL - -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL 0x2UL - -/** - * Register: XiouSlcrSdSdr12preset - */ -#define XIOU_SLCR_SD_SDR12PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL ) -#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL 0x00040004UL - -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL - -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL 0x4UL - -/** - * Register: XiouSlcrSdSdr25preset - */ -#define XIOU_SLCR_SD_SDR25PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL ) -#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL 0x00020002UL - -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL - -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL 0x2UL - -/** - * Register: XiouSlcrSdSdr50prset - */ -#define XIOU_SLCR_SD_SDR50PRSET ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL ) -#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL 0x00010001UL - -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 16UL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL - -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT 0UL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH 13UL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK 0x00001fffUL -#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL 0x1UL - -/** - * Register: XiouSlcrSdSdr104prst - */ -#define XIOU_SLCR_SD_SDR104PRST ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL ) -#define XIOU_SLCR_SD_SDR104PRST_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 16UL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT 0UL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH 13UL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK 0x00001fffUL -#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdDdr50preset - */ -#define XIOU_SLCR_SD_DDR50PRESET ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL ) -#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL 0x00020002UL - -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x1fff0000UL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL - -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH 13UL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK 0x00001fffUL -#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL 0x2UL - -/** - * Register: XiouSlcrSdMaxcur1p8 - */ -#define XIOU_SLCR_SD_MAXCUR1P8 ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL ) -#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x00ff0000UL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK 0x000000ffUL -#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdMaxcur3p0 - */ -#define XIOU_SLCR_SD_MAXCUR3P0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL ) -#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x00ff0000UL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK 0x000000ffUL -#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdMaxcur3p3 - */ -#define XIOU_SLCR_SD_MAXCUR3P3 ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL ) -#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x00ff0000UL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH 8UL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK 0x000000ffUL -#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdDllCtrl - */ -#define XIOU_SLCR_SD_DLL_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL ) -#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 18UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00040000UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 17UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00020000UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 16UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00010000UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT 2UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK 0x00000004UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK 0x00000002UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT 0UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH 1UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK 0x00000001UL -#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL 0x0UL - -/** - * Register: XiouSlcrSdCdnCtrl - */ -#define XIOU_SLCR_SD_CDN_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL ) -#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 16UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00010000UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT 0UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH 1UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK 0x00000001UL -#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrGemCtrl - */ -#define XIOU_SLCR_GEM_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL ) -#define XIOU_SLCR_GEM_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 6UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x000000c0UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 4UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000030UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 2UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x0000000cUL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL - -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT 0UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH 2UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK 0x00000003UL -#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL 0x0UL - -/** - * Register: XiouSlcrTtcApbClk - */ -#define XIOU_SLCR_TTC_APB_CLK ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL ) -#define XIOU_SLCR_TTC_APB_CLK_RSTVAL 0x00000000UL - -#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT 6UL -#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH 2UL -#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK 0x000000c0UL -#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT 4UL -#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH 2UL -#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030UL -#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT 2UL -#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH 2UL -#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000cUL -#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x0UL - -#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT 0UL -#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH 2UL -#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003UL -#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrTapdlyBypass - */ -#define XIOU_SLCR_TAPDLY_BYPASS ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL ) -#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL 0x00000007UL - -#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2UL -#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH 1UL -#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004UL -#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x1UL - -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT 1UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH 1UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK 0x00000002UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL 0x1UL - -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT 0UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH 1UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK 0x00000001UL -#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL 0x1UL - -/** - * Register: XiouSlcrCoherentCtrl - */ -#define XIOU_SLCR_COHERENT_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL ) -#define XIOU_SLCR_COHERENT_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT 28UL -#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK 0xf0000000UL -#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT 24UL -#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK 0x0f000000UL -#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 20UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x00f00000UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT 16UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK 0x000f0000UL -#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 12UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000f000UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 8UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x00000f00UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 4UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x000000f0UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL - -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT 0UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH 4UL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK 0x0000000fUL -#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL 0x0UL - -/** - * Register: XiouSlcrVideoPssClkSel - */ -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL ) -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT 1UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH 1UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK 0x00000002UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL 0x0UL - -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT 0UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH 1UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK 0x00000001UL -#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL 0x0UL - -/** - * Register: XiouSlcrInterconnectRoute - */ -#define XIOU_SLCR_INTERCONNECT_ROUTE ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL ) -#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL 0x00000000UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT 7UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK 0x00000080UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT 6UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK 0x00000040UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 5UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000020UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT 4UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK 0x00000010UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 3UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000008UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 2UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000004UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000002UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL - -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT 0UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH 1UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK 0x00000001UL -#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL 0x0UL - -/** - * Register: XiouSlcrRamXemacps - */ -#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL ) -#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXemacps - */ -#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL ) -#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXemacps - */ -#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL ) -#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXemacps - */ -#define XIOU_SLCR_RAM_XEMACPS ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL ) -#define XIOU_SLCR_RAM_XEMACPS_RSTVAL 0x00005b5bUL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXsdps - */ -#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL ) -#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL - -#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXsdps - */ -#define XIOU_SLCR_RAM_XSDPS ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL ) -#define XIOU_SLCR_RAM_XSDPS_RSTVAL 0x0000005bUL - -#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamCan0 - */ -#define XIOU_SLCR_RAM_CAN0 ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL ) -#define XIOU_SLCR_RAM_CAN0_RSTVAL 0x005b5b5bUL - -#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT 22UL -#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK 0x00400000UL -#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT 19UL -#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK 0x00380000UL -#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT 16UL -#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK 0x00070000UL -#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamCan1 - */ -#define XIOU_SLCR_RAM_CAN1 ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL ) -#define XIOU_SLCR_RAM_CAN1_RSTVAL 0x005b5b5bUL - -#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT 22UL -#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK 0x00400000UL -#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT 19UL -#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK 0x00380000UL -#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT 16UL -#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK 0x00070000UL -#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT 14UL -#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK 0x00004000UL -#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT 11UL -#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK 0x00003800UL -#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT 8UL -#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK 0x00000700UL -#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamLqspi - */ -#define XIOU_SLCR_RAM_LQSPI ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL ) -#define XIOU_SLCR_RAM_LQSPI_RSTVAL 0x00002ddbUL - -#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT 13UL -#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH 1UL -#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK 0x00002000UL -#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT 10UL -#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH 3UL -#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK 0x00001c00UL -#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT 7UL -#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH 3UL -#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK 0x00000380UL -#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrRamXnandps8 - */ -#define XIOU_SLCR_RAM_XNANDPS8 ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL ) -#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL 0x0000005bUL - -#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT 6UL -#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH 1UL -#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK 0x00000040UL -#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL 0x1UL - -#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT 3UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH 3UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK 0x00000038UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL 0x3UL - -#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT 0UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH 3UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK 0x00000007UL -#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL 0x3UL - -/** - * Register: XiouSlcrCtrl - */ -#define XIOU_SLCR_CTRL ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL ) -#define XIOU_SLCR_CTRL_RSTVAL 0x00000000UL - -#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT 0UL -#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH 1UL -#define XIOU_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XiouSlcrIsr - */ -#define XIOU_SLCR_ISR ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL ) -#define XIOU_SLCR_ISR_RSTVAL 0x00000000UL - -#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSlcrImr - */ -#define XIOU_SLCR_IMR ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL ) -#define XIOU_SLCR_IMR_RSTVAL 0x00000001UL - -#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XiouSlcrIer - */ -#define XIOU_SLCR_IER ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL ) -#define XIOU_SLCR_IER_RSTVAL 0x00000000UL - -#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSlcrIdr - */ -#define XIOU_SLCR_IDR ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL ) -#define XIOU_SLCR_IDR_RSTVAL 0x00000000UL - -#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XiouSlcrItr - */ -#define XIOU_SLCR_ITR ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL ) -#define XIOU_SLCR_ITR_RSTVAL 0x00000000UL - -#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XIOU_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h b/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h deleted file mode 100644 index cc05672e..00000000 --- a/lib/bsp/standalone/src/cortexr5/xlpd_slcr.h +++ /dev/null @@ -1,5667 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XLPD_SLCR_H__ -#define __XLPD_SLCR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XlpdSlcr Base Address - */ -#define XLPD_SLCR_BASEADDR 0xFF410000UL - -/** - * Register: XlpdSlcrWprot0 - */ -#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL ) -#define XLPD_SLCR_WPROT0_RSTVAL 0x00000001UL - -#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL -#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL -#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL -#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrCtrl - */ -#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL ) -#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL - -#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL -#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL -#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIsr - */ -#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL ) -#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrImr - */ -#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL ) -#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL - -#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrIer - */ -#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL ) -#define XLPD_SLCR_IER_RSTVAL 0x00000000UL - -#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIdr - */ -#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL ) -#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrItr - */ -#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL ) -#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSafetyChk0 - */ -#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL ) -#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT 0UL -#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH 32UL -#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK 0xffffffffUL -#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSafetyChk1 - */ -#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL ) -#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT 0UL -#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH 32UL -#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK 0xffffffffUL -#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSafetyChk2 - */ -#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL ) -#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT 0UL -#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH 32UL -#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK 0xffffffffUL -#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSafetyChk3 - */ -#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL ) -#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT 0UL -#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH 32UL -#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK 0xffffffffUL -#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrXcsupmuWdtClkSel - */ -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL ) -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL 0x00000000UL - -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT 0UL -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH 1UL -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK 0x00000001UL -#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrAdmaCfg - */ -#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL ) -#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000028UL - -#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT 5UL -#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH 2UL -#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK 0x00000060UL -#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL 0x1UL - -#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL -#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL -#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL -#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL - -/** - * Register: XlpdSlcrAdmaRam - */ -#define XLPD_SLCR_ADMA_RAM ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL ) -#define XLPD_SLCR_ADMA_RAM_RSTVAL 0x00003b3bUL - -#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT 12UL -#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH 3UL -#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK 0x00007000UL -#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL 0x3UL - -#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT 11UL -#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH 1UL -#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK 0x00000800UL -#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL 0x1UL - -#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT 8UL -#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH 3UL -#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK 0x00000700UL -#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL 0x3UL - -#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT 4UL -#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH 3UL -#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK 0x00000070UL -#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL 0x3UL - -#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT 3UL -#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH 1UL -#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK 0x00000008UL -#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL 0x1UL - -#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT 0UL -#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH 3UL -#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK 0x00000007UL -#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL 0x3UL - -/** - * Register: XlpdSlcrErrAibaxiIsr - */ -#define XLPD_SLCR_ERR_AIBAXI_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL ) -#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT 27UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT 26UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT 23UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT 22UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAibaxiImr - */ -#define XLPD_SLCR_ERR_AIBAXI_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL ) -#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL 0x1dcf000fUL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT 27UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT 26UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT 23UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT 22UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrErrAibaxiIer - */ -#define XLPD_SLCR_ERR_AIBAXI_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL ) -#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT 27UL -#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT 26UL -#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT 23UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT 22UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAibaxiIdr - */ -#define XLPD_SLCR_ERR_AIBAXI_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL ) -#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT 27UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT 26UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT 23UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT 22UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAibapbIsr - */ -#define XLPD_SLCR_ERR_AIBAPB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL ) -#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAibapbImr - */ -#define XLPD_SLCR_ERR_AIBAPB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL ) -#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL 0x00000001UL - -#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrErrAibapbIer - */ -#define XLPD_SLCR_ERR_AIBAPB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL ) -#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAibapbIdr - */ -#define XLPD_SLCR_ERR_AIBAPB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL ) -#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT 0UL -#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH 1UL -#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIsoAibaxiReq - */ -#define XLPD_SLCR_ISO_AIBAXI_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL ) -#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT 27UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT 26UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT 23UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT 22UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIsoAibaxiType - */ -#define XLPD_SLCR_ISO_AIBAXI_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL ) -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL 0x19cf000fUL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT 27UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT 26UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT 23UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT 22UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL 0x1UL - -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrIsoAibaxiAck - */ -#define XLPD_SLCR_ISO_AIBAXI_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL ) -#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT 28UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK 0x10000000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT 27UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK 0x08000000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT 26UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK 0x04000000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT 24UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK 0x01000000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT 23UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK 0x00800000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT 22UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK 0x00400000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT 19UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK 0x00080000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT 18UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK 0x00040000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT 17UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK 0x00020000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT 16UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK 0x00010000UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT 3UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK 0x00000008UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT 2UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK 0x00000004UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK 0x00000002UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL 0x0UL - -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIsoAibapbReq - */ -#define XLPD_SLCR_ISO_AIBAPB_REQ ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL ) -#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrIsoAibapbType - */ -#define XLPD_SLCR_ISO_AIBAPB_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL ) -#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL 0x00000001UL - -#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrIsoAibapbAck - */ -#define XLPD_SLCR_ISO_AIBAPB_ACK ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL ) -#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT 0UL -#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH 1UL -#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK 0x00000001UL -#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAtbIsr - */ -#define XLPD_SLCR_ERR_ATB_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL ) -#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT 0UL -#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAtbImr - */ -#define XLPD_SLCR_ERR_ATB_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL ) -#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000003UL - -#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL 0x1UL - -#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT 0UL -#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrErrAtbIer - */ -#define XLPD_SLCR_ERR_ATB_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL ) -#define XLPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT 0UL -#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrErrAtbIdr - */ -#define XLPD_SLCR_ERR_ATB_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL ) -#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT 0UL -#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH 1UL -#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrAtbCmdStoreEn - */ -#define XLPD_SLCR_ATB_CMD_STORE_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL ) -#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL 0x00000003UL - -#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL 0x1UL - -#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT 0UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH 1UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrAtbRespEn - */ -#define XLPD_SLCR_ATB_RESP_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL ) -#define XLPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL 0x0UL - -#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT 0UL -#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH 1UL -#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrAtbRespType - */ -#define XLPD_SLCR_ATB_RESP_TYPE ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL ) -#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL 0x00000003UL - -#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT 1UL -#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH 1UL -#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK 0x00000002UL -#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL 0x1UL - -#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT 0UL -#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH 1UL -#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK 0x00000001UL -#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrAtbPrescale - */ -#define XLPD_SLCR_ATB_PRESCALE ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL ) -#define XLPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL - -#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL -#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL -#define XLPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL -#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL - -#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL -#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL -#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL -#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL - -/** - * Register: XlpdSlcrMutex0 - */ -#define XLPD_SLCR_MUTEX0 ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL ) -#define XLPD_SLCR_MUTEX0_RSTVAL 0x00000000UL - -#define XLPD_SLCR_MUTEX0_ID_SHIFT 0UL -#define XLPD_SLCR_MUTEX0_ID_WIDTH 32UL -#define XLPD_SLCR_MUTEX0_ID_MASK 0xffffffffUL -#define XLPD_SLCR_MUTEX0_ID_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrMutex1 - */ -#define XLPD_SLCR_MUTEX1 ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL ) -#define XLPD_SLCR_MUTEX1_RSTVAL 0x00000000UL - -#define XLPD_SLCR_MUTEX1_ID_SHIFT 0UL -#define XLPD_SLCR_MUTEX1_ID_WIDTH 32UL -#define XLPD_SLCR_MUTEX1_ID_MASK 0xffffffffUL -#define XLPD_SLCR_MUTEX1_ID_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrMutex2 - */ -#define XLPD_SLCR_MUTEX2 ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL ) -#define XLPD_SLCR_MUTEX2_RSTVAL 0x00000000UL - -#define XLPD_SLCR_MUTEX2_ID_SHIFT 0UL -#define XLPD_SLCR_MUTEX2_ID_WIDTH 32UL -#define XLPD_SLCR_MUTEX2_ID_MASK 0xffffffffUL -#define XLPD_SLCR_MUTEX2_ID_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrMutex3 - */ -#define XLPD_SLCR_MUTEX3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL ) -#define XLPD_SLCR_MUTEX3_RSTVAL 0x00000000UL - -#define XLPD_SLCR_MUTEX3_ID_SHIFT 0UL -#define XLPD_SLCR_MUTEX3_ID_WIDTH 32UL -#define XLPD_SLCR_MUTEX3_ID_MASK 0xffffffffUL -#define XLPD_SLCR_MUTEX3_ID_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp0IrqSts - */ -#define XLPD_SLCR_GICP0_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL ) -#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp0IrqMsk - */ -#define XLPD_SLCR_GICP0_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL ) -#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL 0xffffffffUL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicp0IrqEn - */ -#define XLPD_SLCR_GICP0_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL ) -#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp0IrqDis - */ -#define XLPD_SLCR_GICP0_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL ) -#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp0IrqTrig - */ -#define XLPD_SLCR_GICP0_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL ) -#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp1IrqSts - */ -#define XLPD_SLCR_GICP1_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL ) -#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp1IrqMsk - */ -#define XLPD_SLCR_GICP1_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL ) -#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL 0xffffffffUL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicp1IrqEn - */ -#define XLPD_SLCR_GICP1_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL ) -#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp1IrqDis - */ -#define XLPD_SLCR_GICP1_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL ) -#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp1IrqTrig - */ -#define XLPD_SLCR_GICP1_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL ) -#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp2IrqSts - */ -#define XLPD_SLCR_GICP2_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL ) -#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp2IrqMsk - */ -#define XLPD_SLCR_GICP2_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL ) -#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL 0xffffffffUL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicp2IrqEn - */ -#define XLPD_SLCR_GICP2_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL ) -#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp2IrqDis - */ -#define XLPD_SLCR_GICP2_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL ) -#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp2IrqTrig - */ -#define XLPD_SLCR_GICP2_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL ) -#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp3IrqSts - */ -#define XLPD_SLCR_GICP3_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL ) -#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp3IrqMsk - */ -#define XLPD_SLCR_GICP3_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL ) -#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL 0xffffffffUL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicp3IrqEn - */ -#define XLPD_SLCR_GICP3_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL ) -#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp3IrqDis - */ -#define XLPD_SLCR_GICP3_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL ) -#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp3IrqTrig - */ -#define XLPD_SLCR_GICP3_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL ) -#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp4IrqSts - */ -#define XLPD_SLCR_GICP4_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL ) -#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp4IrqMsk - */ -#define XLPD_SLCR_GICP4_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL ) -#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL 0xffffffffUL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicp4IrqEn - */ -#define XLPD_SLCR_GICP4_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL ) -#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp4IrqDis - */ -#define XLPD_SLCR_GICP4_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL ) -#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicp4IrqTrig - */ -#define XLPD_SLCR_GICP4_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL ) -#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT 31UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK 0x80000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT 30UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK 0x40000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT 29UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK 0x20000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT 28UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK 0x10000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT 27UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK 0x08000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT 26UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK 0x04000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT 25UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK 0x02000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT 24UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK 0x01000000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT 23UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK 0x00800000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT 22UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK 0x00400000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT 21UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK 0x00200000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT 20UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK 0x00100000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT 19UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK 0x00080000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT 18UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK 0x00040000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT 17UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK 0x00020000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT 16UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK 0x00010000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT 15UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK 0x00008000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT 14UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK 0x00004000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT 13UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK 0x00002000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT 12UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK 0x00001000UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT 11UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK 0x00000800UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT 10UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK 0x00000400UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT 9UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK 0x00000200UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT 8UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK 0x00000100UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicpPmuIrqSts - */ -#define XLPD_SLCR_GICP_PMU_IRQ_STS ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL ) -#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicpPmuIrqMsk - */ -#define XLPD_SLCR_GICP_PMU_IRQ_MSK ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL ) -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL 0x000000ffUL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL 0x1UL - -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrGicpPmuIrqEn - */ -#define XLPD_SLCR_GICP_PMU_IRQ_EN ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL ) -#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicpPmuIrqDis - */ -#define XLPD_SLCR_GICP_PMU_IRQ_DIS ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL ) -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrGicpPmuIrqTrig - */ -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL ) -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL 0x00000000UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT 7UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK 0x00000080UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT 6UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK 0x00000040UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT 5UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK 0x00000020UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT 4UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK 0x00000010UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT 3UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK 0x00000008UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT 2UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK 0x00000004UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK 0x00000002UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL 0x0UL - -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT 0UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH 1UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK 0x00000001UL -#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrAfiFs - */ -#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL ) -#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL - -#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL -#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL -#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL -#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL - -/** - * Register: XlpdSlcrCci - */ -#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL ) -#define XLPD_SLCR_CCI_RSTVAL 0x03801c07UL - -#define XLPD_SLCR_CCI_SPR_SHIFT 28UL -#define XLPD_SLCR_CCI_SPR_WIDTH 4UL -#define XLPD_SLCR_CCI_SPR_MASK 0xf0000000UL -#define XLPD_SLCR_CCI_SPR_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT 27UL -#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH 1UL -#define XLPD_SLCR_CCI_QVNVNETS4_MASK 0x08000000UL -#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT 26UL -#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH 1UL -#define XLPD_SLCR_CCI_QVNVNETS3_MASK 0x04000000UL -#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT 25UL -#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH 1UL -#define XLPD_SLCR_CCI_QVNVNETS2_MASK 0x02000000UL -#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT 24UL -#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH 1UL -#define XLPD_SLCR_CCI_QVNVNETS1_MASK 0x01000000UL -#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT 23UL -#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH 1UL -#define XLPD_SLCR_CCI_QVNVNETS0_MASK 0x00800000UL -#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT 18UL -#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH 5UL -#define XLPD_SLCR_CCI_QOS_OVRRD_MASK 0x007c0000UL -#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT 17UL -#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH 1UL -#define XLPD_SLCR_CCI_QVN_EN_M2_MASK 0x00020000UL -#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT 16UL -#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH 1UL -#define XLPD_SLCR_CCI_QVN_EN_M1_MASK 0x00010000UL -#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT 13UL -#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH 3UL -#define XLPD_SLCR_CCI_STRPG_GRAN_MASK 0x0000e000UL -#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT 12UL -#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH 1UL -#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK 0x00001000UL -#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT 11UL -#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH 1UL -#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK 0x00000800UL -#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT 10UL -#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH 1UL -#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK 0x00000400UL -#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT 6UL -#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH 4UL -#define XLPD_SLCR_CCI_ECOREVNUM_MASK 0x000003c0UL -#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ASA2_SHIFT 5UL -#define XLPD_SLCR_CCI_ASA2_WIDTH 1UL -#define XLPD_SLCR_CCI_ASA2_MASK 0x00000020UL -#define XLPD_SLCR_CCI_ASA2_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ASA1_SHIFT 4UL -#define XLPD_SLCR_CCI_ASA1_WIDTH 1UL -#define XLPD_SLCR_CCI_ASA1_MASK 0x00000010UL -#define XLPD_SLCR_CCI_ASA1_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ASA0_SHIFT 3UL -#define XLPD_SLCR_CCI_ASA0_WIDTH 1UL -#define XLPD_SLCR_CCI_ASA0_MASK 0x00000008UL -#define XLPD_SLCR_CCI_ASA0_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_OWO2_SHIFT 2UL -#define XLPD_SLCR_CCI_OWO2_WIDTH 1UL -#define XLPD_SLCR_CCI_OWO2_MASK 0x00000004UL -#define XLPD_SLCR_CCI_OWO2_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_OWO1_SHIFT 1UL -#define XLPD_SLCR_CCI_OWO1_WIDTH 1UL -#define XLPD_SLCR_CCI_OWO1_MASK 0x00000002UL -#define XLPD_SLCR_CCI_OWO1_DEFVAL 0x1UL - -#define XLPD_SLCR_CCI_OWO0_SHIFT 0UL -#define XLPD_SLCR_CCI_OWO0_WIDTH 1UL -#define XLPD_SLCR_CCI_OWO0_MASK 0x00000001UL -#define XLPD_SLCR_CCI_OWO0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrCciAddrmap - */ -#define XLPD_SLCR_CCI_ADDRMAP ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL ) -#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL 0x00c000ffUL - -#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT 30UL -#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_15_MASK 0xc0000000UL -#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT 28UL -#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_14_MASK 0x30000000UL -#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT 26UL -#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_13_MASK 0x0c000000UL -#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT 24UL -#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_12_MASK 0x03000000UL -#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT 22UL -#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_11_MASK 0x00c00000UL -#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT 20UL -#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_10_MASK 0x00300000UL -#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT 18UL -#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_9_MASK 0x000c0000UL -#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT 16UL -#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_8_MASK 0x00030000UL -#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT 14UL -#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_7_MASK 0x0000c000UL -#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT 12UL -#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_6_MASK 0x00003000UL -#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT 10UL -#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_5_MASK 0x00000c00UL -#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT 8UL -#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_4_MASK 0x00000300UL -#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL 0x0UL - -#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT 6UL -#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_3_MASK 0x000000c0UL -#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT 4UL -#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_2_MASK 0x00000030UL -#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT 2UL -#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_1_MASK 0x0000000cUL -#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT 0UL -#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH 2UL -#define XLPD_SLCR_CCI_ADDRMAP_0_MASK 0x00000003UL -#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL 0x3UL - -/** - * Register: XlpdSlcrCciQvnprealloc - */ -#define XLPD_SLCR_CCI_QVNPREALLOC ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL ) -#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL 0x00330330UL - -#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT 20UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH 4UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK 0x00f00000UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT 16UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH 4UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK 0x000f0000UL -#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT 8UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH 4UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK 0x00000f00UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL 0x3UL - -#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT 4UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH 4UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK 0x000000f0UL -#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL 0x3UL - -/** - * Register: XlpdSlcrSmmu - */ -#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL ) -#define XLPD_SLCR_SMMU_RSTVAL 0x0000003fUL - -#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT 7UL -#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH 1UL -#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK 0x00000080UL -#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL 0x0UL - -#define XLPD_SLCR_SMMU_CTTW_SHIFT 6UL -#define XLPD_SLCR_SMMU_CTTW_WIDTH 1UL -#define XLPD_SLCR_SMMU_CTTW_MASK 0x00000040UL -#define XLPD_SLCR_SMMU_CTTW_DEFVAL 0x0UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT 5UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK 0x00000020UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL 0x1UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT 4UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK 0x00000010UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL 0x1UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT 3UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK 0x00000008UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL 0x1UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT 2UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK 0x00000004UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL 0x1UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK 0x00000002UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL 0x1UL - -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT 0UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH 1UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK 0x00000001UL -#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrApu - */ -#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL ) -#define XLPD_SLCR_APU_RSTVAL 0x00000001UL - -#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL -#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL -#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL -#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL - -#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL -#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL -#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL -#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL - -#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL -#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL -#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL -#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL - -#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL -#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL -#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL -#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XLPD_SLCR_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h b/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h deleted file mode 100644 index aff3bf2f..00000000 --- a/lib/bsp/standalone/src/cortexr5/xlpd_slcr_secure.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XLPD_SLCR_SECURE_H__ -#define __XLPD_SLCR_SECURE_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XlpdSlcrSecure Base Address - */ -#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL - -/** - * Register: XlpdSlcrSecCtrl - */ -#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL ) -#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL -#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL -#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL -#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecIsr - */ -#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL ) -#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecImr - */ -#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL ) -#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL - -#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL - -/** - * Register: XlpdSlcrSecIer - */ -#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL ) -#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecIdr - */ -#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL ) -#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecItr - */ -#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL ) -#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL -#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL -#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL -#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecRpu - */ -#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL ) -#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL - -#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL -#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecAdma - */ -#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL ) -#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL -#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL -#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL -#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecSafetyChk - */ -#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL ) -#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL - -#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL -#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL -#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL -#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL - -/** - * Register: XlpdSlcrSecUsb - */ -#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL ) -#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL - -#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL - -#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL -#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XLPD_SLCR_SECURE_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h b/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h deleted file mode 100644 index a5145eac..00000000 --- a/lib/bsp/standalone/src/cortexr5/xlpd_xppu.h +++ /dev/null @@ -1,858 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XLPD_XPPU_H__ -#define __XLPD_XPPU_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XlpdXppu Base Address - */ -#define XLPD_XPPU_BASEADDR 0xFF980000UL - -/** - * Register: XlpdXppuCtrl - */ -#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL ) -#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL - -#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL -#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL -#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL -#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL - -#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL -#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL -#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL -#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL - -#define XLPD_XPPU_CTRL_EN_SHIFT 0UL -#define XLPD_XPPU_CTRL_EN_WIDTH 1UL -#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL -#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL - -/** - * Register: XlpdXppuErrSts1 - */ -#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL ) -#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL - -#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XlpdXppuErrSts2 - */ -#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL ) -#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL - -#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL -#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL -#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuPoison - */ -#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL ) -#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL - -#define XLPD_XPPU_POISON_BASE_SHIFT 0UL -#define XLPD_XPPU_POISON_BASE_WIDTH 20UL -#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL -#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XlpdXppuIsr - */ -#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL ) -#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL - -#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL -#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL -#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL -#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL -#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL -#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL -#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL -#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL -#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL -#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL -#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL -#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL -#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL -#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL -#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL -#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL -#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL -#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL -#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL - -#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL -#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL -#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL -#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XlpdXppuImr - */ -#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL ) -#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL - -#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL -#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL -#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL -#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL -#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL -#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL -#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL -#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL -#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL -#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL -#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL -#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL -#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL -#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL -#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL -#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL -#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL -#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL -#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL - -#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL -#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL -#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL -#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XlpdXppuIen - */ -#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL ) -#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL - -#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL -#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL -#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL -#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL -#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL -#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL -#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL -#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL -#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL -#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL -#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL -#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL -#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL -#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL -#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL -#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL -#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL -#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL -#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL - -#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL -#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL -#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL -#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XlpdXppuIds - */ -#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL ) -#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL - -#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL -#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL -#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL -#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL -#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL -#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL -#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL -#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL -#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL -#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL -#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL -#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL -#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL -#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL -#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL -#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL -#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL -#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL -#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL - -#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL -#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL -#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL -#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMMstrIds - */ -#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL ) -#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL - -#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL -#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL -#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL -#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL - -/** - * Register: XlpdXppuMAperture32b - */ -#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL ) -#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL - -#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL -#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL -#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL -#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL - -/** - * Register: XlpdXppuMAperture64kb - */ -#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL ) -#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL - -#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL -#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL -#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL -#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL - -/** - * Register: XlpdXppuMAperture1mb - */ -#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL ) -#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL - -#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL -#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL -#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL -#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL - -/** - * Register: XlpdXppuMAperture512mb - */ -#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL ) -#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL - -#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL -#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL -#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL -#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL - -/** - * Register: XlpdXppuBase32b - */ -#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL ) -#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL - -#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL -#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL -#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL -#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL - -/** - * Register: XlpdXppuBase64kb - */ -#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL ) -#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL - -#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL -#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL -#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL -#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL - -/** - * Register: XlpdXppuBase1mb - */ -#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL ) -#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL - -#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL -#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL -#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL -#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL - -/** - * Register: XlpdXppuBase512mb - */ -#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL ) -#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL - -#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL -#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL -#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL -#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL - -/** - * Register: XlpdXppuMstrId00 - */ -#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL ) -#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL - -#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL - -#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL - -#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL - -/** - * Register: XlpdXppuMstrId01 - */ -#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL ) -#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL - -#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL - -#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId02 - */ -#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL ) -#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL - -#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL - -#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL - -#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL - -/** - * Register: XlpdXppuMstrId03 - */ -#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL ) -#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL - -#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL - -#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL - -#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL - -/** - * Register: XlpdXppuMstrId04 - */ -#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL ) -#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL - -#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL - -#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL - -#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL - -/** - * Register: XlpdXppuMstrId05 - */ -#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL ) -#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL - -#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL - -#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL - -/** - * Register: XlpdXppuMstrId06 - */ -#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL ) -#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL - -#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL - -#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL - -/** - * Register: XlpdXppuMstrId07 - */ -#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL ) -#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL - -#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL - -#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL - -#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL - -/** - * Register: XlpdXppuMstrId08 - */ -#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL ) -#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId09 - */ -#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL ) -#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId10 - */ -#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL ) -#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId11 - */ -#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL ) -#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId12 - */ -#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL ) -#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId13 - */ -#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL ) -#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId14 - */ -#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL ) -#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId15 - */ -#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL ) -#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId16 - */ -#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL ) -#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId17 - */ -#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL ) -#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId18 - */ -#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL ) -#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL - -/** - * Register: XlpdXppuMstrId19 - */ -#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL ) -#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL - -#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL -#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL -#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL -#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL -#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL -#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL -#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL -#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL - -#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL -#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL -#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL -#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XLPD_XPPU_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h b/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h deleted file mode 100644 index 95f7e20a..00000000 --- a/lib/bsp/standalone/src/cortexr5/xlpd_xppu_sink.h +++ /dev/null @@ -1,81 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XLPD_XPPU_SINK_H__ -#define __XLPD_XPPU_SINK_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XlpdXppuSink Base Address - */ -#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL - -/** - * Register: XlpdXppuSinkErrSts - */ -#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL ) -#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL - -#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL -#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL -#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL -#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL - -#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL -#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL -#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL -#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL - -/** - * Register: XlpdXppuSinkIsr - */ -#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL ) -#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL - -#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL -#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL -#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL -#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL - -/** - * Register: XlpdXppuSinkImr - */ -#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL ) -#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL - -#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL -#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL -#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL -#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL - -/** - * Register: XlpdXppuSinkIer - */ -#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL ) -#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL - -#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL -#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL -#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL -#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL - -/** - * Register: XlpdXppuSinkIdr - */ -#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL ) -#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL - -#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL -#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL -#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL -#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XLPD_XPPU_SINK_H__ */ diff --git a/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h b/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h deleted file mode 100644 index 5e3631f3..00000000 --- a/lib/bsp/standalone/src/cortexr5/xocm_xmpu_cfg.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* ### HEADER ### */ - -#ifndef __XOCM_XMPU_CFG_H__ -#define __XOCM_XMPU_CFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * XocmXmpuCfg Base Address - */ -#define XOCM_XMPU_CFG_BASEADDR 0xFFA70000UL - -/** - * Register: XocmXmpuCfgCtrl - */ -#define XOCM_XMPU_CFG_CTRL ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL ) -#define XOCM_XMPU_CFG_CTRL_RSTVAL 0x00000003UL - -#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT 3UL -#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH 1UL -#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK 0x00000008UL -#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT 2UL -#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH 1UL -#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK 0x00000004UL -#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT 0UL -#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK 0x00000001UL -#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL 0x1UL - -/** - * Register: XocmXmpuCfgErrSts1 - */ -#define XOCM_XMPU_CFG_ERR_STS1 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL ) -#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH 32UL -#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL -#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgErrSts2 - */ -#define XOCM_XMPU_CFG_ERR_STS2 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL ) -#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgPoison - */ -#define XOCM_XMPU_CFG_POISON ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL ) -#define XOCM_XMPU_CFG_POISON_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT 20UL -#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH 12UL -#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK 0xfff00000UL -#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_POISON_BASE_SHIFT 0UL -#define XOCM_XMPU_CFG_POISON_BASE_WIDTH 20UL -#define XOCM_XMPU_CFG_POISON_BASE_MASK 0x000fffffUL -#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgIsr - */ -#define XOCM_XMPU_CFG_ISR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL ) -#define XOCM_XMPU_CFG_ISR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT 3UL -#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK 0x00000008UL -#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT 2UL -#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK 0x00000004UL -#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT 1UL -#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK 0x00000002UL -#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT 0UL -#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH 1UL -#define XOCM_XMPU_CFG_ISR_INV_APB_MASK 0x00000001UL -#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgImr - */ -#define XOCM_XMPU_CFG_IMR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL ) -#define XOCM_XMPU_CFG_IMR_RSTVAL 0x0000000fUL - -#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT 3UL -#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK 0x00000008UL -#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT 2UL -#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK 0x00000004UL -#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT 1UL -#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK 0x00000002UL -#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT 0UL -#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH 1UL -#define XOCM_XMPU_CFG_IMR_INV_APB_MASK 0x00000001UL -#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL 0x1UL - -/** - * Register: XocmXmpuCfgIen - */ -#define XOCM_XMPU_CFG_IEN ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL ) -#define XOCM_XMPU_CFG_IEN_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT 3UL -#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK 0x00000008UL -#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT 2UL -#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK 0x00000004UL -#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT 1UL -#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK 0x00000002UL -#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT 0UL -#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH 1UL -#define XOCM_XMPU_CFG_IEN_INV_APB_MASK 0x00000001UL -#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgIds - */ -#define XOCM_XMPU_CFG_IDS ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL ) -#define XOCM_XMPU_CFG_IDS_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT 3UL -#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK 0x00000008UL -#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT 2UL -#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK 0x00000004UL -#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT 1UL -#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH 1UL -#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK 0x00000002UL -#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT 0UL -#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH 1UL -#define XOCM_XMPU_CFG_IDS_INV_APB_MASK 0x00000001UL -#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgLock - */ -#define XOCM_XMPU_CFG_LOCK ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL ) -#define XOCM_XMPU_CFG_LOCK_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT 0UL -#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH 1UL -#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK 0x00000001UL -#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR00Strt - */ -#define XOCM_XMPU_CFG_R00_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL ) -#define XOCM_XMPU_CFG_R00_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR00End - */ -#define XOCM_XMPU_CFG_R00_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL ) -#define XOCM_XMPU_CFG_R00_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R00_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR00Mstr - */ -#define XOCM_XMPU_CFG_R00_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL ) -#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR00 - */ -#define XOCM_XMPU_CFG_R00 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL ) -#define XOCM_XMPU_CFG_R00_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R00_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R00_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R00_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R00_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R00_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R00_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R00_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR01Strt - */ -#define XOCM_XMPU_CFG_R01_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL ) -#define XOCM_XMPU_CFG_R01_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR01End - */ -#define XOCM_XMPU_CFG_R01_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL ) -#define XOCM_XMPU_CFG_R01_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R01_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR01Mstr - */ -#define XOCM_XMPU_CFG_R01_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL ) -#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR01 - */ -#define XOCM_XMPU_CFG_R01 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL ) -#define XOCM_XMPU_CFG_R01_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R01_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R01_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R01_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R01_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R01_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R01_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R01_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR02Strt - */ -#define XOCM_XMPU_CFG_R02_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL ) -#define XOCM_XMPU_CFG_R02_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR02End - */ -#define XOCM_XMPU_CFG_R02_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL ) -#define XOCM_XMPU_CFG_R02_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R02_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR02Mstr - */ -#define XOCM_XMPU_CFG_R02_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL ) -#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR02 - */ -#define XOCM_XMPU_CFG_R02 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL ) -#define XOCM_XMPU_CFG_R02_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R02_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R02_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R02_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R02_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R02_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R02_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R02_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR03Strt - */ -#define XOCM_XMPU_CFG_R03_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL ) -#define XOCM_XMPU_CFG_R03_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR03End - */ -#define XOCM_XMPU_CFG_R03_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL ) -#define XOCM_XMPU_CFG_R03_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R03_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR03Mstr - */ -#define XOCM_XMPU_CFG_R03_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL ) -#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR03 - */ -#define XOCM_XMPU_CFG_R03 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL ) -#define XOCM_XMPU_CFG_R03_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R03_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R03_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R03_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R03_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R03_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R03_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R03_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR04Strt - */ -#define XOCM_XMPU_CFG_R04_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL ) -#define XOCM_XMPU_CFG_R04_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR04End - */ -#define XOCM_XMPU_CFG_R04_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL ) -#define XOCM_XMPU_CFG_R04_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R04_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR04Mstr - */ -#define XOCM_XMPU_CFG_R04_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL ) -#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR04 - */ -#define XOCM_XMPU_CFG_R04 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL ) -#define XOCM_XMPU_CFG_R04_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R04_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R04_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R04_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R04_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R04_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R04_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R04_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR05Strt - */ -#define XOCM_XMPU_CFG_R05_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL ) -#define XOCM_XMPU_CFG_R05_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR05End - */ -#define XOCM_XMPU_CFG_R05_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL ) -#define XOCM_XMPU_CFG_R05_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R05_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR05Mstr - */ -#define XOCM_XMPU_CFG_R05_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL ) -#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR05 - */ -#define XOCM_XMPU_CFG_R05 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL ) -#define XOCM_XMPU_CFG_R05_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R05_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R05_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R05_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R05_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R05_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R05_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R05_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR06Strt - */ -#define XOCM_XMPU_CFG_R06_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL ) -#define XOCM_XMPU_CFG_R06_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR06End - */ -#define XOCM_XMPU_CFG_R06_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL ) -#define XOCM_XMPU_CFG_R06_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R06_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR06Mstr - */ -#define XOCM_XMPU_CFG_R06_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL ) -#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR06 - */ -#define XOCM_XMPU_CFG_R06 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL ) -#define XOCM_XMPU_CFG_R06_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R06_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R06_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R06_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R06_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R06_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R06_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R06_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR07Strt - */ -#define XOCM_XMPU_CFG_R07_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL ) -#define XOCM_XMPU_CFG_R07_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR07End - */ -#define XOCM_XMPU_CFG_R07_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL ) -#define XOCM_XMPU_CFG_R07_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R07_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR07Mstr - */ -#define XOCM_XMPU_CFG_R07_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL ) -#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR07 - */ -#define XOCM_XMPU_CFG_R07 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL ) -#define XOCM_XMPU_CFG_R07_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R07_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R07_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R07_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R07_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R07_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R07_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R07_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR08Strt - */ -#define XOCM_XMPU_CFG_R08_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL ) -#define XOCM_XMPU_CFG_R08_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR08End - */ -#define XOCM_XMPU_CFG_R08_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL ) -#define XOCM_XMPU_CFG_R08_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R08_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR08Mstr - */ -#define XOCM_XMPU_CFG_R08_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL ) -#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR08 - */ -#define XOCM_XMPU_CFG_R08 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL ) -#define XOCM_XMPU_CFG_R08_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R08_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R08_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R08_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R08_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R08_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R08_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R08_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR09Strt - */ -#define XOCM_XMPU_CFG_R09_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL ) -#define XOCM_XMPU_CFG_R09_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR09End - */ -#define XOCM_XMPU_CFG_R09_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL ) -#define XOCM_XMPU_CFG_R09_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R09_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR09Mstr - */ -#define XOCM_XMPU_CFG_R09_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL ) -#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR09 - */ -#define XOCM_XMPU_CFG_R09 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL ) -#define XOCM_XMPU_CFG_R09_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R09_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R09_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R09_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R09_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R09_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R09_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R09_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR10Strt - */ -#define XOCM_XMPU_CFG_R10_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL ) -#define XOCM_XMPU_CFG_R10_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR10End - */ -#define XOCM_XMPU_CFG_R10_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL ) -#define XOCM_XMPU_CFG_R10_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R10_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR10Mstr - */ -#define XOCM_XMPU_CFG_R10_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL ) -#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR10 - */ -#define XOCM_XMPU_CFG_R10 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL ) -#define XOCM_XMPU_CFG_R10_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R10_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R10_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R10_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R10_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R10_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R10_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R10_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR11Strt - */ -#define XOCM_XMPU_CFG_R11_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL ) -#define XOCM_XMPU_CFG_R11_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR11End - */ -#define XOCM_XMPU_CFG_R11_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL ) -#define XOCM_XMPU_CFG_R11_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R11_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR11Mstr - */ -#define XOCM_XMPU_CFG_R11_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL ) -#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR11 - */ -#define XOCM_XMPU_CFG_R11 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL ) -#define XOCM_XMPU_CFG_R11_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R11_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R11_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R11_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R11_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R11_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R11_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R11_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR12Strt - */ -#define XOCM_XMPU_CFG_R12_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL ) -#define XOCM_XMPU_CFG_R12_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR12End - */ -#define XOCM_XMPU_CFG_R12_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL ) -#define XOCM_XMPU_CFG_R12_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R12_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR12Mstr - */ -#define XOCM_XMPU_CFG_R12_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL ) -#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR12 - */ -#define XOCM_XMPU_CFG_R12 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL ) -#define XOCM_XMPU_CFG_R12_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R12_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R12_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R12_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R12_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R12_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R12_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R12_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR13Strt - */ -#define XOCM_XMPU_CFG_R13_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL ) -#define XOCM_XMPU_CFG_R13_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR13End - */ -#define XOCM_XMPU_CFG_R13_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL ) -#define XOCM_XMPU_CFG_R13_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R13_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR13Mstr - */ -#define XOCM_XMPU_CFG_R13_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL ) -#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR13 - */ -#define XOCM_XMPU_CFG_R13 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL ) -#define XOCM_XMPU_CFG_R13_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R13_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R13_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R13_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R13_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R13_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R13_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R13_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR14Strt - */ -#define XOCM_XMPU_CFG_R14_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL ) -#define XOCM_XMPU_CFG_R14_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR14End - */ -#define XOCM_XMPU_CFG_R14_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL ) -#define XOCM_XMPU_CFG_R14_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R14_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR14Mstr - */ -#define XOCM_XMPU_CFG_R14_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL ) -#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR14 - */ -#define XOCM_XMPU_CFG_R14 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL ) -#define XOCM_XMPU_CFG_R14_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R14_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R14_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R14_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R14_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R14_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R14_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R14_EN_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR15Strt - */ -#define XOCM_XMPU_CFG_R15_STRT ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL ) -#define XOCM_XMPU_CFG_R15_STRT_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR15End - */ -#define XOCM_XMPU_CFG_R15_END ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL ) -#define XOCM_XMPU_CFG_R15_END_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT 0UL -#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH 28UL -#define XOCM_XMPU_CFG_R15_END_ADDR_MASK 0x0fffffffUL -#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR15Mstr - */ -#define XOCM_XMPU_CFG_R15_MSTR ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL ) -#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL 0x00000000UL - -#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT 16UL -#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH 16UL -#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK 0xffff0000UL -#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT 0UL -#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH 16UL -#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK 0x0000ffffUL -#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL 0x0UL - -/** - * Register: XocmXmpuCfgR15 - */ -#define XOCM_XMPU_CFG_R15 ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL ) -#define XOCM_XMPU_CFG_R15_RSTVAL 0x00000008UL - -#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT 4UL -#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH 1UL -#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK 0x00000010UL -#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT 3UL -#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH 1UL -#define XOCM_XMPU_CFG_R15_REGNNS_MASK 0x00000008UL -#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL 0x1UL - -#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT 2UL -#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R15_WRALWD_MASK 0x00000004UL -#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT 1UL -#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH 1UL -#define XOCM_XMPU_CFG_R15_RDALWD_MASK 0x00000002UL -#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL 0x0UL - -#define XOCM_XMPU_CFG_R15_EN_SHIFT 0UL -#define XOCM_XMPU_CFG_R15_EN_WIDTH 1UL -#define XOCM_XMPU_CFG_R15_EN_MASK 0x00000001UL -#define XOCM_XMPU_CFG_R15_EN_DEFVAL 0x0UL - - -#ifdef __cplusplus -} -#endif - -#endif /* __XOCM_XMPU_CFG_H__ */