From 7307299d946815b28f85102521bb40320bb199e4 Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Mon, 8 Jun 2015 18:33:28 +0530 Subject: [PATCH] bsp: a9: modified translation_table.s for DDR-less system This patch modifies translation_table.S to put check whether the DDR is present or not to fix the compilation error in case of DDR-less system Signed-off-by: Kinjal Pravinbhai Patel --- lib/bsp/standalone/src/changelog.txt | 3 +++ .../standalone/src/cortexa9/gcc/translation_table.S | 11 ++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/lib/bsp/standalone/src/changelog.txt b/lib/bsp/standalone/src/changelog.txt index 0949aafc..b63afc51 100644 --- a/lib/bsp/standalone/src/changelog.txt +++ b/lib/bsp/standalone/src/changelog.txt @@ -232,4 +232,7 @@ * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler * to update ECC_FLAGS and also take the compiler and archiver as specified * in settings instead of hardcoding it. + * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for + * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and + * accordingly generate the translation table *****************************************************************************************/ diff --git a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S index f340ee66..08d511c5 100644 --- a/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S +++ b/lib/bsp/standalone/src/cortexa9/gcc/translation_table.S @@ -51,6 +51,9 @@ * 0xe0000000 - 0xe02fffff (memory mapped devides) * 0xe0300000 - 0xe0ffffff (reserved) and * 0xe1000000 - 0xe1ffffff (NAND) +* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm +* if DDR is present or not and accordingly generate the +* translation table * * * @note @@ -69,13 +72,19 @@ MMUTable: * Each entry covers a 1MB section. */ .set SECT, 0 + +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR .set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR .set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR .set DDR_SIZE, (DDR_END - DDR_START)+1 .set DDR_REG, DDR_SIZE/0x100000 +#else +.set DDR_REG, 0 +#endif + .set UNDEF_REG, 0x3FF - DDR_REG - /*0x00000000 - 0x00100000 (cacheable )*/ + /*0x00000000 - 0x00100000 (cacheable )*/ .word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ .set SECT, SECT+0x100000