diff --git a/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_sst_dp159_example.c b/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_sst_dp159_example.c index df017343..2208f603 100644 --- a/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_sst_dp159_example.c +++ b/XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_sst_dp159_example.c @@ -533,6 +533,8 @@ static void Dprx_Dp159Config(XDp *InstancePtr, XIic *IicInstancePtr, LaneCount = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LANE_COUNT_SET); + LaneCount &= XDP_RX_OVER_LANE_COUNT_SET_MASK; + LinkRate = XDp_ReadReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LINK_BW_SET); diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp.c b/XilinxProcessorIPLib/drivers/dp/src/xdp.c index e6295aea..d0e03dbc 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.c @@ -1569,6 +1569,14 @@ void XDp_RxSetLaneCount(XDp *InstancePtr, u8 LaneCount) InstancePtr->RxInstance.LinkConfig.LaneCount = LaneCount; + /* Use enhanced framing mode to meet the DisplayPort specification. */ + LaneCount |= XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK; + /* If the core is a DisplayPort v1.2 or newer core, always support + * training pattern 3 to meet the specification. */ + if (InstancePtr->Config.DpProtocol) { + LaneCount |= XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK; + } + XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x1); XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LANE_COUNT_SET, LaneCount);