From 759573e90f6a4a88540112f255a144b5252dbb6e Mon Sep 17 00:00:00 2001
From: Rohit Consul <rohit.consul@xilinx.com>
Date: Fri, 31 Jul 2015 13:47:46 -0700
Subject: [PATCH] v_hscaler: Bug Fix in phase calculation logic

4 Samples/Clock phase calculation logic works on 64bit entities.
However a 32bit variable was used that caused wrong phase
information to be generated. Updated relevant variables to 64b

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
---
 XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c
index a63b717f..af8fb2a0 100644
--- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c
+++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c
@@ -273,10 +273,10 @@ static void CalculatePhases(XV_hscaler *pHsc,
     int x,s;
     int offset = 0;
     int xWritePos = 0;
-    int OutputWriteEn;
+    u64 OutputWriteEn;
     int GetNewPix;
-    int PhaseH;
-    int arrayIdx;
+    u64 PhaseH;
+    u64 arrayIdx;
     int xReadPos = 0;
     int nrRds = 0;
     int nrRdsClck = 0;