diff --git a/XilinxProcessorIPLib/drivers/canps/data/canps.mdd b/XilinxProcessorIPLib/drivers/canps/data/canps.mdd
index 348e99ab..c46cad57 100755
--- a/XilinxProcessorIPLib/drivers/canps/data/canps.mdd
+++ b/XilinxProcessorIPLib/drivers/canps/data/canps.mdd
@@ -33,7 +33,7 @@ OPTION psf_version = 2.1;
 
 BEGIN driver canps
 
-  OPTION supported_peripherals = (ps7_can);
+  OPTION supported_peripherals = (ps7_can ps8_can pss_can);
   OPTION driver_state = ACTIVE;
   OPTION copyfiles = all;
   OPTION VERSION = 3.0;
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps.c
index 3fd73403..c332b1f8 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps.c
@@ -91,10 +91,10 @@ static void StubHandler(void);
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
 				u32 EffectiveAddr)
 {
-
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(ConfigPtr != NULL);
 
@@ -102,7 +102,7 @@ int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
 	 * Set some default values for instance data, don't indicate the device
 	 * is ready to use until everything has been initialized successfully.
 	 */
-	InstancePtr->IsReady = 0;
+	InstancePtr->IsReady = 0U;
 	InstancePtr->CanConfig.BaseAddr = EffectiveAddr;
 	InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId;
 
@@ -124,7 +124,8 @@ int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
 	 */
 	XCanPs_Reset(InstancePtr);
 
-	return XST_SUCCESS;
+	Status = XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -187,23 +188,26 @@ u8 XCanPs_GetMode(XCanPs *InstancePtr)
 
 	StatusReg = XCanPs_GetStatus(InstancePtr);
 
-	if (StatusReg & XCANPS_SR_CONFIG_MASK) {
-		return XCANPS_MODE_CONFIG;
+	if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) {
+		return (u8)XCANPS_MODE_CONFIG;
 
-	} else if (StatusReg & XCANPS_SR_SLEEP_MASK) {
-		return XCANPS_MODE_SLEEP;
+	}
+	else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) {
+		return (u8)XCANPS_MODE_SLEEP;
 
-	} else if (StatusReg & XCANPS_SR_NORMAL_MASK) {
-		if (StatusReg & XCANPS_SR_SNOOP_MASK) {
-			return XCANPS_MODE_SNOOP;
+	}
+	else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) {
+		if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) {
+			return (u8)XCANPS_MODE_SNOOP;
 		} else {
-			return XCANPS_MODE_NORMAL;
+			return (u8)XCANPS_MODE_NORMAL;
 		}
-	} else {
+	}
+	else {
 		/*
 		 * If this line is reached, the device is in Loop Back Mode.
 		 */
-		return XCANPS_MODE_LOOPBACK;
+		return (u8)XCANPS_MODE_LOOPBACK;
 	}
 }
 
@@ -241,11 +245,11 @@ void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
 
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid((OperationMode == XCANPS_MODE_CONFIG) ||
-			(OperationMode == XCANPS_MODE_SLEEP) ||
-			(OperationMode == XCANPS_MODE_NORMAL) ||
-			(OperationMode == XCANPS_MODE_LOOPBACK) ||
-			(OperationMode == XCANPS_MODE_SNOOP));
+	Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) ||
+			(OperationMode == (u8)XCANPS_MODE_SLEEP) ||
+			(OperationMode == (u8)XCANPS_MODE_NORMAL) ||
+			(OperationMode == (u8)XCANPS_MODE_LOOPBACK) ||
+			(OperationMode == (u8)XCANPS_MODE_SNOOP));
 
 	CurrentMode = XCanPs_GetMode(InstancePtr);
 
@@ -254,8 +258,8 @@ void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
 	 * or if current mode is Sleep Mode and the mode to enter is Normal
 	 * Mode, no transition through Configuration Mode is needed.
 	 */
-	if ((CurrentMode == XCANPS_MODE_NORMAL) &&
-		(OperationMode == XCANPS_MODE_SLEEP)) {
+	if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) &&
+		(OperationMode == (u8)XCANPS_MODE_SLEEP)) {
 		/*
 		 * Normal Mode ---> Sleep Mode
 		 */
@@ -263,16 +267,19 @@ void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
 				XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
 		return;
 
-	} else if ((CurrentMode == XCANPS_MODE_SLEEP) &&
-		 (OperationMode == XCANPS_MODE_NORMAL)) {
+	} else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) &&
+		 (OperationMode == (u8)XCANPS_MODE_NORMAL)) {
 		/*
 		 * Sleep Mode ---> Normal Mode
 		 */
 		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_MSR_OFFSET, 0);
+					XCANPS_MSR_OFFSET, 0U);
 		return;
 	}
-
+	else {
+		/*This else was made for misra-c compliance*/
+		;
+	}
 
 	/*
 	 * If the mode transition is not any of the two cases above, CAN must
@@ -280,51 +287,55 @@ void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
 	 * mode.
 	 */
 	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, 0);
+				XCANPS_SRR_OFFSET, 0U);
 
 	/*
 	 * Check if the device has entered Configuration Mode, if not, return to
 	 * the caller.
 	 */
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
 		return;
 	}
 
 	switch (OperationMode) {
-	case XCANPS_MODE_CONFIG:
-		/*
-		 * As CAN is in Configuration Mode already.
-		 * Nothing is needed to be done here.
-		 */
-		break;
+		case XCANPS_MODE_CONFIG:
+			/*
+			 * As CAN is in Configuration Mode already.
+			 * Nothing is needed to be done here.
+			 */
+			break;
 
-	case XCANPS_MODE_SLEEP:
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-		break;
+		case XCANPS_MODE_SLEEP:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
 
-	case XCANPS_MODE_NORMAL:
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_MSR_OFFSET, 0);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-		break;
+		case XCANPS_MODE_NORMAL:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, 0U);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
 
-	case XCANPS_MODE_LOOPBACK:
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-		break;
+		case XCANPS_MODE_LOOPBACK:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
 
-	case XCANPS_MODE_SNOOP:
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
-		break;
+		case XCANPS_MODE_SNOOP:
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK);
+			XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+					XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+			break;
+
+		default:
+			/*This default was made for misra-c compliance*/
+			break;
 
 	}
 }
@@ -383,9 +394,9 @@ void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
 	 */
 	ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
 				XCANPS_ECR_OFFSET);
-	*RxErrorCount = (ErrorCount & XCANPS_ECR_REC_MASK) >>
-				XCANPS_ECR_REC_SHIFT;
-	*TxErrorCount = ErrorCount & XCANPS_ECR_TEC_MASK;
+	*RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >>
+				XCANPS_ECR_REC_SHIFT);
+	*TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK);
 }
 
 /*****************************************************************************/
@@ -459,29 +470,32 @@ void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask)
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
 {
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(FramePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) {
-		return XST_FIFO_NO_ROOM;
+		Status = XST_FIFO_NO_ROOM;
+	} else {
+
+		/*
+		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DW1_OFFSET, FramePtr[2]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXFIFO_DW2_OFFSET, FramePtr[3]);
+
+		Status = XST_SUCCESS;
 	}
-
-	/*
-	 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
-	 */
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXFIFO_DW1_OFFSET, FramePtr[2]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXFIFO_DW2_OFFSET, FramePtr[3]);
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -504,35 +518,38 @@ int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
 {
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(FramePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) {
-		return XST_NO_DATA;
+		Status = XST_NO_DATA;
+	} else {
+
+		/*
+		 * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
+		 */
+		FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_ID_OFFSET);
+		FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DLC_OFFSET);
+		FramePtr[2] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DW1_OFFSET);
+		FramePtr[3] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						XCANPS_RXFIFO_DW2_OFFSET);
+
+		/*
+		 * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
+		 * returns correct RX FIFO occupancy/empty condition.
+		 */
+		XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);
+
+		Status = XST_SUCCESS;
 	}
-
-	/*
-	 * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
-	 */
-	FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_RXFIFO_ID_OFFSET);
-	FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_RXFIFO_DLC_OFFSET);
-	FramePtr[2] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_RXFIFO_DW1_OFFSET);
-	FramePtr[3] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					XCANPS_RXFIFO_DW2_OFFSET);
-
-	/*
-	 * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
-	 * returns correct RX FIFO occupancy/empty condition.
-	 */
-	XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -549,7 +566,7 @@ int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
 *
 * @return
 *		- XST_SUCCESS if TX High Priority Buffer was not full and the
-*		given frame was written into the buffer;
+*		given frame was written into the buffer.
 *		- XST_FIFO_NO_ROOM if there is no room in the TX High Priority
 *		Buffer for this frame.
 *
@@ -560,29 +577,32 @@ int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
 * level before invoking this function.
 *
 ******************************************************************************/
-int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
 {
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(FramePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) {
-		return XST_FIFO_NO_ROOM;
+		Status = XST_FIFO_NO_ROOM;
+	} else {
+
+		/*
+		 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+		 */
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DW1_OFFSET, FramePtr[2]);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_TXHPB_DW2_OFFSET, FramePtr[3]);
+
+		Status = XST_SUCCESS;
 	}
-
-	/*
-	 * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
-	 */
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXHPB_DW1_OFFSET, FramePtr[2]);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_TXHPB_DW2_OFFSET, FramePtr[3]);
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -617,7 +637,7 @@ void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes)
 	EnabledFilters =  XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
 						XCANPS_AFR_OFFSET);
 	EnabledFilters |= FilterIndexes;
-	EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK;
+	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK;
 	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
 			EnabledFilters);
 }
@@ -655,7 +675,7 @@ void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes)
 	 */
 	EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
 					XCANPS_AFR_OFFSET);
-	EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
+	EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
 	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
 			   EnabledFilters);
 }
@@ -695,7 +715,7 @@ u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
 * filter. Read the xcanps.h file and device specification for details.
 *
 * This function should be called only after:
-*   - The given filter is disabled by calling XCanPs_AcceptFilterDisable();
+*   - The given filter is disabled by calling XCanPs_AcceptFilterDisable()
 *   - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
 *	 XCanPs_IsAcceptFilterBusy() returns FALSE.
 *
@@ -715,10 +735,11 @@ u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
 			 u32 MaskValue, u32 IdValue)
 {
 	u32 EnabledFilters;
+	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -732,52 +753,59 @@ int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
 	 */
 	EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr);
 	if ((EnabledFilters & FilterIndex) == FilterIndex) {
-		return XST_FAILURE;
+		Status = XST_FAILURE;
+	} else {
+
+		/*
+		 * If the CAN device is not ready to accept writes to AFMR and AFIR,
+		 * return error code.
+		 */
+		if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
+			Status = XST_FAILURE;
+		} else {
+
+			/*
+			 * Write to the AFMR and AFIR of the specified filter.
+			 */
+			switch (FilterIndex) {
+				case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
+
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR1_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR1_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR2_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR2_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR3_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR3_OFFSET, IdValue);
+					break;
+
+				case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFMR4_OFFSET, MaskValue);
+					XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+							XCANPS_AFIR4_OFFSET, IdValue);
+					break;
+
+				default:
+					/*This default was made for misra-c compliance*/
+					break;
+			}
+
+			Status = XST_SUCCESS;
+		}
 	}
-
-	/*
-	 * If the CAN device is not ready to accept writes to AFMR and AFIR,
-	 * return error code.
-	 */
-	if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
-		return XST_FAILURE;
-	}
-
-	/*
-	 * Write to the AFMR and AFIR of the specified filter.
-	 */
-	switch (FilterIndex) {
-	case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
-
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFMR1_OFFSET, MaskValue);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFIR1_OFFSET, IdValue);
-		break;
-
-	case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFMR2_OFFSET, MaskValue);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFIR2_OFFSET, IdValue);
-		break;
-
-	case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFMR3_OFFSET, MaskValue);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFIR3_OFFSET, IdValue);
-		break;
-
-	case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFMR4_OFFSET, MaskValue);
-		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-				XCANPS_AFIR4_OFFSET, IdValue);
-		break;
-	}
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -817,33 +845,37 @@ void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
 	 * Read from the AFMR and AFIR of the specified filter.
 	 */
 	switch (FilterIndex) {
-	case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
-		*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFMR1_OFFSET);
-		*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFIR1_OFFSET);
-		break;
+		case XCANPS_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR1_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR1_OFFSET);
+			break;
 
-	case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
-		*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFMR2_OFFSET);
-		*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFIR2_OFFSET);
-		break;
+		case XCANPS_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR2_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR2_OFFSET);
+			break;
 
-	case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
-		*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFMR3_OFFSET);
-		*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFIR3_OFFSET);
-		break;
+		case XCANPS_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR3_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR3_OFFSET);
+			break;
 
-	case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
-		*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFMR4_OFFSET);
-		*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-					  XCANPS_AFIR4_OFFSET);
-		break;
+		case XCANPS_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
+			*MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFMR4_OFFSET);
+			*IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+						  XCANPS_AFIR4_OFFSET);
+			break;
+
+		default:
+			/*This default was made for misra-c compliance*/
+			break;
 	}
 }
 
@@ -870,19 +902,22 @@ void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
 {
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
-		return XST_FAILURE;
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET,
+					(u32)Prescaler);
+
+		Status = XST_SUCCESS;
 	}
-
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET,
-				(u32)Prescaler);
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -903,12 +938,13 @@ int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
 ******************************************************************************/
 u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr)
 {
+	u32 ReadValue;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	return (u8) XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+	ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
 					XCANPS_BRPR_OFFSET);
-
+	return ((u8)ReadValue);
 }
 
 /*****************************************************************************/
@@ -938,31 +974,34 @@ u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr)
 * @note		None.
 *
 ******************************************************************************/
-int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
 			  u8 TimeSegment2, u8 TimeSegment1)
 {
 	u32 Value;
+	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(SyncJumpWidth <= 3);
-	Xil_AssertNonvoid(TimeSegment2 <= 7);
-	Xil_AssertNonvoid(TimeSegment1 <= 15 );
+	Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U);
+	Xil_AssertNonvoid(TimeSegment2 <= (u8)7U);
+	Xil_AssertNonvoid(TimeSegment1 <= (u8)15U );
 
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
-		return XST_FAILURE;
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
+
+		Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK;
+		Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) &
+			XCANPS_BTR_TS2_MASK;
+		Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) &
+			XCANPS_BTR_SJW_MASK;
+
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_BTR_OFFSET, Value);
+
+		Status = XST_SUCCESS;
 	}
-
-	Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK;
-	Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) &
-		XCANPS_BTR_TS2_MASK;
-	Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) &
-		XCANPS_BTR_SJW_MASK;
-
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_BTR_OFFSET, Value);
-
-	return XST_SUCCESS;
+	return Status;
 }
 
 /*****************************************************************************/
@@ -1026,26 +1065,30 @@ void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
 *		configuration mode.
 *
 *****************************************************************************/
-int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
 {
 
 	u32 ThrReg;
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Threshold <= 63);
+	Xil_AssertNonvoid(Threshold <= (u8)63);
 
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG)
-		return XST_FAILURE;
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
 
-	ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_WIR_OFFSET);
+		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET);
 
-	ThrReg &= XCANPS_WIR_EW_MASK;
-	ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_WIR_OFFSET, ThrReg);
+		ThrReg &= XCANPS_WIR_EW_MASK;
+		ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET, ThrReg);
 
-	return XST_SUCCESS;
+		Status = XST_SUCCESS;
+	}
+	return Status;
 }
 
 /****************************************************************************/
@@ -1092,26 +1135,30 @@ u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr)
 *		configuration mode.
 *
 *****************************************************************************/
-int XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
 {
 	u32 ThrReg;
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(Threshold <= 63);
+	Xil_AssertNonvoid(Threshold <= (u8)63);
 
-	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG)
-		return XST_FAILURE;
+	if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+		Status = XST_FAILURE;
+	} else {
 
-	ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_WIR_OFFSET);
+		ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET);
 
-	ThrReg &= XCANPS_WIR_FW_MASK;
-	ThrReg |= ((u32)(Threshold << XCANPS_WIR_EW_SHIFT)
-			& XCANPS_WIR_EW_MASK);
-	XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
-			XCANPS_WIR_OFFSET, ThrReg);
+		ThrReg &= XCANPS_WIR_FW_MASK;
+		ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT)
+				& XCANPS_WIR_EW_MASK);
+		XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+				XCANPS_WIR_OFFSET, ThrReg);
 
-	return XST_SUCCESS;
+		Status = XST_SUCCESS;
+	}
+	return Status;
 }
 
 /****************************************************************************/
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps.h b/XilinxProcessorIPLib/drivers/canps/src/xcanps.h
index 6c3c4f44..38022c0f 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps.h
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps.h
@@ -194,7 +194,8 @@
 *			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
 *			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
 * 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
-*						 SDK claims a 40kbps baud rate but it's not.
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.
 * </pre>
 *
 ******************************************************************************/
@@ -209,26 +210,27 @@ extern "C" {
 
 #include "xstatus.h"
 #include "xcanps_hw.h"
+#include "xil_types.h"
 
 /************************** Constant Definitions *****************************/
 
 /** @name CAN operation modes
  *  @{
  */
-#define XCANPS_MODE_CONFIG	0x00000001 /**< Configuration mode */
-#define XCANPS_MODE_NORMAL	0x00000002 /**< Normal mode */
-#define XCANPS_MODE_LOOPBACK	0x00000004 /**< Loop Back mode */
-#define XCANPS_MODE_SLEEP	0x00000008 /**< Sleep mode */
-#define XCANPS_MODE_SNOOP	0x00000010 /**< Snoop mode */
+#define XCANPS_MODE_CONFIG	0x00000001U /**< Configuration mode */
+#define XCANPS_MODE_NORMAL	0x00000002U /**< Normal mode */
+#define XCANPS_MODE_LOOPBACK	0x00000004U /**< Loop Back mode */
+#define XCANPS_MODE_SLEEP	0x00000008U /**< Sleep mode */
+#define XCANPS_MODE_SNOOP	0x00000010U /**< Snoop mode */
 /* @} */
 
 /** @name Callback identifiers used as parameters to XCanPs_SetHandler()
  *  @{
  */
-#define XCANPS_HANDLER_SEND 1 /**< Handler type for frame sending interrupt */
-#define XCANPS_HANDLER_RECV 2 /**< Handler type for frame reception interrupt*/
-#define XCANPS_HANDLER_ERROR  3 /**< Handler type for error interrupt */
-#define XCANPS_HANDLER_EVENT  4 /**< Handler type for all other interrupts */
+#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
+#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
+#define XCANPS_HANDLER_ERROR  3U /**< Handler type for error interrupt */
+#define XCANPS_HANDLER_EVENT  4U /**< Handler type for all other interrupts */
 /* @} */
 
 /**************************** Type Definitions *******************************/
@@ -328,12 +330,12 @@ typedef struct {
 *		- FALSE if the transmission is not done.
 *
 * @note		C-Style signature:
-*		int XCanPs_IsTxDone(XCanPs *InstancePtr);
+*		int XCanPs_IsTxDone(XCanPs *InstancePtr)
 *
 *******************************************************************************/
 #define XCanPs_IsTxDone(InstancePtr) \
-	((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),		\
-		XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) ? TRUE : FALSE)
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),		\
+		XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
 
 
 /****************************************************************************/
@@ -348,12 +350,12 @@ typedef struct {
 *		- FALSE if the TX FIFO is NOT full.
 *
 * @note		C-Style signature:
-*		int XCanPs_IsTxFifoFull(XCanPs *InstancePtr);
+*		int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
 *
 *****************************************************************************/
 #define XCanPs_IsTxFifoFull(InstancePtr) \
-	((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) ? TRUE : FALSE)
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
 
 
 /****************************************************************************/
@@ -368,12 +370,12 @@ typedef struct {
 *		- FALSE if the TX High Priority Buffer is NOT full.
 *
 * @note		C-Style signature:
-*		int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr);
+*		int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
 *
 *****************************************************************************/
 #define XCanPs_IsHighPriorityBufFull(InstancePtr) \
-	((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) ? TRUE : FALSE)
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
 
 
 /****************************************************************************/
@@ -388,12 +390,12 @@ typedef struct {
 *		- FALSE if the RX FIFO is NOT empty.
 *
 * @note		C-Style signature:
-*		int XCanPs_IsRxEmpty(XCanPs *InstancePtr);
+*		int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
 *
 *****************************************************************************/
 #define XCanPs_IsRxEmpty(InstancePtr) \
-	((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) ? FALSE : TRUE)
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
 
 
 /****************************************************************************/
@@ -418,12 +420,12 @@ typedef struct {
 *		AFMR.
 *
 * @note		C-Style signature:
-*		int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr);
+*		int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
 *
 *****************************************************************************/
 #define XCanPs_IsAcceptFilterBusy(InstancePtr) 		\
-	((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
-		XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) ? TRUE : FALSE)
+	(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), 	\
+		XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
 
 
 /****************************************************************************/
@@ -445,7 +447,7 @@ typedef struct {
 *		u32 XCanPs_CreateIdValue(u32 StandardId,
 *					u32 SubRemoteTransReq,
 *					u32 IdExtension, u32 ExtendedId,
-*					u32 RemoteTransReq);
+*					u32 RemoteTransReq)
 *
 *		Read the CAN specification for meaning of each parameter.
 *
@@ -470,7 +472,7 @@ typedef struct {
 * @return	Value that can be assigned to Data Length Code register.
 *
 * @note		C-Style signature:
-*		u32 XCanPs_CreateDlcValue(u32 DataLengCode);
+*		u32 XCanPs_CreateDlcValue(u32 DataLengCode)
 *
 *		Read the CAN specification for meaning of Data Length Code.
 *
@@ -489,7 +491,7 @@ typedef struct {
 * @return	None.
 *
 * @note		C-Style signature:
-*		void XCanPs_ClearTimestamp(XCanPs *InstancePtr);
+*		void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
 *
 *****************************************************************************/
 #define XCanPs_ClearTimestamp(InstancePtr) 			\
@@ -501,7 +503,7 @@ typedef struct {
 /*
  * Functions in xcanps.c
  */
-int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
 				u32 EffectiveAddr);
 
 void XCanPs_Reset(XCanPs *InstancePtr);
@@ -512,31 +514,33 @@ void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
 				 u8 *TxErrorCount);
 u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
 void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
-int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
-int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
-int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
 void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
 void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
 u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
-int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
 			 u32 MaskValue, u32 IdValue);
 void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
 			  u32 *MaskValue, u32 *IdValue);
 
-int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
 u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
-int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
 			  u8 TimeSegment2, u8 TimeSegment1);
 void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
 			   u8 *TimeSegment2, u8 *TimeSegment1);
 
-int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
 u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
 
 /*
  * Diagnostic functions in xcanps_selftest.c
  */
-int XCanPs_SelfTest(XCanPs *InstancePtr);
+s32 XCanPs_SelfTest(XCanPs *InstancePtr);
 
 /*
  * Functions in xcanps_intr.c
@@ -547,7 +551,7 @@ u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
 u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
 void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
 void XCanPs_IntrHandler(void *InstancePtr);
-int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
 			void *CallBackFunc, void *CallBackRef);
 
 /*
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_g.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps_g.c
index 048d79b7..58f1dfc4 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_g.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_g.c
@@ -73,13 +73,13 @@
  */
 XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = {
 	{
-		XPAR_XCANPS_0_DEVICE_ID,	/* Unique ID of device */
-		XPAR_XCANPS_0_BASEADDR		/* Base address of device */
+		(u16)XPAR_XCANPS_0_DEVICE_ID,	/* Unique ID of device */
+		(u32)XPAR_XCANPS_0_BASEADDR		/* Base address of device */
 	},
 #ifdef XPAR_XCANPS_1_DEVICE_ID
 	{
-		XPAR_XCANPS_1_DEVICE_ID,	/* Unique ID of device */
-		XPAR_XCANPS_1_BASEADDR		/* Base address of device */
+		(u16)XPAR_XCANPS_1_DEVICE_ID,	/* Unique ID of device */
+		(u32)XPAR_XCANPS_1_BASEADDR		/* Base address of device */
 	}
 #endif
 };
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.c
index b580c065..8760163f 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.c
@@ -48,8 +48,8 @@
 
 /***************************** Include Files *********************************/
 
-#include "xparameters.h"
 #include "xcanps_hw.h"
+#include "xparameters.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -86,4 +86,4 @@ void XCanPs_ResetHw(u32 BaseAddr)
 {
 	XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
 			   XCANPS_SRR_SRST_MASK);
-}
\ No newline at end of file
+}
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.h b/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.h
index 68ec1835..67af3fac 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.h
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_hw.h
@@ -79,158 +79,158 @@ extern "C" {
 /** @name Register offsets for the CAN. Each register is 32 bits.
  *  @{
  */
-#define XCANPS_SRR_OFFSET	  	0x00 /**< Software Reset Register */
-#define XCANPS_MSR_OFFSET	  	0x04 /**< Mode Select Register */
-#define XCANPS_BRPR_OFFSET	  	0x08 /**< Baud Rate Prescaler */
-#define XCANPS_BTR_OFFSET	  	0x0C /**< Bit Timing Register */
-#define XCANPS_ECR_OFFSET	  	0x10 /**< Error Counter Register */
-#define XCANPS_ESR_OFFSET	  	0x14 /**< Error Status Register */
-#define XCANPS_SR_OFFSET	  	0x18 /**< Status Register */
+#define XCANPS_SRR_OFFSET	  	0x00000000U /**< Software Reset Register */
+#define XCANPS_MSR_OFFSET	  	0x00000004U /**< Mode Select Register */
+#define XCANPS_BRPR_OFFSET	  	0x00000008U /**< Baud Rate Prescaler */
+#define XCANPS_BTR_OFFSET	  	0x0000000CU /**< Bit Timing Register */
+#define XCANPS_ECR_OFFSET	  	0x00000010U /**< Error Counter Register */
+#define XCANPS_ESR_OFFSET	  	0x00000014U /**< Error Status Register */
+#define XCANPS_SR_OFFSET	  	0x00000018U /**< Status Register */
 
-#define XCANPS_ISR_OFFSET	  	0x1C /**< Interrupt Status Register */
-#define XCANPS_IER_OFFSET	  	0x20 /**< Interrupt Enable Register */
-#define XCANPS_ICR_OFFSET	  	0x24 /**< Interrupt Clear Register */
-#define XCANPS_TCR_OFFSET	  	0x28 /**< Timestamp Control Register */
-#define XCANPS_WIR_OFFSET	  	0x2C /**< Watermark Interrupt Reg */
+#define XCANPS_ISR_OFFSET	  	0x0000001CU /**< Interrupt Status Register */
+#define XCANPS_IER_OFFSET	  	0x00000020U /**< Interrupt Enable Register */
+#define XCANPS_ICR_OFFSET	  	0x00000024U /**< Interrupt Clear Register */
+#define XCANPS_TCR_OFFSET	  	0x00000028U /**< Timestamp Control Register */
+#define XCANPS_WIR_OFFSET	  	0x0000002CU /**< Watermark Interrupt Reg */
 
-#define XCANPS_TXFIFO_ID_OFFSET  	0x30 /**< TX FIFO ID */
-#define XCANPS_TXFIFO_DLC_OFFSET 	0x34 /**< TX FIFO DLC */
-#define XCANPS_TXFIFO_DW1_OFFSET	0x38 /**< TX FIFO Data Word 1 */
-#define XCANPS_TXFIFO_DW2_OFFSET 	0x3C /**< TX FIFO Data Word 2 */
+#define XCANPS_TXFIFO_ID_OFFSET  	0x00000030U /**< TX FIFO ID */
+#define XCANPS_TXFIFO_DLC_OFFSET 	0x00000034U /**< TX FIFO DLC */
+#define XCANPS_TXFIFO_DW1_OFFSET	0x00000038U /**< TX FIFO Data Word 1 */
+#define XCANPS_TXFIFO_DW2_OFFSET 	0x0000003CU /**< TX FIFO Data Word 2 */
 
-#define XCANPS_TXHPB_ID_OFFSET   	0x40 /**< TX High Priority Buffer ID */
-#define XCANPS_TXHPB_DLC_OFFSET  	0x44 /**< TX High Priority Buffer DLC */
-#define XCANPS_TXHPB_DW1_OFFSET  	0x48 /**< TX High Priority Buf Data 1 */
-#define XCANPS_TXHPB_DW2_OFFSET  	0x4C /**< TX High Priority Buf Data Word 2 */
+#define XCANPS_TXHPB_ID_OFFSET   	0x00000040U /**< TX High Priority Buffer ID */
+#define XCANPS_TXHPB_DLC_OFFSET  	0x00000044U /**< TX High Priority Buffer DLC */
+#define XCANPS_TXHPB_DW1_OFFSET  	0x00000048U /**< TX High Priority Buf Data 1 */
+#define XCANPS_TXHPB_DW2_OFFSET  	0x0000004CU /**< TX High Priority Buf Data Word 2 */
 
-#define XCANPS_RXFIFO_ID_OFFSET  	0x50 /**< RX FIFO ID */
-#define XCANPS_RXFIFO_DLC_OFFSET 	0x54 /**< RX FIFO DLC */
-#define XCANPS_RXFIFO_DW1_OFFSET 	0x58 /**< RX FIFO Data Word 1 */
-#define XCANPS_RXFIFO_DW2_OFFSET 	0x5C /**< RX FIFO Data Word 2 */
+#define XCANPS_RXFIFO_ID_OFFSET  	0x00000050U /**< RX FIFO ID */
+#define XCANPS_RXFIFO_DLC_OFFSET 	0x00000054U /**< RX FIFO DLC */
+#define XCANPS_RXFIFO_DW1_OFFSET 	0x00000058U /**< RX FIFO Data Word 1 */
+#define XCANPS_RXFIFO_DW2_OFFSET 	0x0000005CU /**< RX FIFO Data Word 2 */
 
-#define XCANPS_AFR_OFFSET	  	0x60 /**< Acceptance Filter Register */
-#define XCANPS_AFMR1_OFFSET	  	0x64 /**< Acceptance Filter Mask 1 */
-#define XCANPS_AFIR1_OFFSET	  	0x68 /**< Acceptance Filter ID  1 */
-#define XCANPS_AFMR2_OFFSET	  	0x6C /**< Acceptance Filter Mask  2 */
-#define XCANPS_AFIR2_OFFSET	  	0x70 /**< Acceptance Filter ID 2 */
-#define XCANPS_AFMR3_OFFSET	  	0x74 /**< Acceptance Filter Mask 3 */
-#define XCANPS_AFIR3_OFFSET	  	0x78 /**< Acceptance Filter ID 3 */
-#define XCANPS_AFMR4_OFFSET	  	0x7C /**< Acceptance Filter Mask  4 */
-#define XCANPS_AFIR4_OFFSET	  	0x80 /**< Acceptance Filter ID 4 */
+#define XCANPS_AFR_OFFSET	  	0x00000060U /**< Acceptance Filter Register */
+#define XCANPS_AFMR1_OFFSET	  	0x00000064U /**< Acceptance Filter Mask 1 */
+#define XCANPS_AFIR1_OFFSET	  	0x00000068U /**< Acceptance Filter ID  1 */
+#define XCANPS_AFMR2_OFFSET	  	0x0000006CU /**< Acceptance Filter Mask  2 */
+#define XCANPS_AFIR2_OFFSET	  	0x00000070U /**< Acceptance Filter ID 2 */
+#define XCANPS_AFMR3_OFFSET	  	0x00000074U /**< Acceptance Filter Mask 3 */
+#define XCANPS_AFIR3_OFFSET	  	0x00000078U /**< Acceptance Filter ID 3 */
+#define XCANPS_AFMR4_OFFSET	  	0x0000007CU /**< Acceptance Filter Mask  4 */
+#define XCANPS_AFIR4_OFFSET	  	0x00000080U /**< Acceptance Filter ID 4 */
 /* @} */
 
 /** @name Software Reset Register (SRR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_SRR_CEN_MASK	0x00000002  /**< Can Enable */
-#define XCANPS_SRR_SRST_MASK	0x00000001  /**< Reset */
+#define XCANPS_SRR_CEN_MASK		0x00000002U  /**< Can Enable */
+#define XCANPS_SRR_SRST_MASK	0x00000001U  /**< Reset */
 /* @} */
 
 /** @name Mode Select Register (MSR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_MSR_SNOOP_MASK	0x00000004 /**< Snoop Mode Select */
-#define XCANPS_MSR_LBACK_MASK	0x00000002 /**< Loop Back Mode Select */
-#define XCANPS_MSR_SLEEP_MASK	0x00000001 /**< Sleep Mode Select */
+#define XCANPS_MSR_SNOOP_MASK	0x00000004U /**< Snoop Mode Select */
+#define XCANPS_MSR_LBACK_MASK	0x00000002U /**< Loop Back Mode Select */
+#define XCANPS_MSR_SLEEP_MASK	0x00000001U /**< Sleep Mode Select */
 /* @} */
 
 /** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_BRPR_BRP_MASK	0x000000FF /**< Baud Rate Prescaler */
+#define XCANPS_BRPR_BRP_MASK	0x000000FFU /**< Baud Rate Prescaler */
 /* @} */
 
 /** @name Bit Timing Register (BTR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_BTR_SJW_MASK	0x00000180 /**< Synchronization Jump Width */
-#define XCANPS_BTR_SJW_SHIFT	7
-#define XCANPS_BTR_TS2_MASK	0x00000070 /**< Time Segment 2 */
-#define XCANPS_BTR_TS2_SHIFT	4
-#define XCANPS_BTR_TS1_MASK	0x0000000F /**< Time Segment 1 */
+#define XCANPS_BTR_SJW_MASK	0x00000180U /**< Synchronization Jump Width */
+#define XCANPS_BTR_SJW_SHIFT	7U
+#define XCANPS_BTR_TS2_MASK	0x00000070U /**< Time Segment 2 */
+#define XCANPS_BTR_TS2_SHIFT	4U
+#define XCANPS_BTR_TS1_MASK	0x0000000FU /**< Time Segment 1 */
 /* @} */
 
 /** @name Error Counter Register (ECR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_ECR_REC_MASK	0x0000FF00 /**< Receive Error Counter */
-#define XCANPS_ECR_REC_SHIFT	8
-#define XCANPS_ECR_TEC_MASK	0x000000FF /**< Transmit Error Counter */
+#define XCANPS_ECR_REC_MASK	0x0000FF00U /**< Receive Error Counter */
+#define XCANPS_ECR_REC_SHIFT		 8U
+#define XCANPS_ECR_TEC_MASK	0x000000FFU /**< Transmit Error Counter */
 /* @} */
 
 /** @name Error Status Register (ESR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_ESR_ACKER_MASK	0x00000010 /**< ACK Error */
-#define XCANPS_ESR_BERR_MASK	0x00000008 /**< Bit Error */
-#define XCANPS_ESR_STER_MASK	0x00000004 /**< Stuff Error */
-#define XCANPS_ESR_FMER_MASK	0x00000002 /**< Form Error */
-#define XCANPS_ESR_CRCER_MASK	0x00000001 /**< CRC Error */
+#define XCANPS_ESR_ACKER_MASK	0x00000010U /**< ACK Error */
+#define XCANPS_ESR_BERR_MASK	0x00000008U /**< Bit Error */
+#define XCANPS_ESR_STER_MASK	0x00000004U /**< Stuff Error */
+#define XCANPS_ESR_FMER_MASK	0x00000002U /**< Form Error */
+#define XCANPS_ESR_CRCER_MASK	0x00000001U /**< CRC Error */
 /* @} */
 
 /** @name Status Register (SR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_SR_SNOOP_MASK	0x00001000 /**< Snoop Mask */
-#define XCANPS_SR_ACFBSY_MASK	0x00000800 /**< Acceptance Filter busy */
-#define XCANPS_SR_TXFLL_MASK	0x00000400 /**< TX FIFO is full */
-#define XCANPS_SR_TXBFLL_MASK	0x00000200 /**< TX High Priority Buffer full */
-#define XCANPS_SR_ESTAT_MASK	0x00000180 /**< Error Status */
-#define XCANPS_SR_ESTAT_SHIFT	7
-#define XCANPS_SR_ERRWRN_MASK	0x00000040 /**< Error Warning */
-#define XCANPS_SR_BBSY_MASK	0x00000020 /**< Bus Busy */
-#define XCANPS_SR_BIDLE_MASK	0x00000010 /**< Bus Idle */
-#define XCANPS_SR_NORMAL_MASK	0x00000008 /**< Normal Mode */
-#define XCANPS_SR_SLEEP_MASK	0x00000004 /**< Sleep Mode */
-#define XCANPS_SR_LBACK_MASK	0x00000002 /**< Loop Back Mode */
-#define XCANPS_SR_CONFIG_MASK	0x00000001 /**< Configuration Mode */
+#define XCANPS_SR_SNOOP_MASK	0x00001000U /**< Snoop Mask */
+#define XCANPS_SR_ACFBSY_MASK	0x00000800U /**< Acceptance Filter busy */
+#define XCANPS_SR_TXFLL_MASK	0x00000400U /**< TX FIFO is full */
+#define XCANPS_SR_TXBFLL_MASK	0x00000200U /**< TX High Priority Buffer full */
+#define XCANPS_SR_ESTAT_MASK	0x00000180U /**< Error Status */
+#define XCANPS_SR_ESTAT_SHIFT			 7U
+#define XCANPS_SR_ERRWRN_MASK	0x00000040U /**< Error Warning */
+#define XCANPS_SR_BBSY_MASK		0x00000020U /**< Bus Busy */
+#define XCANPS_SR_BIDLE_MASK	0x00000010U /**< Bus Idle */
+#define XCANPS_SR_NORMAL_MASK	0x00000008U /**< Normal Mode */
+#define XCANPS_SR_SLEEP_MASK	0x00000004U /**< Sleep Mode */
+#define XCANPS_SR_LBACK_MASK	0x00000002U /**< Loop Back Mode */
+#define XCANPS_SR_CONFIG_MASK	0x00000001U /**< Configuration Mode */
 /* @} */
 
 /** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_IXR_TXFEMP_MASK   0x00004000 /**< Tx Fifo Empty Interrupt */
-#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000 /**< Tx Fifo Watermark Empty */
-#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000 /**< Rx FIFO Watermark Full */
-#define XCANPS_IXR_WKUP_MASK	0x00000800 /**< Wake up Interrupt */
-#define XCANPS_IXR_SLP_MASK	0x00000400 /**< Sleep Interrupt */
-#define XCANPS_IXR_BSOFF_MASK	0x00000200 /**< Bus Off Interrupt */
-#define XCANPS_IXR_ERROR_MASK	0x00000100 /**< Error Interrupt */
-#define XCANPS_IXR_RXNEMP_MASK	0x00000080 /**< RX FIFO Not Empty Interrupt */
-#define XCANPS_IXR_RXOFLW_MASK	0x00000040 /**< RX FIFO Overflow Interrupt */
-#define XCANPS_IXR_RXUFLW_MASK	0x00000020 /**< RX FIFO Underflow Interrupt */
-#define XCANPS_IXR_RXOK_MASK	0x00000010 /**< New Message Received Intr */
-#define XCANPS_IXR_TXBFLL_MASK	0x00000008 /**< TX High Priority Buf Full */
-#define XCANPS_IXR_TXFLL_MASK	0x00000004 /**< TX FIFO Full Interrupt */
-#define XCANPS_IXR_TXOK_MASK	0x00000002 /**< TX Successful Interrupt */
-#define XCANPS_IXR_ARBLST_MASK	0x00000001 /**< Arbitration Lost Interrupt */
-#define XCANPS_IXR_ALL		(XCANPS_IXR_RXFWMFLL_MASK | \
-				XCANPS_IXR_WKUP_MASK   | \
-				XCANPS_IXR_SLP_MASK	| \
-				XCANPS_IXR_BSOFF_MASK  | \
-				XCANPS_IXR_ERROR_MASK  | \
-				XCANPS_IXR_RXNEMP_MASK | \
-				XCANPS_IXR_RXOFLW_MASK | \
-				XCANPS_IXR_RXUFLW_MASK | \
-				XCANPS_IXR_RXOK_MASK   | \
-				XCANPS_IXR_TXBFLL_MASK | \
-				XCANPS_IXR_TXFLL_MASK  | \
-				XCANPS_IXR_TXOK_MASK   | \
-				XCANPS_IXR_ARBLST_MASK)
+#define XCANPS_IXR_TXFEMP_MASK   0x00004000U /**< Tx Fifo Empty Interrupt */
+#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
+#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
+#define XCANPS_IXR_WKUP_MASK	 0x00000800U /**< Wake up Interrupt */
+#define XCANPS_IXR_SLP_MASK		0x00000400U /**< Sleep Interrupt */
+#define XCANPS_IXR_BSOFF_MASK	0x00000200U /**< Bus Off Interrupt */
+#define XCANPS_IXR_ERROR_MASK	0x00000100U /**< Error Interrupt */
+#define XCANPS_IXR_RXNEMP_MASK	0x00000080U /**< RX FIFO Not Empty Interrupt */
+#define XCANPS_IXR_RXOFLW_MASK	0x00000040U /**< RX FIFO Overflow Interrupt */
+#define XCANPS_IXR_RXUFLW_MASK	0x00000020U /**< RX FIFO Underflow Interrupt */
+#define XCANPS_IXR_RXOK_MASK	0x00000010U /**< New Message Received Intr */
+#define XCANPS_IXR_TXBFLL_MASK	0x00000008U /**< TX High Priority Buf Full */
+#define XCANPS_IXR_TXFLL_MASK	0x00000004U /**< TX FIFO Full Interrupt */
+#define XCANPS_IXR_TXOK_MASK	0x00000002U /**< TX Successful Interrupt */
+#define XCANPS_IXR_ARBLST_MASK	0x00000001U /**< Arbitration Lost Interrupt */
+#define XCANPS_IXR_ALL		((u32)XCANPS_IXR_RXFWMFLL_MASK | \
+				(u32)XCANPS_IXR_WKUP_MASK   | \
+				(u32)XCANPS_IXR_SLP_MASK	| \
+				(u32)XCANPS_IXR_BSOFF_MASK  | \
+				(u32)XCANPS_IXR_ERROR_MASK  | \
+				(u32)XCANPS_IXR_RXNEMP_MASK | \
+				(u32)XCANPS_IXR_RXOFLW_MASK | \
+				(u32)XCANPS_IXR_RXUFLW_MASK | \
+				(u32)XCANPS_IXR_RXOK_MASK   | \
+				(u32)XCANPS_IXR_TXBFLL_MASK | \
+				(u32)XCANPS_IXR_TXFLL_MASK  | \
+				(u32)XCANPS_IXR_TXOK_MASK   | \
+				(u32)XCANPS_IXR_ARBLST_MASK)
 /* @} */
 
 /** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_TCR_CTS_MASK	0x00000001 /**< Clear Timestamp counter mask */
+#define XCANPS_TCR_CTS_MASK	0x00000001U /**< Clear Timestamp counter mask */
 /* @} */
 
 /** @name CAN Watermark Register (WIR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_WIR_FW_MASK   	0x0000003F /**< Rx Full Threshold mask */
-#define XCANPS_WIR_EW_MASK 	0x00003F00 /**< Tx Empty Threshold mask */
-#define XCANPS_WIR_EW_SHIFT 	0x00000008 /**< Tx Empty Threshold shift */
+#define XCANPS_WIR_FW_MASK   	0x0000003FU /**< Rx Full Threshold mask */
+#define XCANPS_WIR_EW_MASK 	0x00003F00U /**< Tx Empty Threshold mask */
+#define XCANPS_WIR_EW_SHIFT 	0x00000008U /**< Tx Empty Threshold shift */
 
 /* @} */
 
@@ -238,67 +238,67 @@ extern "C" {
 				Mask/Acceptance Filter ID)
  *  @{
  */
-#define XCANPS_IDR_ID1_MASK	0xFFE00000 /**< Standard Messg Identifier */
-#define XCANPS_IDR_ID1_SHIFT	21
-#define XCANPS_IDR_SRR_MASK	0x00100000 /**< Substitute Remote TX Req */
-#define XCANPS_IDR_SRR_SHIFT	20
-#define XCANPS_IDR_IDE_MASK	0x00080000 /**< Identifier Extension */
-#define XCANPS_IDR_IDE_SHIFT	19
-#define XCANPS_IDR_ID2_MASK	0x0007FFFE /**< Extended Message Ident */
-#define XCANPS_IDR_ID2_SHIFT	1
-#define XCANPS_IDR_RTR_MASK	0x00000001 /**< Remote TX Request */
+#define XCANPS_IDR_ID1_MASK	0xFFE00000U /**< Standard Messg Identifier */
+#define XCANPS_IDR_ID1_SHIFT	21U
+#define XCANPS_IDR_SRR_MASK	0x00100000U /**< Substitute Remote TX Req */
+#define XCANPS_IDR_SRR_SHIFT	20U
+#define XCANPS_IDR_IDE_MASK	0x00080000U /**< Identifier Extension */
+#define XCANPS_IDR_IDE_SHIFT	19U
+#define XCANPS_IDR_ID2_MASK	0x0007FFFEU /**< Extended Message Ident */
+#define XCANPS_IDR_ID2_SHIFT	1U
+#define XCANPS_IDR_RTR_MASK	0x00000001U /**< Remote TX Request */
 /* @} */
 
 /** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
  *  @{
  */
-#define XCANPS_DLCR_DLC_MASK	 0xF0000000	/**< Data Length Code */
-#define XCANPS_DLCR_DLC_SHIFT	 28
-#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFF	/**< Timestamp Mask (Rx only) */
+#define XCANPS_DLCR_DLC_MASK	 0xF0000000U	/**< Data Length Code */
+#define XCANPS_DLCR_DLC_SHIFT	 28U
+#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU	/**< Timestamp Mask (Rx only) */
 
 /* @} */
 
 /** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
  *  @{
  */
-#define XCANPS_DW1R_DB0_MASK	0xFF000000 /**< Data Byte 0 */
-#define XCANPS_DW1R_DB0_SHIFT	24
-#define XCANPS_DW1R_DB1_MASK	0x00FF0000 /**< Data Byte 1 */
-#define XCANPS_DW1R_DB1_SHIFT	16
-#define XCANPS_DW1R_DB2_MASK	0x0000FF00 /**< Data Byte 2 */
-#define XCANPS_DW1R_DB2_SHIFT	8
-#define XCANPS_DW1R_DB3_MASK	0x000000FF /**< Data Byte 3 */
+#define XCANPS_DW1R_DB0_MASK	0xFF000000U /**< Data Byte 0 */
+#define XCANPS_DW1R_DB0_SHIFT	24U
+#define XCANPS_DW1R_DB1_MASK	0x00FF0000U /**< Data Byte 1 */
+#define XCANPS_DW1R_DB1_SHIFT	16U
+#define XCANPS_DW1R_DB2_MASK	0x0000FF00U /**< Data Byte 2 */
+#define XCANPS_DW1R_DB2_SHIFT	8U
+#define XCANPS_DW1R_DB3_MASK	0x000000FFU /**< Data Byte 3 */
 /* @} */
 
 /** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
  *  @{
  */
-#define XCANPS_DW2R_DB4_MASK	0xFF000000 /**< Data Byte 4 */
-#define XCANPS_DW2R_DB4_SHIFT	24
-#define XCANPS_DW2R_DB5_MASK	0x00FF0000 /**< Data Byte 5 */
-#define XCANPS_DW2R_DB5_SHIFT	16
-#define XCANPS_DW2R_DB6_MASK	0x0000FF00 /**< Data Byte 6 */
-#define XCANPS_DW2R_DB6_SHIFT	8
-#define XCANPS_DW2R_DB7_MASK	0x000000FF /**< Data Byte 7 */
+#define XCANPS_DW2R_DB4_MASK	0xFF000000U /**< Data Byte 4 */
+#define XCANPS_DW2R_DB4_SHIFT	24U
+#define XCANPS_DW2R_DB5_MASK	0x00FF0000U /**< Data Byte 5 */
+#define XCANPS_DW2R_DB5_SHIFT	16U
+#define XCANPS_DW2R_DB6_MASK	0x0000FF00U /**< Data Byte 6 */
+#define XCANPS_DW2R_DB6_SHIFT	8U
+#define XCANPS_DW2R_DB7_MASK	0x000000FFU /**< Data Byte 7 */
 /* @} */
 
 /** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
  *  @{
  */
-#define XCANPS_AFR_UAF4_MASK	0x00000008 /**< Use Acceptance Filter No.4 */
-#define XCANPS_AFR_UAF3_MASK	0x00000004 /**< Use Acceptance Filter No.3 */
-#define XCANPS_AFR_UAF2_MASK	0x00000002 /**< Use Acceptance Filter No.2 */
-#define XCANPS_AFR_UAF1_MASK	0x00000001 /**< Use Acceptance Filter No.1 */
-#define XCANPS_AFR_UAF_ALL_MASK	(XCANPS_AFR_UAF4_MASK | \
-					XCANPS_AFR_UAF3_MASK | \
-					XCANPS_AFR_UAF2_MASK | \
-					XCANPS_AFR_UAF1_MASK)
+#define XCANPS_AFR_UAF4_MASK	0x00000008U /**< Use Acceptance Filter No.4 */
+#define XCANPS_AFR_UAF3_MASK	0x00000004U /**< Use Acceptance Filter No.3 */
+#define XCANPS_AFR_UAF2_MASK	0x00000002U /**< Use Acceptance Filter No.2 */
+#define XCANPS_AFR_UAF1_MASK	0x00000001U /**< Use Acceptance Filter No.1 */
+#define XCANPS_AFR_UAF_ALL_MASK	((u32)XCANPS_AFR_UAF4_MASK | \
+					(u32)XCANPS_AFR_UAF3_MASK | \
+					(u32)XCANPS_AFR_UAF2_MASK | \
+					(u32)XCANPS_AFR_UAF1_MASK)
 /* @} */
 
 /** @name CAN frame length constants
  *  @{
  */
-#define XCANPS_MAX_FRAME_SIZE 16 /**< Maximum CAN frame length in bytes */
+#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
 /* @} */
 
 /* For backwards compatibilty */
@@ -332,7 +332,7 @@ extern "C" {
 *
 *****************************************************************************/
 #define XCanPs_ReadReg(BaseAddr, RegOffset) \
-		Xil_In32((BaseAddr) + (RegOffset))
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
 
 
 /****************************************************************************/
@@ -350,7 +350,7 @@ extern "C" {
 *
 *****************************************************************************/
 #define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
-		Xil_Out32((BaseAddr) + (RegOffset), (Data))
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
 
 /************************** Function Prototypes ******************************/
 /*
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_intr.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps_intr.c
index 7f1933fc..30497307 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_intr.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_intr.c
@@ -231,7 +231,7 @@ void XCanPs_IntrHandler(void *InstancePtr)
 	u32 PendingIntr;
 	u32 EventIntr;
 	u32 ErrorStatus;
-	XCanPs *CanPtr = (XCanPs *) InstancePtr;
+	XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr);
 
 	Xil_AssertVoid(CanPtr != NULL);
 	Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -248,14 +248,15 @@ void XCanPs_IntrHandler(void *InstancePtr)
 	/*
 	 * An error interrupt is occurring.
 	 */
-	if ((PendingIntr & XCANPS_IXR_ERROR_MASK)) {
-		ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
-		CanPtr->ErrorHandler(CanPtr->ErrorRef, ErrorStatus);
-
+	if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
+		(CanPtr->ErrorHandler != NULL)) {
+			CanPtr->ErrorHandler(CanPtr->ErrorRef,
+					XCanPs_GetBusErrorStatus(CanPtr));
 		/*
 		 * Clear Error Status Register.
 		 */
-		XCanPs_ClearBusErrorStatus(CanPtr, ErrorStatus);
+		XCanPs_ClearBusErrorStatus(CanPtr,
+					XCanPs_GetBusErrorStatus(CanPtr));
 	}
 
 	/*
@@ -271,18 +272,18 @@ void XCanPs_IntrHandler(void *InstancePtr)
 	 *
 	 * If so, call event callback provided by upper level.
 	 */
-	EventIntr = PendingIntr & (XCANPS_IXR_RXOFLW_MASK |
-				XCANPS_IXR_RXUFLW_MASK |
-				XCANPS_IXR_TXBFLL_MASK |
-				XCANPS_IXR_TXFLL_MASK |
-				XCANPS_IXR_WKUP_MASK |
-				XCANPS_IXR_SLP_MASK |
-				XCANPS_IXR_BSOFF_MASK |
-				XCANPS_IXR_ARBLST_MASK);
-	if (EventIntr) {
+	EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
+				(u32)XCANPS_IXR_RXUFLW_MASK |
+				(u32)XCANPS_IXR_TXBFLL_MASK |
+				(u32)XCANPS_IXR_TXFLL_MASK |
+				(u32)XCANPS_IXR_WKUP_MASK |
+				(u32)XCANPS_IXR_SLP_MASK |
+				(u32)XCANPS_IXR_BSOFF_MASK |
+				(u32)XCANPS_IXR_ARBLST_MASK);
+	if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
 		CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
 
-		if ((EventIntr & XCANPS_IXR_BSOFF_MASK)) {
+		if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
 			/*
 			 * Event callback should reset whole device if "Enter
 			 * Bus Off Status" interrupt occurred. All pending
@@ -290,12 +291,16 @@ void XCanPs_IntrHandler(void *InstancePtr)
 			 * handling of other interrupts is needed any more.
 			 */
 			return;
+		} else {
+			/*This else was made for misra-c compliance*/
+			;
 		}
 	}
 
 
-	if ((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
-			XCANPS_IXR_RXNEMP_MASK))) {
+	if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
+			XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
+		(CanPtr->RecvHandler != NULL)) {
 
 		/*
 		 * This case happens when
@@ -317,7 +322,8 @@ void XCanPs_IntrHandler(void *InstancePtr)
 	/*
 	 * A frame was transmitted successfully.
 	 */
-	if ((PendingIntr & XCANPS_IXR_TXOK_MASK)) {
+	if (((PendingIntr & XCANPS_IXR_TXOK_MASK) != (u32)0) &&
+		(CanPtr->SendHandler != NULL)) {
 		CanPtr->SendHandler(CanPtr->SendRef);
 	}
 }
@@ -365,38 +371,46 @@ void XCanPs_IntrHandler(void *InstancePtr)
 * it with the new handler.
 *
 ******************************************************************************/
-int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
 			void *CallBackFunc, void *CallBackRef)
 {
+	s32 Status;
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	switch (HandlerType) {
-	case XCANPS_HANDLER_SEND:
-		InstancePtr->SendHandler =
-			(XCanPs_SendRecvHandler) CallBackFunc;
-		InstancePtr->SendRef = CallBackRef;
-		break;
+		case XCANPS_HANDLER_SEND:
+			InstancePtr->SendHandler =
+				(XCanPs_SendRecvHandler) CallBackFunc;
+			InstancePtr->SendRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
 
-	case XCANPS_HANDLER_RECV:
-		InstancePtr->RecvHandler =
-			(XCanPs_SendRecvHandler) CallBackFunc;
-		InstancePtr->RecvRef = CallBackRef;
-		break;
+		case XCANPS_HANDLER_RECV:
+			InstancePtr->RecvHandler =
+				(XCanPs_SendRecvHandler) CallBackFunc;
+			InstancePtr->RecvRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
 
-	case XCANPS_HANDLER_ERROR:
-		InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) CallBackFunc;
-		InstancePtr->ErrorRef = CallBackRef;
-		break;
+		case XCANPS_HANDLER_ERROR:
+			InstancePtr->ErrorHandler =
+				(XCanPs_ErrorHandler) CallBackFunc;
+			InstancePtr->ErrorRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
 
-	case XCANPS_HANDLER_EVENT:
-		InstancePtr->EventHandler = (XCanPs_EventHandler) CallBackFunc;
-		InstancePtr->EventRef = CallBackRef;
-		break;
-
-	default:
-		return (XST_INVALID_PARAM);
+		case XCANPS_HANDLER_EVENT:
+			InstancePtr->EventHandler =
+				(XCanPs_EventHandler) CallBackFunc;
+			InstancePtr->EventRef = CallBackRef;
+			Status = XST_SUCCESS;
+			break;
 
+		default:
+			Status = XST_INVALID_PARAM;
+			break;
 	}
-	return (XST_SUCCESS);
+	return Status;
 }
+
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_selftest.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps_selftest.c
index f768258c..47449adf 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_selftest.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_selftest.c
@@ -63,9 +63,9 @@
 
 /************************** Constant Definitions ****************************/
 
-#define XCANPS_MAX_FRAME_SIZE_IN_WORDS (XCANPS_MAX_FRAME_SIZE / sizeof(u32))
+#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32)))
 
-#define FRAME_DATA_LENGTH	8 /* Frame Data field length */
+#define FRAME_DATA_LENGTH	8U /* Frame Data field length */
 
 /**************************** Type Definitions ******************************/
 
@@ -111,11 +111,13 @@ static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
 * have a chance to check reason(s) causing the failure.
 *
 ******************************************************************************/
-int XCanPs_SelfTest(XCanPs *InstancePtr)
+s32 XCanPs_SelfTest(XCanPs *InstancePtr)
 {
 	u8 *FramePtr;
-	u32 Status;
+	s32 Status;
 	u32 Index;
+	u8 GetModeResult;
+	u32 RxEmptyResult;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -128,7 +130,8 @@ int XCanPs_SelfTest(XCanPs *InstancePtr)
 	 * it is not Configuration Mode.
 	 */
 	if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
-		return XST_FAILURE;
+		Status = XST_FAILURE;
+		return Status;
 	}
 
 	/*
@@ -137,64 +140,81 @@ int XCanPs_SelfTest(XCanPs *InstancePtr)
 	 * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B,
 	 * ISO 11898-1 specifications.
 	 */
-	XCanPs_SetBaudRatePrescaler(InstancePtr, 29);
-	XCanPs_SetBitTiming(InstancePtr, 3, 2, 15);
+	(void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U);
+	(void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U);
 
 	/*
 	 * Enter the loop back mode.
 	 */
 	XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK);
-	while (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_LOOPBACK);
+	GetModeResult = XCanPs_GetMode(InstancePtr);
+	while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) {
+		GetModeResult = XCanPs_GetMode(InstancePtr);
+	}
 
 	/*
 	 * Create a frame to send with known values so we can verify them
 	 * on receive.
 	 */
-	TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000, 0, 0, 0, 0);
-	TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8);
+	TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U);
+	TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U);
 
-	FramePtr = (u8 *) (&TxFrame[2]);
-	for (Index = 0; Index < 8; Index++) {
-		*FramePtr++ = (u8) Index;
+	FramePtr = (u8 *)((void *)(&TxFrame[2]));
+	for (Index = 0U; Index < 8U; Index++) {
+		if(*FramePtr != 0U) {
+			*FramePtr = (u8)Index;
+			*FramePtr++;
+		}
 	}
 
 	/*
 	 * Send the frame.
 	 */
 	Status = XCanPs_Send(InstancePtr, TxFrame);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
+	if (Status != (s32)XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
 	}
 
 	/*
 	 * Wait until the frame arrives RX FIFO via internal loop back.
 	 */
-	while (XCanPs_IsRxEmpty(InstancePtr) == TRUE);
+	RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+			XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+
+	while (RxEmptyResult == (u32)0U) {
+		RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+				XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+	}
 
 	/*
 	 * Receive the frame.
 	 */
 	Status = XCanPs_Recv(InstancePtr, RxFrame);
-	if (Status != XST_SUCCESS) {
-		return XST_FAILURE;
+	if (Status != (s32)XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
 	}
 
 	/*
 	 * Verify Identifier and Data Length Code.
 	 */
 	if (RxFrame[0] !=
-		(u32)XCanPs_CreateIdValue((u32)2000, 0, 0, 0, 0)) {
-		return XST_FAILURE;
+		(u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) {
+		Status = XST_FAILURE;
+		return Status;
 	}
 
 	if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) {
-		return XST_FAILURE;
+		Status = XST_FAILURE;
+		return Status;
 	}
 
 
-	for (Index = 2; Index < XCANPS_MAX_FRAME_SIZE_IN_WORDS; Index++) {
+	for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) {
 		if (RxFrame[Index] != TxFrame[Index]) {
-			return XST_FAILURE;
+			Status = XST_FAILURE;
+			return Status;
 		}
 	}
 
@@ -203,5 +223,8 @@ int XCanPs_SelfTest(XCanPs *InstancePtr)
 	 */
 	XCanPs_Reset(InstancePtr);
 
-	return XST_SUCCESS;
+	Status = XST_SUCCESS;
+	return Status;
 }
+
+
diff --git a/XilinxProcessorIPLib/drivers/canps/src/xcanps_sinit.c b/XilinxProcessorIPLib/drivers/canps/src/xcanps_sinit.c
index dd1e7604..b97dbc37 100755
--- a/XilinxProcessorIPLib/drivers/canps/src/xcanps_sinit.c
+++ b/XilinxProcessorIPLib/drivers/canps/src/xcanps_sinit.c
@@ -54,8 +54,8 @@
 
 /***************************** Include Files *********************************/
 
-#include "xparameters.h"
 #include "xcanps.h"
+#include "xparameters.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -66,7 +66,8 @@
 /************************** Function Prototypes ******************************/
 
 /************************** Variable Definitions *****************************/
-extern XCanPs_Config XCanPs_ConfigTable[];
+
+extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES];
 
 /*****************************************************************************/
 /**
@@ -88,12 +89,12 @@ XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId)
 	XCanPs_Config *CfgPtr = NULL;
 	u32 Index;
 
-	for (Index = 0; Index < XPAR_XCANPS_NUM_INSTANCES; Index++) {
+	for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) {
 		if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) {
 			CfgPtr = &XCanPs_ConfigTable[Index];
 			break;
 		}
 	}
 
-	return CfgPtr;
+	return (XCanPs_Config *)CfgPtr;
 }