diff --git a/XilinxProcessorIPLib/drivers/spips/data/spips.mdd b/XilinxProcessorIPLib/drivers/spips/data/spips.mdd
old mode 100755
new mode 100644
index 7492ee9a..f1931cff
--- a/XilinxProcessorIPLib/drivers/spips/data/spips.mdd
+++ b/XilinxProcessorIPLib/drivers/spips/data/spips.mdd
@@ -28,12 +28,21 @@
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
#
+
+<pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 3.0 vm 12/09/14 support for Zynq Ultrascale Mp added
+*
+
###############################################################################
OPTION psf_version = 2.1;
BEGIN driver spips
- OPTION supported_peripherals = (ps7_spi);
+ OPTION supported_peripherals = (ps7_spi ps8_spi pss_spi);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION NAME = spips;
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips.c b/XilinxProcessorIPLib/drivers/spips/src/xspips.c
old mode 100755
new mode 100644
index 255450e3..8e7f35f3
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips.c
@@ -95,7 +95,7 @@
*
*****************************************************************************/
#define XSpiPs_SendByte(BaseAddress, Data) \
- XSpiPs_Out32((BaseAddress) + XSPIPS_TXD_OFFSET, (Data))
+ XSpiPs_Out32((BaseAddress) + (u32)XSPIPS_TXD_OFFSET, (u32)(Data))
/****************************************************************************/
/*
@@ -112,12 +112,12 @@
*
*****************************************************************************/
#define XSpiPs_RecvByte(BaseAddress) \
- (u8)XSpiPs_In32((BaseAddress) + XSPIPS_RXD_OFFSET)
+ XSpiPs_In32((u32)((BaseAddress) + (u32)XSPIPS_RXD_OFFSET))
/************************** Function Prototypes ******************************/
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
+ u32 ByteCount);
/************************** Variable Definitions *****************************/
@@ -156,9 +156,10 @@ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
* @note None.
*
******************************************************************************/
-int XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config *ConfigPtr,
+s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config *ConfigPtr,
u32 EffectiveAddr)
{
+ s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
@@ -169,31 +170,33 @@ int XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config *ConfigPtr,
* initializing. This assumes the busy flag is cleared at startup.
*/
if (InstancePtr->IsBusy == TRUE) {
- return XST_DEVICE_IS_STARTED;
+ Status = (s32)XST_DEVICE_IS_STARTED;
+ } else {
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->StatusHandler = StubStatusHandler;
+
+ InstancePtr->SendBufferPtr = NULL;
+ InstancePtr->RecvBufferPtr = NULL;
+ InstancePtr->RequestedBytes = 0U;
+ InstancePtr->RemainingBytes = 0U;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Reset the SPI device to get it into its initial state. It is
+ * expected that device configuration will take place after this
+ * initialization is done, but before the device is started.
+ */
+ XSpiPs_Reset(InstancePtr);
+ Status = (s32)XST_SUCCESS;
}
- /*
- * Set some default values.
- */
- InstancePtr->IsBusy = FALSE;
-
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->StatusHandler = StubStatusHandler;
-
- InstancePtr->SendBufferPtr = NULL;
- InstancePtr->RecvBufferPtr = NULL;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->RemainingBytes = 0;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- /*
- * Reset the SPI device to get it into its initial state. It is
- * expected that device configuration will take place after this
- * initialization is done, but before the device is started.
- */
- XSpiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
+ return Status;
}
@@ -302,102 +305,104 @@ void XSpiPs_Reset(XSpiPs *InstancePtr)
* no two threads are transferring data on the SPI bus at the same time.
*
******************************************************************************/
-int XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, unsigned ByteCount)
+s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount)
{
u32 ConfigReg;
- u8 TransCount = 0;
+ u8 TransCount = 0U;
+ s32 StatusTransfer;
/*
* The RecvBufPtr argument can be null
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(ByteCount > 0U);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
/*
* Check whether there is another transfer in progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
+ if (InstancePtr->IsBusy == TRUE) {
+ StatusTransfer = (s32)XST_DEVICE_BUSY;
+ } else {
- /*
- * Set the busy flag, which will be cleared in the ISR when the
- * transfer is entirely done.
- */
- InstancePtr->IsBusy = TRUE;
+ /*
+ * Set the busy flag, which will be cleared in the ISR when the
+ * transfer is entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
/*
* If manual chip select mode, initialize the slave select value.
*/
- if (XSpiPs_IsManualChipSelect(InstancePtr)) {
+ if (XSpiPs_IsManualChipSelect(InstancePtr) != FALSE) {
ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
/*
* Set the slave select value.
*/
- ConfigReg &= ~XSPIPS_CR_SSCTRL_MASK;
+ ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
ConfigReg |= InstancePtr->SlaveSelect;
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
XSPIPS_CR_OFFSET, ConfigReg);
}
- /*
- * Enable the device.
- */
- XSpiPs_Enable(InstancePtr);
+ /*
+ * Enable the device.
+ */
+ XSpiPs_Enable(InstancePtr);
- /*
- * Clear all the interrrupts.
- */
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_SR_OFFSET,
- XSPIPS_IXR_WR_TO_CLR_MASK);
+ /*
+ * Clear all the interrrupts.
+ */
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_SR_OFFSET,
+ XSPIPS_IXR_WR_TO_CLR_MASK);
- /*
- * Fill the TXFIFO with as many bytes as it will take (or as many as
- * we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XSPIPS_FIFO_DEPTH)) {
- XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
- *InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr++;
- InstancePtr->RemainingBytes--;
- TransCount++;
- }
+ /*
+ * Fill the TXFIFO with as many bytes as it will take (or as many as
+ * we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0U) &&
+ (TransCount < XSPIPS_FIFO_DEPTH)) {
+ XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
+ *InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += 1;
+ InstancePtr->RemainingBytes--;
+ TransCount++;
+ }
- /*
- * Enable interrupts (connecting to the interrupt controller and
- * enabling interrupts should have been done by the caller).
- */
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_IER_OFFSET, XSPIPS_IXR_DFLT_MASK);
-
- /*
- * If master mode and manual start mode, issue manual start command
- * to start the transfer.
- */
- if (XSpiPs_IsManualStart(InstancePtr)
- && XSpiPs_IsMaster(InstancePtr)) {
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
- ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+ /*
+ * Enable interrupts (connecting to the interrupt controller and
+ * enabling interrupts should have been done by the caller).
+ */
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET, ConfigReg);
- }
+ XSPIPS_IER_OFFSET, XSPIPS_IXR_DFLT_MASK);
- return XST_SUCCESS;
+ /*
+ * If master mode and manual start mode, issue manual start command
+ * to start the transfer.
+ */
+ if ((XSpiPs_IsManualStart(InstancePtr) == TRUE)
+ && (XSpiPs_IsMaster(InstancePtr) == TRUE)) {
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+ ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET, ConfigReg);
+ }
+ StatusTransfer = (s32)XST_SUCCESS;
+ }
+ return StatusTransfer;
}
/*****************************************************************************/
@@ -454,157 +459,163 @@ int XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
* no two threads are transferring data on the SPI bus at the same time.
*
******************************************************************************/
-int XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, unsigned ByteCount)
+s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount)
{
u32 StatusReg;
u32 ConfigReg;
u32 TransCount;
+ u32 CheckTransfer;
+ s32 Status_Polled;
+ u8 TempData;
/*
* The RecvBufPtr argument can be NULL.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(ByteCount > 0U);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Check whether there is another transfer in progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared when the transfer is
- * entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * If manual chip select mode, initialize the slave select value.
- */
- if (XSpiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
- /*
- * Set the slave select value.
- */
- ConfigReg &= ~XSPIPS_CR_SSCTRL_MASK;
- ConfigReg |= InstancePtr->SlaveSelect;
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XSpiPs_Enable(InstancePtr);
-
- while((InstancePtr->RemainingBytes > 0) ||
- (InstancePtr->RequestedBytes > 0)) {
- TransCount = 0;
- /*
- * Fill the TXFIFO with as many bytes as it will take (or as
- * many as we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XSPIPS_FIFO_DEPTH)) {
- XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
- *InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr++;
- InstancePtr->RemainingBytes--;
- ++TransCount;
- }
+ if (InstancePtr->IsBusy == TRUE) {
+ Status_Polled = (s32)XST_DEVICE_BUSY;
+ } else {
/*
- * If master mode and manual start mode, issue manual start
- * command to start the transfer.
+ * Set the busy flag, which will be cleared when the transfer is
+ * entirely done.
*/
- if (XSpiPs_IsManualStart(InstancePtr)
- && XSpiPs_IsMaster(InstancePtr)) {
- ConfigReg = XSpiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
- ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * If manual chip select mode, initialize the slave select value.
+ */
+ if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+ /*
+ * Set the slave select value.
+ */
+ ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
+ ConfigReg |= InstancePtr->SlaveSelect;
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
XSPIPS_CR_OFFSET, ConfigReg);
}
/*
- * Wait for the transfer to finish by polling Tx fifo status.
+ * Enable the device.
*/
- do {
- StatusReg = XSpiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XSPIPS_SR_OFFSET);
- if ( StatusReg & XSPIPS_IXR_MODF_MASK )
- {
- /*
- * Clear the mode fail bit
- */
- XSpiPs_WriteReg(
- InstancePtr->Config.BaseAddress,
- XSPIPS_SR_OFFSET,
- XSPIPS_IXR_MODF_MASK);
- return XST_SEND_ERROR;
+ XSpiPs_Enable(InstancePtr);
+
+ while((InstancePtr->RemainingBytes > (u32)0U) ||
+ (InstancePtr->RequestedBytes > (u32)0U)) {
+ TransCount = 0U;
+ /*
+ * Fill the TXFIFO with as many bytes as it will take (or as
+ * many as we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > (u32)0U) &&
+ ((u32)TransCount < (u32)XSPIPS_FIFO_DEPTH)) {
+ XSpiPs_SendByte(InstancePtr->Config.BaseAddress,
+ *InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += 1;
+ InstancePtr->RemainingBytes--;
+ ++TransCount;
}
- } while ((StatusReg & XSPIPS_IXR_TXOW_MASK) == 0);
+
+ /*
+ * If master mode and manual start mode, issue manual start
+ * command to start the transfer.
+ */
+ if ((XSpiPs_IsManualStart(InstancePtr) == TRUE)
+ && (XSpiPs_IsMaster(InstancePtr) == TRUE)) {
+ ConfigReg = XSpiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+ ConfigReg |= XSPIPS_CR_MANSTRT_MASK;
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ CheckTransfer = (u32)0U;
+ while (CheckTransfer == 0U){
+ StatusReg = XSpiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XSPIPS_SR_OFFSET);
+ if ( (StatusReg & XSPIPS_IXR_MODF_MASK) != 0U) {
+ /*
+ * Clear the mode fail bit
+ */
+ XSpiPs_WriteReg(
+ InstancePtr->Config.BaseAddress,
+ XSPIPS_SR_OFFSET,
+ XSPIPS_IXR_MODF_MASK);
+ return (s32)XST_SEND_ERROR;
+ }
+ CheckTransfer = (StatusReg &
+ XSPIPS_IXR_TXOW_MASK);
+ }
+
+ /*
+ * A transmit has just completed. Process received data and
+ * check for more data to transmit.
+ * First get the data received as a result of the transmit
+ * that just completed. Receive data based on the
+ * count obtained while filling tx fifo. Always get the
+ * received data, but only fill the receive buffer if it
+ * points to something (the upper layer software may not
+ * care to receive data).
+ */
+ while (TransCount != (u32)0U) {
+ TempData = (u8)XSpiPs_RecvByte(
+ InstancePtr->Config.BaseAddress);
+ if (InstancePtr->RecvBufferPtr != NULL) {
+ *(InstancePtr->RecvBufferPtr) = TempData;
+ InstancePtr->RecvBufferPtr += 1;
+ }
+ InstancePtr->RequestedBytes--;
+ --TransCount;
+ }
+ }
/*
- * A transmit has just completed. Process received data and
- * check for more data to transmit.
- * First get the data received as a result of the transmit
- * that just completed. Receive data based on the
- * count obtained while filling tx fifo. Always get the
- * received data, but only fill the receive buffer if it
- * points to something (the upper layer software may not
- * care to receive data).
+ * Clear the slave selects now, before terminating the transfer.
*/
- while (TransCount) {
- u8 TempData;
- TempData = XSpiPs_RecvByte(
- InstancePtr->Config.BaseAddress);
- if (InstancePtr->RecvBufferPtr != NULL) {
- *InstancePtr->RecvBufferPtr++ = (u8) TempData;
- }
- InstancePtr->RequestedBytes--;
- --TransCount;
+ if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+ ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET, ConfigReg);
}
+
+ /*
+ * Clear the busy flag.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XSpiPs_Disable(InstancePtr);
+ Status_Polled = (s32)XST_SUCCESS;
}
-
- /*
- * Clear the slave selects now, before terminating the transfer.
- */
- if (XSpiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
- ConfigReg |= XSPIPS_CR_SSCTRL_MASK;
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- InstancePtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XSpiPs_Disable(InstancePtr);
-
- return XST_SUCCESS;
+ return Status_Polled;
}
/*****************************************************************************/
@@ -641,10 +652,10 @@ int XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
* has no affect when the device is configured as a slave.
*
******************************************************************************/
-int XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel)
+s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel)
{
u32 ConfigReg;
-
+ s32 Status_Slave;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(SlaveSel <= XSPIPS_CR_SSCTRL_MAXIMUM);
@@ -653,38 +664,39 @@ int XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel)
* Do not allow the slave select to change while a transfer is in
* progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
- /*
- * If decode slave select option is set,
- * then set slave select value directly.
- * Update the Instance structure member.
- */
- if ( XSpiPs_IsDecodeSSelect( InstancePtr ) ) {
- InstancePtr->SlaveSelect = SlaveSel << XSPIPS_CR_SSCTRL_SHIFT;
- }
- else {
- /*
- * Set the bit position to low using SlaveSel. Update the Instance
- * structure member.
- */
- InstancePtr->SlaveSelect = ((~(1 << SlaveSel)) & \
- XSPIPS_CR_SSCTRL_MAXIMUM) << XSPIPS_CR_SSCTRL_SHIFT;
- }
+ if (InstancePtr->IsBusy == TRUE) {
+ Status_Slave = (s32)XST_DEVICE_BUSY;
+ } else {
+ /*
+ * If decode slave select option is set,
+ * then set slave select value directly.
+ * Update the Instance structure member.
+ */
+ if ( XSpiPs_IsDecodeSSelect( InstancePtr ) == TRUE) {
+ InstancePtr->SlaveSelect = ((u32)SlaveSel) << XSPIPS_CR_SSCTRL_SHIFT;
+ }
+ else {
+ /*
+ * Set the bit position to low using SlaveSel. Update the Instance
+ * structure member.
+ */
+ InstancePtr->SlaveSelect = ((~(1U << SlaveSel)) & \
+ XSPIPS_CR_SSCTRL_MAXIMUM) << XSPIPS_CR_SSCTRL_SHIFT;
+ }
- /*
- * Read the config register, update the slave select value and write
- * back to config register.
- */
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
- ConfigReg &= (~XSPIPS_CR_SSCTRL_MASK);
- ConfigReg |= InstancePtr->SlaveSelect;
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_CR_OFFSET,
- ConfigReg);
-
- return XST_SUCCESS;
+ /*
+ * Read the config register, update the slave select value and write
+ * back to config register.
+ */
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+ ConfigReg &= (u32)(~XSPIPS_CR_SSCTRL_MASK);
+ ConfigReg |= InstancePtr->SlaveSelect;
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_CR_OFFSET,
+ ConfigReg);
+ Status_Slave = (s32)XST_SUCCESS;
+ }
+ return Status_Slave;
}
/*****************************************************************************/
@@ -702,7 +714,7 @@ int XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel)
u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
{
u32 ConfigReg;
- u8 SlaveSel;
+ u32 SlaveSel;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -715,7 +727,7 @@ u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
/*
* If decode slave select option is set, then read value directly.
*/
- if ( XSpiPs_IsDecodeSSelect( InstancePtr ) ) {
+ if ( XSpiPs_IsDecodeSSelect( InstancePtr ) == TRUE) {
SlaveSel = ConfigReg;
}
else {
@@ -723,11 +735,11 @@ u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
/*
* Get the slave select value
*/
- if(ConfigReg == 0x0F) {
+ if(ConfigReg == 0x0FU) {
/*
* No slave selected
*/
- SlaveSel = 0xF;
+ SlaveSel = 0xFU;
}else {
/*
* Get selected slave number (0,1 or 2)
@@ -735,7 +747,7 @@ u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
SlaveSel = ((~ConfigReg) & XSPIPS_CR_SSCTRL_MAXIMUM)/2;
}
}
- return SlaveSel;
+ return (u8)SlaveSel;
}
/*****************************************************************************/
@@ -772,7 +784,7 @@ u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
* @param InstancePtr is a pointer to the XSpiPs instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
+* @param FunctionPtr is the pointer to the callback function.
*
* @return None.
*
@@ -783,13 +795,13 @@ u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr)
*
******************************************************************************/
void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
- XSpiPs_StatusHandler FuncPtr)
+ XSpiPs_StatusHandler FunctionPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(FunctionPtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- InstancePtr->StatusHandler = FuncPtr;
+ InstancePtr->StatusHandler = FunctionPtr;
InstancePtr->StatusRef = CallBackRef;
}
@@ -810,7 +822,7 @@ void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
*
******************************************************************************/
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount)
+ u32 ByteCount)
{
(void) CallBackRef;
(void) StatusEvent;
@@ -863,12 +875,12 @@ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
* master since the hardware does not drive the slave select as a slave.
*
******************************************************************************/
-void XSpiPs_InterruptHandler(void *InstancePtr)
+void XSpiPs_InterruptHandler(XSpiPs *InstancePtr)
{
- XSpiPs *SpiPtr = (XSpiPs *)InstancePtr;
+ XSpiPs *SpiPtr = InstancePtr;
u32 IntrStatus;
u32 ConfigReg;
- unsigned BytesDone; /* Number of bytes done so far. */
+ u32 BytesDone; /* Number of bytes done so far. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(SpiPtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -892,7 +904,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* before checking for progress of a transfer, since this error needs
* to abort any operation in progress.
*/
- if (XSPIPS_IXR_MODF_MASK == (IntrStatus & XSPIPS_IXR_MODF_MASK)) {
+ if ((u32)XSPIPS_IXR_MODF_MASK == (u32)(IntrStatus & XSPIPS_IXR_MODF_MASK)) {
BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
/*
@@ -912,7 +924,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
}
- if (IntrStatus & XSPIPS_IXR_TXOW_MASK) {
+ if ((IntrStatus & XSPIPS_IXR_TXOW_MASK) != 0U) {
u8 TempData;
u32 TransCount;
/*
@@ -927,10 +939,11 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
*/
TransCount = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
- while (TransCount) {
- TempData = XSpiPs_RecvByte(SpiPtr->Config.BaseAddress);
+ while (TransCount != 0U) {
+ TempData = (u8)XSpiPs_RecvByte(SpiPtr->Config.BaseAddress);
if (SpiPtr->RecvBufferPtr != NULL) {
- *SpiPtr->RecvBufferPtr++ = (u8) TempData;
+ *SpiPtr->RecvBufferPtr = TempData;
+ SpiPtr->RecvBufferPtr += 1;
}
SpiPtr->RequestedBytes--;
--TransCount;
@@ -940,17 +953,17 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* Fill the TXFIFO until data exists, otherwise fill upto
* FIFO depth.
*/
- while ((SpiPtr->RemainingBytes > 0) &&
+ while ((SpiPtr->RemainingBytes > 0U) &&
(TransCount < XSPIPS_FIFO_DEPTH)) {
XSpiPs_SendByte(SpiPtr->Config.BaseAddress,
*SpiPtr->SendBufferPtr);
- SpiPtr->SendBufferPtr++;
+ SpiPtr->SendBufferPtr += 1;
SpiPtr->RemainingBytes--;
++TransCount;
}
- if ((SpiPtr->RemainingBytes == 0) &&
- (SpiPtr->RequestedBytes == 0)) {
+ if ((SpiPtr->RemainingBytes == 0U) &&
+ (SpiPtr->RequestedBytes == 0U)) {
/*
* No more data to send. Disable the interrupt and
* inform the upper layer software that the transfer
@@ -964,7 +977,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* Disable slave select lines as the transfer
* is complete.
*/
- if (XSpiPs_IsManualChipSelect(InstancePtr)) {
+ if (XSpiPs_IsManualChipSelect(InstancePtr) == TRUE) {
ConfigReg = XSpiPs_ReadReg(
SpiPtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
@@ -1000,8 +1013,8 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* Start the transfer by not inhibiting the transmitter
* any longer.
*/
- if (XSpiPs_IsManualStart(SpiPtr)
- && XSpiPs_IsMaster(SpiPtr)) {
+ if ((XSpiPs_IsManualStart(SpiPtr) == TRUE)
+ && (XSpiPs_IsMaster(SpiPtr) == TRUE)) {
ConfigReg = XSpiPs_ReadReg(
SpiPtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
@@ -1016,7 +1029,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
/*
* Check for overflow and underflow errors.
*/
- if (IntrStatus & XSPIPS_IXR_RXOVR_MASK) {
+ if ((IntrStatus & XSPIPS_IXR_RXOVR_MASK) != 0U) {
BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
SpiPtr->IsBusy = FALSE;
@@ -1024,7 +1037,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* The Slave select lines are being manually controlled.
* Disable them because the transfer is complete.
*/
- if (XSpiPs_IsManualChipSelect(SpiPtr)) {
+ if (XSpiPs_IsManualChipSelect(SpiPtr) == TRUE) {
ConfigReg = XSpiPs_ReadReg(
SpiPtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
@@ -1038,7 +1051,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
XST_SPI_RECEIVE_OVERRUN, BytesDone);
}
- if (IntrStatus & XSPIPS_IXR_TXUF_MASK) {
+ if ((IntrStatus & XSPIPS_IXR_TXUF_MASK) != 0U) {
BytesDone = SpiPtr->RequestedBytes - SpiPtr->RemainingBytes;
SpiPtr->IsBusy = FALSE;
@@ -1046,7 +1059,7 @@ void XSpiPs_InterruptHandler(void *InstancePtr)
* The Slave select lines are being manually controlled.
* Disable them because the transfer is complete.
*/
- if (XSpiPs_IsManualChipSelect(SpiPtr)) {
+ if (XSpiPs_IsManualChipSelect(SpiPtr) == TRUE) {
ConfigReg = XSpiPs_ReadReg(
SpiPtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
@@ -1083,14 +1096,20 @@ void XSpiPs_Abort(XSpiPs *InstancePtr)
{
XSpiPs_Disable(InstancePtr);
+ u8 Temp;
+ u32 Check;
/*
* Clear the RX FIFO and drop any data.
*/
- while ((XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK) ==
- XSPIPS_IXR_RXNEMPTY_MASK) {
- (void) XSpiPs_RecvByte(InstancePtr->Config.BaseAddress);
+ Check = (XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK);
+ while (Check != (u32)0U) {
+ Temp = (u8)XSpiPs_RecvByte(InstancePtr->Config.BaseAddress);
+ if(Temp != (u8)0U){
+ }
+ Check = (XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK);
}
/*
@@ -1100,8 +1119,8 @@ void XSpiPs_Abort(XSpiPs *InstancePtr)
XSPIPS_SR_OFFSET,
XSPIPS_IXR_MODF_MASK);
- InstancePtr->RemainingBytes = 0;
- InstancePtr->RequestedBytes = 0;
+ InstancePtr->RemainingBytes = 0U;
+ InstancePtr->RequestedBytes = 0U;
InstancePtr->IsBusy = FALSE;
}
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips.h b/XilinxProcessorIPLib/drivers/spips/src/xspips.h
old mode 100755
new mode 100644
index a7d9fcc8..48b3ea98
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips.h
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips.h
@@ -238,6 +238,8 @@
* Added prototypes of reset API and related constant
* definitions.
* Added check for MODF in polled transfer function.
+* 3.0 vm 12/09/14 Modified driver source code for MISRA-C:2012 compliance.
+* Support for Zynq Ultrascale Mp added.
*
* </pre>
*
@@ -314,12 +316,12 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_MASTER_OPTION 0x1 /**< Master mode option */
-#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XSPIPS_DECODE_SSELECT_OPTION 0x8 /**< Select 16 slaves Option */
-#define XSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start mode option */
+#define XSPIPS_MASTER_OPTION 0x00000001U /**< Master mode option */
+#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x00000002U /**< Active Low Clock option */
+#define XSPIPS_CLK_PHASE_1_OPTION 0x00000004U /**< Clock Phase one option */
+#define XSPIPS_DECODE_SSELECT_OPTION 0x00000008U /**< Select 16 slaves Option */
+#define XSPIPS_FORCE_SSELECT_OPTION 0x00000010U /**< Force Slave Select */
+#define XSPIPS_MANUAL_START_OPTION 0x00000020U /**< Manual Start mode option */
/*@}*/
@@ -331,13 +333,13 @@ extern "C" {
* @{
*/
-#define XSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+#define XSPIPS_CLK_PRESCALE_4 0x01U /**< PCLK/4 Prescaler */
+#define XSPIPS_CLK_PRESCALE_8 0x02U /**< PCLK/8 Prescaler */
+#define XSPIPS_CLK_PRESCALE_16 0x03U /**< PCLK/16 Prescaler */
+#define XSPIPS_CLK_PRESCALE_32 0x04U /**< PCLK/32 Prescaler */
+#define XSPIPS_CLK_PRESCALE_64 0x05U /**< PCLK/64 Prescaler */
+#define XSPIPS_CLK_PRESCALE_128 0x06U /**< PCLK/128 Prescaler */
+#define XSPIPS_CLK_PRESCALE_256 0x07U /**< PCLK/256 Prescaler */
/*@}*/
@@ -349,10 +351,10 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_EVENT_MODE_FAULT 1 /**< Mode fault error */
-#define XSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+#define XSPIPS_EVENT_MODE_FAULT 1U /**< Mode fault error */
+#define XSPIPS_EVENT_TRANSFER_DONE 2U /**< Transfer done */
+#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3U /**< TX FIFO empty */
+#define XSPIPS_EVENT_RECEIVE_OVERRUN 4U /**< Receive data loss because
RX FIFO full */
/*@}*/
@@ -377,7 +379,7 @@ extern "C" {
* requested if the status event indicates an error.
*/
typedef void (*XSpiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
+ u32 ByteCount);
/**
* This typedef contains configuration information for the device.
@@ -399,8 +401,8 @@ typedef struct {
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- unsigned RequestedBytes; /**< Number of bytes to transfer (state) */
- unsigned RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 RequestedBytes; /**< Number of bytes to transfer (state) */
+ u32 RemainingBytes; /**< Number of bytes left to transfer(state) */
u32 IsBusy; /**< A transfer is in progress (state) */
u32 SlaveSelect; /**< The slave select value when
XSPIPS_FORCE_SSELECT_OPTION is set */
@@ -427,8 +429,8 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_IsManualStart(InstancePtr) \
- ((XSpiPs_GetOptions(InstancePtr) & \
- XSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+ (((XSpiPs_GetOptions(InstancePtr) & \
+ XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
@@ -446,8 +448,8 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_IsManualChipSelect(InstancePtr) \
- ((XSpiPs_GetOptions(InstancePtr) & \
- XSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+ (((XSpiPs_GetOptions(InstancePtr) & \
+ XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
@@ -465,8 +467,8 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_IsDecodeSSelect(InstancePtr) \
- ((XSpiPs_GetOptions(InstancePtr) & \
- XSPIPS_DECODE_SSELECT_OPTION) ? TRUE : FALSE)
+ (((XSpiPs_GetOptions(InstancePtr) & \
+ XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
@@ -484,8 +486,8 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_IsMaster(InstancePtr) \
- ((XSpiPs_GetOptions(InstancePtr) & \
- XSPIPS_MASTER_OPTION) ? TRUE : FALSE)
+ (((XSpiPs_GetOptions(InstancePtr) & \
+ XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/**
@@ -561,7 +563,7 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_GetTXWatermark(InstancePtr) \
- XSpiPs_In32((InstancePtr->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
+ XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
@@ -599,7 +601,7 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_GetRXWatermark(InstancePtr) \
- XSpiPs_In32((InstancePtr->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
+ XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
@@ -615,7 +617,7 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_Enable(InstancePtr) \
- XSpiPs_Out32((InstancePtr->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
+ XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
XSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
@@ -632,7 +634,7 @@ typedef struct {
*
*****************************************************************************/
#define XSpiPs_Disable(InstancePtr) \
- XSpiPs_Out32((InstancePtr->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0)
+ XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U)
/************************** Function Prototypes ******************************/
@@ -644,41 +646,41 @@ XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xspips.c
*/
-int XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config * Config,
+s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config * ConfigPtr,
u32 EffectiveAddr);
void XSpiPs_Reset(XSpiPs *InstancePtr);
-int XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- unsigned ByteCount);
+s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
-int XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, unsigned ByteCount);
+s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
- XSpiPs_StatusHandler FuncPtr);
-void XSpiPs_InterruptHandler(void *InstancePtr);
+ XSpiPs_StatusHandler FunctionPtr);
+void XSpiPs_InterruptHandler(XSpiPs *InstancePtr);
void XSpiPs_Abort(XSpiPs *InstancePtr);
-int XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SelectValue);
+s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel);
u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr);
/*
* Functions for selftest, in xspips_selftest.c
*/
-int XSpiPs_SelfTest(XSpiPs *InstancePtr);
+s32 XSpiPs_SelfTest(XSpiPs *InstancePtr);
/*
* Functions for options, in xspips_options.c
*/
-int XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options);
+s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options);
u32 XSpiPs_GetOptions(XSpiPs *InstancePtr);
-int XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler);
+s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler);
u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr);
-int XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
void XSpiPs_GetDelays(XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_g.c b/XilinxProcessorIPLib/drivers/spips/src/xspips_g.c
old mode 100755
new mode 100644
index 4a44e973..ca459c53
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_g.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_g.c
@@ -72,15 +72,15 @@
*/
XSpiPs_Config XSpiPs_ConfigTable[XPAR_XSPIPS_NUM_INSTANCES] = {
{
- XPAR_XSPIPS_0_DEVICE_ID, /* Device ID for instance */
- XPAR_XSPIPS_0_BASEADDR, /* Device base address */
- XPAR_XSPIPS_0_CLOCK_HZ
+ (u16)XPAR_XSPIPS_0_DEVICE_ID, /* Device ID for instance */
+ (u32)XPAR_XSPIPS_0_BASEADDR, /* Device base address */
+ (u32)XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ
},
#ifdef XPAR_XSPIPS_1_DEVICE_ID
{
- XPAR_XSPIPS_1_DEVICE_ID, /* Device ID for instance */
- XPAR_XSPIPS_1_BASEADDR, /* Device base address */
- XPAR_XSPIPS_1_CLOCK_HZ
+ (u16)XPAR_XSPIPS_1_DEVICE_ID, /* Device ID for instance */
+ (u32)XPAR_XSPIPS_1_BASEADDR, /* Device base address */
+ (u32)XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ
}
#endif
};
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.c b/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.c
old mode 100755
new mode 100644
index 95bf9855..2b786eaa
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.c
@@ -69,7 +69,7 @@
*
* Resets the spi module
*
-* @param None
+* @param BaseAddress is the base address of the device.
*
* @return None
*
@@ -78,7 +78,7 @@
******************************************************************************/
void XSpiPs_ResetHw(u32 BaseAddress)
{
-
+ u32 Check;
/*
* Disable Interrupts
*/
@@ -89,7 +89,7 @@ void XSpiPs_ResetHw(u32 BaseAddress)
* Disable device
*/
XSpiPs_WriteReg(BaseAddress, XSPIPS_ER_OFFSET,
- 0);
+ 0U);
/*
* Write default value to RX and TX threshold registers
* RX threshold should be set to 1 here as the corresponding
@@ -103,9 +103,12 @@ void XSpiPs_ResetHw(u32 BaseAddress)
/*
* Clear RXFIFO
*/
- while ((XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
- XSPIPS_IXR_RXNEMPTY_MASK) != 0) {
- XSpiPs_ReadReg(BaseAddress, XSPIPS_RXD_OFFSET);
+ Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
+ XSPIPS_IXR_RXNEMPTY_MASK);
+ while (Check != 0U) {
+ (void)XSpiPs_ReadReg(BaseAddress, XSPIPS_RXD_OFFSET);
+ Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
+ XSPIPS_IXR_RXNEMPTY_MASK);
}
/*
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.h b/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.h
old mode 100755
new mode 100644
index d2dbbd27..f2ff75a9
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.h
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.h
@@ -78,18 +78,18 @@ extern "C" {
* Register offsets from the base address of an SPI device.
* @{
*/
-#define XSPIPS_CR_OFFSET 0x00 /**< Configuration */
-#define XSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XSPIPS_TXD_OFFSET 0x1C /**< Data Transmit Register */
-#define XSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */
+#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */
+#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */
+#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */
+#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */
+#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */
+#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */
+#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */
+#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */
+#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */
+#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */
+#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */
/* @} */
/** @name Configuration Register
@@ -98,26 +98,26 @@ extern "C" {
* affects the operation of an SPI device. Read/Write.
* @{
*/
-#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000 /**< Modefail Generation
+#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
Enable */
-#define XSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */
+#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
Enable */
-#define XSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XSPIPS_CR_SSCTRL_MASK 0x00003C00 /**< Slave Select Decode */
-#define XSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XSPIPS_CR_SSCTRL_MAXIMUM 0xF /**< Slave Select maximum value */
-#define XSPIPS_CR_SSDECEN_MASK 0x00000200 /**< Slave Select Decode Enable */
+#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */
+#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */
+#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */
+#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */
+#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */
-#define XSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */
+#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */
+#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */
-#define XSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */
+#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */
-#define XSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-#define XSPIPS_CR_RESET_STATE 0x00020000 /**< Mode Fail Generation Enable */
+#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */
+#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */
/* @} */
@@ -156,20 +156,20 @@ extern "C" {
* @{
*/
-#define XSPIPS_IXR_TXUF_MASK 0x00000040 /**< Tx FIFO Underflow */
-#define XSPIPS_IXR_RXFULL_MASK 0x00000020 /**< Rx FIFO Full */
-#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< Rx FIFO Not Empty */
-#define XSPIPS_IXR_TXFULL_MASK 0x00000008 /**< Tx FIFO Full */
-#define XSPIPS_IXR_TXOW_MASK 0x00000004 /**< Tx FIFO Overwater */
-#define XSPIPS_IXR_MODF_MASK 0x00000002 /**< Mode Fault */
-#define XSPIPS_IXR_RXOVR_MASK 0x00000001 /**< Rx FIFO Overrun */
-#define XSPIPS_IXR_DFLT_MASK 0x00000027 /**< Default interrupts
+#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */
+#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */
+#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */
+#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */
+#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */
+#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */
+#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */
+#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts
mask */
-#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043 /**< Interrupts which
+#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which
need write to clear */
-#define XSPIPS_ISR_RESET_STATE 0x04 /**< Default to tx/rx
+#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx
* reg empty */
-#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043 /**< Disable all
+#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all
* interrupts */
/* @} */
@@ -180,7 +180,7 @@ extern "C" {
* Read/Write
* @{
*/
-#define XSPIPS_ER_ENABLE_MASK 0x00000001 /**< SPI Enable Bit Mask */
+#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */
/* @} */
@@ -190,17 +190,17 @@ extern "C" {
* slave mode. Read/Write
* @{
*/
-#define XSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay for slave select
+#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select
* de-assertion between
* word transfers mask */
-#define XSPIPS_DR_NSS_SHIFT 24 /**< Delay for slave select
+#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select
* de-assertion between
* word transfers shift */
-#define XSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers mask */
-#define XSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */
+#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */
+#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */
+#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */
+#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */
/* @} */
@@ -213,7 +213,7 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */
/* @} */
@@ -226,8 +226,8 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_TXWR_MASK 0x0000007F /**< Transmit Watermark Mask */
-#define XSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */
+#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark
* register reset value */
/* @} */
@@ -239,8 +239,8 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_RXWR_MASK 0x0000007F /**< Receive Watermark Mask */
-#define XSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */
+#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark
* register reset value */
/* @} */
@@ -250,7 +250,7 @@ extern "C" {
*
* @{
*/
-#define XSPIPS_FIFO_DEPTH 128 /**< FIFO depth of Tx and Rx */
+#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */
/* @} */
/**************************** Type Definitions *******************************/
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_options.c b/XilinxProcessorIPLib/drivers/spips/src/xspips_options.c
old mode 100755
new mode 100644
index 4289883b..92e07e67
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_options.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_options.c
@@ -115,11 +115,12 @@ static OptionsMap OptionsTable[] = {
* This function is not thread-safe.
*
******************************************************************************/
-int XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options)
+s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options)
{
u32 ConfigReg;
- unsigned int Index;
+ u32 Index;
u32 CurrentConfigReg;
+ s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -128,60 +129,62 @@ int XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options)
* Do not allow the slave select to change while a transfer is in
* progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
+ if (InstancePtr->IsBusy == TRUE) {
+ Status = (s32)XST_DEVICE_BUSY;
+ } else {
+
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+
+ CurrentConfigReg = ConfigReg;
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0U; Index < XSPIPS_NUM_OPTIONS; Index++) {
+ if ((Options & OptionsTable[Index].Option) != (u32)0U) {
+ /* Turn it on */
+ ConfigReg |= OptionsTable[Index].Mask;
+ }
+ else {
+ /* Turn it off */
+ ConfigReg &= ~(OptionsTable[Index].Mask);
+ }
+ }
+
+
+ /*
+ * If CPOL-CPHA bits are toggled from previous state,
+ * disable before writing the configuration register and then enable.
+ */
+ if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
+ (ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
+ ((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
+ (ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
+ XSpiPs_Disable(InstancePtr);
+ }
+
+ /*
+ * Now write the Config register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Enable
+ */
+ if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
+ (ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
+ ((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
+ (ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
+ XSpiPs_Enable(InstancePtr);
+ }
+
+ Status = (s32)XST_SUCCESS;
}
-
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
-
- CurrentConfigReg = ConfigReg;
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0; Index < XSPIPS_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
- /* Turn it on */
- ConfigReg |= OptionsTable[Index].Mask;
- }
- else {
- /* Turn it off */
- ConfigReg &= ~(OptionsTable[Index].Mask);
- }
- }
-
-
- /*
- * If CPOL-CPHA bits are toggled from previous state,
- * disable before writing the configuration register and then enable.
- */
- if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
- (ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
- ((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
- (ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
- XSpiPs_Disable(InstancePtr);
- }
-
- /*
- * Now write the Config register. Leave it to the upper layers
- * to restart the device.
- */
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Enable
- */
- if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
- (ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
- ((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
- (ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
- XSpiPs_Enable(InstancePtr);
- }
-
- return XST_SUCCESS;
+ return Status;
}
/*****************************************************************************/
@@ -203,9 +206,9 @@ int XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options)
******************************************************************************/
u32 XSpiPs_GetOptions(XSpiPs *InstancePtr)
{
- u32 OptionsFlag = 0;
+ u32 OptionsFlag = 0U;
u32 ConfigReg;
- unsigned int Index;
+ u32 Index;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -250,39 +253,42 @@ u32 XSpiPs_GetOptions(XSpiPs *InstancePtr)
* This function is not thread-safe.
*
******************************************************************************/
-int XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler)
+s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler)
{
u32 ConfigReg;
+ s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Prescaler > 0) && (Prescaler <= XSPIPS_CR_PRESC_MAXIMUM));
+ Xil_AssertNonvoid((Prescaler > 0U) && (Prescaler <= XSPIPS_CR_PRESC_MAXIMUM));
/*
* Do not allow the prescaler to be changed while a transfer is in
* progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
+ if (InstancePtr->IsBusy == TRUE) {
+ Status = (s32)XST_DEVICE_BUSY;
+ } else {
+
+ /*
+ * Read the Config register, mask out the interesting bits, and set
+ * them with the shifted value passed into the function. Write the
+ * results back to the Config register.
+ */
+ ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET);
+
+ ConfigReg &= (u32)(~XSPIPS_CR_PRESC_MASK);
+ ConfigReg |= (u32) ((u32)Prescaler & (u32)XSPIPS_CR_PRESC_MAXIMUM) <<
+ XSPIPS_CR_PRESC_SHIFT;
+
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ Status = (s32)XST_SUCCESS;
}
-
- /*
- * Read the Config register, mask out the interesting bits, and set
- * them with the shifted value passed into the function. Write the
- * results back to the Config register.
- */
- ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET);
-
- ConfigReg &= ~XSPIPS_CR_PRESC_MASK;
- ConfigReg |= (u32) (Prescaler & XSPIPS_CR_PRESC_MAXIMUM) <<
- XSPIPS_CR_PRESC_SHIFT;
-
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_CR_OFFSET,
- ConfigReg);
-
- return XST_SUCCESS;
+ return Status;
}
/*****************************************************************************/
@@ -345,10 +351,11 @@ u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr)
* @note None.
*
******************************************************************************/
-int XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit)
{
u32 DelayRegister;
+ s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -357,20 +364,22 @@ int XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
* Do not allow the delays to change while a transfer is in
* progress. Not thread-safe.
*/
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
+ if (InstancePtr->IsBusy == TRUE) {
+ Status = (s32)XST_DEVICE_BUSY;
+ } else {
+
+ /* Shift, Mask and OR the values to build the register settings */
+ DelayRegister = (u32) DelayNss << XSPIPS_DR_NSS_SHIFT;
+ DelayRegister |= (u32) DelayBtwn << XSPIPS_DR_BTWN_SHIFT;
+ DelayRegister |= (u32) DelayAfter << XSPIPS_DR_AFTER_SHIFT;
+ DelayRegister |= (u32) DelayInit;
+
+ XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSPIPS_DR_OFFSET, DelayRegister);
+
+ Status = (s32)XST_SUCCESS;
}
-
- /* Shift, Mask and OR the values to build the register settings */
- DelayRegister = (u32) DelayNss << XSPIPS_DR_NSS_SHIFT;
- DelayRegister |= (u32) DelayBtwn << XSPIPS_DR_BTWN_SHIFT;
- DelayRegister |= (u32) DelayAfter << XSPIPS_DR_AFTER_SHIFT;
- DelayRegister |= (u32) DelayInit;
-
- XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSPIPS_DR_OFFSET, DelayRegister);
-
- return XST_SUCCESS;
+ return Status;
}
/*****************************************************************************/
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_selftest.c b/XilinxProcessorIPLib/drivers/spips/src/xspips_selftest.c
old mode 100755
new mode 100644
index dbd9a042..4da2c660
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_selftest.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_selftest.c
@@ -87,9 +87,9 @@
* @note None.
*
******************************************************************************/
-int XSpiPs_SelfTest(XSpiPs *InstancePtr)
+s32 XSpiPs_SelfTest(XSpiPs *InstancePtr)
{
- int Status;
+ s32 Status;
u32 Register;
u8 DelayTestNss;
u8 DelayTestBtwn;
@@ -110,19 +110,19 @@ int XSpiPs_SelfTest(XSpiPs *InstancePtr)
Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
XSPIPS_CR_OFFSET);
if (Register != XSPIPS_CR_RESET_STATE) {
- return XST_REGISTER_ERROR;
+ return (s32)XST_REGISTER_ERROR;
}
Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
XSPIPS_SR_OFFSET);
if (Register != XSPIPS_ISR_RESET_STATE) {
- return XST_REGISTER_ERROR;
+ return (s32)XST_REGISTER_ERROR;
}
- DelayTestNss = 0x5A;
- DelayTestBtwn = 0xA5;
- DelayTestAfter = 0xAA;
- DelayTestInit = 0x55;
+ DelayTestNss = 0x5AU;
+ DelayTestBtwn = 0xA5U;
+ DelayTestAfter = 0xAAU;
+ DelayTestInit = 0x55U;
/*
* Write and read the delay register, just to be sure there is some
@@ -130,19 +130,19 @@ int XSpiPs_SelfTest(XSpiPs *InstancePtr)
*/
Status = XSpiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
DelayTestAfter, DelayTestInit);
- if (Status != XST_SUCCESS) {
+ if (Status != (s32)XST_SUCCESS) {
return Status;
}
XSpiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
&DelayTestAfter, &DelayTestInit);
- if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
- (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
- return XST_REGISTER_ERROR;
+ if ((0x5AU != DelayTestNss) || (0xA5U != DelayTestBtwn) ||
+ (0xAAU != DelayTestAfter) || (0x55U != DelayTestInit)) {
+ return (s32)XST_REGISTER_ERROR;
}
- Status = XSpiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
- if (Status != XST_SUCCESS) {
+ Status = XSpiPs_SetDelays(InstancePtr, 0U, 0U, 0U, 0U);
+ if (Status != (s32)XST_SUCCESS) {
return Status;
}
@@ -151,5 +151,5 @@ int XSpiPs_SelfTest(XSpiPs *InstancePtr)
*/
XSpiPs_Reset(InstancePtr);
- return XST_SUCCESS;
+ return (s32)XST_SUCCESS;
}
diff --git a/XilinxProcessorIPLib/drivers/spips/src/xspips_sinit.c b/XilinxProcessorIPLib/drivers/spips/src/xspips_sinit.c
old mode 100755
new mode 100644
index 94d35b62..74d74097
--- a/XilinxProcessorIPLib/drivers/spips/src/xspips_sinit.c
+++ b/XilinxProcessorIPLib/drivers/spips/src/xspips_sinit.c
@@ -62,7 +62,7 @@
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
-extern XSpiPs_Config XSpiPs_ConfigTable[];
+extern XSpiPs_Config XSpiPs_ConfigTable[XPAR_XSPIPS_NUM_INSTANCES];
/*****************************************************************************/
/**
@@ -84,13 +84,13 @@ extern XSpiPs_Config XSpiPs_ConfigTable[];
XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId)
{
XSpiPs_Config *CfgPtr = NULL;
- int Index;
+ u32 Index;
- for (Index = 0; Index < XPAR_XSPIPS_NUM_INSTANCES; Index++) {
+ for (Index = 0U; Index < (u32)XPAR_XSPIPS_NUM_INSTANCES; Index++) {
if (XSpiPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XSpiPs_ConfigTable[Index];
break;
}
}
- return CfgPtr;
+ return (XSpiPs_Config *)CfgPtr;
}