Copyright � 1995-2014 Xilinx, Inc. All rights reserved.
+ + \ No newline at end of file diff --git a/XilinxProcessorIPLib/drivers/llfifo/examples/xllfifo_interrupt_example.c b/XilinxProcessorIPLib/drivers/llfifo/examples/xllfifo_interrupt_example.c new file mode 100644 index 00000000..85f00caa --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/examples/xllfifo_interrupt_example.c @@ -0,0 +1,619 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xllfifo_interrupt_example.c + * This file demonstrates how to use the Streaming fifo driver on the xilinx AXI + * Streaming FIFO IP.The AXI4-Stream FIFO core allows memory mapped access to a + * AXI-Stream interface. The core can be used to interface to AXI Streaming IPs + * similar to the LogiCORE IP AXI Ethernet core, without having to use full DMA + * solution. + * + * This is the interrupt example for the FIFO it assumes that at the + * h/w level FIFO is connected in loopback.In these we write known amount of + * data to the FIFO and wait for interrupts and after compltely receiving the + * data compares it with the data transmitted. + * + * Note: The TDEST Must be enabled in the H/W design inorder to get + * correct RDR value. + * + *+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 3.00a adk 08/10/2013 initial release CR:727787 + * + *+ * + * *************************************************************************** + */ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "xil_exception.h" +#include "xstreamer.h" +#include "xil_cache.h" +#include "xllfifo.h" +#include "xstatus.h" + +#ifdef XPAR_UARTNS550_0_BASEADDR +#include "xuartns550_l.h" /* to use uartns550 */ +#endif + +#ifdef XPAR_INTC_0_DEVICE_ID + #include "xintc.h" +#else + #include "xscugic.h" +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID + +#ifdef XPAR_INTC_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#define FIFO_INTR_ID XPAR_INTC_0_LLFIFO_0_VEC_ID +#else +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#define FIFO_INTR_ID XPAR_FABRIC_LLFIFO_0_VEC_ID +#endif + +#ifdef XPAR_INTC_0_DEVICE_ID + #define INTC XIntc + #define INTC_HANDLER XIntc_InterruptHandler +#else + #define INTC XScuGic + #define INTC_HANDLER XScuGic_InterruptHandler +#endif + + +#define WORD_SIZE 4 /* Size of words in bytes */ + +#define MAX_PACKET_LEN 4 + +#define NO_OF_PACKETS 64 + +#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN + +#undef DEBUG + +/************************** Function Prototypes ******************************/ +#ifdef XPAR_UARTNS550_0_BASEADDR +static void Uart550_Setup(void); +#endif + +int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId); +int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr); +static void FifoHandler(XLlFifo *Fifo); +static void FifoRecvHandler(XLlFifo *Fifo); +static void FifoSendHandler(XLlFifo *Fifo); +static void FifoErrorHandler(XLlFifo *InstancePtr, u32 Pending); +int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr, + u16 FifoIntrId); +static void DisableIntrSystem(INTC *IntcInstancePtr, u16 FifoIntrId); + +/* + * Flags interrupt handlers use to notify the application context the events. + */ +volatile int Done; +volatile int Error; + +/************************** Variable Definitions *****************************/ + +/* + * Device instance definitions + */ +XLlFifo FifoInstance; + +/* + * Instance of the Interrupt Controller + */ +static INTC Intc; + +u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE]; +u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE]; + +/*****************************************************************************/ +/** +* +* Main function +* +* This function is the main entry of the AXI FIFO interrupt test. +* +* @param None +* +* @return - XST_SUCCESS if tests pass +* - XST_FAILURE if fails. +* +* @note None +* +******************************************************************************/ +int main() +{ + int Status; + + xil_printf("--- Entering main() ---\n\r"); + + Status = XLlFifoInterruptExample(&FifoInstance, FIFO_DEV_ID); + if (Status != XST_SUCCESS) { + xil_printf("Axi Streaming FIFO Interrupt Example Test Failed"); + xil_printf("--- Exiting main() ---\n\r"); + return XST_FAILURE; + } + + xil_printf("Axi Streaming FIFO Interrupt Example Test passed\n\r"); + xil_printf("--- Exiting main() ---\n\r"); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function demonstrates the usage of AXI FIFO +* It does the following: +* - Set up the output terminal if UART16550 is in the hardware build +* - Initialize the Axi FIFO Device. +* - Set up the interrupt handler for fifo +* - Transmit the data +* - Compare the data +* - Return the result +* +* @param InstancePtr is a pointer to the instance of the +* XLlFifo instance. +* @param DeviceId is Device ID of the Axi Fifo Deive instance, +* typically XPAR_
+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 3.00a adk 08/10/2013 initial release CR:727787 + * + *+ * + * *************************************************************************** + */ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "xil_exception.h" +#include "xstreamer.h" +#include "xil_cache.h" +#include "xllfifo.h" +#include "xstatus.h" + +#ifdef XPAR_UARTNS550_0_BASEADDR +#include "xuartns550_l.h" /* to use uartns550 */ +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID + +#define WORD_SIZE 4 /* Size of words in bytes */ + +#define MAX_PACKET_LEN 4 + +#define NO_OF_PACKETS 64 + +#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN + +#undef DEBUG + +/************************** Function Prototypes ******************************/ +#ifdef XPAR_UARTNS550_0_BASEADDR +static void Uart550_Setup(void); +#endif + +int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId); +int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr); +int RxReceive(XLlFifo *InstancePtr, u32 *DestinationAddr); + +/************************** Variable Definitions *****************************/ +/* + * Device instance definitions + */ +XLlFifo FifoInstance; + +u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE]; +u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE]; + +/*****************************************************************************/ +/** +* +* Main function +* +* This function is the main entry of the Axi FIFO Polling test. +* +* @param None +* +* @return - XST_SUCCESS if tests pass +* - XST_FAILURE if fails. +* +* @note None +* +******************************************************************************/ +int main() +{ + int Status; + + xil_printf("--- Entering main() ---\n\r"); + + Status = XLlFifoPollingExample(&FifoInstance, FIFO_DEV_ID); + if (Status != XST_SUCCESS) { + xil_printf("Axi Streaming FIFO Polling Example TestFailed\n\r"); + xil_printf("--- Exiting main() ---\n\r"); + return XST_FAILURE; + } + + xil_printf("Axi Streaming FIFO Polling Example Test passed\n\r"); + xil_printf("--- Exiting main() ---\n\r"); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function demonstrates the usage AXI FIFO +* It does the following: +* - Set up the output terminal if UART16550 is in the hardware build +* - Initialize the Axi FIFO Device. +* - Transmit the data +* - Receive the data from fifo +* - Compare the data +* - Return the result +* +* @param InstancePtr is a pointer to the instance of the +* XLlFifo component. +* @param DeviceId is Device ID of the Axi Fifo Deive instance, +* typically XPAR_
+ * while (XLlFifo_RxOccupancy(&RxInstance)) {
+ * frame_len = XLlFifo_RxGetLen(&RxInstance);
+ * while (frame_len) {
+ * unsigned bytes = min(sizeof(buffer), frame_len);
+ * XLlFifo_Read(&RxInstance, buffer, bytes);
+ * // ********
+ * // do something with buffer here
+ * // ********
+ * frame_len -= bytes;
+ * }
+ * }
+ *
+ *
+ * This FIFO hardware core does not support a sequence where the
+ * calling code calls RxGetLen() twice in a row and then receive the data
+ * for two frames. Each frame must be read in by calling RxGetLen() just
+ * prior to reading the data.
+ *
+ *
+ * frame_left = frame_len;
+ * while (frame_left) {
+ * unsigned bytes = min(sizeof(buffer), frame_left);
+ * XLlFifo_Write(&TxInstance, buffer, bytes);
+ * // ********
+ * // do something here to refill buffer
+ * // ********
+ * frame_left -= bytes;
+ * }
+ * XLlFifo_TxSetLen(&RxInstance, frame_len);
+ *
+ *
+ * This FIFO hardware core does not support a sequence where the
+ * calling code writes the data for two frames and then calls TxSetLen()
+ * twice in a row. Each frame must be written by writting the data for one
+ * frame and then calling TxSetLen().
+ *
+ * + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.00a jvb 10/12/06 First release + * 1.01a sdm 08/22/08 Removed support for static interrupt handlers from the + * MDD file + * 1.02a jz 12/04/09 Hal phase 1 support + * 2.01a asa 09/17/10 Added code for resetting Local Link/AXI Streaming + * interface for CR574868 + * 2.02a asa 12/27/11 Changed the function XStrm_Read in xtreamer.c to reset + * HeadIndex to zero when all bytes have been read. + * Changed the macro XStrm_IsRxInternalEmpty in file + * xtreamer.h to use FrmByteCnt instead of HeadIndex. + * When FrmByteCnt is zero, this means all internal buffers + * in streamer are empty. Earlier implementation using + * HeadIndex was not very clear and could give improper + * results for some cases. + * Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h + * These changes are done to fix the CR 604650. + * 2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET + * defines for the new registers, and XLLF_INT_TFPF_MASK, + * XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and + * XLLF_INT_RFPE_MASK for the new version of the + * AXI4-Stream FIFO core (v2.01a and later) + * + * 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are + * In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword. + * In XLlfifo.h file updated XLlfifo structure for + * Axi4BaseAddress and for Datainterface type provided + * polling and interrupt examples. XLlfifo_IsRxDone Macro + * Is added in the XLlfifo.h file for polledmode exmaple. + * Added Static initialzation for the driver. + * XLlFifo_Initialize is still used to make the driver + * backward compatible. + * 4.0 adk 19/12/13 Updated as per the New Tcl API's + * + *+ * + *****************************************************************************/ +#ifndef XLLFIFO_H /* prevent circular inclusions */ +#define XLLFIFO_H /* by using preprocessor symbols */ + +/* force C linkage */ +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/* This order needs to be kept this way to avoid xstatus/xil_types conflict */ +#include "xstreamer.h" +#include "xllfifo_hw.h" + +/**************************** Type Definitions *******************************/ + +/** + * This typedef defines a run-time instance of an XLlFifo device. + */ +typedef struct XLlFifo { + u32 BaseAddress; /**< BaseAddress is the physical base address of the + * device's registers + */ + + u32 IsReady; /**< IsReady is non-zero if the driver instance + * has been initialized. + */ + + u32 Axi4BaseAddress; /**< BaseAddress if the FIFO Data interface is + * AXI4 this address should use for FIFO + * access + */ + u32 Datainterface; /**< Data interface of the FIFO. This value is zero + * if the Datainterface is AXI4-lite. + */ + XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer + * instance for the receive channel. + */ + XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer + * instance for the transmit channel. + */ +} XLlFifo; + +typedef struct XLlFifo_Config { + u32 DeviceId; /**< Deviceid of the AXI FIFO */ + u32 BaseAddress; /**< Base Address of the AXI FIFO */ + u32 Axi4BaseAddress; /**< Axi4 interface Base address */ + u32 Datainterface; /**< Type of Datainterface */ +}XLlFifo_Config; + +/****************************************************************************/ +/** +* +* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface +* the FIFO specified by InstancePtr. XLlFifo_TxReset resets also sends a +* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any +* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO +* not yet transmitted. +* +* @param InstancePtr references the FIFO on which to operate. +* +* @return N/A +* +* @note +* C-style signature: +* void XLlFifo_Reset(XLlFifo *InstancePtr) +* +*****************************************************************************/ +#define XLlFifo_Reset(InstancePtr) \ + XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \ + XLLF_LLR_RESET_MASK) + + +/****************************************************************************/ +/** +* +* XLlFifo_Status returns a bit mask of the interrupt status register (ISR) +* for the FIFO specified by InstancePtr. XLlFifo_Status can be used +* to query the status of the FIFO without having to have interrupts enabled. +* +* @param InstancePtr references the FIFO on which to operate. +* +* @return XLlFifo_IntStatus returns a bit mask of the status conditions. +* The mask will be a set of bitwise or'd values from the +*
XLLF_INT_*_MASK preprocessor symbols.
+*
+* @note
+* C-style signature:
+* u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Status(InstancePtr) \
+ XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntEnable enables the interrupts specified in Mask for the
+* FIFO specified by InstancePtr. The corresponding interrupt for each bit
+* set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param Mask contains a bit mask of the interrupts to enable. The mask
+* can be formed using a set of bitwise or'd values from the
+* XLLF_INT_*_MASK preprocessor symbols.
+*
+* @return N/A
+*
+* @note
+* C-style signature:
+* void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntEnable(InstancePtr, Mask) \
+{ \
+ u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+ XLLF_IER_OFFSET); \
+ Reg |= ((Mask) & XLLF_INT_ALL_MASK); \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+ Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntDisable disables the interrupts specified in Mask for the
+* FIFO specified by InstancePtr. The corresponding interrupt for each bit
+* set to 1 in Mask, will be disabled. In other words, XLlFifo_IntDisable
+* uses the "set a bit to clear it" scheme.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param Mask contains a bit mask of the interrupts to disable. The mask
+* can be formed using a set of bitwise or'd values from the
+* XLLF_INT_*_MASK preprocessor symbols.
+*
+* @return N/A
+*
+* @note
+* C-style signature:
+* void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntDisable(InstancePtr, Mask) \
+{ \
+ u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+ XLLF_IER_OFFSET); \
+ Reg &= ~((Mask) & XLLF_INT_ALL_MASK); \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+ Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
+* FIFO specified by InstancePtr. Each bit set to 1 in the return value
+* represents a pending interrupt.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_IntPending returns a bit mask of the interrupts that are
+* pending. The mask will be a set of bitwise or'd values from the
+* XLLF_INT_*_MASK preprocessor symbols.
+*
+* @note
+* C-style signature:
+* u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_ipie_value;
+extern u32 _xllfifo_ipis_value;
+#define XLlFifo_IntPending(InstancePtr) \
+ (_xllfifo_ipie_value = XLlFifo_ReadReg( \
+ (InstancePtr)->BaseAddress, XLLF_IER_OFFSET), \
+ _xllfifo_ipis_value = XLlFifo_ReadReg( \
+ (InstancePtr)->BaseAddress, XLLF_ISR_OFFSET), \
+ (_xllfifo_ipie_value & _xllfifo_ipis_value))
+#else
+#define XLlFifo_IntPending(InstancePtr) \
+ (XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) & \
+ XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntClear clears pending interrupts specified in Mask for the
+* FIFO specified by InstancePtr. The corresponding pending interrupt for
+* each bit set to 1 in Mask, will be cleared. In other words,
+* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param Mask contains a bit mask of the pending interrupts to clear. The
+* mask can be formed using a set of bitwise or'd values from the
+* XLLF_INT_*_MASK preprocessor symbols.
+*
+* @note
+* C-style signature:
+* void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntClear(InstancePtr, Mask) \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
+ ((Mask) & XLLF_INT_ALL_MASK))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_RxReset resets the receive channel of the FIFO specified by
+* InstancePtr. XLlFifo_RxReset drops any bytes in the FIFO not yet
+* retrieved.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Rx Reset
+* complete (RRC) bit.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return N/A
+*
+* @note
+* C-style signature:
+* void XLlFifo_RxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_RxReset(InstancePtr) \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
+ XLLF_RDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
+* by InstancePtr, is empty.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
+* FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+* int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxEmpty(InstancePtr) \
+ ((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
+ ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the receive channel of the FIFO, specified by InstancePtr.
+*
+* The xps_ll_fifo core uses the same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
+* 1, which means one length value (a reserved fifo location) and no data
+* values.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_RxOccupancy returns the occupancy count for the specified
+* packet FIFO.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxOccupancy(InstancePtr) \
+ XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
+* the next frame from the receive channel of the FIFO, specified by
+* InstancePtr.
+*
+* Note that the program must first call XLlFifo_RxGetLen before pulling data
+* out of the receive channel of the FIFO with XLlFifo_Read.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_RxGetLen returns the number of bytes available in the next
+* frame.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxGetLen(InstancePtr) \
+ XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO
+* referenced by InstancePtr to the block of memory, referenced by
+* BufPtr.
+*
+* Care must be taken to ensure that the number of bytes read with one or more
+* calls to XLlFifo_Read() does not exceed the number of bytes available given
+* from the last call to XLlFifo_RxGetLen().
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param BufPtr specifies the memory address to place the data read.
+*
+* @param Bytes specifies the number of bytes to read.
+*
+* @return N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
+ XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
+* InstancePtr. XLlFifo_TxReset drops any bytes in the FIFO not yet
+* transmitted.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Tx Reset
+* complete (TRC) bit.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return N/A
+*
+* @note
+* C-style signature:
+* void XLlFifo_TxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxReset(InstancePtr) \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
+ XLLF_TDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
+* of the FIFO, specified by InstancePtr, is complete. XLlFifo_IsTxDone
+* works only if the TC bit in the IS register is cleared before sending a
+* frame.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_IsTxDone returns TRUE when the transmit channel of the
+* FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
+*
+* @note
+* C-style signature:
+* int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsTxDone(InstancePtr) \
+ ((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+ XLLF_INT_TC_MASK) \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxDone returns true if the reception in the receive channel
+* of the FIFO, specified by InstancePtr, is complete. XLlFifo_IsRxDone
+* works only if the RC bit in the ISR register is cleared before receiving a
+* frame.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_IsRxDone returns TRUE when the receive channel of the
+* FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
+*
+* @note
+* C-style signature:
+* int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxDone(InstancePtr) \
+ ((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+ XLLF_INT_RC_MASK) \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxVacancy returns the number of unused 32 bit words available
+* (vacancy) in the send channel of the FIFO specified by InstancePtr.
+*
+* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
+* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
+* and no data values yet present.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
+* the specified FIFO.
+*
+* @note
+* C-style signature:
+* u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxVacancy(InstancePtr) \
+ XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the
+* transmit channel of the FIFO specified by InstancePtr.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param Bytes specifies the frame length in bytes.
+*
+* @return N/A
+*
+* @note
+*
+* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
+*
+******************************************************************************/
+#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
+ XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Write writes Bytes bytes of the block of memory, referenced by
+* BufPtr, to the transmit channel of the FIFO referenced by
+* InstancePtr.
+*
+* Care must be taken to ensure that the number of bytes written with one or
+* more calls to XLlFifo_Write() matches the number of bytes given in the next
+* call to XLlFifo_TxSetLen().
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @param BufPtr specifies the memory address of data to write.
+*
+* @param Bytes specifies the number of bytes to write.
+*
+* @return N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
+ XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
+*
+* The TDR stores the destination address corresponding to the packet to be
+* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
+* the following sequence should be followed
+* - Write the destination address into TDR first,
+* - Write the packet data to the Transmit Data FIFO next
+* - Write the length of the packet into the Transmit Length Register.
+*
+* @param InstancePtr references the FIFO on which to operate.
+* @param Tdest is the Transmit Destination address to be written to TDR.
+*
+* @return N/A
+*
+* @note C Signature:
+* void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
+*
+******************************************************************************/
+#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
+ XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
+ Tdest & 0xF)
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
+*
+* The RDR contains destination address corresponding to the valid packet that
+* is received. The RDR should only be read when a receive packet is available
+* for processing (the receive occupancy is not zero).
+* Once the RDR is read, the receive packet data should be read from the receive
+* data FIFO before the RDR is read again. The RDR values are stored in the
+* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
+* The RDR value for the subsequent packet to be processed is moved to the RDR
+* when the previous RDR value has been read.
+*
+* @param InstancePtr references the FIFO on which to operate.
+*
+* @return The Receive Destination address read from the RDR.
+*
+* @note C Signature:
+* u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_ReadRdr(InstancePtr) \
+ XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+/*
+ * Initialization functions xllfifo.c
+ */
+int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
+ XLlFifo_Config *Config, u32 EffectiveAddress);
+void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
+XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
+u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
+u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
+u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
+void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
+u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
+void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* XLLFIFO_H end of preprocessor protection symbols */
diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_g.c b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_g.c
new file mode 100644
index 00000000..628a946e
--- /dev/null
+++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_g.c
@@ -0,0 +1,66 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtrafgen_g.c
+*
+* Provide a template for user to define their own hardware settings.
+*
+* If using XPS, this file will be automatically generated.
+*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 3.00a adk 9/10/2013 initial release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xllfifo.h" + +/************************** Constant Definitions *****************************/ + +XLlFifo_Config XLlFifo_ConfigTable[] = +{ + { + XPAR_AXI_FIFO_MM_S_1_DEVICE_ID, + XPAR_AXI_FIFO_MM_S_1_BASEADDR, + XPAR_AXI_FIFO_MM_S_1_AXI4_BASEADDR, + XPAR_AXI_FIFO_MM_S_1_DATA_INTERFACE_TYPE + } +}; diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h new file mode 100644 index 00000000..bb7fa206 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h @@ -0,0 +1,237 @@ +/****************************************************************************** +* +* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xllfifo_hw.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the xps_ll_fifo core. +* High-level driver functions are defined in xpfifo.h. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a jvb 10/16/06 First release. +* 1.02a jz 12/04/09 Hal phase 1 support +* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release +* 2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET +* defines for the new registers, and XLLF_INT_TFPF_MASK, +* XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and +* XLLF_INT_RFPE_MASK for the new version of the +* AXI4-Stream FIFO core (v2.01a and later) +*+* +******************************************************************************/ + +#ifndef XLLFIFO_HW_H /* prevent circular inclusions */ +#define XLLFIFO_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xdebug.h" +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. + */ + +/** @name Registers + * @{ + */ +#define XLLF_ISR_OFFSET 0x00000000 /**< Interrupt Status */ +#define XLLF_IER_OFFSET 0x00000004 /**< Interrupt Enable */ + +#define XLLF_TDFR_OFFSET 0x00000008 /**< Transmit Reset */ +#define XLLF_TDFV_OFFSET 0x0000000c /**< Transmit Vacancy */ +#define XLLF_TDFD_OFFSET 0x00000010 /**< Transmit Data */ +#define XLLF_TLF_OFFSET 0x00000014 /**< Transmit Length */ + +#define XLLF_RDFR_OFFSET 0x00000018 /**< Receive Reset */ +#define XLLF_RDFO_OFFSET 0x0000001c /**< Receive Occupancy */ +#define XLLF_RDFD_OFFSET 0x00000020 /**< Receive Data */ +#define XLLF_RLF_OFFSET 0x00000024 /**< Receive Length */ +#define XLLF_LLR_OFFSET 0x00000028 /**< Local Link Reset */ +#define XLLF_TDR_OFFSET 0x0000002C /**< Transmit Destination */ +#define XLLF_RDR_OFFSET 0x00000030 /**< Receive Destination */ + +/*@}*/ + +/* Register masks. The following constants define bit locations of various + * control bits in the registers. Constants are not defined for those registers + * that have a single bit field representing all 32 bits. For further + * information on the meaning of the various bit masks, refer to the HW spec. + */ + +/** @name Interrupt bits + * These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET + * registers. + * @{ + */ +#define XLLF_INT_RPURE_MASK 0x80000000 /**< Receive under-read */ +#define XLLF_INT_RPORE_MASK 0x40000000 /**< Receive over-read */ +#define XLLF_INT_RPUE_MASK 0x20000000 /**< Receive underrun (empty) */ +#define XLLF_INT_TPOE_MASK 0x10000000 /**< Transmit overrun */ +#define XLLF_INT_TC_MASK 0x08000000 /**< Transmit complete */ +#define XLLF_INT_RC_MASK 0x04000000 /**< Receive complete */ +#define XLLF_INT_TSE_MASK 0x02000000 /**< Transmit length mismatch */ +#define XLLF_INT_TRC_MASK 0x01000000 /**< Transmit reset complete */ +#define XLLF_INT_RRC_MASK 0x00800000 /**< Receive reset complete */ +#define XLLF_INT_TFPF_MASK 0x00400000 /**< Tx FIFO Programmable Full, + * AXI FIFO MM2S Only */ +#define XLLF_INT_TFPE_MASK 0x00200000 /**< Tx FIFO Programmable Empty + * AXI FIFO MM2S Only */ +#define XLLF_INT_RFPF_MASK 0x00100000 /**< Rx FIFO Programmable Full + * AXI FIFO MM2S Only */ +#define XLLF_INT_RFPE_MASK 0x00080000 /**< Rx FIFO Programmable Empty + * AXI FIFO MM2S Only */ +#define XLLF_INT_ALL_MASK 0xfff80000 /**< All the ints */ +#define XLLF_INT_ERROR_MASK 0xf2000000 /**< Error status ints */ +#define XLLF_INT_RXERROR_MASK 0xe0000000 /**< Receive Error status ints */ +#define XLLF_INT_TXERROR_MASK 0x12000000 /**< Transmit Error status ints */ +/*@}*/ + +/** @name Reset register values + * These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET + * reset registers. + * @{ + */ +#define XLLF_RDFR_RESET_MASK 0x000000a5 /**< receive reset value */ +#define XLLF_TDFR_RESET_MASK 0x000000a5 /**< Transmit reset value */ +#define XLLF_LLR_RESET_MASK 0x000000a5 /**< Local Link reset value */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**** debug macros ****/ +#define XLlFifo_reg_name(RegOffset) \ + (((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \ + ((RegOffset) == XLLF_IER_OFFSET) ? "IER": \ + ((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \ + ((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \ + ((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \ + ((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \ + ((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \ + ((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \ + ((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \ + ((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \ + "unknown") + +#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value) \ + xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \ + XLlFifo_reg_name(RegOffset), \ + (RegOffset) + (BaseAddress)) + +#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value) \ + xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \ + XLlFifo_reg_name(RegOffset), \ + (RegOffset) + (BaseAddress), (Value)) +/**** end debug macros ****/ + +/****************************************************************************/ +/** +* +* XLlFifo_ReadReg returns the value of the register at the offet, +* RegOffset, from the memory mapped base address, BaseAddress. +* +* @param BaseAddress specifies the base address of the device. +* +* @param RegOffset specifies the offset from BaseAddress. +* +* @return XLlFifo_ReadReg returns the value of the specified register. +* +* @note +* C-style signature: +* u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#ifdef DEBUG +extern u32 _xllfifo_rr_value; +#define XLlFifo_ReadReg(BaseAddress, RegOffset) \ + ((((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \ + "XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \ + (RegOffset)) : 0), \ + _xllfifo_rr_value = Xil_In32((BaseAddress) + (RegOffset)), \ + XLlFifo_print_reg_i((BaseAddress), (RegOffset), _xllfifo_rr_value), \ + _xllfifo_rr_value) +#else +#define XLlFifo_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) +#endif + +/****************************************************************************/ +/** +* +* XLlFifo_WriteReg writes the value, Value, to the register at the +* offet, RegOffset, from the memory mapped base address, +* BaseAddress. +* +* @param BaseAddress specifies the base address of the device. +* +* @param RegOffset specifies the offset from BaseAddress. +* +* @param Value is value to write to the register. +* +* @return N/A +* +* @note +* C-style signature: +* void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value) +* +*****************************************************************************/ +#ifdef DEBUG +#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \ + (((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \ + "XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \ + (RegOffset)) : 0), \ + XLlFifo_print_reg_o((BaseAddress), (RegOffset), (Value)), \ + (Xil_Out32((BaseAddress) + (RegOffset), (Value))) +#else +#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \ + ((Xil_Out32((BaseAddress) + (RegOffset), (Value)))) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* XLLFIFO_HW_H end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_sinit.c b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_sinit.c new file mode 100644 index 00000000..f6108ffb --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_sinit.c @@ -0,0 +1,85 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xtrafgen_sinit.c +* +* This file contains static initialzation functionality for Axi Streaming FIFO +* driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 3.00a adk 9/10/2013 initial release +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xllfifo.h" + +/*****************************************************************************/ +/** + * Look up the hardware configuration for a device instance + * + * @param DeviceId is the unique device ID of the device to lookup for + * + * @return + * The configuration structure for the device. If the device ID is + * not found,a NULL pointer is returned. + * + * @note None + * + ******************************************************************************/ +XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId) +{ + extern XLlFifo_Config XLlFifo_ConfigTable[]; + XLlFifo_Config *CfgPtr; + u32 Index; + + CfgPtr = NULL; + + for (Index = 0; Index < XPAR_XLLFIFO_NUM_INSTANCES; Index++) { + if (XLlFifo_ConfigTable[Index].DeviceId == DeviceId) { + + CfgPtr = &XLlFifo_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} diff --git a/XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.c b/XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.c new file mode 100644 index 00000000..f619472e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.c @@ -0,0 +1,513 @@ +/****************************************************************************** +* +* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/* +* @file xstreamer.c +* +* See xtreamer.h for a description on how to use this driver. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a jvb 10/13/06 First release - based on Robert McGee's streaming packet +* fifo driver. +* 1.02a jz 12/04/09 Hal phase 1 support +* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release +* 2.02a asa 12/28/11 The function XStrm_Read is changed to reset HeadIndex +* to zero when all the bytes are read. +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstreamer.h" +#include "xil_assert.h" + +/* + * Implementation Notes + * + * --- Receive --- + * + * The basic algorithm for receiving bytes through this byte streamer copies a + * fifo key-hole width chunk from the fifo into a holding buffer and then doles + * out the bytes from the holding buffer. In some cases, when the buffer given + * happens to already be aligned in memory, this algorithm will bypass the + * holding buffer. + * + * Here is a picture to depict this process: + * + * Initial state: holding buffer + * +--------------+ + * |
+ * frame_len = XStrm_RxGetLen(&RxInstance);
+ * while (frame_len) {
+ * unsigned bytes = min(sizeof(buffer), frame_len);
+ * XStrm_Read(&RxInstance, buffer, bytes);
+ * // do something with buffer here
+ * frame_len -= bytes;
+ * }
+ *
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ *
+ * frame_left = frame_len;
+ * while (frame_left) {
+ * unsigned bytes = min(sizeof(buffer), frame_left);
+ * XStrm_Write(&TxInstance, buffer, bytes);
+ * // do something here to refill buffer
+ * }
+ * XStrm_TxSetLen(&RxInstance, frame_len);
+ *
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.00a jvb 10/12/06 First release + * 1.02a jz 12/04/09 Hal phase 1 support + * 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release + * 2.02a asa 12/28/11 The macro XStrm_IsRxInternalEmpty is changed to use + * FrmByteCnt instead of HeadIndex. + *+ * + *****************************************************************************/ +#ifndef XSTREAMER_H /* prevent circular inclusions */ +#define XSTREAMER_H /* by using preprocessor symbols */ + +/* force C linkage */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "xenv.h" +#include "xdebug.h" +#include "xil_types.h" + +/* + * key hole size in 32 bit words + */ +#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS 4 + +/* + * This union is used simply to force a 32bit alignment on the + * buffer. Only the 'bytes' member is really used. + */ +union XStrm_AlignedBufferType { + u32 _words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS]; + char bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS * 4]; +}; + +typedef int(*XStrm_XferFnType) (void *FifoInstance, void *BufPtr, + unsigned WordCount); +typedef u32 (*XStrm_GetLenFnType) (void *FifoInstance); +typedef void (*XStrm_SetLenFnType) (void *FifoInstance, + u32 ByteCount); +typedef u32 (*XStrm_GetOccupancyFnType) (void *FifoInstance); +typedef u32 (*XStrm_GetVacancyFnType) (void *FifoInstance); + +/** + * This typedef defines a run-time instance of a receive byte-streamer. + */ +typedef struct XStrm_RxFifoStreamer { + union XStrm_AlignedBufferType AlignedBuffer; + unsigned HeadIndex; /**< HeadIndex is the index to the AlignedBuffer + * as bytes. + */ + unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes. + */ + unsigned FrmByteCnt; /**< FrmByteCnt is the number of bytes in the next + * Frame. + */ + void *FifoInstance; /**< FifoInstance is the FIFO driver instance to + * pass to ReadFn, GetLenFn, and GetOccupancyFn + * routines. + */ + XStrm_XferFnType ReadFn; /**< ReadFn is the routine the streamer + * uses to receive bytes from the Fifo. + */ + XStrm_GetLenFnType GetLenFn; /**< GetLenFn is the routine the streamer + * uses to initiate receive operations + * on the FIFO. + */ + XStrm_GetOccupancyFnType GetOccupancyFn; /**< GetOccupancyFn is the + * routine the streamer uses + * to get the occupancy from + * the FIFO. + */ +} XStrm_RxFifoStreamer; + +/** + * This typedef defines a run-time instance of a transmit byte-streamer. + */ +typedef struct XStrm_TxFifoStreamer { + union XStrm_AlignedBufferType AlignedBuffer; + unsigned TailIndex; /**< TailIndex is the index to the AlignedBuffer + * as bytes + */ + unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes. + */ + + void *FifoInstance; /**< FifoInstance is the FIFO driver instance to + * pass to WriteFn, SetLenFn, and GetVacancyFn + * routines. + */ + XStrm_XferFnType WriteFn; /**< WriteFn is the routine the streamer + * uses to transmit bytes to the Fifo. + */ + XStrm_SetLenFnType SetLenFn; /**< SetLenFn is the routine the streamer + * uses to initiate transmit operations + * on the FIFO. + */ + XStrm_GetVacancyFnType GetVacancyFn; /**< GetVaccancyFn is the routine + * the streamer uses to get the + * vacancy from the FIFO. + */ +} XStrm_TxFifoStreamer; + +/*****************************************************************************/ +/* +* +* XStrm_TxVacancy returns the number of unused 32-bit words available (vacancy) +* between the streamer, specified by InstancePtr, and the FIFO this +* streamer is using. +* +* @param InstancePtr references the streamer on which to operate. +* +* @return XStrm_TxVacancy returns the vacancy count in number of 32 bit words. +* +* @note +* +* C Signature: u32 XStrm_TxVacancy(XStrm_TxFifoStreamer *InstancePtr) +* +* The amount of bytes in the holding buffer (rounded up to whole 32-bit words) +* is subtracted from the vacancy value of FIFO this streamer is using. This is +* to ensure the caller can write the number words given in the return value and +* not overflow the FIFO. +* +******************************************************************************/ +#define XStrm_TxVacancy(InstancePtr) \ + (((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \ + (((InstancePtr)->TailIndex + 3) / 4)) + +/*****************************************************************************/ +/* +* +* XStrm_RxOccupancy returns the number of 32-bit words available (occupancy) to +* be read from the streamer, specified by InstancePtr, and FIFO this +* steamer is using. +* +* @param InstancePtr references the streamer on which to operate. +* +* @return XStrm_RxOccupancy returns the occupancy count in number of 32 bit +* words. +* +* @note +* +* C Signature: u32 XStrm_RxOccupancy(XStrm_RxFifoStreamer *InstancePtr) +* +* The amount of bytes in the holding buffer (rounded up to whole 32-bit words) +* is added to the occupancy value of FIFO this streamer is using. This is to +* ensure the caller will get a little more accurate occupancy value. +* +******************************************************************************/ +#ifdef DEBUG +extern u32 _xstrm_ro_value; +extern u32 _xstrm_buffered; +#define XStrm_RxOccupancy(InstancePtr) \ + (_xstrm_ro_value = ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)), \ + xdbg_printf(XDBG_DEBUG_FIFO_RX, "reg: %d; frmbytecnt: %d\n", \ + _xstrm_ro_value, (InstancePtr)->FrmByteCnt), \ + (((InstancePtr)->FrmByteCnt) ? \ + _xstrm_buffered = ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \ + 0), \ + xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered_bytes: %d\n", _xstrm_buffered), \ + xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered (rounded): %d\n", _xstrm_buffered), \ + (_xstrm_ro_value + _xstrm_buffered)) +#else +#define XStrm_RxOccupancy(InstancePtr) \ + ( \ + ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \ + ( \ + ((InstancePtr)->FrmByteCnt) ? \ + ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \ + 0 \ + ) \ + ) +#endif + +/****************************************************************************/ +/* +* +* XStrm_IsRxInternalEmpty returns true if the streamer, specified by +* InstancePtr, is not holding any bytes in it's internal buffers. Note +* that this routine does not reflect information about the state of the +* FIFO used by this streamer. +* +* @param InstancePtr references the streamer on which to operate. +* +* @return XStrm_IsRxInternalEmpty returns TRUE when the streamer is not +* holding any bytes in it's internal buffers. Otherwise, +* XStrm_IsRxInternalEmpty returns FALSE. +* +* @note +* C-style signature: +* int XStrm_IsRxInternalEmpty(XStrm_RxFifoStreamer *InstancePtr) +* +*****************************************************************************/ +#define XStrm_IsRxInternalEmpty(InstancePtr) \ + (((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE) + +void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr, + unsigned FifoWidth, void *FifoInstance, + XStrm_XferFnType ReadFn, + XStrm_GetLenFnType GetLenFn, + XStrm_GetOccupancyFnType GetOccupancyFn); + +void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr, + unsigned FifoWidth, void *FifoInstance, + XStrm_XferFnType WriteFn, + XStrm_SetLenFnType SetLenFn, + XStrm_GetVacancyFnType GetVacancyFn); + +void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes); +void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr, + unsigned bytes); + +u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr); +void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr, + unsigned bytes); + +#ifdef __cplusplus +} +#endif +#endif /* XSTREAMER_H end of preprocessor protection symbols */