From 86bd3b7ed3a5037e1600a0d1cc8956ad29ddd482 Mon Sep 17 00:00:00 2001 From: Kedareswara rao Appana Date: Thu, 21 Aug 2014 15:45:45 +0530 Subject: [PATCH] doxygen: Update doxygen for the drivers to include .h files in documentation. This patch updates the doxygen for the drivers llfifo,mbox,mig_7series,mutex,nandps to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana --- .../llfifo/doc/html/api/annotated.html | 43 +- .../drivers/llfifo/doc/html/api/classes.html | 39 + .../drivers/llfifo/doc/html/api/files.html | 49 +- .../llfifo/doc/html/api/functions.html | 141 +- .../llfifo/doc/html/api/functions_vars.html | 141 +- .../drivers/llfifo/doc/html/api/globals.html | 413 +- .../llfifo/doc/html/api/globals_defs.html | 325 +- .../llfifo/doc/html/api/globals_func.html | 134 +- .../llfifo/doc/html/api/globals_type.html | 61 + .../llfifo/doc/html/api/globals_vars.html | 49 + .../drivers/llfifo/doc/html/api/index.html | 114 +- .../html/api/struct_x_ll_fifo-members.html | 55 +- .../llfifo/doc/html/api/struct_x_ll_fifo.html | 255 +- .../struct_x_ll_fifo___config-members.html | 40 + .../html/api/struct_x_ll_fifo___config.html | 106 + ...uct_x_strm___rx_fifo_streamer-members.html | 58 +- .../api/struct_x_strm___rx_fifo_streamer.html | 301 +- ...uct_x_strm___tx_fifo_streamer-members.html | 56 +- .../api/struct_x_strm___tx_fifo_streamer.html | 269 +- .../drivers/llfifo/doc/html/api/tabs.css | 15 +- ..._x_strm___aligned_buffer_type-members.html | 38 + .../union_x_strm___aligned_buffer_type.html | 74 + .../llfifo/doc/html/api/xdebug_8h.html | 77 + .../llfifo/doc/html/api/xllfifo_8c.html | 419 +- .../llfifo/doc/html/api/xllfifo_8h.html | 940 +++ .../llfifo/doc/html/api/xllfifo__g_8c.html | 64 + .../llfifo/doc/html/api/xllfifo__hw_8h.html | 1369 ++-- .../doc/html/api/xllfifo__sinit_8c.html | 69 + .../llfifo/doc/html/api/xstreamer_8c.html | 253 + .../llfifo/doc/html/api/xstreamer_8h.html | 434 + .../drivers/mbox/doc/html/api/annotated.html | 41 +- .../drivers/mbox/doc/html/api/classes.html | 39 + .../drivers/mbox/doc/html/api/files.html | 44 +- .../drivers/mbox/doc/html/api/functions.html | 83 +- .../mbox/doc/html/api/functions_vars.html | 83 +- .../drivers/mbox/doc/html/api/globals.html | 269 +- .../mbox/doc/html/api/globals_defs.html | 172 +- .../mbox/doc/html/api/globals_func.html | 142 +- .../mbox/doc/html/api/globals_vars.html | 49 + .../drivers/mbox/doc/html/api/index.html | 74 +- .../doc/html/api/struct_x_mbox-members.html | 47 +- .../mbox/doc/html/api/struct_x_mbox.html | 127 +- .../api/struct_x_mbox___config-members.html | 53 +- .../doc/html/api/struct_x_mbox___config.html | 223 +- .../drivers/mbox/doc/html/api/tabs.css | 15 +- .../drivers/mbox/doc/html/api/xmbox_8c.html | 1018 +-- .../drivers/mbox/doc/html/api/xmbox_8h.html | 664 ++ .../mbox/doc/html/api/xmbox__g_8c.html | 89 +- .../mbox/doc/html/api/xmbox__hw_8h.html | 1101 ++- .../mbox/doc/html/api/xmbox__sinit_8c.html | 97 +- .../mig_7series/doc/html/api/files.html | 36 + .../mig_7series/doc/html/api/index.html | 30 +- .../drivers/mig_7series/doc/html/api/tabs.css | 15 +- .../doc/html/api/xmig__7series_8h.html | 36 + .../drivers/mutex/doc/html/api/annotated.html | 41 +- .../drivers/mutex/doc/html/api/classes.html | 39 + .../drivers/mutex/doc/html/api/files.html | 44 +- .../drivers/mutex/doc/html/api/functions.html | 79 +- .../mutex/doc/html/api/functions_vars.html | 79 +- .../drivers/mutex/doc/html/api/globals.html | 168 +- .../mutex/doc/html/api/globals_defs.html | 98 +- .../mutex/doc/html/api/globals_func.html | 107 +- .../mutex/doc/html/api/globals_vars.html | 49 + .../drivers/mutex/doc/html/api/index.html | 65 +- .../doc/html/api/struct_x_mutex-members.html | 47 +- .../mutex/doc/html/api/struct_x_mutex.html | 127 +- .../api/struct_x_mutex___config-members.html | 51 +- .../doc/html/api/struct_x_mutex___config.html | 191 +- .../drivers/mutex/doc/html/api/tabs.css | 15 +- .../drivers/mutex/doc/html/api/xmutex_8c.html | 637 +- .../drivers/mutex/doc/html/api/xmutex_8h.html | 484 ++ .../mutex/doc/html/api/xmutex__g_8c.html | 86 +- .../mutex/doc/html/api/xmutex__hw_8h.html | 419 +- .../doc/html/api/xmutex__selftest_8c.html | 124 +- .../mutex/doc/html/api/xmutex__sinit_8c.html | 97 +- .../nandps/doc/html/api/annotated.html | 41 +- .../drivers/nandps/doc/html/api/classes.html | 40 + .../drivers/nandps/doc/html/api/doxygen.png | Bin 1280 -> 0 bytes .../doc/html/api/driver_api_doxygen.css | 334 - .../drivers/nandps/doc/html/api/files.html | 44 +- .../nandps/doc/html/api/functions.html | 592 +- .../nandps/doc/html/api/functions_vars.html | 590 +- .../drivers/nandps/doc/html/api/globals.html | 101 +- .../nandps/doc/html/api/globals_0x63.html | 102 +- .../nandps/doc/html/api/globals_0x67.html | 98 +- .../nandps/doc/html/api/globals_0x6e.html | 106 +- .../nandps/doc/html/api/globals_0x6f.html | 287 +- .../nandps/doc/html/api/globals_0x70.html | 102 +- .../nandps/doc/html/api/globals_0x72.html | 122 +- .../nandps/doc/html/api/globals_0x73.html | 98 +- .../nandps/doc/html/api/globals_0x78.html | 1150 ++- .../nandps/doc/html/api/globals_defs.html | 127 +- .../doc/html/api/globals_defs_0x6f.html | 189 + .../doc/html/api/globals_defs_0x78.html | 1041 ++- .../nandps/doc/html/api/globals_enum.html | 71 +- .../nandps/doc/html/api/globals_eval.html | 132 +- .../nandps/doc/html/api/globals_func.html | 155 +- .../nandps/doc/html/api/globals_type.html | 51 + .../nandps/doc/html/api/globals_vars.html | 86 +- .../drivers/nandps/doc/html/api/index.html | 92 +- .../api/struct____attribute____-members.html | 151 +- .../doc/html/api/struct____attribute____.html | 1791 ++-- ...x_nand_ps___bad_block_pattern-members.html | 51 +- .../struct_x_nand_ps___bad_block_pattern.html | 191 +- .../struct_x_nand_ps___bbt_desc-members.html | 59 +- .../html/api/struct_x_nand_ps___bbt_desc.html | 319 +- ...ct_x_nand_ps___command_format-members.html | 51 +- .../struct_x_nand_ps___command_format.html | 191 +- .../struct_x_nand_ps___config-members.html | 51 +- .../html/api/struct_x_nand_ps___config.html | 191 +- ...struct_x_nand_ps___ecc_config-members.html | 53 +- .../api/struct_x_nand_ps___ecc_config.html | 223 +- .../struct_x_nand_ps___features-members.html | 45 +- .../html/api/struct_x_nand_ps___features.html | 88 +- .../struct_x_nand_ps___geometry-members.html | 67 +- .../html/api/struct_x_nand_ps___geometry.html | 447 +- .../api/struct_x_nand_ps_tag-members.html | 79 +- .../doc/html/api/struct_x_nand_ps_tag.html | 639 +- .../drivers/nandps/doc/html/api/tabs.css | 15 +- .../nandps/doc/html/api/xnandps_8c.html | 1159 ++- .../nandps/doc/html/api/xnandps_8h.html | 1286 +++ .../nandps/doc/html/api/xnandps__bbm_8c.html | 376 +- .../nandps/doc/html/api/xnandps__bbm_8h.html | 1003 +-- .../nandps/doc/html/api/xnandps__g_8c.html | 102 +- .../nandps/doc/html/api/xnandps__hw_8h.html | 7194 +++++++---------- .../nandps/doc/html/api/xnandps__onfi_8c.html | 260 +- .../nandps/doc/html/api/xnandps__onfi_8h.html | 1588 ++-- .../doc/html/api/xnandps__sinit_8c.html | 159 +- 128 files changed, 21094 insertions(+), 16481 deletions(-) create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/classes.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_type.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_vars.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config-members.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type-members.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xdebug_8h.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8h.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__g_8c.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__sinit_8c.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8c.html create mode 100755 XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8h.html create mode 100755 XilinxProcessorIPLib/drivers/mbox/doc/html/api/classes.html create mode 100755 XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_vars.html create mode 100755 XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8h.html create mode 100755 XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/files.html create mode 100755 XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/xmig__7series_8h.html create mode 100755 XilinxProcessorIPLib/drivers/mutex/doc/html/api/classes.html create mode 100755 XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_vars.html create mode 100755 XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8h.html create mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/classes.html delete mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/doxygen.png delete mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/driver_api_doxygen.css create mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x6f.html create mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_type.html create mode 100755 XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8h.html diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/annotated.html index 78e299e4..f1d120af 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/annotated.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/annotated.html @@ -2,28 +2,41 @@ - Class List + Xilinx Driver llfifo v4_0: Class List - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
+ + + +

Class List

Here are the classes, structs, unions and interfaces with brief descriptions: + +
XLlFifo
XLlFifo_Config
XStrm_AlignedBufferType
XStrm_RxFifoStreamer
XStrm_TxFifoStreamer
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/classes.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/classes.html new file mode 100755 index 00000000..750243af --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/classes.html @@ -0,0 +1,39 @@ + + + + + Xilinx Driver llfifo v4_0: Alphabetical List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

Class Index

X
+ +
  X  
+		XLlFifo_Config   XStrm_AlignedBufferType   XStrm_RxFifoStreamer   XStrm_TxFifoStreamer   
XLlFifo   
X
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/files.html index 31e57376..dcb43aea 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/files.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/files.html @@ -2,27 +2,44 @@ - File Index + Xilinx Driver llfifo v4_0: File Index - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

File List

Here is a list of all documented files with brief descriptions: + + + +
+

File List

Here is a list of all files with brief descriptions:
+ + + + + +
xdebug.h
xllfifo.c
xllfifo.h
xllfifo_g.c
xllfifo_hw.h
xllfifo_sinit.c
xstreamer.c
xstreamer.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions.html index adbf10dc..1f4a29ff 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions.html @@ -2,50 +2,111 @@ - Class Members + Xilinx Driver llfifo v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + -Here is a list of all documented class members with links to the class documentation for each member: -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions_vars.html index b6419bda..ff96f034 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions_vars.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/functions_vars.html @@ -2,50 +2,111 @@ - Class Members - Variables + Xilinx Driver llfifo v4_0: Class Members - Variables - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + -  -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals.html index 85b241a5..a373dfe5 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals.html @@ -2,78 +2,355 @@ - Class Members + Xilinx Driver llfifo v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- -
-
-
    -
  • x
    • -
-
-

-Here is a list of all documented file members with links to the documentation: -

-

- x -

+ +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_defs.html index 9034e866..829bfbb9 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_defs.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_defs.html @@ -2,76 +2,271 @@ - Class Members + Xilinx Driver llfifo v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- -
-
-
    -
  • x
    • -
-
-

+ +

+
  -

-

- x -

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_func.html index b1c80c88..55b3961e 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_func.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_func.html @@ -2,36 +2,120 @@ - Class Members + Xilinx Driver llfifo v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + +
  -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_type.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_type.html new file mode 100755 index 00000000..8e0a9347 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_type.html @@ -0,0 +1,61 @@ + + + + + Xilinx Driver llfifo v4_0: Class Members + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+  +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_vars.html new file mode 100755 index 00000000..7e9d8fed --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/globals_vars.html @@ -0,0 +1,49 @@ + + + + + Xilinx Driver llfifo v4_0: Class Members + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+  +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/index.html index c4cb6051..3a63fd98 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/index.html @@ -2,83 +2,84 @@ - llfifo v4_0 + Xilinx Driver llfifo v4_0: llfifo v4_0 - +

Xilinx Processor IP Library

Software Drivers
- -
-
-

llfifo v4_0

-

-The Xilinx Dual Channel Fifo driver component. This driver supports the Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.

-For a full description of the bridge features, please see the HW spec. This driver supports the following features:

    -
  • Memory mapped access to host interface registers
  • API for polled frame transfers
  • API for interrupt driven frame transfers
  • Virtual memory support
  • Full duplex operation
-

+ + +

+
+

llfifo v4_0

The Xilinx Dual Channel Fifo driver component. This driver supports the Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.

+

For a full description of the bridge features, please see the HW spec. This driver supports the following features:

+
    +
  • Memory mapped access to host interface registers
    • +
  • API for polled frame transfers
    • +
  • API for interrupt driven frame transfers
    • +
  • Virtual memory support
    • +
  • Full duplex operation
    • +

Driver Description

-

-This driver enables higher layer software to access the XPS_llFifo core using any alignment in the data buffers.

-This driver supports send and receive channels in the same instance structure in the same fashion as the hardware core.

+

This driver enables higher layer software to access the XPS_llFifo core using any alignment in the data buffers.

+

This driver supports send and receive channels in the same instance structure in the same fashion as the hardware core.

Initialization

-

-An instance of this driver is initialized using a call to Initialize().

+

An instance of this driver is initialized using a call to Initialize().

Usage

-

-It is fairly simple to use the API provided by this FIFO driver. The only somewhat tricky part is that the calling code must correctly call a couple routines in the right sequence for receive and transmit.

-This sequence is described here. Check the routine functional descriptions for information on how to use a specific API routine.

+

It is fairly simple to use the API provided by this FIFO driver. The only somewhat tricky part is that the calling code must correctly call a couple routines in the right sequence for receive and transmit.

+

This sequence is described here. Check the routine functional descriptions for information on how to use a specific API routine.

Receive

-

-A frame is received by using the following sequence:
- 1) call XLlFifo_RxOccupancy() to check the occupancy count
- 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame
- 3) call XLlFifo_Read() one or more times to read the number of bytes reported by XLlFifo_RxGetLen().
-

-For example: 

- 	while (XLlFifo_RxOccupancy(&RxInstance)) {
- 		frame_len = XLlFifo_RxGetLen(&RxInstance);
+
A frame is received by using the following sequence:

+ 1) call XLlFifo_RxOccupancy() to check the occupancy count

+ 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame

+ 3) call XLlFifo_Read() one or more times to read the number of bytes reported by XLlFifo_RxGetLen().

+

+
For example: 

+
+	while (XLlFifo_RxOccupancy(&RxInstance)) {
+		frame_len = XLlFifo_RxGetLen(&RxInstance);
 		while (frame_len) {
  			unsigned bytes = min(sizeof(buffer), frame_len);
- 			XLlFifo_Read(&RxInstance, buffer, bytes);
+			XLlFifo_Read(&RxInstance, buffer, bytes);
  			// ********
  			// do something with buffer here
  			// ********
  			frame_len -= bytes;
 		}
  	}
- 

-This FIFO hardware core does not support a sequence where the calling code calls RxGetLen() twice in a row and then receive the data for two frames. Each frame must be read in by calling RxGetLen() just prior to reading the data.

+

This FIFO hardware core does not support a sequence where the calling code calls RxGetLen() twice in a row and then receive the data for two frames. Each frame must be read in by calling RxGetLen() just prior to reading the data.

Transmit

-

-A frame is transmittted by using the following sequence:
- 1) call XLlFifo_Write() one or more times to write all the of bytes in the next frame.
- 2) call XLlFifo_TxSetLen() to begin the transmission of frame just written.
-

-For example: 

+
A frame is transmittted by using the following sequence:

+ 1) call XLlFifo_Write() one or more times to write all the of bytes in the next frame.

+ 2) call XLlFifo_TxSetLen() to begin the transmission of frame just written.

+

+
For example: 

+
  	frame_left = frame_len;
  	while (frame_left) {
  		unsigned bytes = min(sizeof(buffer), frame_left);
- 		XLlFifo_Write(&TxInstance, buffer, bytes);
+		XLlFifo_Write(&TxInstance, buffer, bytes);
  		// ********
  		// do something here to refill buffer
  		// ********
  		frame_left -= bytes;
  	}
- 	XLlFifo_TxSetLen(&RxInstance, frame_len);
- 

-This FIFO hardware core does not support a sequence where the calling code writes the data for two frames and then calls TxSetLen() twice in a row. Each frame must be written by writting the data for one frame and then calling TxSetLen().

+	XLlFifo_TxSetLen(&RxInstance, frame_len);
+

This FIFO hardware core does not support a sequence where the calling code writes the data for two frames and then calls TxSetLen() twice in a row. Each frame must be written by writting the data for one frame and then calling TxSetLen().

Interrupts

-

-This driver does not handle interrupts from the FIFO hardware. The software layer above may make use of the interrupts by setting up its own handlers for the interrupts.

+

This driver does not handle interrupts from the FIFO hardware. The software layer above may make use of the interrupts by setting up its own handlers for the interrupts.

- MODIFICATION HISTORY:

-

 Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
 Ver   Who  Date     Changes
  ----- ---- -------- -------------------------------------------------------
  1.00a jvb  10/12/06 First release
  1.01a sdm  08/22/08 Removed support for static interrupt handlers from the
@@ -94,15 +95,14 @@ This driver does not handle interrupts from the FIFO hardware. The software laye
 		       in streamer are empty. Earlier implementation using
 		       HeadIndex was not very clear and could give improper
 		       results for some cases.
-		       Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
+		       Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
 		       These changes are done to fix the CR 604650.
  2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
 		         defines for the new registers, and XLLF_INT_TFPF_MASK,
 		         XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
 		         XLLF_INT_RFPE_MASK for the new version of the
-		         AXI4-Stream FIFO core (v2.01a and later)

-

 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
- 		      In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
+		         AXI4-Stream FIFO core (v2.01a and later)
 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
+		      In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
  		      In XLlfifo.h file updated XLlfifo structure for 
  		      Axi4BaseAddress and for Datainterface type provided 
 		      polling and interrupt examples. XLlfifo_IsRxDone Macro 
@@ -110,5 +110,9 @@ This driver does not handle interrupts from the FIFO hardware. The software laye
 		      Added Static initialzation for the driver. 
 		      XLlFifo_Initialize is still used to make the driver
 		      backward compatible.
- 4.0   adk  19/12/13 Updated as per the New Tcl API's

-
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + 4.0 adk 19/12/13 Updated as per the New Tcl API's
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo-members.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo-members.html index 2827f317..28bdbe98 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo-members.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo-members.html @@ -2,30 +2,41 @@ - Member List + Xilinx Driver llfifo v4_0: Member List - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XLlFifo Member List

This is the complete list of members for XLlFifo, including all inherited members.

- - - - - - -
Axi4BaseAddressXLlFifo
BaseAddressXLlFifo
DatainterfaceXLlFifo
IsReadyXLlFifo
RxStreamerXLlFifo
TxStreamerXLlFifo
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

+
+

XLlFifo Member List

This is the complete list of members for XLlFifo, including all inherited members. + + + + + + +
Axi4BaseAddressXLlFifo
BaseAddressXLlFifo
DatainterfaceXLlFifo
IsReadyXLlFifo
RxStreamerXLlFifo
TxStreamerXLlFifo
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo.html index 2610b39d..92db724b 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo.html @@ -2,185 +2,138 @@ - XLlFifo Struct Reference + Xilinx Driver llfifo v4_0: XLlFifo Struct Reference - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XLlFifo Struct Reference

#include <xllfifo.h> -

-List of all members.

Detailed Description

-This typedef defines a run-time instance of an XLlFifo device. -

+ + +

+
+

XLlFifo Struct Reference

+

#include <xllfifo.h>

+ +

List of all members.

- - - - - - - - - - - - - - + + + + + + +

Public Attributes

u32 BaseAddress
u32 IsReady
u32 Axi4BaseAddress
u32 Datainterface
XStrm_RxFifoStreamer RxStreamer
XStrm_TxFifoStreamer TxStreamer

Public Attributes

u32 BaseAddress
u32 IsReady
u32 Axi4BaseAddress
u32 Datainterface
XStrm_RxFifoStreamer RxStreamer
XStrm_TxFifoStreamer TxStreamer
-

Member Data Documentation

-

- - - - -
- +

Detailed Description

+

This typedef defines a run-time instance of an XLlFifo device.

+

Member Data Documentation

+ +
+
+
- +
u32 XLlFifo::Axi4BaseAddress u32 XLlFifo::Axi4BaseAddress
-
- - - - - -
-   - + +
+

BaseAddress if the FIFO Data interface is AXI4 this address should use for FIFO access

-

-BaseAddress if the FIFO Data interface is AXI4 this address should use for FIFO access

-

- - - - -
- + + + +
+
+
- +
u32 XLlFifo::BaseAddress u32 XLlFifo::BaseAddress
-
- - - - - -
-   - + +
+

BaseAddress is the physical base address of the device's registers

-

-BaseAddress is the physical base address of the device's registers

-

- - - - -
- + + + +
+
+
- +
u32 XLlFifo::Datainterface u32 XLlFifo::Datainterface
-
- - - - - -
-   - + +
+

Data interface of the FIFO. This value is zero if the Datainterface is AXI4-lite.

-

-Data interface of the FIFO. This value is zero if the Datainterface is AXI4-lite.

-

- - - - -
- + + + +
+
+
- +
u32 XLlFifo::IsReady u32 XLlFifo::IsReady
-
- - - - - -
-   - + +
+

IsReady is non-zero if the driver instance has been initialized.

-

-IsReady is non-zero if the driver instance has been initialized.

-

- - - - -
- + + + +
+
+
- +
XStrm_RxFifoStreamer XLlFifo::RxStreamer XStrm_RxFifoStreamer XLlFifo::RxStreamer
-
- - - - - -
-   - + +
+

RxStreamer is the byte streamer instance for the receive channel.

-

-RxStreamer is the byte streamer instance for the receive channel.

-

- - - - -
- + + + +
+
+
- +
XStrm_TxFifoStreamer XLlFifo::TxStreamer XStrm_TxFifoStreamer XLlFifo::TxStreamer
-
- - - - - -
-   - + +
+

TxStreamer is the byte streamer instance for the transmit channel.

+ +
+ +
The documentation for this struct was generated from the following file: + +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + -

-TxStreamer is the byte streamer instance for the transmit channel.

-

The documentation for this struct was generated from the following file:
    -
  • xllfifo.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config-members.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config-members.html new file mode 100755 index 00000000..1fd8e83b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config-members.html @@ -0,0 +1,40 @@ + + + + + Xilinx Driver llfifo v4_0: Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

XLlFifo_Config Member List

This is the complete list of members for XLlFifo_Config, including all inherited members. + + + + +
Axi4BaseAddressXLlFifo_Config
BaseAddressXLlFifo_Config
DatainterfaceXLlFifo_Config
DeviceIdXLlFifo_Config
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config.html new file mode 100755 index 00000000..778e3d0e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_ll_fifo___config.html @@ -0,0 +1,106 @@ + + + + + Xilinx Driver llfifo v4_0: XLlFifo_Config Struct Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

XLlFifo_Config Struct Reference

+

#include <xllfifo.h>

+ +

List of all members.

+ + + + + + +

Public Attributes

u32 DeviceId
u32 BaseAddress
u32 Axi4BaseAddress
u32 Datainterface
+

Member Data Documentation

+ +
+
+ + + + +
u32 XLlFifo_Config::Axi4BaseAddress
+
+
+

Axi4 interface Base address

+ +
+
+ +
+
+ + + + +
u32 XLlFifo_Config::BaseAddress
+
+
+

Base Address of the AXI FIFO

+ +
+
+ +
+
+ + + + +
u32 XLlFifo_Config::Datainterface
+
+
+

Type of Datainterface

+ +
+
+ +
+
+ + + + +
u32 XLlFifo_Config::DeviceId
+
+
+

Deviceid of the AXI FIFO

+ +
+
+
The documentation for this struct was generated from the following file: +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer-members.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer-members.html index 254cc72b..cc898f82 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer-members.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer-members.html @@ -2,31 +2,43 @@ - Member List + Xilinx Driver llfifo v4_0: Member List - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XStrm_RxFifoStreamer Member List

This is the complete list of members for XStrm_RxFifoStreamer, including all inherited members.

- - - - - - - -
FifoInstanceXStrm_RxFifoStreamer
FifoWidthXStrm_RxFifoStreamer
FrmByteCntXStrm_RxFifoStreamer
GetLenFnXStrm_RxFifoStreamer
GetOccupancyFnXStrm_RxFifoStreamer
HeadIndexXStrm_RxFifoStreamer
ReadFnXStrm_RxFifoStreamer
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

+
+

XStrm_RxFifoStreamer Member List

This is the complete list of members for XStrm_RxFifoStreamer, including all inherited members. + + + + + + + + +
AlignedBufferXStrm_RxFifoStreamer
FifoInstanceXStrm_RxFifoStreamer
FifoWidthXStrm_RxFifoStreamer
FrmByteCntXStrm_RxFifoStreamer
GetLenFnXStrm_RxFifoStreamer
GetOccupancyFnXStrm_RxFifoStreamer
HeadIndexXStrm_RxFifoStreamer
ReadFnXStrm_RxFifoStreamer
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer.html index 4896ae4e..1281fe59 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___rx_fifo_streamer.html @@ -2,210 +2,167 @@ - XStrm_RxFifoStreamer Struct Reference + Xilinx Driver llfifo v4_0: XStrm_RxFifoStreamer Struct Reference - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XStrm_RxFifoStreamer Struct Reference

#include <xstreamer.h> -

-List of all members.

Detailed Description

-This typedef defines a run-time instance of a receive byte-streamer. -

+ + +

+
+

XStrm_RxFifoStreamer Struct Reference

+

#include <xstreamer.h>

+ +

List of all members.

- - - - - - - - - - - - - - - - + + + + + + + + +

Public Attributes

unsigned HeadIndex
unsigned FifoWidth
unsigned FrmByteCnt
void * FifoInstance
XStrm_XferFnType ReadFn
XStrm_GetLenFnType GetLenFn
XStrm_GetOccupancyFnType GetOccupancyFn

Public Attributes

union XStrm_AlignedBufferType AlignedBuffer
unsigned HeadIndex
unsigned FifoWidth
unsigned FrmByteCnt
void * FifoInstance
XStrm_XferFnType ReadFn
XStrm_GetLenFnType GetLenFn
XStrm_GetOccupancyFnType GetOccupancyFn
-

Member Data Documentation

-

- - - - -
- +

Detailed Description

+

This typedef defines a run-time instance of a receive byte-streamer.

+

Member Data Documentation

+ +
+
+
- +
void* XStrm_RxFifoStreamer::FifoInstance union XStrm_AlignedBufferType XStrm_RxFifoStreamer::AlignedBuffer [write]
-
- - - - - -
-   - + +
-

-FifoInstance is the FIFO driver instance to pass to ReadFn, GetLenFn, and GetOccupancyFn routines.

-

- - - - -
- + + + +
+
+
- +
unsigned XStrm_RxFifoStreamer::FifoWidth void* XStrm_RxFifoStreamer::FifoInstance
-
- - - - - -
-   - + +
+

FifoInstance is the FIFO driver instance to pass to ReadFn, GetLenFn, and GetOccupancyFn routines.

-

-FifoWidth is the FIFO key hole width in bytes.

-

- - - - -
- + + + +
+
+
- +
unsigned XStrm_RxFifoStreamer::FrmByteCnt unsigned XStrm_RxFifoStreamer::FifoWidth
-
- - - - - -
-   - + +
+

FifoWidth is the FIFO key hole width in bytes.

-

-FrmByteCnt is the number of bytes in the next Frame.

-

- - - - -
- + + + +
+
+
- +
XStrm_GetLenFnType XStrm_RxFifoStreamer::GetLenFn unsigned XStrm_RxFifoStreamer::FrmByteCnt
-
- - - - - -
-   - + +
+

FrmByteCnt is the number of bytes in the next Frame.

-

-GetLenFn is the routine the streamer uses to initiate receive operations on the FIFO.

-

- - - - -
- + + + +
+
+
- +
XStrm_GetOccupancyFnType XStrm_RxFifoStreamer::GetOccupancyFn XStrm_GetLenFnType XStrm_RxFifoStreamer::GetLenFn
-
- - - - - -
-   - + +
+

GetLenFn is the routine the streamer uses to initiate receive operations on the FIFO.

-

-GetOccupancyFn is the routine the streamer uses to get the occupancy from the FIFO.

-

- - - - -
- + + + +
+
+
- +
unsigned XStrm_RxFifoStreamer::HeadIndex XStrm_GetOccupancyFnType XStrm_RxFifoStreamer::GetOccupancyFn
-
- - - - - -
-   - + +
+

GetOccupancyFn is the routine the streamer uses to get the occupancy from the FIFO.

-

-HeadIndex is the index to the AlignedBuffer as bytes.

-

- - - - -
- + + + +
+
+
- +
XStrm_XferFnType XStrm_RxFifoStreamer::ReadFn unsigned XStrm_RxFifoStreamer::HeadIndex
-
- - - - - -
-   - + +
+

HeadIndex is the index to the AlignedBuffer as bytes.

+ +
+ + +
+
+ + + + +
XStrm_XferFnType XStrm_RxFifoStreamer::ReadFn
+
+
+

ReadFn is the routine the streamer uses to receive bytes from the Fifo.

+ +
+
+
The documentation for this struct was generated from the following file: + +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + -

-ReadFn is the routine the streamer uses to receive bytes from the Fifo.

-

The documentation for this struct was generated from the following file:
    -
  • xstreamer.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer-members.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer-members.html index 7e7e57b5..58cd9d90 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer-members.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer-members.html @@ -2,30 +2,42 @@ - Member List + Xilinx Driver llfifo v4_0: Member List - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XStrm_TxFifoStreamer Member List

This is the complete list of members for XStrm_TxFifoStreamer, including all inherited members.

- - - - - - -
FifoInstanceXStrm_TxFifoStreamer
FifoWidthXStrm_TxFifoStreamer
GetVacancyFnXStrm_TxFifoStreamer
SetLenFnXStrm_TxFifoStreamer
TailIndexXStrm_TxFifoStreamer
WriteFnXStrm_TxFifoStreamer
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

+
+

XStrm_TxFifoStreamer Member List

This is the complete list of members for XStrm_TxFifoStreamer, including all inherited members. + + + + + + + +
AlignedBufferXStrm_TxFifoStreamer
FifoInstanceXStrm_TxFifoStreamer
FifoWidthXStrm_TxFifoStreamer
GetVacancyFnXStrm_TxFifoStreamer
SetLenFnXStrm_TxFifoStreamer
TailIndexXStrm_TxFifoStreamer
WriteFnXStrm_TxFifoStreamer
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer.html index d28123e7..17a1145c 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/struct_x_strm___tx_fifo_streamer.html @@ -2,185 +2,152 @@ - XStrm_TxFifoStreamer Struct Reference + Xilinx Driver llfifo v4_0: XStrm_TxFifoStreamer Struct Reference - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

XStrm_TxFifoStreamer Struct Reference

#include <xstreamer.h> -

-List of all members.

Detailed Description

-This typedef defines a run-time instance of a transmit byte-streamer. -

+ + +

+
+

XStrm_TxFifoStreamer Struct Reference

+

#include <xstreamer.h>

+ +

List of all members.

- - - - - - - - - - - - - - + + + + + + + +

Public Attributes

unsigned TailIndex
unsigned FifoWidth
void * FifoInstance
XStrm_XferFnType WriteFn
XStrm_SetLenFnType SetLenFn
XStrm_GetVacancyFnType GetVacancyFn

Public Attributes

union XStrm_AlignedBufferType AlignedBuffer
unsigned TailIndex
unsigned FifoWidth
void * FifoInstance
XStrm_XferFnType WriteFn
XStrm_SetLenFnType SetLenFn
XStrm_GetVacancyFnType GetVacancyFn
-

Member Data Documentation

-

- - - - -
- +

Detailed Description

+

This typedef defines a run-time instance of a transmit byte-streamer.

+

Member Data Documentation

+ +
+
+
- +
void* XStrm_TxFifoStreamer::FifoInstance union XStrm_AlignedBufferType XStrm_TxFifoStreamer::AlignedBuffer [write]
-
- - - - - -
-   - + +
-

-FifoInstance is the FIFO driver instance to pass to WriteFn, SetLenFn, and GetVacancyFn routines.

-

- - - - -
- + + + +
+
+
- +
unsigned XStrm_TxFifoStreamer::FifoWidth void* XStrm_TxFifoStreamer::FifoInstance
-
- - - - - -
-   - + +
+

FifoInstance is the FIFO driver instance to pass to WriteFn, SetLenFn, and GetVacancyFn routines.

-

-FifoWidth is the FIFO key hole width in bytes.

-

- - - - -
- + + + +
+
+
- +
XStrm_GetVacancyFnType XStrm_TxFifoStreamer::GetVacancyFn unsigned XStrm_TxFifoStreamer::FifoWidth
-
- - - - - -
-   - + +
+

FifoWidth is the FIFO key hole width in bytes.

-

-GetVaccancyFn is the routine the streamer uses to get the vacancy from the FIFO.

-

- - - - -
- + + + +
+
+
- +
XStrm_SetLenFnType XStrm_TxFifoStreamer::SetLenFn XStrm_GetVacancyFnType XStrm_TxFifoStreamer::GetVacancyFn
-
- - - - - -
-   - + +
+

GetVaccancyFn is the routine the streamer uses to get the vacancy from the FIFO.

-

-SetLenFn is the routine the streamer uses to initiate transmit operations on the FIFO.

-

- - - - -
- + + + +
+
+
- +
unsigned XStrm_TxFifoStreamer::TailIndex XStrm_SetLenFnType XStrm_TxFifoStreamer::SetLenFn
-
- - - - - -
-   - + +
+

SetLenFn is the routine the streamer uses to initiate transmit operations on the FIFO.

-

-TailIndex is the index to the AlignedBuffer as bytes

-

- - - - -
- + + + +
+
+
- +
XStrm_XferFnType XStrm_TxFifoStreamer::WriteFn unsigned XStrm_TxFifoStreamer::TailIndex
-
- - - - - -
-   - + +
+

TailIndex is the index to the AlignedBuffer as bytes

+ +
+ + +
+
+ + + + +
XStrm_XferFnType XStrm_TxFifoStreamer::WriteFn
+
+
+

WriteFn is the routine the streamer uses to transmit bytes to the Fifo.

+ +
+
+
The documentation for this struct was generated from the following file: + +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + -

-WriteFn is the routine the streamer uses to transmit bytes to the Fifo.

-

The documentation for this struct was generated from the following file:
    -
  • xstreamer.h
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/tabs.css b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/tabs.css index a61552a6..a4441634 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/tabs.css +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/tabs.css @@ -32,7 +32,7 @@ DIV.tabs A float : left; background : url("tab_r.gif") no-repeat right top; border-bottom : 1px solid #84B0C7; - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -57,7 +57,7 @@ DIV.tabs SPAN white-space : nowrap; } -DIV.tabs INPUT +DIV.tabs #MSearchBox { float : right; display : inline; @@ -66,7 +66,7 @@ DIV.tabs INPUT DIV.tabs TD { - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -82,21 +82,24 @@ DIV.tabs A:hover SPAN background-position: 0% -150px; } -DIV.tabs LI#current A +DIV.tabs LI.current A { background-position: 100% -150px; border-width : 0px; } -DIV.tabs LI#current SPAN +DIV.tabs LI.current SPAN { background-position: 0% -150px; padding-bottom : 6px; } -DIV.nav +DIV.navpath { background : none; border : none; border-bottom : 1px solid #84B0C7; + text-align : center; + margin : 2px; + padding : 2px; } diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type-members.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type-members.html new file mode 100755 index 00000000..838a7e50 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type-members.html @@ -0,0 +1,38 @@ + + + + + Xilinx Driver llfifo v4_0: Member List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

XStrm_AlignedBufferType Member List

This is the complete list of members for XStrm_AlignedBufferType, including all inherited members. + + +
_wordsXStrm_AlignedBufferType
bytesXStrm_AlignedBufferType
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type.html new file mode 100755 index 00000000..6a0ebb69 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/union_x_strm___aligned_buffer_type.html @@ -0,0 +1,74 @@ + + + + + Xilinx Driver llfifo v4_0: XStrm_AlignedBufferType Union Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

XStrm_AlignedBufferType Union Reference

+

#include <xstreamer.h>

+ +

List of all members.

+ + + + +

Public Attributes

u32 _words [LARGEST_FIFO_KEYHOLE_SIZE_WORDS]
char bytes [LARGEST_FIFO_KEYHOLE_SIZE_WORDS *4]
+

Member Data Documentation

+ +
+
+ + + + +
u32 XStrm_AlignedBufferType::_words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS]
+
+
+ +
+
+ +
+
+ + + + +
char XStrm_AlignedBufferType::bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS *4]
+
+
+ +
+
+
The documentation for this union was generated from the following file: +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xdebug_8h.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xdebug_8h.html new file mode 100755 index 00000000..9dc57a17 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xdebug_8h.html @@ -0,0 +1,77 @@ + + + + + Xilinx Driver llfifo v4_0: xdebug.h File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xdebug.h File Reference

+ + + +

Defines

#define xdbg_stmnt(x)
#define xdbg_printf(...)
+

Define Documentation

+ +
+
+ + + + + + + + + +
#define xdbg_printf( ...  ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + +
#define xdbg_stmnt(x  ) 
+
+
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8c.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8c.html index 1ef7280c..68501196 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8c.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8c.html @@ -2,30 +2,53 @@ - xllfifo.c File Reference + Xilinx Driver llfifo v4_0: xllfifo.c File Reference - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

xllfifo.c File Reference

Detailed Description

-The Xilinx local link FIFO driver component. This driver supports the Xilinx xps_ll_fifo core.

+ + +

+
+

xllfifo.c File Reference

#include "xstatus.h"
+#include "xllfifo.h"
+#include "xil_assert.h"
+ + + + + + + + + + + + + + +

Defines

#define FIFO_WIDTH_BYTES   4

Functions

 xdbg_stmnt (u32 _xllfifo_rr_value;)
u32 XLlFifo_iRxGetLen (XLlFifo *InstancePtr)
int XLlFifo_iRead_Aligned (XLlFifo *InstancePtr, void *BufPtr, unsigned WordCount)
u32 XLlFifo_iTxVacancy (XLlFifo *InstancePtr)
void XLlFifo_iTxSetLen (XLlFifo *InstancePtr, u32 Bytes)
int XLlFifo_iWrite_Aligned (XLlFifo *InstancePtr, void *BufPtr, unsigned WordCount)
int XLlFifo_CfgInitialize (XLlFifo *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)
u32 XLlFifo_RxGetWord (XLlFifo *InstancePtr)
void XLlFifo_TxPutWord (XLlFifo *InstancePtr, u32 Word)
void XLlFifo_Initialize (XLlFifo *InstancePtr, u32 BaseAddress)
+

Detailed Description

+

The Xilinx local link FIFO driver component. This driver supports the Xilinx xps_ll_fifo core.

- MODIFICATION HISTORY:

-

 Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
 Ver   Who  Date     Changes
  ----- ---- -------- -------------------------------------------------------
  1.00a jvb  10/13/06 First release
  1.00a xd   12/17/07 Added type casting to fix CR #456850
@@ -37,115 +60,295 @@ The Xilinx local link FIFO driver component. This driver supports the Xilinx xps
  		        XLlFifo_RxGetWord, XLlFifo_TxPutword inorder to 
  		        handle AXI4 Datainterface. Added Config 
  		        initialization for the driver.
-
-

-#include "xstatus.h"
-#include "xllfifo.h"
-#include "xil_assert.h"
- - - - - - - -

Functions

int XLlFifo_CfgInitialize (XLlFifo *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)
void XLlFifo_Initialize (XLlFifo *InstancePtr, u32 BaseAddress)
-

Function Documentation

-

- - - - -
- +

Define Documentation

+ +
+
+
- - - - - - - - - - - - - - - - - - - - - +
int XLlFifo_CfgInitialize ( XLlFifo *  InstancePtr,
XLlFifo_Config *  Config,
u32  EffectiveAddress
) #define FIFO_WIDTH_BYTES   4
-
- - - - - -
-   - + +
-

-XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

-

Parameters:
+
+ +

Function Documentation

+ +
+
+ + + + + + + + + +
xdbg_stmnt (u32 _xllfifo_rr_value;  ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int XLlFifo_CfgInitialize (XLlFifo *  InstancePtr,
XLlFifo_Config *  Config,
u32  EffectiveAddress 
)
+
+
+

XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

+
Parameters:
InstancePtr is a pointer to the Axi Streaming FIFO instance to be worked on.
CfgPtr references the structure holding the hardware configuration for the Axi Streaming FIFO core to initialize.
EffectiveAddr is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config->BaseAddress for this parameters, passing the physical address instead.
+
-
Returns:
N/A
-
-

- - - - -
- +
Returns:
N/A
+ + + + +
+
+
- - - - + + + + - - - - + + + + - - - + + +
void XLlFifo_Initialize ( XLlFifo *  InstancePtr, void XLlFifo_Initialize (XLlFifo *  InstancePtr,
u32  BaseAddressu32  BaseAddress 
) )
-
- - - - - -
-   - - -

-XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

-

Parameters:
+ +
+

XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

+
Parameters:
InstancePtr references the memory instance to be associated with the FIFO device upon initialization.
BaseAddress is the processor address used to access the base address of the Fifo device.
+
-
Returns:
N/A
-
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

Returns:
N/A
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int XLlFifo_iRead_Aligned (XLlFifo *  InstancePtr,
void *  BufPtr,
unsigned  WordCount 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_iRxGetLen (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XLlFifo_iTxSetLen (XLlFifo *  InstancePtr,
u32  Bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_iTxVacancy (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int XLlFifo_iWrite_Aligned (XLlFifo *  InstancePtr,
void *  BufPtr,
unsigned  WordCount 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_RxGetWord (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XLlFifo_TxPutWord (XLlFifo *  InstancePtr,
u32  Word 
)
+
+
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8h.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8h.html new file mode 100755 index 00000000..6da1d974 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo_8h.html @@ -0,0 +1,940 @@ + + + + + Xilinx Driver llfifo v4_0: xllfifo.h File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xllfifo.h File Reference

#include "xstreamer.h"
+#include "xllfifo_hw.h"
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Classes

struct  XLlFifo
struct  XLlFifo_Config

Defines

#define XLLFIFO_H
#define XLlFifo_Reset(InstancePtr)
#define XLlFifo_Status(InstancePtr)   XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
#define XLlFifo_IntEnable(InstancePtr, Mask)
#define XLlFifo_IntDisable(InstancePtr, Mask)
#define XLlFifo_IntPending(InstancePtr)
#define XLlFifo_IntClear(InstancePtr, Mask)
#define XLlFifo_RxReset(InstancePtr)
#define XLlFifo_IsRxEmpty(InstancePtr)
#define XLlFifo_RxOccupancy(InstancePtr)   XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
#define XLlFifo_RxGetLen(InstancePtr)   XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
#define XLlFifo_Read(InstancePtr, BufPtr, Bytes)   XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
#define XLlFifo_TxReset(InstancePtr)
#define XLlFifo_IsTxDone(InstancePtr)
#define XLlFifo_IsRxDone(InstancePtr)
#define XLlFifo_TxVacancy(InstancePtr)   XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
#define XLlFifo_TxSetLen(InstancePtr, Bytes)   XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
#define XLlFifo_Write(InstancePtr, BufPtr, Bytes)   XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
#define XLlFifo_WriteTdr(InstancePtr, Tdest)
#define XLlFifo_ReadRdr(InstancePtr)   XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)

Functions

int XLlFifo_CfgInitialize (XLlFifo *InstancePtr, XLlFifo_Config *Config, u32 EffectiveAddress)
void XLlFifo_Initialize (XLlFifo *InstancePtr, u32 BaseAddress)
XLlFifo_Config * XLlFfio_LookupConfig (u32 DeviceId)
u32 XLlFifo_iRxOccupancy (XLlFifo *InstancePtr)
u32 XLlFifo_iRxGetLen (XLlFifo *InstancePtr)
u32 XLlFifo_iTxVacancy (XLlFifo *InstancePtr)
void XLlFifo_iTxSetLen (XLlFifo *InstancePtr, u32 Bytes)
u32 XLlFifo_RxGetWord (XLlFifo *InstancePtr)
void XLlFifo_TxPutWord (XLlFifo *InstancePtr, u32 Word)
+

Detailed Description

+

Define Documentation

+ +
+
+ + + + +
#define XLLFIFO_H
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_IntClear(InstancePtr,
Mask  ) 
+
+
+Value:
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
+                        ((Mask) & XLLF_INT_ALL_MASK))
+

XLlFifo_IntClear clears pending interrupts specified in Mask for the FIFO specified by InstancePtr. The corresponding pending interrupt for each bit set to 1 in Mask, will be cleared. In other words, XLlFifo_IntClear uses the "set a bit to clear it" scheme.

+
Parameters:
+ + + +
InstancePtr references the FIFO on which to operate.
Mask contains a bit mask of the pending interrupts to clear. The mask can be formed using a set of bitwise or'd values from the XLLF_INT_*_MASK preprocessor symbols.
+
+
+
Note:
C-style signature: void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
+ +
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_IntDisable(InstancePtr,
Mask  ) 
+
+
+Value:
{ \
+        u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+                        XLLF_IER_OFFSET); \
+        Reg &= ~((Mask) & XLLF_INT_ALL_MASK);  \
+        XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+                        Reg); \
+}
+

XLlFifo_IntDisable disables the interrupts specified in Mask for the FIFO specified by InstancePtr. The corresponding interrupt for each bit set to 1 in Mask, will be disabled. In other words, XLlFifo_IntDisable uses the "set a bit to clear it" scheme.

+
Parameters:
+ + + +
InstancePtr references the FIFO on which to operate.
Mask contains a bit mask of the interrupts to disable. The mask can be formed using a set of bitwise or'd values from the XLLF_INT_*_MASK preprocessor symbols.
+
+
+
Returns:
N/A
+
Note:
C-style signature: void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
+ +
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_IntEnable(InstancePtr,
Mask  ) 
+
+
+Value:
{ \
+        u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+                        XLLF_IER_OFFSET); \
+        Reg |= ((Mask) & XLLF_INT_ALL_MASK);                    \
+        XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+                        Reg); \
+}
+

XLlFifo_IntEnable enables the interrupts specified in Mask for the FIFO specified by InstancePtr. The corresponding interrupt for each bit set to 1 in Mask, will be enabled.

+
Parameters:
+ + + +
InstancePtr references the FIFO on which to operate.
Mask contains a bit mask of the interrupts to enable. The mask can be formed using a set of bitwise or'd values from the XLLF_INT_*_MASK preprocessor symbols.
+
+
+
Returns:
N/A
+
Note:
C-style signature: void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_IntPending(InstancePtr  ) 
+
+
+Value:
(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) &  \
+         XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
+

XLlFifo_IntPending returns a bit mask of the pending interrupts for the FIFO specified by InstancePtr. Each bit set to 1 in the return value represents a pending interrupt.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_IntPending returns a bit mask of the interrupts that are pending. The mask will be a set of bitwise or'd values from the XLLF_INT_*_MASK preprocessor symbols.
+
Note:
C-style signature: u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_IsRxDone(InstancePtr  ) 
+
+
+Value:
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+                XLLF_INT_RC_MASK) \
+                ? TRUE : FALSE)
+

XLlFifo_IsRxDone returns true if the reception in the receive channel of the FIFO, specified by InstancePtr, is complete. XLlFifo_IsRxDone works only if the RC bit in the ISR register is cleared before receiving a frame.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_IsRxDone returns TRUE when the receive channel of the FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
+
Note:
C-style signature: int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_IsRxEmpty(InstancePtr  ) 
+
+
+Value:
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
+                                                        ? TRUE : FALSE)
+

XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified by InstancePtr, is empty.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_IsRxEmpty returns TRUE when the receive channel of the FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
+
Note:
C-style signature: int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_IsTxDone(InstancePtr  ) 
+
+
+Value:
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+                XLLF_INT_TC_MASK) \
+                ? TRUE : FALSE)
+

XLlFifo_IsTxDone returns true if the transmission in the transmit channel of the FIFO, specified by InstancePtr, is complete. XLlFifo_IsTxDone works only if the TC bit in the IS register is cleared before sending a frame.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_IsTxDone returns TRUE when the transmit channel of the FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
+
Note:
C-style signature: int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + +
#define XLlFifo_Read(InstancePtr,
BufPtr,
Bytes  )    XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
+
+
+

XLlFifo_Read reads Bytes bytes from the receive channel of the FIFO referenced by InstancePtr to the block of memory, referenced by BufPtr.

+

Care must be taken to ensure that the number of bytes read with one or more calls to XLlFifo_Read() does not exceed the number of bytes available given from the last call to XLlFifo_RxGetLen().

+
Parameters:
+ + + + +
InstancePtr references the FIFO on which to operate.
BufPtr specifies the memory address to place the data read.
Bytes specifies the number of bytes to read.
+
+
+
Returns:
N/A
+
Note:
Error handling is handled through hardware exceptions and interrupts.
+

C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)

+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_ReadRdr(InstancePtr  )    XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
+
+
+

XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).

+

The RDR contains destination address corresponding to the valid packet that is received. The RDR should only be read when a receive packet is available for processing (the receive occupancy is not zero). Once the RDR is read, the receive packet data should be read from the receive data FIFO before the RDR is read again. The RDR values are stored in the receive data FIFO by the AXI4-Stream FIFO core with the data of each packet. The RDR value for the subsequent packet to be processed is moved to the RDR when the previous RDR value has been read.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
The Receive Destination address read from the RDR.
+
Note:
C Signature: u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_Reset(InstancePtr  ) 
+
+
+Value:
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
+                        XLLF_LLR_RESET_MASK)
+

XLlFifo_Reset resets both the Tx and Rx channels and the local link interface the FIFO specified by InstancePtr. XLlFifo_TxReset resets also sends a reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO not yet transmitted.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
N/A
+
Note:
C-style signature: void XLlFifo_Reset(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_RxGetLen(InstancePtr  )    XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
+
+
+

XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the receive channel of the FIFO, specified by InstancePtr.

+

Note that the program must first call XLlFifo_RxGetLen before pulling data out of the receive channel of the FIFO with XLlFifo_Read.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_RxGetLen returns the number of bytes available in the next frame.
+
Note:
+

C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)

+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_RxOccupancy(InstancePtr  )    XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
+
+
+

XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the receive channel of the FIFO, specified by InstancePtr.

+

The xps_ll_fifo core uses the same fifo to store data values and frame length values. Upon initialization, the XLlFifo_RxOccupancy will give the value of 1, which means one length value (a reserved fifo location) and no data values.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_RxOccupancy returns the occupancy count for the specified packet FIFO.
+
Note:
+

C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)

+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_RxReset(InstancePtr  ) 
+
+
+Value:
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
+                        XLLF_RDFR_RESET_MASK)
+

XLlFifo_RxReset resets the receive channel of the FIFO specified by InstancePtr. XLlFifo_RxReset drops any bytes in the FIFO not yet retrieved.

+

The calling software may want to test for the completion of the reset by reading the interrupt status (IS) register and testing for the Rx Reset complete (RRC) bit.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
N/A
+
Note:
C-style signature: void XLlFifo_RxReset(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_Status(InstancePtr  )    XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
+
+
+

XLlFifo_Status returns a bit mask of the interrupt status register (ISR) for the FIFO specified by InstancePtr. XLlFifo_Status can be used to query the status of the FIFO without having to have interrupts enabled.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_IntStatus returns a bit mask of the status conditions. The mask will be a set of bitwise or'd values from the XLLF_INT_*_MASK preprocessor symbols.
+
Note:
C-style signature: u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_TxReset(InstancePtr  ) 
+
+
+Value:
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
+                        XLLF_TDFR_RESET_MASK)
+

XLlFifo_TxReset resets the transmit channel of the FIFO specified by InstancePtr. XLlFifo_TxReset drops any bytes in the FIFO not yet transmitted.

+

The calling software may want to test for the completion of the reset by reading the interrupt status (IS) register and testing for the Tx Reset complete (TRC) bit.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
N/A
+
Note:
C-style signature: void XLlFifo_TxReset(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_TxSetLen(InstancePtr,
Bytes  )    XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
+
+
+

XLlFifo_TxSetLen begins a hardware transfer of Bytes bytes out of the transmit channel of the FIFO specified by InstancePtr.

+
Parameters:
+ + + +
InstancePtr references the FIFO on which to operate.
Bytes specifies the frame length in bytes.
+
+
+
Returns:
N/A
+
Note:
+

C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)

+ +
+
+ +
+
+ + + + + + + + + +
#define XLlFifo_TxVacancy(InstancePtr  )    XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
+
+
+

XLlFifo_TxVacancy returns the number of unused 32 bit words available (vacancy) in the send channel of the FIFO specified by InstancePtr.

+

The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length values. Upon initialization, the XLlFifo_TxVacancy will give the value of FIFO_WIDTH - 1, which means one length value used (a reserved fifo location) and no data values yet present.

+
Parameters:
+ + +
InstancePtr references the FIFO on which to operate.
+
+
+
Returns:
XLlFifo_TxVacancy returns the vacancy count in 32-bit words for the specified FIFO.
+
Note:
C-style signature: u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + +
#define XLlFifo_Write(InstancePtr,
BufPtr,
Bytes  )    XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
+
+
+

XLlFifo_Write writes Bytes bytes of the block of memory, referenced by BufPtr, to the transmit channel of the FIFO referenced by InstancePtr.

+

Care must be taken to ensure that the number of bytes written with one or more calls to XLlFifo_Write() matches the number of bytes given in the next call to XLlFifo_TxSetLen().

+
Parameters:
+ + + + +
InstancePtr references the FIFO on which to operate.
BufPtr specifies the memory address of data to write.
Bytes specifies the number of bytes to write.
+
+
+
Returns:
N/A
+
Note:
Error handling is handled through hardware exceptions and interrupts.
+

C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)

+ +
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_WriteTdr(InstancePtr,
Tdest  ) 
+
+
+Value:
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
+                          Tdest & 0xF)
+

XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)

+

The TDR stores the destination address corresponding to the packet to be transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core the following sequence should be followed

+
    +
  • Write the destination address into TDR first,
    • +
  • Write the packet data to the Transmit Data FIFO next
    • +
  • Write the length of the packet into the Transmit Length Register.
    • +
+
Parameters:
+ + + +
InstancePtr references the FIFO on which to operate.
Tdest is the Transmit Destination address to be written to TDR.
+
+
+
Returns:
N/A
+
Note:
C Signature: void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + +
XLlFifo_Config* XLlFfio_LookupConfig (u32  DeviceId ) 
+
+
+

Look up the hardware configuration for a device instance

+
Parameters:
+ + +
DeviceId is the unique device ID of the device to lookup for
+
+
+
Returns:
The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.
+
Note:
None
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int XLlFifo_CfgInitialize (XLlFifo *  InstancePtr,
XLlFifo_Config *  Config,
u32  EffectiveAddress 
)
+
+
+

XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

+
Parameters:
+ + + + +
InstancePtr is a pointer to the Axi Streaming FIFO instance to be worked on.
CfgPtr references the structure holding the hardware configuration for the Axi Streaming FIFO core to initialize.
EffectiveAddr is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config->BaseAddress for this parameters, passing the physical address instead.
+
+
+
Returns:
N/A
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XLlFifo_Initialize (XLlFifo *  InstancePtr,
u32  BaseAddress 
)
+
+
+

XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the InstancePtr that references it.

+
Parameters:
+ + + +
InstancePtr references the memory instance to be associated with the FIFO device upon initialization.
BaseAddress is the processor address used to access the base address of the Fifo device.
+
+
+
Returns:
N/A
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_iRxGetLen (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_iRxOccupancy (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XLlFifo_iTxSetLen (XLlFifo *  InstancePtr,
u32  Bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_iTxVacancy (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XLlFifo_RxGetWord (XLlFifo *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XLlFifo_TxPutWord (XLlFifo *  InstancePtr,
u32  Word 
)
+
+
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__g_8c.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__g_8c.html new file mode 100755 index 00000000..0aa1e156 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__g_8c.html @@ -0,0 +1,64 @@ + + + + + Xilinx Driver llfifo v4_0: xllfifo_g.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xllfifo_g.c File Reference

#include "xparameters.h"
+#include "xllfifo.h"
+ + + +

Variables

XLlFifo_Config XLlFifo_ConfigTable []
+

Variable Documentation

+ +
+
+ + + + +
XLlFifo_Config XLlFifo_ConfigTable[]
+
+
+Initial value:
+{
+        {
+                XPAR_AXI_FIFO_MM_S_1_DEVICE_ID,
+                XPAR_AXI_FIFO_MM_S_1_BASEADDR,
+                XPAR_AXI_FIFO_MM_S_1_AXI4_BASEADDR,
+                XPAR_AXI_FIFO_MM_S_1_DATA_INTERFACE_TYPE
+        }
+}
+
+
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__hw_8h.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__hw_8h.html index b120b7f8..db9fd423 100755 --- a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__hw_8h.html +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__hw_8h.html @@ -2,30 +2,89 @@ - xllfifo_hw.h File Reference + Xilinx Driver llfifo v4_0: xllfifo_hw.h File Reference - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

xllfifo_hw.h File Reference

Detailed Description

-This header file contains identifiers and low-level driver functions (or macros) that can be used to access the xps_ll_fifo core. High-level driver functions are defined in xpfifo.h.

+ + +

+
+

xllfifo_hw.h File Reference

#include "xdebug.h"
+#include "xil_io.h"
+#include "xil_types.h"
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define XLLFIFO_HW_H
#define XLlFifo_reg_name(RegOffset)
#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value)
#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value)
#define XLlFifo_ReadReg(BaseAddress, RegOffset)   (Xil_In32((BaseAddress) + (RegOffset)))
#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)   ((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
Registers

+

#define XLLF_ISR_OFFSET   0x00000000
#define XLLF_IER_OFFSET   0x00000004
#define XLLF_TDFR_OFFSET   0x00000008
#define XLLF_TDFV_OFFSET   0x0000000c
#define XLLF_TDFD_OFFSET   0x00000010
#define XLLF_TLF_OFFSET   0x00000014
#define XLLF_RDFR_OFFSET   0x00000018
#define XLLF_RDFO_OFFSET   0x0000001c
#define XLLF_RDFD_OFFSET   0x00000020
#define XLLF_RLF_OFFSET   0x00000024
#define XLLF_LLR_OFFSET   0x00000028
#define XLLF_TDR_OFFSET   0x0000002C
#define XLLF_RDR_OFFSET   0x00000030
Interrupt bits

These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET registers.

+

#define XLLF_INT_RPURE_MASK   0x80000000
#define XLLF_INT_RPORE_MASK   0x40000000
#define XLLF_INT_RPUE_MASK   0x20000000
#define XLLF_INT_TPOE_MASK   0x10000000
#define XLLF_INT_TC_MASK   0x08000000
#define XLLF_INT_RC_MASK   0x04000000
#define XLLF_INT_TSE_MASK   0x02000000
#define XLLF_INT_TRC_MASK   0x01000000
#define XLLF_INT_RRC_MASK   0x00800000
#define XLLF_INT_TFPF_MASK   0x00400000
#define XLLF_INT_TFPE_MASK   0x00200000
#define XLLF_INT_RFPF_MASK   0x00100000
#define XLLF_INT_RFPE_MASK   0x00080000
#define XLLF_INT_ALL_MASK   0xfff80000
#define XLLF_INT_ERROR_MASK   0xf2000000
#define XLLF_INT_RXERROR_MASK   0xe0000000
#define XLLF_INT_TXERROR_MASK   0x12000000
Reset register values

These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET reset registers.

+

#define XLLF_RDFR_RESET_MASK   0x000000a5
#define XLLF_TDFR_RESET_MASK   0x000000a5
#define XLLF_LLR_RESET_MASK   0x000000a5
+

Detailed Description

+

This header file contains identifiers and low-level driver functions (or macros) that can be used to access the xps_ll_fifo core. High-level driver functions are defined in xpfifo.h.

- MODIFICATION HISTORY:

-

 Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
 Ver   Who  Date     Changes
  ----- ---- -------- -------------------------------------------------------
  1.00a jvb  10/16/06 First release.
  1.02a jz   12/04/09  Hal phase 1 support
@@ -35,932 +94,648 @@ This header file contains identifiers and low-level driver functions (or macros)
 		       XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
 		       XLLF_INT_RFPE_MASK for the new version of the
 		       AXI4-Stream FIFO core (v2.01a and later)
-
-

-#include "xdebug.h"
-#include "xil_io.h"
-#include "xil_types.h"
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Registers

#define XLLF_ISR_OFFSET   0x00000000
#define XLLF_IER_OFFSET   0x00000004
#define XLLF_TDFR_OFFSET   0x00000008
#define XLLF_TDFV_OFFSET   0x0000000c
#define XLLF_TDFD_OFFSET   0x00000010
#define XLLF_TLF_OFFSET   0x00000014
#define XLLF_RDFR_OFFSET   0x00000018
#define XLLF_RDFO_OFFSET   0x0000001c
#define XLLF_RDFD_OFFSET   0x00000020
#define XLLF_RLF_OFFSET   0x00000024
#define XLLF_LLR_OFFSET   0x00000028
#define XLLF_TDR_OFFSET   0x0000002C
#define XLLF_RDR_OFFSET   0x00000030

Interrupt bits

These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET registers.

#define XLLF_INT_RPURE_MASK   0x80000000
#define XLLF_INT_RPORE_MASK   0x40000000
#define XLLF_INT_RPUE_MASK   0x20000000
#define XLLF_INT_TPOE_MASK   0x10000000
#define XLLF_INT_TC_MASK   0x08000000
#define XLLF_INT_RC_MASK   0x04000000
#define XLLF_INT_TSE_MASK   0x02000000
#define XLLF_INT_TRC_MASK   0x01000000
#define XLLF_INT_RRC_MASK   0x00800000
#define XLLF_INT_TFPF_MASK   0x00400000
#define XLLF_INT_TFPE_MASK   0x00200000
#define XLLF_INT_RFPF_MASK   0x00100000
#define XLLF_INT_RFPE_MASK   0x00080000
#define XLLF_INT_ALL_MASK   0xfff80000
#define XLLF_INT_ERROR_MASK   0xf2000000
#define XLLF_INT_RXERROR_MASK   0xe0000000
#define XLLF_INT_TXERROR_MASK   0x12000000

Reset register values

These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET reset registers.

#define XLLF_RDFR_RESET_MASK   0x000000a5
#define XLLF_TDFR_RESET_MASK   0x000000a5
#define XLLF_LLR_RESET_MASK   0x000000a5

Defines

#define XLlFifo_ReadReg(BaseAddress, RegOffset)   (Xil_In32((BaseAddress) + (RegOffset)))
#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value)   ((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
-

Define Documentation

-

- - - - -
- +

Define Documentation

+ +
+
+
- +
#define XLLF_IER_OFFSET   0x00000004 #define XLLF_IER_OFFSET   0x00000004
-
- - - - - -
-   - + +
+

Interrupt Enable

-

-Interrupt Enable

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_ALL_MASK   0xfff80000 #define XLLF_INT_ALL_MASK   0xfff80000
-
- - - - - -
-   - + +
+

All the ints

-

-All the ints

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_ERROR_MASK   0xf2000000 #define XLLF_INT_ERROR_MASK   0xf2000000
-
- - - - - -
-   - + +
+

Error status ints

-

-Error status ints

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RC_MASK   0x04000000 #define XLLF_INT_RC_MASK   0x04000000
-
- - - - - -
-   - + +
+

Receive complete

-

-Receive complete

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RFPE_MASK   0x00080000 #define XLLF_INT_RFPE_MASK   0x00080000
-
- - - - - -
-   - + +
+

Rx FIFO Programmable Empty AXI FIFO MM2S Only

-

-Rx FIFO Programmable Empty AXI FIFO MM2S Only

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RFPF_MASK   0x00100000 #define XLLF_INT_RFPF_MASK   0x00100000
-
- - - - - -
-   - + +
+

Rx FIFO Programmable Full AXI FIFO MM2S Only

-

-Rx FIFO Programmable Full AXI FIFO MM2S Only

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RPORE_MASK   0x40000000 #define XLLF_INT_RPORE_MASK   0x40000000
-
- - - - - -
-   - + +
+

Receive over-read

-

-Receive over-read

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RPUE_MASK   0x20000000 #define XLLF_INT_RPUE_MASK   0x20000000
-
- - - - - -
-   - + +
+

Receive underrun (empty)

-

-Receive underrun (empty)

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RPURE_MASK   0x80000000 #define XLLF_INT_RPURE_MASK   0x80000000
-
- - - - - -
-   - + +
+

Receive under-read

-

-Receive under-read

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RRC_MASK   0x00800000 #define XLLF_INT_RRC_MASK   0x00800000
-
- - - - - -
-   - + +
+

Receive reset complete

-

-Receive reset complete

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_RXERROR_MASK   0xe0000000 #define XLLF_INT_RXERROR_MASK   0xe0000000
-
- - - - - -
-   - + +
+

Receive Error status ints

-

-Receive Error status ints

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TC_MASK   0x08000000 #define XLLF_INT_TC_MASK   0x08000000
-
- - - - - -
-   - + +
+

Transmit complete

-

-Transmit complete

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TFPE_MASK   0x00200000 #define XLLF_INT_TFPE_MASK   0x00200000
-
- - - - - -
-   - + +
+

Tx FIFO Programmable Empty AXI FIFO MM2S Only

-

-Tx FIFO Programmable Empty AXI FIFO MM2S Only

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TFPF_MASK   0x00400000 #define XLLF_INT_TFPF_MASK   0x00400000
-
- - - - - -
-   - + +
+

Tx FIFO Programmable Full, AXI FIFO MM2S Only

-

-Tx FIFO Programmable Full, AXI FIFO MM2S Only

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TPOE_MASK   0x10000000 #define XLLF_INT_TPOE_MASK   0x10000000
-
- - - - - -
-   - + +
+

Transmit overrun

-

-Transmit overrun

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TRC_MASK   0x01000000 #define XLLF_INT_TRC_MASK   0x01000000
-
- - - - - -
-   - + +
+

Transmit reset complete

-

-Transmit reset complete

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TSE_MASK   0x02000000 #define XLLF_INT_TSE_MASK   0x02000000
-
- - - - - -
-   - + +
+

Transmit length mismatch

-

-Transmit length mismatch

-

- - - - -
- + + + +
+
+
- +
#define XLLF_INT_TXERROR_MASK   0x12000000 #define XLLF_INT_TXERROR_MASK   0x12000000
-
- - - - - -
-   - + +
+

Transmit Error status ints

-

-Transmit Error status ints

-

- - - - -
- + + + +
+
+
- +
#define XLLF_ISR_OFFSET   0x00000000 #define XLLF_ISR_OFFSET   0x00000000
-
- - - - - -
-   - + +
+

Interrupt Status

-

-Interrupt Status

-

- - - - -
- + + + +
+
+
- +
#define XLLF_LLR_OFFSET   0x00000028 #define XLLF_LLR_OFFSET   0x00000028
-
- - - - - -
-   - + +
+

Local Link Reset

-

-Local Link Reset

-

- - - - -
- + + + +
+
+
- +
#define XLLF_LLR_RESET_MASK   0x000000a5 #define XLLF_LLR_RESET_MASK   0x000000a5
-
- - - - - -
-   - + +
+

Local Link reset value

-

-Local Link reset value

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RDFD_OFFSET   0x00000020 #define XLLF_RDFD_OFFSET   0x00000020
-
- - - - - -
-   - + +
+

Receive Data

-

-Receive Data

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RDFO_OFFSET   0x0000001c #define XLLF_RDFO_OFFSET   0x0000001c
-
- - - - - -
-   - + +
+

Receive Occupancy

-

-Receive Occupancy

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RDFR_OFFSET   0x00000018 #define XLLF_RDFR_OFFSET   0x00000018
-
- - - - - -
-   - + +
+

Receive Reset

-

-Receive Reset

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RDFR_RESET_MASK   0x000000a5 #define XLLF_RDFR_RESET_MASK   0x000000a5
-
- - - - - -
-   - + +
+

receive reset value

-

-receive reset value

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RDR_OFFSET   0x00000030 #define XLLF_RDR_OFFSET   0x00000030
-
- - - - - -
-   - + +
+

Receive Destination

-

-Receive Destination

-

- - - - -
- + + + +
+
+
- +
#define XLLF_RLF_OFFSET   0x00000024 #define XLLF_RLF_OFFSET   0x00000024
-
- - - - - -
-   - + +
+

Receive Length

-

-Receive Length

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TDFD_OFFSET   0x00000010 #define XLLF_TDFD_OFFSET   0x00000010
-
- - - - - -
-   - + +
+

Transmit Data

-

-Transmit Data

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TDFR_OFFSET   0x00000008 #define XLLF_TDFR_OFFSET   0x00000008
-
- - - - - -
-   - + +
+

Transmit Reset

-

-Transmit Reset

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TDFR_RESET_MASK   0x000000a5 #define XLLF_TDFR_RESET_MASK   0x000000a5
-
- - - - - -
-   - + +
+

Transmit reset value

-

-Transmit reset value

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TDFV_OFFSET   0x0000000c #define XLLF_TDFV_OFFSET   0x0000000c
-
- - - - - -
-   - + +
+

Transmit Vacancy

-

-Transmit Vacancy

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TDR_OFFSET   0x0000002C #define XLLF_TDR_OFFSET   0x0000002C
-
- - - - - -
-   - + +
+

Transmit Destination

-

-Transmit Destination

-

- - - - -
- + + + +
+
+
- +
#define XLLF_TLF_OFFSET   0x00000014 #define XLLF_TLF_OFFSET   0x00000014
-
- - - - - -
-   - + +
+

Transmit Length

-

-Transmit Length

-

- - - - -
- + + + +
+
+
- - - - - - - - - +
#define XLlFifo_ReadReg ( BaseAddress,
RegOffset   )    (Xil_In32((BaseAddress) + (RegOffset)))#define XLLFIFO_HW_H
-
- - - - - -
-   - + +
-

-XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped base address, BaseAddress.

-

Parameters:
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +
#define XLlFifo_print_reg_i(BaseAddress,
RegOffset,
Value  ) 
+
+
+Value:
xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \
+                         XLlFifo_reg_name(RegOffset), \
+                        (RegOffset) + (BaseAddress), (Value))
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + + +
#define XLlFifo_print_reg_o(BaseAddress,
RegOffset,
Value  ) 
+
+
+Value:
xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \
+                          XLlFifo_reg_name(RegOffset), \
+                         (RegOffset) + (BaseAddress))
+
+
+
+ +
+
+ + + + + + + + + + + + + + +
#define XLlFifo_ReadReg(BaseAddress,
RegOffset  )    (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+

XLlFifo_ReadReg returns the value of the register at the offet, RegOffset, from the memory mapped base address, BaseAddress.

+
Parameters:
BaseAddress specifies the base address of the device.
RegOffset specifies the offset from BaseAddress.
+
-
Returns:
XLlFifo_ReadReg returns the value of the specified register.
-
Note:
C-style signature: u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
-
-

- - - - -
- +
Returns:
XLlFifo_ReadReg returns the value of the specified register.
+
Note:
C-style signature: u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
+ + + + +
+
+
- - - - - - - - - - - - + + + + + +
#define XLlFifo_WriteReg ( BaseAddress,
RegOffset,
Value   )    ((Xil_Out32((BaseAddress) + (RegOffset), (Value))))#define XLlFifo_reg_name(RegOffset  ) 
-
- - - - - -
-   - - -

-XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress.

-

Parameters:
+ +
+Value:
(((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \
+        ((RegOffset) == XLLF_IER_OFFSET) ? "IER": \
+        ((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \
+        ((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \
+        ((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \
+        ((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \
+        ((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \
+        ((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \
+        ((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \
+        ((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \
+        "unknown")
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +
#define XLlFifo_WriteReg(BaseAddress,
RegOffset,
Value  )    ((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
+
+
+

XLlFifo_WriteReg writes the value, Value, to the register at the offet, RegOffset, from the memory mapped base address, BaseAddress.

+
Parameters:
BaseAddress specifies the base address of the device.
RegOffset specifies the offset from BaseAddress.
Value is value to write to the register.
+
-
Returns:
N/A
-
Note:
C-style signature: void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
-
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

Returns:
N/A
+
Note:
C-style signature: void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__sinit_8c.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__sinit_8c.html new file mode 100755 index 00000000..44902544 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xllfifo__sinit_8c.html @@ -0,0 +1,69 @@ + + + + + Xilinx Driver llfifo v4_0: xllfifo_sinit.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xllfifo_sinit.c File Reference

#include "xparameters.h"
+#include "xllfifo.h"
+ + + +

Functions

XLlFifo_Config * XLlFfio_LookupConfig (u32 DeviceId)
+

Function Documentation

+ +
+
+ + + + + + + + + +
XLlFifo_Config* XLlFfio_LookupConfig (u32  DeviceId ) 
+
+
+

Look up the hardware configuration for a device instance

+
Parameters:
+ + +
DeviceId is the unique device ID of the device to lookup for
+
+
+
Returns:
The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.
+
Note:
None
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8c.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8c.html new file mode 100755 index 00000000..0cb36724 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8c.html @@ -0,0 +1,253 @@ + + + + + Xilinx Driver llfifo v4_0: xstreamer.c File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xstreamer.c File Reference

#include "xstreamer.h"
+#include "xil_assert.h"
+ + + + + + + + + + +

Defines

#define min(x, y)   (((x) < (y)) ? (x) : (y))

Functions

 xdbg_stmnt (u32 _xstrm_ro_value;)
void XStrm_TxInitialize (XStrm_TxFifoStreamer *InstancePtr, unsigned FifoWidth, void *FifoInstance, XStrm_XferFnType WriteFn, XStrm_SetLenFnType SetLenFn, XStrm_GetVacancyFnType GetVacancyFn)
u32 XStrm_RxGetLen (XStrm_RxFifoStreamer *InstancePtr)
void XStrm_Read (XStrm_RxFifoStreamer *InstancePtr, void *BufPtr, unsigned Bytes)
void XStrm_TxSetLen (XStrm_TxFifoStreamer *InstancePtr, u32 Bytes)
void XStrm_Write (XStrm_TxFifoStreamer *InstancePtr, void *BufPtr, unsigned Bytes)
+

Define Documentation

+ +
+
+ + + + + + + + + + + + + + +
#define min(x,
y  )    (((x) < (y)) ? (x) : (y))
+
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + +
xdbg_stmnt (u32 _xstrm_ro_value;  ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_Read (XStrm_RxFifoStreamer *  InstancePtr,
void *  BufPtr,
unsigned  Bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XStrm_RxGetLen (XStrm_RxFifoStreamer *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_TxInitialize (XStrm_TxFifoStreamer *  InstancePtr,
unsigned  FifoWidth,
void *  FifoInstance,
XStrm_XferFnType  WriteFn,
XStrm_SetLenFnType  SetLenFn,
XStrm_GetVacancyFnType  GetVacancyFn 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XStrm_TxSetLen (XStrm_TxFifoStreamer *  InstancePtr,
u32  Bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_Write (XStrm_TxFifoStreamer *  InstancePtr,
void *  BufPtr,
unsigned  Bytes 
)
+
+
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8h.html b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8h.html new file mode 100755 index 00000000..414abb6c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/llfifo/doc/html/api/xstreamer_8h.html @@ -0,0 +1,434 @@ + + + + + Xilinx Driver llfifo v4_0: xstreamer.h File Reference + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

xstreamer.h File Reference

#include "xenv.h"
+#include "xdebug.h"
+#include "xil_types.h"
+ + + + + + + + + + + + + + + + + + + + + + + + +

Classes

union  XStrm_AlignedBufferType
struct  XStrm_RxFifoStreamer
struct  XStrm_TxFifoStreamer

Defines

#define XSTREAMER_H
#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS   4
#define XStrm_TxVacancy(InstancePtr)
#define XStrm_RxOccupancy(InstancePtr)
#define XStrm_IsRxInternalEmpty(InstancePtr)   (((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)

Typedefs

typedef int(* XStrm_XferFnType )(void *FifoInstance, void *BufPtr, unsigned WordCount)
typedef u32(* XStrm_GetLenFnType )(void *FifoInstance)
typedef void(* XStrm_SetLenFnType )(void *FifoInstance, u32 ByteCount)
typedef u32(* XStrm_GetOccupancyFnType )(void *FifoInstance)
typedef u32(* XStrm_GetVacancyFnType )(void *FifoInstance)

Functions

void XStrm_RxInitialize (XStrm_RxFifoStreamer *InstancePtr, unsigned FifoWidth, void *FifoInstance, XStrm_XferFnType ReadFn, XStrm_GetLenFnType GetLenFn, XStrm_GetOccupancyFnType GetOccupancyFn)
void XStrm_TxInitialize (XStrm_TxFifoStreamer *InstancePtr, unsigned FifoWidth, void *FifoInstance, XStrm_XferFnType WriteFn, XStrm_SetLenFnType SetLenFn, XStrm_GetVacancyFnType GetVacancyFn)
void XStrm_TxSetLen (XStrm_TxFifoStreamer *InstancePtr, u32 Bytes)
void XStrm_Write (XStrm_TxFifoStreamer *InstancePtr, void *BufPtr, unsigned bytes)
u32 XStrm_RxGetLen (XStrm_RxFifoStreamer *InstancePtr)
void XStrm_Read (XStrm_RxFifoStreamer *InstancePtr, void *BufPtr, unsigned bytes)
+

Define Documentation

+ +
+
+ + + + +
#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS   4
+
+
+ +
+
+ +
+
+ + + + +
#define XSTREAMER_H
+
+
+ +
+
+ +
+
+ + + + + + + + + +
#define XStrm_IsRxInternalEmpty(InstancePtr  )    (((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
#define XStrm_RxOccupancy(InstancePtr  ) 
+
+
+Value:
( \
+          ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \
+          ( \
+            ((InstancePtr)->FrmByteCnt) ? \
+              ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+              0 \
+          ) \
+        )
+
+
+
+ +
+
+ + + + + + + + + +
#define XStrm_TxVacancy(InstancePtr  ) 
+
+
+Value:
(((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \
+                        (((InstancePtr)->TailIndex + 3) / 4))
+
+
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef u32(* XStrm_GetLenFnType)(void *FifoInstance)
+
+
+ +
+
+ +
+
+ + + + +
typedef u32(* XStrm_GetOccupancyFnType)(void *FifoInstance)
+
+
+ +
+
+ +
+
+ + + + +
typedef u32(* XStrm_GetVacancyFnType)(void *FifoInstance)
+
+
+ +
+
+ +
+
+ + + + +
typedef void(* XStrm_SetLenFnType)(void *FifoInstance, u32 ByteCount)
+
+
+ +
+
+ +
+
+ + + + +
typedef int(* XStrm_XferFnType)(void *FifoInstance, void *BufPtr, unsigned WordCount)
+
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_Read (XStrm_RxFifoStreamer *  InstancePtr,
void *  BufPtr,
unsigned  bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + +
u32 XStrm_RxGetLen (XStrm_RxFifoStreamer *  InstancePtr ) 
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_RxInitialize (XStrm_RxFifoStreamer *  InstancePtr,
unsigned  FifoWidth,
void *  FifoInstance,
XStrm_XferFnType  ReadFn,
XStrm_GetLenFnType  GetLenFn,
XStrm_GetOccupancyFnType  GetOccupancyFn 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_TxInitialize (XStrm_TxFifoStreamer *  InstancePtr,
unsigned  FifoWidth,
void *  FifoInstance,
XStrm_XferFnType  WriteFn,
XStrm_SetLenFnType  SetLenFn,
XStrm_GetVacancyFnType  GetVacancyFn 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void XStrm_TxSetLen (XStrm_TxFifoStreamer *  InstancePtr,
u32  Bytes 
)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void XStrm_Write (XStrm_TxFifoStreamer *  InstancePtr,
void *  BufPtr,
unsigned  bytes 
)
+
+
+ +
+
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/annotated.html index 75738a7e..ceeb6ae0 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/annotated.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/annotated.html @@ -2,27 +2,38 @@ - Class List + Xilinx Driver mbox v4_0: Class List - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
+ + + +

Class List

Here are the classes, structs, unions and interfaces with brief descriptions:
XMbox
XMbox_Config
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/classes.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/classes.html new file mode 100755 index 00000000..84ab7622 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/classes.html @@ -0,0 +1,39 @@ + + + + + Xilinx Driver mbox v4_0: Alphabetical List + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+

Class Index

X
+ +
  X  
+		XMbox   XMbox_Config   
X
+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/files.html index 53319ac6..6264c04a 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/files.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/files.html @@ -2,29 +2,41 @@ - File Index + Xilinx Driver mbox v4_0: File Index - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-

File List

Here is a list of all documented files with brief descriptions: + + + +
+

File List

Here is a list of all files with brief descriptions:
+
xmbox.c
xmbox.h
xmbox_g.c
xmbox_hw.h
xmbox_sinit.c
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions.html index 97fd6a55..95294d84 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions.html @@ -2,40 +2,63 @@ - Class Members + Xilinx Driver mbox v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + -Here is a list of all documented class members with links to the class documentation for each member: -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions_vars.html index edcb5395..612e6c2b 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions_vars.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/functions_vars.html @@ -2,40 +2,63 @@ - Class Members - Variables + Xilinx Driver mbox v4_0: Class Members - Variables - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + -  -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals.html index 0dbc1014..f4c04442 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals.html @@ -2,80 +2,209 @@ - Class Members + Xilinx Driver mbox v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- -
-
-
    -
  • x
    • -
-
-

-Here is a list of all documented file members with links to the documentation: -

-

- x -

+ +

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_defs.html index c7b661fd..d61dcb21 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_defs.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_defs.html @@ -2,58 +2,134 @@ - Class Members + Xilinx Driver mbox v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + -  -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_func.html index 209809a8..86f9470b 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_func.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_func.html @@ -2,49 +2,115 @@ - Class Members + Xilinx Driver mbox v4_0: Class Members - +

Xilinx Processor IP Library

Software Drivers
- -
-
-
-
-
- + + + +
  -

-

+
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_vars.html new file mode 100755 index 00000000..1814a22b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/globals_vars.html @@ -0,0 +1,49 @@ + + + + + Xilinx Driver mbox v4_0: Class Members + + + +

Xilinx Processor IP Library

+Software Drivers +
+ + + +
+  +
+

+Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

+ + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/index.html index 45fbad05..7ae12032 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/index.html @@ -2,46 +2,51 @@ - mbox v4_0 + Xilinx Driver mbox v4_0: mbox v4_0 - +

Xilinx Processor IP Library

Software Drivers
- -
-
-

mbox v4_0

-

-The Xilinx mailbox driver. This driver supports the Xilinx Mailbox device. More detailed description of the driver operation can be found in the xmbox.c file.

+ + +

+
+

mbox v4_0

The Xilinx mailbox driver. This driver supports the Xilinx Mailbox device. More detailed description of the driver operation can be found in the xmbox.c file.

    -
  • The Xilinx Mailbox is intended to be used as a bi-directional communication core between a pair of processors. The mailbox API shall allow software to send messages in a FIFO fashion, where the receiver is intended to be software on another processor.
  • The mailbox implementation provides for a way to "send" and "receive" in an atomic fashion using seperate FIFOs in the mailbox core.
  • The API itself does not stop the use case where there is more than one sender on the transmit side and more than one receiver on the receiving side (just like TCP/IP sockets). However, unless there is a protocol implemented in the messages being transferred, it is typically good practice to assign just one transmit processor and one receiver processor to a single mailbox.
  • The API provides for both blocking and non-blocking semantics on the send and receive operations.
-

-Initialization & Configuration

-The XMbox_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

+

  • The Xilinx Mailbox is intended to be used as a bi-directional communication core between a pair of processors. The mailbox API shall allow software to send messages in a FIFO fashion, where the receiver is intended to be software on another processor.
    • +
  • The mailbox implementation provides for a way to "send" and "receive" in an atomic fashion using seperate FIFOs in the mailbox core.
    • +
  • The API itself does not stop the use case where there is more than one sender on the transmit side and more than one receiver on the receiving side (just like TCP/IP sockets). However, unless there is a protocol implemented in the messages being transferred, it is typically good practice to assign just one transmit processor and one receiver processor to a single mailbox.
    • +
  • The API provides for both blocking and non-blocking semantics on the send and receive operations.
    • + +

    Initialization & Configuration

    +

    The XMbox_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

      -
    • XMbox_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in XMbox_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed. This function returns the CfgPtr argument used by the CfgInitialize function described below.
    -

    +

  • XMbox_LookupConfig(DeviceId) - Use the device identifier to find the static configuration structure defined in XMbox_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed. This function returns the CfgPtr argument used by the CfgInitialize function described below.
    • +
      -
    • XMbox_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure. The EffectiveAddress argument is required regardless of operating system environment, i.e. in standalone, CfgPtr->BaseAddress is recommended, not the xparameters.h define.
    -

    -Interrupts

    -The Mailbox hardware has two interrupt outputs, one for each interface.

    -For an interface that uses Direct FSL the associated interrupt pin shall be high while there is data in the FIFO for this interface.

    -For a PLB interface there shall be 3 associated interrupt sources that can be controlled through dedicated registers. Each of these sources shall be associated with a specific bit position in the related register. The sources shall be: Send Threshold Interrupt (STI), Receive Threshold Interrupt (RTI) and FIFO Error (ERR). RTI is set when the number of entries in the receive FIFO become greater than the RIT value (rising edge on RTA). STI is set when the number of entries in the send FIFO becomes equal or less than the SIT value (rising edge on STA). RTI and STI are only set when their respective conditions goes from false to true, not continuously when the condition is fulfilled.

    -The Mailbox driver does not have an interrupt service routine. It is the responsibility of the caller of Mailbox functions to manage the interrupt including connecting to the interrupt and enabling/disabling the interrupt. The user can create a handler to service the interrupts generated by the Mailbox IP.

    -Using the Blocking version of the Read function is not recommended since the processor will hang until the requested length is received, which might be quite a long time.

    -

    Note:
    -This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

    -Possible Optimization technique: If the interface for the hardware is only expected to be the memory mapped or the FSL interface for the lifetime of the project, it is reasonable to remove the other, unused, leg through the functions which allow access to the other interface method, i.e. if FSL is the only available interface the memory mapped clause in the if statements can be removed improving the performance some due to the lack of the test and branch.

    +

  • XMbox_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure. The EffectiveAddress argument is required regardless of operating system environment, i.e. in standalone, CfgPtr->BaseAddress is recommended, not the xparameters.h define.
    • + +

    Interrupts

    +

    The Mailbox hardware has two interrupt outputs, one for each interface.

    +

    For an interface that uses Direct FSL the associated interrupt pin shall be high while there is data in the FIFO for this interface.

    +

    For a PLB interface there shall be 3 associated interrupt sources that can be controlled through dedicated registers. Each of these sources shall be associated with a specific bit position in the related register. The sources shall be: Send Threshold Interrupt (STI), Receive Threshold Interrupt (RTI) and FIFO Error (ERR). RTI is set when the number of entries in the receive FIFO become greater than the RIT value (rising edge on RTA). STI is set when the number of entries in the send FIFO becomes equal or less than the SIT value (rising edge on STA). RTI and STI are only set when their respective conditions goes from false to true, not continuously when the condition is fulfilled.

    +

    The Mailbox driver does not have an interrupt service routine. It is the responsibility of the caller of Mailbox functions to manage the interrupt including connecting to the interrupt and enabling/disabling the interrupt. The user can create a handler to service the interrupts generated by the Mailbox IP.

    +

    Using the Blocking version of the Read function is not recommended since the processor will hang until the requested length is received, which might be quite a long time.

    +
    Note:
    +

    This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.

    +

    Possible Optimization technique: If the interface for the hardware is only expected to be the memory mapped or the FSL interface for the lifetime of the project, it is reasonable to remove the other, unused, leg through the functions which allow access to the other interface method, i.e. if FSL is the only available interface the memory mapped clause in the if statements can be removed improving the performance some due to the lack of the test and branch.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
@@ -64,4 +69,9 @@ Possible Optimization technique: If the interface for the hardware is only expec
 		       tests will not be run if there is only one Processor
 		       in design CR#715626
  4.0   adk  19/12/13 Updated as per the New Tcl API's
-
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox-members.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox-members.html index 45da736e..b7aa65cb 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox-members.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox-members.html @@ -2,26 +2,37 @@ - Member List + Xilinx Driver mbox v4_0: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMbox Member List

    This is the complete list of members for XMbox, including all inherited members.

    - - -
    ConfigXMbox
    IsReadyXMbox
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XMbox Member List

    This is the complete list of members for XMbox, including all inherited members. + + +
    ConfigXMbox
    IsReadyXMbox
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox.html index 377f57d4..ecc2e92d 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox.html @@ -2,85 +2,78 @@ - XMbox Struct Reference + Xilinx Driver mbox v4_0: XMbox Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMbox Struct Reference

    #include <xmbox.h> -

    -List of all members.

    Detailed Description

    -The XMbox driver instance data. The user is required to allocate a variable of this type for every mbox device in the system. A pointer to a variable of this type is then passed to the driver API functions. -

    + + +

    +
    +

    XMbox Struct Reference

    +

    #include <xmbox.h>

    + +

    List of all members.

    - - - - - - + + +

    Public Attributes

    XMbox_Config Config
    u32 IsReady

    Public Attributes

    XMbox_Config Config
    u32 IsReady
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    The XMbox driver instance data. The user is required to allocate a variable of this type for every mbox device in the system. A pointer to a variable of this type is then passed to the driver API functions.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    XMbox_Config XMbox::Config XMbox_Config XMbox::Config
    -
    - - - - - -
    -   - + +
    +

    Configuration data, includes base address

    -

    -Configuration data, includes base address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XMbox::IsReady u32 XMbox::IsReady
    -
    - - - - - -
    -   - + +
    +

    Device is initialized and ready

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Device is initialized and ready

    -

    The documentation for this struct was generated from the following file:
      -
    • xmbox.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config-members.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config-members.html index 4abe6977..72031ffc 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config-members.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config-members.html @@ -2,29 +2,40 @@ - Member List + Xilinx Driver mbox v4_0: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMbox_Config Member List

    This is the complete list of members for XMbox_Config, including all inherited members.

    - - - - - -
    BaseAddressXMbox_Config
    DeviceIdXMbox_Config
    RecvIDXMbox_Config
    SendIDXMbox_Config
    UseFSLXMbox_Config
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XMbox_Config Member List

    This is the complete list of members for XMbox_Config, including all inherited members. + + + + + +
    BaseAddressXMbox_Config
    DeviceIdXMbox_Config
    RecvIDXMbox_Config
    SendIDXMbox_Config
    UseFSLXMbox_Config
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config.html index a12fd8e0..ebb3ebf4 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/struct_x_mbox___config.html @@ -2,160 +2,123 @@ - XMbox_Config Struct Reference + Xilinx Driver mbox v4_0: XMbox_Config Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMbox_Config Struct Reference

    #include <xmbox.h> -

    -List of all members.

    Detailed Description

    -This typedef contains configuration information for the device. -

    + + +

    +
    +

    XMbox_Config Struct Reference

    +

    #include <xmbox.h>

    + +

    List of all members.

    - - - - - - - - - - - - + + + + + +

    Public Attributes

    u16 DeviceId
    u32 BaseAddress
    u8 UseFSL
    u8 SendID
    u8 RecvID

    Public Attributes

    u16 DeviceId
    u32 BaseAddress
    u8 UseFSL
    u8 SendID
    u8 RecvID
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    This typedef contains configuration information for the device.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u32 XMbox_Config::BaseAddress u32 XMbox_Config::BaseAddress
    -
    - - - - - -
    -   - + +
    +

    Register base address

    -

    -Register base address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 XMbox_Config::DeviceId u16 XMbox_Config::DeviceId
    -
    - - - - - -
    -   - + +
    +

    Unique ID of device

    -

    -Unique ID of device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XMbox_Config::RecvID u8 XMbox_Config::RecvID
    -
    - - - - - -
    -   - + +
    +

    FSL link for the read i/f mailbox.

    -

    -FSL link for the read i/f mailbox.

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XMbox_Config::SendID u8 XMbox_Config::SendID
    -
    - - - - - -
    -   - + +
    +

    FSL link for the write i/f mailbox.

    -

    -FSL link for the write i/f mailbox.

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XMbox_Config::UseFSL u8 XMbox_Config::UseFSL
    -
    - - - - - -
    -   - + +
    +

    use the FSL for the interface.

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -use the FSL for the interface.

    -

    The documentation for this struct was generated from the following file:
      -
    • xmbox.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/tabs.css b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/tabs.css index a61552a6..a4441634 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/tabs.css +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/tabs.css @@ -32,7 +32,7 @@ DIV.tabs A float : left; background : url("tab_r.gif") no-repeat right top; border-bottom : 1px solid #84B0C7; - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -57,7 +57,7 @@ DIV.tabs SPAN white-space : nowrap; } -DIV.tabs INPUT +DIV.tabs #MSearchBox { float : right; display : inline; @@ -66,7 +66,7 @@ DIV.tabs INPUT DIV.tabs TD { - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -82,21 +82,24 @@ DIV.tabs A:hover SPAN background-position: 0% -150px; } -DIV.tabs LI#current A +DIV.tabs LI.current A { background-position: 100% -150px; border-width : 0px; } -DIV.tabs LI#current SPAN +DIV.tabs LI.current SPAN { background-position: 0% -150px; padding-bottom : 6px; } -DIV.nav +DIV.navpath { background : none; border : none; border-bottom : 1px solid #84B0C7; + text-align : center; + margin : 2px; + padding : 2px; } diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8c.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8c.html index 73edaea0..3181deed 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8c.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8c.html @@ -2,30 +2,56 @@ - xmbox.c File Reference + Xilinx Driver mbox v4_0: xmbox.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmbox.c File Reference

    Detailed Description

    -Contains required functions for the XMbox driver.

    + + +

    +
    +

    xmbox.c File Reference

    #include <string.h>
    +#include "xmbox.h"
    +#include "xil_assert.h"
    + + + + + + + + + + + + + + + + + +

    Functions

    int XMbox_CfgInitialize (XMbox *InstancePtr, XMbox_Config *ConfigPtr, u32 EffectiveAddress)
    int XMbox_Read (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesRecvdPtr)
    void XMbox_ReadBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    int XMbox_Write (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesSentPtr)
    void XMbox_WriteBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    u32 XMbox_IsEmpty (XMbox *InstancePtr)
    u32 XMbox_IsFull (XMbox *InstancePtr)
    int XMbox_Flush (XMbox *InstancePtr)
    void XMbox_SetInterruptEnable (XMbox *InstancePtr, u32 Mask)
    u32 XMbox_GetInterruptEnable (XMbox *InstancePtr)
    u32 XMbox_GetInterruptStatus (XMbox *InstancePtr)
    void XMbox_ClearInterrupt (XMbox *InstancePtr, u32 Mask)
    void XMbox_SetSendThreshold (XMbox *InstancePtr, u32 Value)
    void XMbox_SetReceiveThreshold (XMbox *InstancePtr, u32 Value)
    u32 XMbox_GetStatus (XMbox *InstancePtr)
    +

    Detailed Description

    +

    Contains required functions for the XMbox driver.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
@@ -43,737 +69,579 @@ Contains required functions for the XMbo
 			Removed _m from the function names.
 			Renamed _mIsEmpty to _IsEmptyHw and _mIsFull
 			to _IsFullHw.
- 3.02a bss  08/18/12   Added XMbox_GetStatus API for CR 676187

    -
    -

    -#include <string.h>
    -#include "xmbox.h"
    -#include "xil_assert.h"
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Functions

    int XMbox_CfgInitialize (XMbox *InstancePtr, XMbox_Config *ConfigPtr, u32 EffectiveAddress)
    int XMbox_Read (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesRecvdPtr)
    void XMbox_ReadBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    int XMbox_Write (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesSentPtr)
    void XMbox_WriteBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    u32 XMbox_IsEmpty (XMbox *InstancePtr)
    u32 XMbox_IsFull (XMbox *InstancePtr)
    int XMbox_Flush (XMbox *InstancePtr)
    void XMbox_SetInterruptEnable (XMbox *InstancePtr, u32 Mask)
    u32 XMbox_GetInterruptEnable (XMbox *InstancePtr)
    u32 XMbox_GetInterruptStatus (XMbox *InstancePtr)
    void XMbox_ClearInterrupt (XMbox *InstancePtr, u32 Mask)
    void XMbox_SetSendThreshold (XMbox *InstancePtr, u32 Value)
    void XMbox_SetReceiveThreshold (XMbox *InstancePtr, u32 Value)
    u32 XMbox_GetStatus (XMbox *InstancePtr)
    -

    Function Documentation

    -

    - - - - -
    - + 3.02a bss 08/18/12 Added XMbox_GetStatus API for CR 676187

    Function Documentation

    + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMbox_CfgInitialize ( XMbox *  InstancePtr, int XMbox_CfgInitialize (XMbox *  InstancePtr,
    XMbox_Config *  ConfigPtr, XMbox_Config *  ConfigPtr,
    u32  EffectiveAddressu32  EffectiveAddress 
    ) )
    -
    - - - - - -
    -   - - -

    -Initializes a specific mailbox.

    -

    Parameters:
    + +
    +

    Initializes a specific mailbox.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    CfgPtr is the device configuration structure containing required HW build data.
    EffectiveAddr is the Physical address of the hardware in a Virtual Memory operating system environment. It is the Base Address in a stand alone environment.
    +
    -
    Returns:
      -
    • XST_SUCCESS if initialization was successful
    +
    Returns:
      +
    • XST_SUCCESS if initialization was successful
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_ClearInterrupt ( XMbox *  InstancePtr, void XMbox_ClearInterrupt (XMbox *  InstancePtr,
    u32  Masku32  Mask 
    ) )
    -
    - - - - - -
    -   - - -

    -Clears pending interrupts with the provided mask. This function should be called after the software has serviced the interrupts that are pending. This function clears the corresponding bits of the Interrupt Status Register. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    -

    Parameters:
    + +
    +

    Clears pending interrupts with the provided mask. This function should be called after the software has serviced the interrupts that are pending. This function clears the corresponding bits of the Interrupt Status Register. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    Mask is a logical OR of XMB_IX_* constants found in xmbox_hw.h.
    +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    int XMbox_Flush ( XMbox *  InstancePtr  ) int XMbox_Flush (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Resets the mailbox FIFOs by empting the READ FIFO and making sure the Error Status is zero.

    -

    Parameters:
    + +
    +

    Resets the mailbox FIFOs by empting the READ FIFO and making sure the Error Status is zero.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    -
    Returns:
      -
    • XST_SUCCESS on success.
    • XST_FAILURE if there are any outstanding errors.
    +
    Returns:
      +
    • XST_SUCCESS on success.
      • +
    • XST_FAILURE if there are any outstanding errors.
      • +
    -
    Note:
    Data from read FIFO is thrown away.
    -
    -

    - - - - -
    - +
    Note:
    Data from read FIFO is thrown away.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    u32 XMbox_GetInterruptEnable ( XMbox *  InstancePtr  ) u32 XMbox_GetInterruptEnable (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Retrieves the interrupt enable for the mailbox. AND the result of this function with XMB_IX_* to determine which interrupts of this mailbox are enabled. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    -

    Parameters:
    + +
    +

    Retrieves the interrupt enable for the mailbox. AND the result of this function with XMB_IX_* to determine which interrupts of this mailbox are enabled. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    +
    -
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    u32 XMbox_GetInterruptStatus ( XMbox *  InstancePtr  ) u32 XMbox_GetInterruptStatus (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Retrieve the interrupt status for the mailbox. AND the results of this function with XMB_IX_* to determine which interrupts are currently pending to the processor. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    -

    Parameters:
    + +
    +

    Retrieve the interrupt status for the mailbox. AND the results of this function with XMB_IX_* to determine which interrupts are currently pending to the processor. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    +
    -
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    -
    -

    - - - - -
    - +
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    u32 XMbox_GetStatus ( XMbox *  InstancePtr  ) u32 XMbox_GetStatus (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Returns Status register contents. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    Parameters:
    + +
    +

    Returns Status register contents. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    +
    -
    Returns:
    Value returns Status Register contents.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    Value returns Status Register contents.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    u32 XMbox_IsEmpty ( XMbox *  InstancePtr  ) u32 XMbox_IsEmpty (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Checks to see if there is data available to be read.

    -

    Parameters:
    + +
    +

    Checks to see if there is data available to be read.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    -
    Returns:
      -
    • FALSE if there is data to be read.
    • TRUE is there no data to be read.
    +
    Returns:
      +
    • FALSE if there is data to be read.
      • +
    • TRUE is there no data to be read.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    u32 XMbox_IsFull ( XMbox *  InstancePtr  ) u32 XMbox_IsFull (XMbox *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Checks to see if there is room in the write FIFO.

    -

    Parameters:
    + +
    +

    Checks to see if there is room in the write FIFO.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    -
    Returns:
      -
    • FALSE if there is room in write FIFO.
    • TRUE if there is room in write FIFO.
    +
    Returns:
      +
    • FALSE if there is room in write FIFO.
      • +
    • TRUE if there is room in write FIFO.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMbox_Read ( XMbox *  InstancePtr, int XMbox_Read (XMbox *  InstancePtr,
    u32 *  BufferPtr, u32 *  BufferPtr,
    u32  RequestedBytes, u32  RequestedBytes,
    u32 *  BytesRecvdPtru32 *  BytesRecvdPtr 
    ) )
    -
    - - - - - -
    -   - - -

    -Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    -This function is non blocking.

    -

    Parameters:
    + +
    +

    Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +

    This function is non blocking.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the buffer to read the mailbox contents into, aligned to a word boundary.
    RequestedBytes is the number of bytes of data requested.
    BytesRecvdPtr is the memory that is updated with the number of bytes of data actually read.
    +
    -
    Returns:
      -
    • XST_SUCCESS on success.
    • XST_NO_DATA ifthere was no data in the mailbox.
    +
    Returns:
      +
    • XST_SUCCESS on success.
      • +
    • XST_NO_DATA ifthere was no data in the mailbox.
      • +
    -On success, the number of bytes read is returned through the pointer. The call may return with fewer bytes placed in the buffer than requested (not including zero). This is not necessarily an error condition and indicates the amount of data that was currently available in the mailbox.

    -

    Note:
    None.
    -
    -

    - - - - -
    - +

    On success, the number of bytes read is returned through the pointer. The call may return with fewer bytes placed in the buffer than requested (not including zero). This is not necessarily an error condition and indicates the amount of data that was currently available in the mailbox.

    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_ReadBlocking ( XMbox *  InstancePtr, void XMbox_ReadBlocking (XMbox *  InstancePtr,
    u32 *  BufferPtr, u32 *  BufferPtr,
    u32  RequestedBytesu32  RequestedBytes 
    ) )
    -
    - - - - - -
    -   - - -

    -Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    -

    Parameters:
    + +
    +

    Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the buffer to read the mailbox contents into, aligned to a word boundary.
    RequestedBytes is the number of bytes of data requested.
    +
    -
    Returns:
    None.
    -
    Note:
    The call blocks until the number of bytes requested are available.
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    The call blocks until the number of bytes requested are available.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_SetInterruptEnable ( XMbox *  InstancePtr, void XMbox_SetInterruptEnable (XMbox *  InstancePtr,
    u32  Masku32  Mask 
    ) )
    -
    - - - - - -
    -   - - -

    -Sets the interrupt enable register for this mailbox. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    -

    Parameters:
    + +
    +

    Sets the interrupt enable register for this mailbox. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    Mask is a logical OR of XMB_IX_* constants found in xmbox_hw.h.
    +
    -
    Returns:
    None.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_SetReceiveThreshold ( XMbox *  InstancePtr, void XMbox_SetReceiveThreshold (XMbox *  InstancePtr,
    u32  Valueu32  Value 
    ) )
    -
    - - - - - -
    -   - - -

    -Set the Receive Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    Parameters:
    + +
    +

    Set the Receive Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    Value is a value to set for the RIT. Only lower Log2(FIFO Depth) bits are used.
    +
    -
    Returns:
    None.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_SetSendThreshold ( XMbox *  InstancePtr, void XMbox_SetSendThreshold (XMbox *  InstancePtr,
    u32  Valueu32  Value 
    ) )
    -
    - - - - - -
    -   - - -

    -Sets the Send Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    -

    Parameters:
    + +
    +

    Sets the Send Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the instance to be worked on.
    Value is a value to set for the SIT. Only lower Log2(FIFO Depth) bits are used.
    +
    -
    Returns:
    None.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMbox_Write ( XMbox *  InstancePtr, int XMbox_Write (XMbox *  InstancePtr,
    u32 *  BufferPtr, u32 *  BufferPtr,
    u32  RequestedBytes, u32  RequestedBytes,
    u32 *  BytesSentPtru32 *  BytesSentPtr 
    ) )
    -
    - - - - - -
    -   - - -

    -Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr.The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    -This function is non blocking.

    -

    Parameters:
    + +
    +

    Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr.The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +

    This function is non blocking.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the source data buffer, aligned to a word boundary.
    RequestedBytes is the number of bytes requested to be written.
    BytesRecvdPtr points to memory which is updated with the actual number of bytes written, return value.
    +
    -
    Returns:
    +
    Returns:
      -
    • XST_SUCCESS on success.
    • XST_FIFO_NO_ROOM if the fifo was full.
    -

    -On success, the number of bytes successfully written into the destination mailbox is returned in the provided pointer. The call may return with zero. This is not necessarily an error condition and indicates that the mailbox is currently full.

    -

    Note:
    The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    -
    -

    - - - - -
    - +
  • XST_SUCCESS on success.
    • +
  • XST_FIFO_NO_ROOM if the fifo was full.
    • + +

    On success, the number of bytes successfully written into the destination mailbox is returned in the provided pointer. The call may return with zero. This is not necessarily an error condition and indicates that the mailbox is currently full.

    +
    Note:
    The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    void XMbox_WriteBlocking ( XMbox *  InstancePtr, void XMbox_WriteBlocking (XMbox *  InstancePtr,
    u32 *  BufferPtr, u32 *  BufferPtr,
    u32  RequestedBytesu32  RequestedBytes 
    ) )
    -
    - - - - - -
    -   - - -

    -Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    -

    Parameters:
    + +
    +

    Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +
    Parameters:
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the source data buffer, aligned to a word boundary.
    RequestedBytes is the number of bytes requested to be written.
    +
    -
    Returns:
    None.
    -
    Note:
    The call blocks until the number of bytes requested are written. The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Returns:
    None.
    +
    Note:
    The call blocks until the number of bytes requested are written. The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8h.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8h.html new file mode 100755 index 00000000..e58b39d2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox_8h.html @@ -0,0 +1,664 @@ + + + + + Xilinx Driver mbox v4_0: xmbox.h File Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    xmbox.h File Reference

    #include "xstatus.h"
    +#include "xmbox_hw.h"
    + + + + + + + + + + + + + + + + + + + + + + + +

    Classes

    struct  XMbox_Config
    struct  XMbox

    Defines

    #define XMBOX_H

    Functions

    int XMbox_CfgInitialize (XMbox *InstancePtr, XMbox_Config *ConfigPtr, u32 EffectiveAddress)
    int XMbox_Read (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesRecvdPtr)
    void XMbox_ReadBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    int XMbox_Write (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes, u32 *BytesSentPtr)
    void XMbox_WriteBlocking (XMbox *InstancePtr, u32 *BufferPtr, u32 RequestedBytes)
    u32 XMbox_IsEmpty (XMbox *InstancePtr)
    u32 XMbox_IsFull (XMbox *InstancePtr)
    int XMbox_Flush (XMbox *InstancePtr)
    void XMbox_SetInterruptEnable (XMbox *InstancePtr, u32 Mask)
    u32 XMbox_GetInterruptEnable (XMbox *InstancePtr)
    u32 XMbox_GetInterruptStatus (XMbox *InstancePtr)
    void XMbox_ClearInterrupt (XMbox *InstancePtr, u32 Mask)
    u32 XMbox_GetStatus (XMbox *InstancePtr)
    void XMbox_SetSendThreshold (XMbox *InstancePtr, u32 Value)
    void XMbox_SetReceiveThreshold (XMbox *InstancePtr, u32 Value)
    XMbox_Config * XMbox_LookupConfig (u16 DeviceId)
    +

    Detailed Description

    +

    Define Documentation

    + +
    +
    + + + + +
    #define XMBOX_H
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMbox_CfgInitialize (XMbox *  InstancePtr,
    XMbox_Config *  ConfigPtr,
    u32  EffectiveAddress 
    )
    +
    +
    +

    Initializes a specific mailbox.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    CfgPtr is the device configuration structure containing required HW build data.
    EffectiveAddr is the Physical address of the hardware in a Virtual Memory operating system environment. It is the Base Address in a stand alone environment.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if initialization was successful
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void XMbox_ClearInterrupt (XMbox *  InstancePtr,
    u32  Mask 
    )
    +
    +
    +

    Clears pending interrupts with the provided mask. This function should be called after the software has serviced the interrupts that are pending. This function clears the corresponding bits of the Interrupt Status Register. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the instance to be worked on.
    Mask is a logical OR of XMB_IX_* constants found in xmbox_hw.h.
    +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + +
    int XMbox_Flush (XMbox *  InstancePtr ) 
    +
    +
    +

    Resets the mailbox FIFOs by empting the READ FIFO and making sure the Error Status is zero.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS on success.
      • +
    • XST_FAILURE if there are any outstanding errors.
      • +
    +
    +
    Note:
    Data from read FIFO is thrown away.
    + +
    +
    + +
    +
    + + + + + + + + + +
    u32 XMbox_GetInterruptEnable (XMbox *  InstancePtr ) 
    +
    +
    +

    Retrieves the interrupt enable for the mailbox. AND the result of this function with XMB_IX_* to determine which interrupts of this mailbox are enabled. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the instance to be worked on.
    +
    +
    +
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + +
    u32 XMbox_GetInterruptStatus (XMbox *  InstancePtr ) 
    +
    +
    +

    Retrieve the interrupt status for the mailbox. AND the results of this function with XMB_IX_* to determine which interrupts are currently pending to the processor. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the instance to be worked on.
    +
    +
    +
    Returns:
    Mask of interrupt bits made up of XMB_IX_* constants found in xmbox_hw.h.
    + +
    +
    + +
    +
    + + + + + + + + + +
    u32 XMbox_GetStatus (XMbox *  InstancePtr ) 
    +
    +
    +

    Returns Status register contents. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the instance to be worked on.
    +
    +
    +
    Returns:
    Value returns Status Register contents.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + +
    u32 XMbox_IsEmpty (XMbox *  InstancePtr ) 
    +
    +
    +

    Checks to see if there is data available to be read.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    +
    +
    Returns:
      +
    • FALSE if there is data to be read.
      • +
    • TRUE is there no data to be read.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + +
    u32 XMbox_IsFull (XMbox *  InstancePtr ) 
    +
    +
    +

    Checks to see if there is room in the write FIFO.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    +
    +
    +
    Returns:
      +
    • FALSE if there is room in write FIFO.
      • +
    • TRUE if there is room in write FIFO.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + +
    XMbox_Config* XMbox_LookupConfig (u16  DeviceId ) 
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMbox_Read (XMbox *  InstancePtr,
    u32 *  BufferPtr,
    u32  RequestedBytes,
    u32 *  BytesRecvdPtr 
    )
    +
    +
    +

    Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +

    This function is non blocking.

    +
    Parameters:
    + + + + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the buffer to read the mailbox contents into, aligned to a word boundary.
    RequestedBytes is the number of bytes of data requested.
    BytesRecvdPtr is the memory that is updated with the number of bytes of data actually read.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS on success.
      • +
    • XST_NO_DATA ifthere was no data in the mailbox.
      • +
    +
    +

    On success, the number of bytes read is returned through the pointer. The call may return with fewer bytes placed in the buffer than requested (not including zero). This is not necessarily an error condition and indicates the amount of data that was currently available in the mailbox.

    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    void XMbox_ReadBlocking (XMbox *  InstancePtr,
    u32 *  BufferPtr,
    u32  RequestedBytes 
    )
    +
    +
    +

    Reads requested bytes from the mailbox referenced by InstancePtr,into the buffer pointed to by the provided pointer. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the buffer to read the mailbox contents into, aligned to a word boundary.
    RequestedBytes is the number of bytes of data requested.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    The call blocks until the number of bytes requested are available.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void XMbox_SetInterruptEnable (XMbox *  InstancePtr,
    u32  Mask 
    )
    +
    +
    +

    Sets the interrupt enable register for this mailbox. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the instance to be worked on.
    Mask is a logical OR of XMB_IX_* constants found in xmbox_hw.h.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void XMbox_SetReceiveThreshold (XMbox *  InstancePtr,
    u32  Value 
    )
    +
    +
    +

    Set the Receive Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the instance to be worked on.
    Value is a value to set for the RIT. Only lower Log2(FIFO Depth) bits are used.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void XMbox_SetSendThreshold (XMbox *  InstancePtr,
    u32  Value 
    )
    +
    +
    +

    Sets the Send Interrupt Threshold. This function can only be used for Non-FSL interface. If not, the function will fail in an assert.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the instance to be worked on.
    Value is a value to set for the SIT. Only lower Log2(FIFO Depth) bits are used.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMbox_Write (XMbox *  InstancePtr,
    u32 *  BufferPtr,
    u32  RequestedBytes,
    u32 *  BytesSentPtr 
    )
    +
    +
    +

    Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr.The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +

    This function is non blocking.

    +
    Parameters:
    + + + + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the source data buffer, aligned to a word boundary.
    RequestedBytes is the number of bytes requested to be written.
    BytesRecvdPtr points to memory which is updated with the actual number of bytes written, return value.
    +
    +
    +
    Returns:
    +
      +
    • XST_SUCCESS on success.
      • +
    • XST_FIFO_NO_ROOM if the fifo was full.
      • +
    +

    On success, the number of bytes successfully written into the destination mailbox is returned in the provided pointer. The call may return with zero. This is not necessarily an error condition and indicates that the mailbox is currently full.

    +
    Note:
    The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    void XMbox_WriteBlocking (XMbox *  InstancePtr,
    u32 *  BufferPtr,
    u32  RequestedBytes 
    )
    +
    +
    +

    Writes the requested bytes from the buffer pointed to by the provided pointer into the mailbox referenced by InstancePtr. The number of bytes must be a multiple of 4 (bytes). If not, the call will fail in an assert.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMbox instance to be worked on.
    BufferPtr is the source data buffer, aligned to a word boundary.
    RequestedBytes is the number of bytes requested to be written.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    The call blocks until the number of bytes requested are written. The provided buffer pointed to by BufferPtr must be aligned to a word boundary.
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__g_8c.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__g_8c.html index ffdf5f36..d85b95b3 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__g_8c.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__g_8c.html @@ -2,39 +2,72 @@ - xmbox_g.c File Reference + Xilinx Driver mbox v4_0: xmbox_g.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmbox_g.c File Reference

    Detailed Description

    -This file contains a configuration table that specifies the configuration of Mbox devices in the system.

    + + +

    +
    +

    xmbox_g.c File Reference

    #include "xmbox.h"
    +#include "xparameters.h"
    + + + +

    Variables

    XMbox_Config XMbox_ConfigTable []
    +

    Detailed Description

    +

    This file contains a configuration table that specifies the configuration of Mbox devices in the system.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- ---------------------------------------------------
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
-

    -

    Note:
    -None. -

    -#include "xmbox.h"
    -#include "xparameters.h"
    - - -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Note:
    +

    None.

    +

    Variable Documentation

    + +
    +
    + + + + +
    XMbox_Config XMbox_ConfigTable[]
    +
    +
    +Initial value:
    +{
+        {
+                XPAR_XMBOX_0_DEVICE_ID,
+                XPAR_XMBOX_0_BASEADDR,
+                XPAR_XMBOX_0_USE_FSL,
+                XPAR_XMBOX_0_SEND_ID,
+                XPAR_XMBOX_0_RECV_ID
+        }
+}
+
    +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__hw_8h.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__hw_8h.html index cda2db4d..33ec6b80 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__hw_8h.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__hw_8h.html @@ -2,30 +2,80 @@ - xmbox_hw.h File Reference + Xilinx Driver mbox v4_0: xmbox_hw.h File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmbox_hw.h File Reference

    Detailed Description

    -This header file contains identifiers and driver macros that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation. The driver functions/APIs are defined in xmbox.h.

    + + +

    +
    +

    xmbox_hw.h File Reference

    #include "xil_io.h"
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Defines

    #define XMBOX_HW_H
    #define XMbox_ReadReg(BaseAddress, RegOffset)   Xil_In32((BaseAddress) + (RegOffset))
    #define XMbox_WriteReg(BaseAddress, RegOffset, ValueToWrite)   Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))
    #define XMbox_WriteMBox(BaseAddress, ValueToWrite)   XMbox_WriteReg (BaseAddress, XMB_WRITE_REG_OFFSET, ValueToWrite)
    #define XMbox_ReadMBox(BaseAddress)   XMbox_ReadReg (BaseAddress, XMB_READ_REG_OFFSET)
    #define XMbox_IsEmptyHw(BaseAddress)   ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_EMPTY))
    #define XMbox_IsFullHw(BaseAddress)   ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_FULL))
    #define XMbox_FSLReadMBox(ID)   0
    #define XMbox_FSLWriteMBox(ID, ValueToWrite)
    #define XMbox_FSLIsEmpty(ID)   0
    #define XMbox_FSLIsFull(ID)   0
    Register Offset Definitions

    Register offsets within a mbox.

    +

    #define XMB_WRITE_REG_OFFSET   0x00
    #define XMB_READ_REG_OFFSET   0x08
    #define XMB_STATUS_REG_OFFSET   0x10
    #define XMB_ERROR_REG_OFFSET   0x14
    #define XMB_SIT_REG_OFFSET   0x18
    #define XMB_RIT_REG_OFFSET   0x1C
    #define XMB_IS_REG_OFFSET   0x20
    #define XMB_IE_REG_OFFSET   0x24
    #define XMB_IP_REG_OFFSET   0x28
    Status register bit definitions

    These status bits are used to poll the FIFOs

    +

    #define XMB_STATUS_FIFO_EMPTY   0x00000001
    #define XMB_STATUS_FIFO_FULL   0x00000002
    #define XMB_STATUS_STA   0x00000004
    #define XMB_STATUS_RTA   0x00000008
    Interrupt Registers(s) bits definitions.

    The IS, IE, and IP registers all have the same bit definition.

    +

    #define XMB_IX_STA   0x01
    #define XMB_IX_RTA   0x02
    #define XMB_IX_ERR   0x04
    Error bits definition.

    +

    #define XMB_ERROR_FIFO_EMPTY   0x00000001
    #define XMB_ERROR_FIFO_FULL   0x00000002
    +

    Detailed Description

    +

    This header file contains identifiers and driver macros that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation. The driver functions/APIs are defined in xmbox.h.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date       Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date       Changes
  ----- ---- --------   -----------------------------------------------
  1.00a va              First release
  1.00a ecm  06/01/07   Cleanup, new coding standard, check into XCS
@@ -41,717 +91,546 @@ This header file contains identifiers and driver macros that can be used to acce
 			Removed _m from the function names.
 			Renamed _mIsEmpty to _IsEmptyHw and _mIsFull
 			to _IsFullHw.
-
    -

    -#include "xil_io.h"
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Register Offset Definitions

    Register offsets within a mbox.

    #define XMB_WRITE_REG_OFFSET   0x00
    #define XMB_READ_REG_OFFSET   0x08
    #define XMB_STATUS_REG_OFFSET   0x10
    #define XMB_ERROR_REG_OFFSET   0x14
    #define XMB_SIT_REG_OFFSET   0x18
    #define XMB_RIT_REG_OFFSET   0x1C
    #define XMB_IS_REG_OFFSET   0x20
    #define XMB_IE_REG_OFFSET   0x24
    #define XMB_IP_REG_OFFSET   0x28

    Status register bit definitions

    These status bits are used to poll the FIFOs

    #define XMB_STATUS_FIFO_EMPTY   0x00000001
    #define XMB_STATUS_FIFO_FULL   0x00000002
    #define XMB_STATUS_STA   0x00000004
    #define XMB_STATUS_RTA   0x00000008

    Interrupt Registers(s) bits definitions.

    The IS, IE, and IP registers all have the same bit definition.

    #define XMB_IX_STA   0x01
    #define XMB_IX_RTA   0x02
    #define XMB_IX_ERR   0x04

    Error bits definition.

    #define XMB_ERROR_FIFO_EMPTY   0x00000001
    #define XMB_ERROR_FIFO_FULL   0x00000002

    Defines

    #define XMbox_ReadReg(BaseAddress, RegOffset)   Xil_In32((BaseAddress) + (RegOffset))
    #define XMbox_WriteReg(BaseAddress, RegOffset, ValueToWrite)   Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))
    #define XMbox_WriteMBox(BaseAddress, ValueToWrite)   XMbox_WriteReg (BaseAddress, XMB_WRITE_REG_OFFSET, ValueToWrite)
    #define XMbox_ReadMBox(BaseAddress)   XMbox_ReadReg (BaseAddress, XMB_READ_REG_OFFSET)
    #define XMbox_IsEmptyHw(BaseAddress)   ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_EMPTY))
    #define XMbox_IsFullHw(BaseAddress)   ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_FULL))
    -

    Define Documentation

    -

    - - - - -
    - +

    Define Documentation

    + +
    +
    +
    - +
    #define XMB_ERROR_FIFO_EMPTY   0x00000001 #define XMB_ERROR_FIFO_EMPTY   0x00000001
    -
    - - - - - -
    -   - + +
    +

    Receive FIFO is Empty

    -

    -Receive FIFO is Empty

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_ERROR_FIFO_FULL   0x00000002 #define XMB_ERROR_FIFO_FULL   0x00000002
    -
    - - - - - -
    -   - + +
    +

    Send FIFO is Full

    -

    -Send FIFO is Full

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_ERROR_REG_OFFSET   0x14 #define XMB_ERROR_REG_OFFSET   0x14
    -
    - - - - - -
    -   - + +
    +

    Mbox Error reg

    -

    -Mbox Error reg

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IE_REG_OFFSET   0x24 #define XMB_IE_REG_OFFSET   0x24
    -
    - - - - - -
    -   - + +
    +

    Mbox interrupt enable register

    -

    -Mbox interrupt enable register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IP_REG_OFFSET   0x28 #define XMB_IP_REG_OFFSET   0x28
    -
    - - - - - -
    -   - + +
    +

    Mbox interrupt pending register

    -

    -Mbox interrupt pending register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IS_REG_OFFSET   0x20 #define XMB_IS_REG_OFFSET   0x20
    -
    - - - - - -
    -   - + +
    +

    Mbox interrupt status register

    -

    -Mbox interrupt status register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IX_ERR   0x04 #define XMB_IX_ERR   0x04
    -
    - - - - - -
    -   - + +
    +

    Mailbox Error, when read on empty or write on full

    -

    -Mailbox Error, when read on empty or write on full

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IX_RTA   0x02 #define XMB_IX_RTA   0x02
    -
    - - - - - -
    -   - + +
    +

    Receive Threshold Active, when the number of Receive FIFO entries is greater than Receive Interrupt Threshold

    -

    -Receive Threshold Active, when the number of Receive FIFO entries is greater than Receive Interrupt Threshold

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_IX_STA   0x01 #define XMB_IX_STA   0x01
    -
    - - - - - -
    -   - + +
    +

    Send Threshold Active, when the number of Send FIFO entries is less than and equal to Send Interrupt Threshold

    -

    -Send Threshold Active, when the number of Send FIFO entries is less than and equal to Send Interrupt Threshold

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_READ_REG_OFFSET   0x08 #define XMB_READ_REG_OFFSET   0x08
    -
    - - - - - -
    -   - + +
    +

    Mbox read register

    -

    -Mbox read register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_RIT_REG_OFFSET   0x1C #define XMB_RIT_REG_OFFSET   0x1C
    -
    - - - - - -
    -   - + +
    +

    Mbox receive interrupt threshold register

    -

    -Mbox receive interrupt threshold register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_SIT_REG_OFFSET   0x18 #define XMB_SIT_REG_OFFSET   0x18
    -
    - - - - - -
    -   - + +
    +

    Mbox send interrupt threshold register

    -

    -Mbox send interrupt threshold register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_STATUS_FIFO_EMPTY   0x00000001 #define XMB_STATUS_FIFO_EMPTY   0x00000001
    -
    - - - - - -
    -   - + +
    +

    Receive FIFO is Empty

    -

    -Receive FIFO is Empty

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_STATUS_FIFO_FULL   0x00000002 #define XMB_STATUS_FIFO_FULL   0x00000002
    -
    - - - - - -
    -   - + +
    +

    Send FIFO is Full

    -

    -Send FIFO is Full

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_STATUS_REG_OFFSET   0x10 #define XMB_STATUS_REG_OFFSET   0x10
    -
    - - - - - -
    -   - + +
    +

    Mbox status reg

    -

    -Mbox status reg

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_STATUS_RTA   0x00000008 #define XMB_STATUS_RTA   0x00000008
    -
    - - - - - -
    -   - + +
    +

    Receive FIFO Threshold Status

    -

    -Receive FIFO Threshold Status

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_STATUS_STA   0x00000004 #define XMB_STATUS_STA   0x00000004
    -
    - - - - - -
    -   - + +
    +

    Send FIFO Threshold Status

    -

    -Send FIFO Threshold Status

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMB_WRITE_REG_OFFSET   0x00 #define XMB_WRITE_REG_OFFSET   0x00
    -
    - - - - - -
    -   - + +
    +

    Mbox write register

    -

    -Mbox write register

    -

    - - - - -
    - + + + +
    +
    +
    - - - - - - + + + + + +
    #define XMbox_IsEmptyHw ( BaseAddress   )    ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_EMPTY))#define XMbox_FSLIsEmpty(ID  )    0
    -
    - - - - - -
    -   - + +
    -

    -Checks if the Read FIFO is Empty.

    -

    Parameters:
    +
    + + +
    +
    + + + + + + + + + +
    #define XMbox_FSLIsFull(ID  )    0
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + +
    #define XMbox_FSLReadMBox(ID  )    0
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + +
    #define XMbox_FSLWriteMBox(ID,
    ValueToWrite  ) 
    +
    +
    + +
    +
    + +
    +
    + + + + +
    #define XMBOX_HW_H
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + +
    #define XMbox_IsEmptyHw(BaseAddress  )    ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_EMPTY))
    +
    +
    +

    Checks if the Read FIFO is Empty.

    +
    Parameters:
    BaseAddress contains the base address of the mbox device.
    +
    -
    Returns:
      -
    • TRUE if the FIFO is empty.
    • FALSE if there is data to be read from the FIFO.
    +
    Returns:
      +
    • TRUE if the FIFO is empty.
      • +
    • FALSE if there is data to be read from the FIFO.
      • +
    -
    Note:
    C-style signature: u32 XMbox_IsEmptyHw(u32 BaseAddress);
    -
    -

    - - - - -
    - +
    Note:
    C-style signature: u32 XMbox_IsEmptyHw(u32 BaseAddress);
    + + + + +
    +
    +
    - - - - - - + + + + + +
    #define XMbox_IsFullHw ( BaseAddress   )    ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_FULL))#define XMbox_IsFullHw(BaseAddress  )    ((XMbox_ReadReg (BaseAddress, XMB_STATUS_REG_OFFSET) & XMB_STATUS_FIFO_FULL))
    -
    - - - - - -
    -   - - -

    -Checks if there is room in the Write FIFO.

    -

    Parameters:
    + +
    +

    Checks if there is room in the Write FIFO.

    +
    Parameters:
    BaseAddress contains the base address of the mbox device.
    +
    -
    Returns:
      -
    • FALSE if there is room in FIFO,
    • TRUE if there is no room in the FIFO
    +
    Returns:
      +
    • FALSE if there is room in FIFO,
      • +
    • TRUE if there is no room in the FIFO
      • +
    -
    Note:
    C-style signature: u32 XMbox_IsFullHw(u32 BaseAddress);
    -
    -

    - - - - -
    - +
    Note:
    C-style signature: u32 XMbox_IsFullHw(u32 BaseAddress);
    + + + + +
    +
    +
    - - - - - - + + + + + +
    #define XMbox_ReadMBox ( BaseAddress   )    XMbox_ReadReg (BaseAddress, XMB_READ_REG_OFFSET)#define XMbox_ReadMBox(BaseAddress  )    XMbox_ReadReg (BaseAddress, XMB_READ_REG_OFFSET)
    -
    - - - - - -
    -   - - -

    -Read the mbox read FIFO.

    -

    Parameters:
    + +
    +

    Read the mbox read FIFO.

    +
    Parameters:
    BaseAddress contains the base address of the mbox device.
    +
    -
    Returns:
    The value read from the register, a 32 bit value.
    -
    Note:
    C-style signature: u32 XMbox_ReadMBox(u32 BaseAddress);
    -
    -

    - - - - -
    - +
    Returns:
    The value read from the register, a 32 bit value.
    +
    Note:
    C-style signature: u32 XMbox_ReadMBox(u32 BaseAddress);
    + + + + +
    +
    +
    - - - - - - - - - + + + + + + + + + + +
    #define XMbox_ReadReg ( BaseAddress,
    RegOffset   )    Xil_In32((BaseAddress) + (RegOffset))#define XMbox_ReadReg(BaseAddress,
    RegOffset  )    Xil_In32((BaseAddress) + (RegOffset))
    -
    - - - - - -
    -   - - -

    -Read one of the mbox registers.

    -

    Parameters:
    + +
    +

    Read one of the mbox registers.

    +
    Parameters:
    BaseAddress contains the base address of the mbox device.
    RegOffset contains the offset from the 1st register of the mbox to select the specific register of the mbox.
    +
    -
    Returns:
    The value read from the register, a 32 bit value.
    -
    Note:
    C-style signature: u32 XMbox_ReadReg(u32 BaseAddress, unsigned RegOffset);
    -
    -

    - - - - -
    - +
    Returns:
    The value read from the register, a 32 bit value.
    +
    Note:
    C-style signature: u32 XMbox_ReadReg(u32 BaseAddress, unsigned RegOffset);
    + + + + +
    +
    +
    - - - - - - - - - + + + + + + + + + + +
    #define XMbox_WriteMBox ( BaseAddress,
    ValueToWrite   )    XMbox_WriteReg (BaseAddress, XMB_WRITE_REG_OFFSET, ValueToWrite)#define XMbox_WriteMBox(BaseAddress,
    ValueToWrite  )    XMbox_WriteReg (BaseAddress, XMB_WRITE_REG_OFFSET, ValueToWrite)
    -
    - - - - - -
    -   - - -

    -Write the mbox write register.

    -

    Parameters:
    + +
    +

    Write the mbox write register.

    +
    Parameters:
    BaseAddress contains the base address of the mbox device.
    ValueToWrite contains the value to be written.
    +
    -
    Returns:
    None.
    -
    Note:
    C-style signature: u32 XMbox_WriteMBox(u32 BaseAddress, u32 ValueToWrite);
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    C-style signature: u32 XMbox_WriteMBox(u32 BaseAddress, u32 ValueToWrite);
    + + + + +
    +
    +
    - - - - - - - - - - - - + + + + + + + + + + + + + + + +
    #define XMbox_WriteReg ( BaseAddress,
    RegOffset,
    ValueToWrite   )    Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))#define XMbox_WriteReg(BaseAddress,
    RegOffset,
    ValueToWrite  )    Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))
    -
    - - - - - -
    -   - - -

    -Write a specified value to a register of a mbox.

    -

    Parameters:
    + +
    +

    Write a specified value to a register of a mbox.

    +
    Parameters:
    BaseAddress is the base address of the mbox device.
    RegOffset contain the offset from the 1st register of the mbox to select the specific register of the mbox.
    ValueToWrite is the 32 bit value to be written to the register.
    +
    -
    Returns:
    None
    -
    Note:
    C-style signature: void XMbox_WriteReg(u32 BaseAddress, unsigned RegOffset, u32 ValueToWrite);
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Returns:
    None
    +
    Note:
    C-style signature: void XMbox_WriteReg(u32 BaseAddress, unsigned RegOffset, u32 ValueToWrite);
    + +
    +
    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__sinit_8c.html b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__sinit_8c.html index 5f00dc0f..4f199c7f 100755 --- a/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__sinit_8c.html +++ b/XilinxProcessorIPLib/drivers/mbox/doc/html/api/xmbox__sinit_8c.html @@ -2,37 +2,80 @@ - xmbox_sinit.c File Reference + Xilinx Driver mbox v4_0: xmbox_sinit.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmbox_sinit.c File Reference

    Detailed Description

    -Implements static initialization See xmbox.h for more information about the component.

    -

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
- ----- ---- -------- ---------------------------------------------------
- 1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS

    -
    -

    -#include "xmbox.h"
    -#include "xparameters.h"
    + + +

    +
    +

    xmbox_sinit.c File Reference

    #include "xmbox.h"
    +#include "xparameters.h"
    - + + + +

    Functions

    XMbox_Config * XMbox_LookupConfig (u16 DeviceId)

    Variables

    XMbox_Config XMbox_ConfigTable []
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Detailed Description

    +

    Implements static initialization See xmbox.h for more information about the component.

    +
    + MODIFICATION HISTORY:
     Ver   Who  Date     Changes
+ ----- ---- -------- ---------------------------------------------------
+ 1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS

    Function Documentation

    + +
    +
    + + + + + + + + + +
    XMbox_Config* XMbox_LookupConfig (u16  DeviceId ) 
    +
    +
    + +
    +
    +

    Variable Documentation

    + +
    +
    + + + + +
    XMbox_Config XMbox_ConfigTable[]
    +
    +
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/files.html new file mode 100755 index 00000000..d5381971 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/files.html @@ -0,0 +1,36 @@ + + + + + Xilinx Driver mig_7series v2_0: File Index + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    File List

    Here is a list of all files with brief descriptions: + +
    xmig_7series.h
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/index.html index 5f2fdc17..7efd2a35 100755 --- a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/index.html @@ -2,18 +2,28 @@ - mig_7series v2_0 + Xilinx Driver mig_7series v2_0: mig_7series v2_0 - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -

    mig_7series v2_0

    -

    -This driver exists only to allow the SDK tools to create a memory test application and to populate xparameters.h with memory range constants. There is no source code. VER WHO DATE Changes 2.0 adk 19/12/13 Updated as per the New Tcl API's Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    mig_7series v2_0

    This driver exists only to allow the SDK tools to create a memory test application and to populate xparameters.h with memory range constants. There is no source code. VER WHO DATE Changes 2.0 adk 19/12/13 Updated as per the New Tcl API's

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/tabs.css b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/tabs.css index a61552a6..a4441634 100755 --- a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/tabs.css +++ b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/tabs.css @@ -32,7 +32,7 @@ DIV.tabs A float : left; background : url("tab_r.gif") no-repeat right top; border-bottom : 1px solid #84B0C7; - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -57,7 +57,7 @@ DIV.tabs SPAN white-space : nowrap; } -DIV.tabs INPUT +DIV.tabs #MSearchBox { float : right; display : inline; @@ -66,7 +66,7 @@ DIV.tabs INPUT DIV.tabs TD { - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -82,21 +82,24 @@ DIV.tabs A:hover SPAN background-position: 0% -150px; } -DIV.tabs LI#current A +DIV.tabs LI.current A { background-position: 100% -150px; border-width : 0px; } -DIV.tabs LI#current SPAN +DIV.tabs LI.current SPAN { background-position: 0% -150px; padding-bottom : 6px; } -DIV.nav +DIV.navpath { background : none; border : none; border-bottom : 1px solid #84B0C7; + text-align : center; + margin : 2px; + padding : 2px; } diff --git a/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/xmig__7series_8h.html b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/xmig__7series_8h.html new file mode 100755 index 00000000..016dfdc2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mig_7series/doc/html/api/xmig__7series_8h.html @@ -0,0 +1,36 @@ + + + + + Xilinx Driver mig_7series v2_0: xmig_7series.h File Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    xmig_7series.h File Reference

    +
    +

    Detailed Description

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/annotated.html index 742c2d47..2a90693d 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/annotated.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/annotated.html @@ -2,27 +2,38 @@ - Class List + Xilinx Driver mutex v4_0: Class List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    + + + +

    Class List

    Here are the classes, structs, unions and interfaces with brief descriptions:
    XMutex
    XMutex_Config
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/classes.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/classes.html new file mode 100755 index 00000000..5ba2c35b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/classes.html @@ -0,0 +1,39 @@ + + + + + Xilinx Driver mutex v4_0: Alphabetical List + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    Class Index

    X
    + +
      X  
    +    		XMutex   XMutex_Config   
    X
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/files.html index 1469c61f..c4f20d8e 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/files.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/files.html @@ -2,30 +2,42 @@ - File Index + Xilinx Driver mutex v4_0: File Index - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    File List

    Here is a list of all documented files with brief descriptions: + + + +
    +

    File List

    Here is a list of all files with brief descriptions:
    +
    xmutex.c
    xmutex.h
    xmutex_g.c
    xmutex_hw.h
    xmutex_selftest.c
    xmutex_sinit.c
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions.html index b290c679..2a409c62 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions.html @@ -2,39 +2,60 @@ - Class Members + Xilinx Driver mutex v4_0: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -Here is a list of all documented class members with links to the class documentation for each member: -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions_vars.html index 224ef563..8aadcbe7 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions_vars.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/functions_vars.html @@ -2,39 +2,60 @@ - Class Members - Variables + Xilinx Driver mutex v4_0: Class Members - Variables - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals.html index 8e3629af..6846f734 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals.html @@ -2,50 +2,138 @@ - Class Members + Xilinx Driver mutex v4_0: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -Here is a list of all documented file members with links to the documentation: -

    -

    + + +

    - o -

    + + +

    - x -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_defs.html index 2d89a67a..a73edb97 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_defs.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_defs.html @@ -2,41 +2,77 @@ - Class Members + Xilinx Driver mutex v4_0: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_func.html index 1742825c..75d33134 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_func.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_func.html @@ -2,43 +2,84 @@ - Class Members + Xilinx Driver mutex v4_0: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_vars.html new file mode 100755 index 00000000..cfea9162 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/globals_vars.html @@ -0,0 +1,49 @@ + + + + + Xilinx Driver mutex v4_0: Class Members + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +  +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/index.html index 7aec4fce..f66af8dd 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/index.html @@ -2,40 +2,46 @@ - mutex v4_0 + Xilinx Driver mutex v4_0: mutex v4_0 - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -

    mutex v4_0

    -

    -The Xilinx Mutex driver. This driver supports the Xilinx Mutex Core. More detailed description of the driver operation can be found in the xmutex.c file.

    -Features

    -The Xilinx Mutex supports the following features:

    -

    -This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver. The effective address provided to the XMutex_CfgInitialize() function can be either the real, physical address or the remapped virtual address. The remapping of this address occurs above this driver, no remapping occurs within the driver itself.

    -Initialization & Configuration

    -The XMutex_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

    -To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

    + + +

    +
    +

    mutex v4_0

    The Xilinx Mutex driver. This driver supports the Xilinx Mutex Core. More detailed description of the driver operation can be found in the xmutex.c file.

    +

    Features

    +

    The Xilinx Mutex supports the following features:

      -
    • XMutex_LookupConfig (DeviceId) - Use the device identifier to find the static configuration structure defined in XMutex_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed. This function returns the CfgPtr argument used by the CfgInitialize function described below.
    -

    +

  • Provide for synchronization between multiple processors in the system.
    • +
  • Write to lock scheme with CPU ID encoded.
    • +
  • Multiple Mutex locks within a single instance of the device.
    • +
  • An optional user field within each Mutex that can be read or written to by software.
    • + +

    This driver is intended to be RTOS and processor independent. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver. The effective address provided to the XMutex_CfgInitialize() function can be either the real, physical address or the remapped virtual address. The remapping of this address occurs above this driver, no remapping occurs within the driver itself.

    +

    Initialization & Configuration

    +

    The XMutex_Config structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.

    +

    To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:

      -
    • XMutex_CfgInitialize (InstancePtr, ConfigPtr, EffectiveAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure. The EffectiveAddress argument is required regardless of operating system environment, i.e. in standalone, ConfigPtr->BaseAddress is recommended and not the xparameters definition..
    -

    +

  • XMutex_LookupConfig (DeviceId) - Use the device identifier to find the static configuration structure defined in XMutex_g.c. This is setup by the tools. For some operating systems the config structure will be initialized by the software and this call is not needed. This function returns the CfgPtr argument used by the CfgInitialize function described below.
    • + +
      +
    • XMutex_CfgInitialize (InstancePtr, ConfigPtr, EffectiveAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure. The EffectiveAddress argument is required regardless of operating system environment, i.e. in standalone, ConfigPtr->BaseAddress is recommended and not the xparameters definition..
      • +
    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
@@ -50,4 +56,9 @@ To support multiple runtime loading and initialization strategies employed by va
  3.02a bss  01/31/13 Updated driver tcl to fix CR #679127
  4.0   adk  19/12/13 Updated as per the New Tcl API's
  4.00a bss  03/05/14 Modified XMutex_CfgInitialize to fix CR# 770096
-
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex-members.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex-members.html index 5f459ea6..89c91ee2 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex-members.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex-members.html @@ -2,26 +2,37 @@ - Member List + Xilinx Driver mutex v4_0: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMutex Member List

    This is the complete list of members for XMutex, including all inherited members.

    - - -
    ConfigXMutex
    IsReadyXMutex
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XMutex Member List

    This is the complete list of members for XMutex, including all inherited members. + + +
    ConfigXMutex
    IsReadyXMutex
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex.html index d05c0f70..ccec7699 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex.html @@ -2,85 +2,78 @@ - XMutex Struct Reference + Xilinx Driver mutex v4_0: XMutex Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMutex Struct Reference

    #include <xmutex.h> -

    -List of all members.

    Detailed Description

    -The XMutex driver instance data. The user is required to allocate a variable of this type for every Mutex device in the system. A pointer to a variable of this type is then passed to the driver API functions. -

    + + +

    +
    +

    XMutex Struct Reference

    +

    #include <xmutex.h>

    + +

    List of all members.

    - - - - - - + + +

    Public Attributes

    XMutex_Config Config
    u32 IsReady

    Public Attributes

    XMutex_Config Config
    u32 IsReady
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    The XMutex driver instance data. The user is required to allocate a variable of this type for every Mutex device in the system. A pointer to a variable of this type is then passed to the driver API functions.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    XMutex_Config XMutex::Config XMutex_Config XMutex::Config
    -
    - - - - - -
    -   - + +
    +

    Configuration data, includes base address

    -

    -Configuration data, includes base address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XMutex::IsReady u32 XMutex::IsReady
    -
    - - - - - -
    -   - + +
    +

    Device is initialized and ready

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Device is initialized and ready

    -

    The documentation for this struct was generated from the following file:
      -
    • xmutex.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config-members.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config-members.html index 69c05922..be5f79dd 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config-members.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config-members.html @@ -2,28 +2,39 @@ - Member List + Xilinx Driver mutex v4_0: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMutex_Config Member List

    This is the complete list of members for XMutex_Config, including all inherited members.

    - - - - -
    BaseAddressXMutex_Config
    DeviceIdXMutex_Config
    NumMutexXMutex_Config
    UserRegXMutex_Config
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XMutex_Config Member List

    This is the complete list of members for XMutex_Config, including all inherited members. + + + + +
    BaseAddressXMutex_Config
    DeviceIdXMutex_Config
    NumMutexXMutex_Config
    UserRegXMutex_Config
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config.html index 2022e9a6..414592eb 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/struct_x_mutex___config.html @@ -2,135 +2,108 @@ - XMutex_Config Struct Reference + Xilinx Driver mutex v4_0: XMutex_Config Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XMutex_Config Struct Reference

    #include <xmutex.h> -

    -List of all members.

    Detailed Description

    -This typedef contains configuration information for the device. -

    + + +

    +
    +

    XMutex_Config Struct Reference

    +

    #include <xmutex.h>

    + +

    List of all members.

    - - - - - - - - - - + + + + +

    Public Attributes

    u16 DeviceId
    u32 BaseAddress
    u32 NumMutex
    u8 UserReg

    Public Attributes

    u16 DeviceId
    u32 BaseAddress
    u32 NumMutex
    u8 UserReg
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    This typedef contains configuration information for the device.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u32 XMutex_Config::BaseAddress u32 XMutex_Config::BaseAddress
    -
    - - - - - -
    -   - + +
    +

    Register base address

    -

    -Register base address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 XMutex_Config::DeviceId u16 XMutex_Config::DeviceId
    -
    - - - - - -
    -   - + +
    +

    Unique ID of device

    -

    -Unique ID of device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XMutex_Config::NumMutex u32 XMutex_Config::NumMutex
    -
    - - - - - -
    -   - + +
    +

    Number of Mutexes in this device

    -

    -Number of Mutexes in this device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XMutex_Config::UserReg u8 XMutex_Config::UserReg
    -
    - - - - - -
    -   - + +
    +

    User Register, access not controlled by Mutex

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -User Register, access not controlled by Mutex

    -

    The documentation for this struct was generated from the following file:
      -
    • xmutex.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/tabs.css b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/tabs.css index a61552a6..a4441634 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/tabs.css +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/tabs.css @@ -32,7 +32,7 @@ DIV.tabs A float : left; background : url("tab_r.gif") no-repeat right top; border-bottom : 1px solid #84B0C7; - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -57,7 +57,7 @@ DIV.tabs SPAN white-space : nowrap; } -DIV.tabs INPUT +DIV.tabs #MSearchBox { float : right; display : inline; @@ -66,7 +66,7 @@ DIV.tabs INPUT DIV.tabs TD { - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -82,21 +82,24 @@ DIV.tabs A:hover SPAN background-position: 0% -150px; } -DIV.tabs LI#current A +DIV.tabs LI.current A { background-position: 100% -150px; border-width : 0px; } -DIV.tabs LI#current SPAN +DIV.tabs LI.current SPAN { background-position: 0% -150px; padding-bottom : 6px; } -DIV.nav +DIV.navpath { background : none; border : none; border-bottom : 1px solid #84B0C7; + text-align : center; + margin : 2px; + padding : 2px; } diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8c.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8c.html index f7c14f51..f4b780e3 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8c.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8c.html @@ -2,30 +2,51 @@ - xmutex.c File Reference + Xilinx Driver mutex v4_0: xmutex.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmutex.c File Reference

    Detailed Description

    -Contains required functions for the XMutex driver.

    + + +

    +
    +

    xmutex.c File Reference

    #include <string.h>
    +#include "xmutex.h"
    +#include "xparameters.h"
    +#include "xil_types.h"
    +#include "xil_assert.h"
    + + + + + + + + + + +

    Functions

    int XMutex_CfgInitialize (XMutex *InstancePtr, XMutex_Config *ConfigPtr, u32 EffectiveAddress)
    void XMutex_Lock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Trylock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Unlock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_IsLocked (XMutex *InstancePtr, u8 MutexNumber)
    void XMutex_GetStatus (XMutex *InstancePtr, u8 MutexNumber, u32 *Locked, u32 *Owner)
    int XMutex_GetUser (XMutex *InstancePtr, u8 MutexNumber, u32 *User)
    int XMutex_SetUser (XMutex *InstancePtr, u8 MutexNumber, u32 User)
    +

    Detailed Description

    +

    Contains required functions for the XMutex driver.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00b ecm  06/01/07 Cleanup, new coding standard, check into XCS
@@ -35,452 +56,372 @@ Contains required functions for the XMu
  3.00a hbm  10/15/09 Migrated to HAL phase 1 to use xil_io, xil_types,
 			and xil_assert.
  4.00a bss  03/05/14 Modified XMutex_CfgInitialize to fix CR# 770096
-
    -

    -#include <string.h>
    -#include "xmutex.h"
    -#include "xparameters.h"
    -#include "xil_types.h"
    -#include "xil_assert.h"
    - - - - - - - - - - - - - - - - - - - -

    Functions

    int XMutex_CfgInitialize (XMutex *InstancePtr, XMutex_Config *ConfigPtr, u32 EffectiveAddress)
    void XMutex_Lock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Trylock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Unlock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_IsLocked (XMutex *InstancePtr, u8 MutexNumber)
    void XMutex_GetStatus (XMutex *InstancePtr, u8 MutexNumber, u32 *Locked, u32 *Owner)
    int XMutex_GetUser (XMutex *InstancePtr, u8 MutexNumber, u32 *User)
    int XMutex_SetUser (XMutex *InstancePtr, u8 MutexNumber, u32 User)
    -

    Function Documentation

    -

    - - - - -
    - +

    Function Documentation

    + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_CfgInitialize ( XMutex *  InstancePtr, int XMutex_CfgInitialize (XMutex *  InstancePtr,
    XMutex_Config *  ConfigPtr, XMutex_Config *  ConfigPtr,
    u32  EffectiveAddressu32  EffectiveAddress 
    ) )
    -
    - - - - - -
    -   - - -

    -Initializes a specific Mutex instance/driver.

    -

    Parameters:
    + +
    +

    Initializes a specific Mutex instance/driver.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    ConfigPtr is the device configuration structure containing required HW build data.
    EffectiveAddress is the Physical address of the hardware in a Virtual Memory operating system environment. It is the Base Address in a stand alone environment.
    +
    -
    Returns:
      -
    • XST_SUCCESS if initialization was successful
    +
    Returns:
      +
    • XST_SUCCESS if initialization was successful
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    void XMutex_GetStatus ( XMutex *  InstancePtr, void XMutex_GetStatus (XMutex *  InstancePtr,
    u8  MutexNumber, u8  MutexNumber,
    u32 *  Locked, u32 *  Locked,
    u32 *  Owneru32 *  Owner 
    ) )
    -
    - - - - - -
    -   - - -

    -Gets the current status of a Mutex lock within a Mutex device.

    -

    Parameters:
    + +
    +

    Gets the current status of a Mutex lock within a Mutex device.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    Locked is a pointer where the current lock status is stored. Sets memory pointed to by 'Locked' to 1 if the Mutex is locked and 0 if it is unlocked.
    Owner is a pointer where the current owner status is stored. . If the Mutex is locked, the memory pointed to by 'Owner' is updated to reflect the CPU ID that has currently locked this Mutex.
    +
    -
    Returns:
    None.
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    None.
    +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_GetUser ( XMutex *  InstancePtr, int XMutex_GetUser (XMutex *  InstancePtr,
    u8  MutexNumber, u8  MutexNumber,
    u32 *  Useru32 *  User 
    ) )
    -
    - - - - - -
    -   - - -

    -Gets the USER register of a Mutex lock within a Mutex device.

    -

    Parameters:
    + +
    +

    Gets the USER register of a Mutex lock within a Mutex device.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    User is a pointer to an u32 where the current user register value is stored by this function.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful. Memory pointed to by User is updated to reflect the contents of the user register.
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
    +
    Returns:
      +
    • XST_SUCCESS if successful. Memory pointed to by User is updated to reflect the contents of the user register.
      • +
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_IsLocked ( XMutex *  InstancePtr, int XMutex_IsLocked (XMutex *  InstancePtr,
    u8  MutexNumberu8  MutexNumber 
    ) )
    -
    - - - - - -
    -   - - -

    -Gets the current lock state of a Mutex lock within a Mutex device.

    -

    Parameters:
    + +
    +

    Gets the current lock state of a Mutex lock within a Mutex device.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    -
    Returns:
      -
    • TRUE if locked
    • FALSE if unlocked
    +
    Returns:
      +
    • TRUE if locked
      • +
    • FALSE if unlocked
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    void XMutex_Lock ( XMutex *  InstancePtr, void XMutex_Lock (XMutex *  InstancePtr,
    u8  MutexNumberu8  MutexNumber 
    ) )
    -
    - - - - - -
    -   - - -

    -Locks a particular Mutex lock within a Mutex device. Call blocks till the Mutex is locked.

    -

    Parameters:
    + +
    +

    Locks a particular Mutex lock within a Mutex device. Call blocks till the Mutex is locked.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    -
    Returns:
    None
    -
    Note:
      -
    • XMutex_Trylock is a blocking call. This call blocks until the user gets the lock.
    • Use XMutex_Trylock for a Non-Blocking call. The user gets the lock if it is available and returns immediately if the lock is not available.
    +
    Returns:
    None
    +
    Note:
      +
    • XMutex_Trylock is a blocking call. This call blocks until the user gets the lock.
      • +
    • Use XMutex_Trylock for a Non-Blocking call. The user gets the lock if it is available and returns immediately if the lock is not available.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_SetUser ( XMutex *  InstancePtr, int XMutex_SetUser (XMutex *  InstancePtr,
    u8  MutexNumber, u8  MutexNumber,
    u32  Useru32  User 
    ) )
    -
    - - - - - -
    -   - - -

    -Sets the USER register of a Mutex lock within a Mutex device.

    -

    Parameters:
    + +
    +

    Sets the USER register of a Mutex lock within a Mutex device.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    User is the value to update the USER register with.
    +
    -
    Returns:
      -
    • XST_SUCCESS if the USER register is written with the given value .
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
    +
    Returns:
      +
    • XST_SUCCESS if the USER register is written with the given value .
      • +
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_Trylock ( XMutex *  InstancePtr, int XMutex_Trylock (XMutex *  InstancePtr,
    u8  MutexNumberu8  MutexNumber 
    ) )
    -
    - - - - - -
    -   - - -

    -Locks a particular Mutex lock within a Mutex device. Call returns immediately if the Mutex is already locked (This is Non-Blocking call).

    -

    Parameters:
    + +
    +

    Locks a particular Mutex lock within a Mutex device. Call returns immediately if the Mutex is already locked (This is Non-Blocking call).

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    -
    Returns:
      -
    • XST_SUCCESS if locking was successful.
    • XST_DEVICE_BUSY if the Mutex was found to be already locked
    +
    Returns:
      +
    • XST_SUCCESS if locking was successful.
      • +
    • XST_DEVICE_BUSY if the Mutex was found to be already locked
      • +
    -
    Note:
      -
    • This is Non-Blocking call, the user gets the lock if it is available else XST_DEVICE_BUSY is returned.
    • Use XMutex_Lock if you need to block until a lock is obtained.
    +
    Note:
      +
    • This is Non-Blocking call, the user gets the lock if it is available else XST_DEVICE_BUSY is returned.
      • +
    • Use XMutex_Lock if you need to block until a lock is obtained.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XMutex_Unlock ( XMutex *  InstancePtr, int XMutex_Unlock (XMutex *  InstancePtr,
    u8  MutexNumberu8  MutexNumber 
    ) )
    -
    - - - - - -
    -   - - -

    -Unlocks a particular Mutex lock within a Mutex device.

    -

    Parameters:
    + +
    +

    Unlocks a particular Mutex lock within a Mutex device.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    -
    Returns:
    +
    Returns:
      -
    • XST_SUCCESS if locking was successful.
    • XST_FAILURE if the Mutex was locked by process with different ID.
    -

    -

    Note:
    None.
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

  • XST_SUCCESS if locking was successful.
    • +
  • XST_FAILURE if the Mutex was locked by process with different ID.
    • + +
    Note:
    None.
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8h.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8h.html new file mode 100755 index 00000000..496d4354 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex_8h.html @@ -0,0 +1,484 @@ + + + + + Xilinx Driver mutex v4_0: xmutex.h File Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    xmutex.h File Reference

    #include "xstatus.h"
    +#include "xmutex_hw.h"
    +#include "xil_types.h"
    + + + + + + + + + + + + + + + + + +

    Classes

    struct  XMutex_Config
    struct  XMutex

    Defines

    #define XMUTEX_H

    Functions

    int XMutex_CfgInitialize (XMutex *InstancePtr, XMutex_Config *ConfigPtr, u32 EffectiveAddress)
    void XMutex_Lock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Trylock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_Unlock (XMutex *InstancePtr, u8 MutexNumber)
    int XMutex_IsLocked (XMutex *InstancePtr, u8 MutexNumber)
    void XMutex_GetStatus (XMutex *InstancePtr, u8 MutexNumber, u32 *Locked, u32 *Owner)
    int XMutex_GetUser (XMutex *InstancePtr, u8 MutexNumber, u32 *User)
    int XMutex_SetUser (XMutex *InstancePtr, u8 MutexNumber, u32 User)
    XMutex_Config * XMutex_LookupConfig (u16 DeviceId)
    int XMutex_SelfTest (XMutex *InstancePtr)
    +

    Detailed Description

    +

    Define Documentation

    + +
    +
    + + + + +
    #define XMUTEX_H
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMutex_CfgInitialize (XMutex *  InstancePtr,
    XMutex_Config *  ConfigPtr,
    u32  EffectiveAddress 
    )
    +
    +
    +

    Initializes a specific Mutex instance/driver.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    ConfigPtr is the device configuration structure containing required HW build data.
    EffectiveAddress is the Physical address of the hardware in a Virtual Memory operating system environment. It is the Base Address in a stand alone environment.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if initialization was successful
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    void XMutex_GetStatus (XMutex *  InstancePtr,
    u8  MutexNumber,
    u32 *  Locked,
    u32 *  Owner 
    )
    +
    +
    +

    Gets the current status of a Mutex lock within a Mutex device.

    +
    Parameters:
    + + + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    Locked is a pointer where the current lock status is stored. Sets memory pointed to by 'Locked' to 1 if the Mutex is locked and 0 if it is unlocked.
    Owner is a pointer where the current owner status is stored. . If the Mutex is locked, the memory pointed to by 'Owner' is updated to reflect the CPU ID that has currently locked this Mutex.
    +
    +
    +
    Returns:
    None.
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMutex_GetUser (XMutex *  InstancePtr,
    u8  MutexNumber,
    u32 *  User 
    )
    +
    +
    +

    Gets the USER register of a Mutex lock within a Mutex device.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    User is a pointer to an u32 where the current user register value is stored by this function.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful. Memory pointed to by User is updated to reflect the contents of the user register.
      • +
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int XMutex_IsLocked (XMutex *  InstancePtr,
    u8  MutexNumber 
    )
    +
    +
    +

    Gets the current lock state of a Mutex lock within a Mutex device.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    +
    +
    Returns:
      +
    • TRUE if locked
      • +
    • FALSE if unlocked
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void XMutex_Lock (XMutex *  InstancePtr,
    u8  MutexNumber 
    )
    +
    +
    +

    Locks a particular Mutex lock within a Mutex device. Call blocks till the Mutex is locked.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    +
    +
    Returns:
    None
    +
    Note:
      +
    • XMutex_Trylock is a blocking call. This call blocks until the user gets the lock.
      • +
    • Use XMutex_Trylock for a Non-Blocking call. The user gets the lock if it is available and returns immediately if the lock is not available.
      • +
    +
    + +
    +
    + +
    +
    + + + + + + + + + +
    XMutex_Config* XMutex_LookupConfig (u16  DeviceId ) 
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + +
    int XMutex_SelfTest (XMutex *  InstancePtr ) 
    +
    +
    +

    Selftest a particular Mutex hardware core.

    +
    Parameters:
    + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if test was successful.
      • +
    • XST_FAILURE if test was not successful.
      • +
    +
    +
    Note:
    +

    This test is destructive. It will fail if the Mutex is currently being used. This is also a blocking call, if there is another process which has the Mutex, the first _lock will hand the test until the other process releases it.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XMutex_SetUser (XMutex *  InstancePtr,
    u8  MutexNumber,
    u32  User 
    )
    +
    +
    +

    Sets the USER register of a Mutex lock within a Mutex device.

    +
    Parameters:
    + + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    User is the value to update the USER register with.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if the USER register is written with the given value .
      • +
    • XST_NO_FEATURE if the Mutex was not configured with a USER register.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int XMutex_Trylock (XMutex *  InstancePtr,
    u8  MutexNumber 
    )
    +
    +
    +

    Locks a particular Mutex lock within a Mutex device. Call returns immediately if the Mutex is already locked (This is Non-Blocking call).

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if locking was successful.
      • +
    • XST_DEVICE_BUSY if the Mutex was found to be already locked
      • +
    +
    +
    Note:
      +
    • This is Non-Blocking call, the user gets the lock if it is available else XST_DEVICE_BUSY is returned.
      • +
    • Use XMutex_Lock if you need to block until a lock is obtained.
      • +
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int XMutex_Unlock (XMutex *  InstancePtr,
    u8  MutexNumber 
    )
    +
    +
    +

    Unlocks a particular Mutex lock within a Mutex device.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the XMutex instance to be worked on.
    MutexNumber is the specific Mutex lock within the device to operate on. Each device may contain multiple Mutex locks. The Mutex number is a zero based number with a range of 0 - (InstancePtr->Config.NumMutex - 1).
    +
    +
    +
    Returns:
    +
      +
    • XST_SUCCESS if locking was successful.
      • +
    • XST_FAILURE if the Mutex was locked by process with different ID.
      • +
    +
    Note:
    None.
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__g_8c.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__g_8c.html index 97d95392..f7a1b8a1 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__g_8c.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__g_8c.html @@ -2,39 +2,71 @@ - xmutex_g.c File Reference + Xilinx Driver mutex v4_0: xmutex_g.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmutex_g.c File Reference

    Detailed Description

    -This file contains a configuration table that specifies the configuration of Mutex devices in the system.

    + + +

    +
    +

    xmutex_g.c File Reference

    #include "xmutex.h"
    +#include "xparameters.h"
    + + + +

    Variables

    XMutex_Config XMutex_ConfigTable []
    +

    Detailed Description

    +

    This file contains a configuration table that specifies the configuration of Mutex devices in the system.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- ---------------------------------------------------
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
-

    -

    Note:
    None.
    +
    Note:
    None.
    +

    Variable Documentation

    + +
    +
    + + + + +
    XMutex_Config XMutex_ConfigTable[]
    +
    +
    +Initial value:
    +{
+        {
+                XPAR_MUTEX_0_DEVICE_ID,
+                XPAR_MUTEX_0_BASEADDR,
+                XPAR_MUTEX_0_NUM_MUTEX,
+                XPAR_MUTEX_0_ENABLE_USER
+        }
+}
+
    +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -#include "xmutex.h"
    -#include "xparameters.h"
    - - -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__hw_8h.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__hw_8h.html index 13315ef6..fd25abf2 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__hw_8h.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__hw_8h.html @@ -2,266 +2,263 @@ - xmutex_hw.h File Reference + Xilinx Driver mutex v4_0: xmutex_hw.h File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmutex_hw.h File Reference

    Detailed Description

    -This header file contains identifiers/definitions and macros that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation. The driver functions are defined in xmutex.h.

    + + +

    +
    +

    xmutex_hw.h File Reference

    #include "xil_io.h"
    + + + + + + + + + + + + + + + + +

    Defines

    #define XMUTEX_HW_H
    #define XMU_MUTEX_OFFSET   256
    #define XMutex_Offset(i)   (XMU_MUTEX_OFFSET * i)
    #define XMutex_ReadReg(BaseAddress, MutexNumber, RegOffset)   Xil_In32((BaseAddress) + XMutex_Offset(MutexNumber) + (RegOffset))
    #define XMutex_WriteReg(BaseAddress, MutexNumber, RegOffset, ValueToWrite)
    Register Offset Definitions

    Register offsets within a Mutex, there are multiple Mutexes within a single device

    +

    #define XMU_MUTEX_REG_OFFSET   0
    #define XMU_USER_REG_OFFSET   4
    Mutex Register Bit Definitions

    +

    #define LOCKED_BIT   0x00000001
    #define OWNER_MASK   0x000001FE
    #define OWNER_SHIFT   0x00000001
    +

    Detailed Description

    +

    This header file contains identifiers/definitions and macros that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation. The driver functions are defined in xmutex.h.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
  3.00a hbm  10/15/09 Migrated to HAL phase 1 to use xil_io, xil_types,
 			and xil_assert.
-
    -

    -#include "xil_io.h"
    - - - - - - - - - - - - - - - - - - - - -

    Register Offset Definitions

    Register offsets within a Mutex, there are multiple Mutexes within a single device

    #define XMU_MUTEX_REG_OFFSET   0
    #define XMU_USER_REG_OFFSET   4

    Mutex Register Bit Definitions

    #define LOCKED_BIT   0x00000001
    #define OWNER_MASK   0x000001FE
    #define OWNER_SHIFT   0x00000001

    Defines

    #define XMutex_ReadReg(BaseAddress, MutexNumber, RegOffset)   Xil_In32((BaseAddress) + XMutex_Offset(MutexNumber) + (RegOffset))
    #define XMutex_WriteReg(BaseAddress, MutexNumber, RegOffset, ValueToWrite)
    -

    Define Documentation

    -

    - - - - -
    - +

    Define Documentation

    + +
    +
    +
    - +
    #define LOCKED_BIT   0x00000001 #define LOCKED_BIT   0x00000001
    -
    - - - - - -
    -   - + +
    +

    This is the Lock bit. Set to 1 indicates that the lock is currently owned by the processor ID specified by the CPU_ID (OWNER_MASK) in this register. Set to 0 indicates that the lock is free.

    -

    -This is the Lock bit. Set to 1 indicates that the lock is currently owned by the processor ID specified by the CPU_ID (OWNER_MASK) in this register. Set to 0 indicates that the lock is free.

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define OWNER_MASK   0x000001FE #define OWNER_MASK   0x000001FE
    -
    - - - - - -
    -   - + +
    +

    This is CPU_ID Mask. CPU_ID indicates the ID the processor holding the lock.

    -

    -This is CPU_ID Mask. CPU_ID indicates the ID the processor holding the lock.

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define OWNER_SHIFT   0x00000001 #define OWNER_SHIFT   0x00000001
    -
    - - - - - -
    -   - + +
    +

    This is CPU_ID Shift

    -

    -This is CPU_ID Shift

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMU_MUTEX_REG_OFFSET   0 #define XMU_MUTEX_OFFSET   256
    -
    - - - - - -
    -   - + +
    -

    -Mutex register

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XMU_USER_REG_OFFSET   4 #define XMU_MUTEX_REG_OFFSET   0
    -
    - - - - - -
    -   - + +
    +

    Mutex register

    -

    -User register

    -

    - - - - -
    - + + + +
    +
    +
    - - - - - - - - - - - - +
    #define XMutex_ReadReg ( BaseAddress,
    MutexNumber,
    RegOffset   )    Xil_In32((BaseAddress) + XMutex_Offset(MutexNumber) + (RegOffset))#define XMU_USER_REG_OFFSET   4
    -
    - - - - - -
    -   - + +
    +

    User register

    -

    -Read one of the Mutex registers.

    -

    Parameters:
    +
    + + +
    +
    + + + + +
    #define XMUTEX_HW_H
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + +
    #define XMutex_Offset(i  )    (XMU_MUTEX_OFFSET * i)
    +
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + +
    #define XMutex_ReadReg(BaseAddress,
    MutexNumber,
    RegOffset  )    Xil_In32((BaseAddress) + XMutex_Offset(MutexNumber) + (RegOffset))
    +
    +
    +

    Read one of the Mutex registers.

    +
    Parameters:
    BaseAddress contains the base address of the Mutex device.
    MutexNumber contains the specific Mutex within the device, a zero based number, 0 - (NumMutexConfigured in HW - 1).
    RegOffset contains the offset from the 1st register of the Mutex to select the specific register of the Mutex.
    +
    -
    Returns:
    The 32 bit value read from the register.
    -
    Note:
    C-style signature: u32 XMutex_ReadReg(u32 BaseAddress, u8 MutexNumber, unsigned RegOffset)
    -
    -

    - - - - -
    - +
    Returns:
    The 32 bit value read from the register.
    +
    Note:
    C-style signature: u32 XMutex_ReadReg(u32 BaseAddress, u8 MutexNumber, unsigned RegOffset)
    + + + + +
    +
    +
    - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + +
    #define XMutex_WriteReg ( BaseAddress,
    MutexNumber,
    RegOffset,
    ValueToWrite   ) #define XMutex_WriteReg(BaseAddress,
    MutexNumber,
    RegOffset,
    ValueToWrite  ) 
    -
    - - - - - -
    -   - - -

    -Value:

    Xil_Out32(((BaseAddress) + XMutex_Offset(MutexNumber) +            \
+
    +
    +Value:
    Xil_Out32(((BaseAddress) + XMutex_Offset(MutexNumber) +            \
                         (RegOffset)), (ValueToWrite))
-
    Write a specified value to a register of a Mutex.

    -

    Parameters:
    +

    Write a specified value to a register of a Mutex.

    +
    Parameters:
    BaseAddress is the base address of the Mutex device.
    MutexNumber is the specific Mutex within the device, a zero based number, 0 - (NumMutexConfigured in HW - 1).
    RegOffset contain the offset from the 1st register of the Mutex to select the specific register of the Mutex.
    ValueToWrite is the 32 bit value to be written to the register.
    +
    -
    Returns:
    C-style signature: void XMutex_WriteReg(u32 BaseAddress, u8 MutexNumber, unsigned RegOffset, u32 ValueToWrite)
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Returns:
    C-style signature: void XMutex_WriteReg(u32 BaseAddress, u8 MutexNumber, unsigned RegOffset, u32 ValueToWrite)
    + +
    + + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__selftest_8c.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__selftest_8c.html index 09a97ea4..8462a8d9 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__selftest_8c.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__selftest_8c.html @@ -2,84 +2,84 @@ - xmutex_selftest.c File Reference + Xilinx Driver mutex v4_0: xmutex_selftest.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmutex_selftest.c File Reference

    Detailed Description

    -Contains XMutex driver selftest code.

    + + +

    +
    +

    xmutex_selftest.c File Reference

    #include "xstatus.h"
    +#include "xmutex.h"
    +#include "xparameters.h"
    +#include "xil_types.h"
    + + + +

    Functions

    int XMutex_SelfTest (XMutex *InstancePtr)
    +

    Detailed Description

    +

    Contains XMutex driver selftest code.

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
+ MODIFICATION HISTORY:
     Ver   Who  Date     Changes
  ----- ---- -------- -----------------------------------------------
  1.00a va            First release
  1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS
  3.00a hbm  10/15/09 Migrated to HAL phase 1 to use xil_io, xil_types,
 			and xil_assert.
-
    -

    -#include "xstatus.h"
    -#include "xmutex.h"
    -#include "xparameters.h"
    -#include "xil_types.h"
    - - - - - -

    Functions

    int XMutex_SelfTest (XMutex *InstancePtr)
    -

    Function Documentation

    -

    - - - - -
    - +

    Function Documentation

    + +
    +
    +
    - - - - - - + + + + + +
    int XMutex_SelfTest ( XMutex *  InstancePtr  ) int XMutex_SelfTest (XMutex *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -Selftest a particular Mutex hardware core.

    -

    Parameters:
    + +
    +

    Selftest a particular Mutex hardware core.

    +
    Parameters:
    InstancePtr is a pointer to the XMutex instance to be worked on.
    +
    -
    Returns:
      -
    • XST_SUCCESS if test was successful.
    • XST_FAILURE if test was not successful.
    +
    Returns:
      +
    • XST_SUCCESS if test was successful.
      • +
    • XST_FAILURE if test was not successful.
      • +
    -
    Note:
    -This test is destructive. It will fail if the Mutex is currently being used. This is also a blocking call, if there is another process which has the Mutex, the first _lock will hand the test until the other process releases it.
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Note:
    +

    This test is destructive. It will fail if the Mutex is currently being used. This is also a blocking call, if there is another process which has the Mutex, the first _lock will hand the test until the other process releases it.

    + +
    + + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__sinit_8c.html b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__sinit_8c.html index 099e15b0..339b8492 100755 --- a/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__sinit_8c.html +++ b/XilinxProcessorIPLib/drivers/mutex/doc/html/api/xmutex__sinit_8c.html @@ -2,37 +2,80 @@ - xmutex_sinit.c File Reference + Xilinx Driver mutex v4_0: xmutex_sinit.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xmutex_sinit.c File Reference

    Detailed Description

    -Implements static initialization See xmutex.h for more information about the driver.

    -

    - MODIFICATION HISTORY:

    -

     Ver   Who  Date     Changes
- ----- ---- -------- ---------------------------------------------------
- 1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS

    -
    -

    -#include "xmutex.h"
    -#include "xparameters.h"
    + + +

    +
    +

    xmutex_sinit.c File Reference

    #include "xmutex.h"
    +#include "xparameters.h"
    - + + + +

    Functions

    XMutex_Config * XMutex_LookupConfig (u16 DeviceId)

    Variables

    XMutex_Config XMutex_ConfigTable []
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Detailed Description

    +

    Implements static initialization See xmutex.h for more information about the driver.

    +
    + MODIFICATION HISTORY:
     Ver   Who  Date     Changes
+ ----- ---- -------- ---------------------------------------------------
+ 1.00a ecm  06/01/07 Cleanup, new coding standard, check into XCS

    Function Documentation

    + +
    +
    + + + + + + + + + +
    XMutex_Config* XMutex_LookupConfig (u16  DeviceId ) 
    +
    +
    + +
    +
    +

    Variable Documentation

    + +
    +
    + + + + +
    XMutex_Config XMutex_ConfigTable[]
    +
    +
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/annotated.html index ff5fa6bc..3db024cd 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/annotated.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/annotated.html @@ -2,25 +2,31 @@ - Class List + Xilinx Driver nandps v2_1: Class List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    + + + +

    Class List

    Here are the classes, structs, unions and interfaces with brief descriptions: @@ -32,4 +38,9 @@
    __attribute__
    XNandPs_BadBlockPattern
    XNandPs_Geometry
    XNandPsTag
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/classes.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/classes.html new file mode 100755 index 00000000..84a23436 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/classes.html @@ -0,0 +1,40 @@ + + + + + Xilinx Driver nandps v2_1: Alphabetical List + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    Class Index

    X | _
    + +
      X  
    +    		XNandPs_CommandFormat   XNandPs_EccConfig   XNandPs_Geometry   
      _  
    +
    XNandPs_BadBlockPattern   XNandPs_Config   XNandPs_Features   XNandPsTag   __attribute__   
    XNandPs_BbtDesc   
    X | _
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/doxygen.png b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/doxygen.png deleted file mode 100755 index d8021941e6c836bb05e83ed25dfaddc81912c980..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1280 zcmaJ>ZA?>F7(Vx-ms?upS`b@hdRtmn6o^%HU>M$hfGrBvQnk$LE?p^P!kn&ikhyq! zY2(FDtPXHSsr8ekTL96Bi%aRiwbe1)9HN7TF?E|PZe}sTZ5g}%Up&b29$!M_f=;UuUj_~ict%VUD&}wa|7J%WA+iPu0_*&*JvboE*x!mtn z?x+G<=Qc+bX{xKNuCi2BIvcjfstS10X7d_r5szPf{V z8NN|dy?Mb)$*)20OoR907`7mf^hPx4JIge7fLd}IC$2r z0SNkkAPL;1Qua+uSS02;9l4&? zn79g^7@tk%=QF^5Km!93ha2>IiGF&wOR=de@G=;E)w(L`pQ;t)wQX7b_p(C;k0j-u zhnCoxqpHWr6a~#E$Fbw_84gWg`+znj=@4NvatZJiPljhi=eLjzLhP+J)a-?B{?r1` z1G(CnB*VPf%P{lO3P;IQq)p_Ow=GiVL?nX>(VY69VJSM^`orc&$1I@S`$#w z8jLpx7Z-?@5;*+EYeYW{{VAxD+fzBxAc!s^azuGc_gxI%zap}&1NHWy-5!e<5V88e2A9e$rdNB>tS+DLPZKZCRBJ@sQMiMLgV|{G$V6D zJ2x&N2)fmkAdE#j_4_eQVFMc$$MEipda;9A;yVF_jESMt=n(`b-_De)LBek=d1CRw zT!hP1s|1$5LE&Xo$yh<0IUD}hv1cCS@MJ;n$nFDph{9e0VG{r6Rww(-x9+ zsa|gCNjj%EdLYXAmtII*SJ5`@_H5bm{YdrBZ1RJ`jlff~R=WYEQAC-MepGM{mE}E~ zn#z+g_TpmlczJONri@%?hOX}&N;)OwRXC5QDJ2{h9e zd0N}s+vm81E7Sg%Smu4+Y~HGg0B2Ly{x5_V8;>wK3{ZShoN(;M4QBiad#%qDCHPL) zU64B`W(-uudK3g4i$(fm%`8_!^DoX)mXvByNK284@$KXB{Pnh$f+%gbw(roNn S`K7h|)&QoWGQ+1jn*9%)IMrqV diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/driver_api_doxygen.css b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/driver_api_doxygen.css deleted file mode 100755 index 8b5d35bb..00000000 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/driver_api_doxygen.css +++ /dev/null @@ -1,334 +0,0 @@ -BODY { - background-color: #FFFFFF; - font-family: Verdana, Arial, Helvetica, Sans-serif; -} - -H1 { - margin-bottom: 0em; - font-size: 2.00em; - font-style: normal; - color: #990033; -} - -H2 { - font-size: 1.05em; - font-style: normal; - color: #666666; -} - -H3 { - font-size: 1.00em; - font-style: normal; - color: #000000; -} - -H4 { - font-size: .90em; - font-style: italic; - color: #000000; -} - -H5 { - font-size: .90em; - font-style: italic; - color: #000000; -} - -H6 { - font-size: .90em; - font-style: italic; - color: #000000; -} - -OL { -} - -UL { -} - -LI { -} - -P { - color: #000000; -} - -P.Caution { - color: #990033; -} - -P.Code { - font-family: Courier New, Courier, Mono; - color: #003399; -} - -P.HeadingDBox { - font-weight: bold; -} - -P.HeadingGlossary { - font-weight: bold; -} - -P.LinkGlossary { - margin-bottom: .50em; -} - -P.Note { -} - -P.SysInOut { - font-family: Courier New, Courier, Mono; -} - -P.TableFootnote { - font-size: .80em; - margin-bottom: .70em; -} - -P.TableHeading { - font-weight: bold; - color: #FFFFFF; -} - -P.TableTitle { - font-style: italic; - font-weight: bold; -} - -SPAN.aEmphasis { - font-style: italic; -} - -SPAN.aFilename { - font-family: Courier New, Courier, Mono; -} - - -SPAN.aGUISysIn { - font-family: Verdana, Arial, Helvetica, Sans-serif; - font-weight: bold; -} - -SPAN.aReference { - font-style: italic; -} - -SPAN.aSysIn { - font-family: Courier New, Courier, Monospace; - font-weight: bold; -} - -SPAN.aSysOut { - font-family: Courier New, Courier, Monospace; -} - -SPAN.aSymbol { - font-family: Symbol; -} - -CAPTION { font-weight: bold } -DIV.qindex { - width: 100%; - background-color: #eeeeff; - border: 1px solid #B0B0B0; - text-align: center; - margin: 2px; - padding: 2px; -} -A.qindex { - text-decoration: none; - font-weight: bold; - color: #1A419D; - padding: 2px; -} -A.qindex:visited { - text-decoration: none; - font-weight: bold; - color: #1A419D - padding: 2px; -} -A.qindex:hover { - text-decoration: none; - background-color: #ddddff; - padding: 2px; -} -A.qindexHL { - text-decoration: none; - font-weight: bold; - background-color: #6666cc; - color: #ffffff; - padding: 2 6px; - border: 1px double #9295C2; - } -A.qindexHL:hover { - text-decoration: none; - background-color: #6666cc; - color: #ffffff; - padding: 2px 6px; -} -A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } -A.el { text-decoration: none; font-weight: bold } -A.elRef { font-weight: bold } -A.code { text-decoration: none; font-weight: normal; color: #1A419D} -A.codeRef { font-weight: normal; color: #1A419D} -A:hover { text-decoration: none; background-color: #f2f2ff } -DL.el { margin-left: -1cm } -PRE.fragment { - border: 1px solid #CCCCCC; - background-color: #f5f5f5; - margin-top: 4px; - margin-bottom: 4px; - margin-left: 2px; - margin-right: 8px; - padding-left: 6px; - padding-right: 6px; - padding-top: 4px; - padding-bottom: 4px; -} -DIV.fragment { - border: 1px solid #CCCCCC; - background-color: #f5f5f5; - padding: 6px; -} -DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } -TD.md { background-color: #F4F4FB; font-weight: bold; } -TD.mdname1 { background-color: #F4F4FB; font-weight: bold; color: #602020; } -TD.mdname { background-color: #F4F4FB; font-weight: bold; color: #602020; width: 600px; } -DIV.groupHeader { margin-left: 16px; margin-top: 12px; margin-bottom: 6px; font-weight: bold } -DIV.groupText { margin-left: 16px; font-style: italic; font-size: smaller } -BODY { - background: white; - color: black; - margin-right: 20px; - margin-left: 20px; -} -TD.indexkey { - background-color: #eeeeff; - font-weight: bold; - padding-right : 10px; - padding-top : 2px; - padding-left : 10px; - padding-bottom : 2px; - margin-left : 0px; - margin-right : 0px; - margin-top : 2px; - margin-bottom : 2px; - border: 1px solid #CCCCCC; -} -TD.indexvalue { - background-color: #eeeeff; - font-style: italic; - padding-right : 10px; - padding-top : 2px; - padding-left : 10px; - padding-bottom : 2px; - margin-left : 0px; - margin-right : 0px; - margin-top : 2px; - margin-bottom : 2px; - border: 1px solid #CCCCCC; -} -TR.memlist { - background-color: #f0f0f0; -} -P.formulaDsp { text-align: center; } -IMG.formulaDsp { } -IMG.formulaInl { vertical-align: middle; } -SPAN.keyword { color: #008000 } -SPAN.keywordtype { color: #604020 } -SPAN.keywordflow { color: #e08000 } -SPAN.comment { color: #800000 } -SPAN.preprocessor { color: #806020 } -SPAN.stringliteral { color: #002080 } -SPAN.charliteral { color: #008080 } -.mdTable { - border: 1px solid #868686; - background-color: #F4F4FB; -} -.mdRow { - padding: 8px 10px; -} -.mdescLeft { - font-size: smaller; - font-family: Verdana, Arial, Helvetica, sans-serif; - background-color: #FAFAFA; - padding-left: 8px; - border-top: 1px none #E0E0E0; - border-right: 1px none #E0E0E0; - border-bottom: 1px none #E0E0E0; - border-left: 1px none #E0E0E0; - margin: 0px; -} -.mdescRight { - font-size: smaller; - font-family: Verdana, Arial, Helvetica, sans-serif; - font-style: italic; - background-color: #FAFAFA; - padding-left: 4px; - border-top: 1px none #E0E0E0; - border-right: 1px none #E0E0E0; - border-bottom: 1px none #E0E0E0; - border-left: 1px none #E0E0E0; - margin: 0px; - padding-bottom: 0px; - padding-right: 8px; -} -.memItemLeft { - padding: 1px 0px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-style: solid; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-family: Verdana, Arial, Helvetica, sans-serif; - font-size: 12px; -} -.memItemRight { - padding: 1px 0px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-style: solid; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-family: Verdana, Arial, Helvetica, sans-serif; - font-size: 13px; -} -.search { color: #003399; - font-weight: bold; -} -FORM.search { - margin-bottom: 0px; - margin-top: 0px; -} -INPUT.search { font-size: 75%; - color: #000080; - font-weight: normal; - background-color: #eeeeff; -} -TD.tiny { font-size: 75%; -} -a { - color: #252E78; -} -a:visited { - color: #3D2185; -} diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/files.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/files.html index 8a98ad07..ab4d7100 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/files.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/files.html @@ -2,27 +2,34 @@ - File Index + Xilinx Driver nandps v2_1: File Index - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    File List

    Here is a list of all documented files with brief descriptions: + + + +
    +

    File List

    Here is a list of all files with brief descriptions:
    + @@ -31,4 +38,9 @@
    xnandps.c
    xnandps.h
    xnandps_bbm.c
    xnandps_bbm.h
    xnandps_g.c
    xnandps_onfi.h
    xnandps_sinit.c
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions.html index 9c5dd29a..bcb6a9bd 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions.html @@ -2,194 +2,454 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented class members with links to the class documentation for each member: -

    -

    - a -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions_vars.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions_vars.html index c12dd34c..7cf53ee3 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions_vars.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/functions_vars.html @@ -2,194 +2,454 @@ - Class Members - Variables + Xilinx Driver nandps v2_1: Class Members - Variables - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    + +

    +
      -

    -

    - a -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals.html index 67042a64..b6f51382 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals.html @@ -2,53 +2,68 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - b -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x63.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x63.html index 79c8280a..4070359b 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x63.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x63.html @@ -2,54 +2,68 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - c -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x67.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x67.html index f1201003..5f58bada 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x67.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x67.html @@ -2,53 +2,65 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - g -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6e.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6e.html index 2536600d..ce8f7217 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6e.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6e.html @@ -2,55 +2,71 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - n -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6f.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6f.html index 866da150..22ec5911 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6f.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x6f.html @@ -2,98 +2,209 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - o -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x70.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x70.html index 47b722d7..d3212c18 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x70.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x70.html @@ -2,54 +2,68 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - p -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x72.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x72.html index 07f144bd..3f0cd85f 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x72.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x72.html @@ -2,59 +2,83 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - r -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x73.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x73.html index ffd6affd..e08fd55a 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x73.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x73.html @@ -2,53 +2,65 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - s -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x78.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x78.html index aeb650b0..a268c91c 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x78.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_0x78.html @@ -2,273 +2,897 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    - -
    -

    -Here is a list of all documented file members with links to the documentation: -

    -

    - x -

    + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs.html index fd45091f..1a8ccd2f 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs.html @@ -2,87 +2,60 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    -
      -
    • o
      • -
    • x
      • -
    -
    -

    + +

    +
      -

    -

    - o -

    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

    - b -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x6f.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x6f.html new file mode 100755 index 00000000..3607ac9a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x6f.html @@ -0,0 +1,189 @@ + + + + + Xilinx Driver nandps v2_1: Class Members + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +  + +

    - o -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x78.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x78.html index 32ef7c30..19deee57 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x78.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_defs_0x78.html @@ -2,251 +2,812 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - -
    -
    -
      -
    • o
      • -
    • x
      • -
    -
    -

    + +

    +
      -

    -

    - x -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_enum.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_enum.html index 0b71b5a5..680f731e 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_enum.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_enum.html @@ -2,38 +2,53 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_eval.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_eval.html index 76a2114f..7e9c7f8d 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_eval.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_eval.html @@ -2,51 +2,101 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_func.html index 34e355f1..4ff83bc2 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_func.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_func.html @@ -2,53 +2,124 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + +
      -

    -

    + + +

    - x -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_type.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_type.html new file mode 100755 index 00000000..a84f9622 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_type.html @@ -0,0 +1,51 @@ + + + + + Xilinx Driver nandps v2_1: Class Members + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +  +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_vars.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_vars.html index 75f49e55..d4561732 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_vars.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/globals_vars.html @@ -2,42 +2,64 @@ - Class Members + Xilinx Driver nandps v2_1: Class Members - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -
    - + + + -  -

    -

    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/index.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/index.html index 18afdd7c..303725fb 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/index.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/index.html @@ -2,50 +2,57 @@ - xnandps v2_0 + Xilinx Driver nandps v2_1: nandps v2_1 - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -

    xnandps v2_0

    -

    -This file implements a driver for the NAND flash controller.

    -Driver Initialization

    -The function call XNandPs_CfgInitialize() should be called by the application before any other function in the driver. The initialization function takes device specific data (like device id, instance id, and base address) and initializes the XNandPs instance with the device specific data.

    -Device Geometry

    -NAND flash device is memory device and it is segmented into areas called Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device can have multiple LUN. LUN is sequential raw of multiple blocks of the same size. A block is the smallest erasable unit of data within the Flash array of a LUN. The size of each block is based on a power of 2. There is no restriction on the number of blocks within the LUN. A block contains a number of pages. A page is the smallest addressable unit for read and program operations. The arrangement of LUN, blocks, and pages is referred to by this module as the part's geometry.

    -The cells within the part can be programmed from a logic 1 to a logic 0 and not the other way around. To change a cell back to a logic 1, the entire block containing that cell must be erased. When a block is erased all bytes contain the value 0xFF. The number of times a block can be erased is finite. Eventually the block will wear out and will no longer be capable of erasure. As of this writing, the typical flash block can be erased 100,000 or more times.

    -The jobs done by this driver typically are:

      -
    • 8/16 bit operational mode
    • Read, Write, and Erase operation
    • Read, Write cache operation
    • Read, Write Spare area operation
    • HW Error Check and Correction (ECC)
    -

    -Write Operation

    -The write call can be used to write a minimum of one byte and a maximum entire flash. If the address offset specified to write is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The write is blocking in nature in that the control is returned back to user only after the write operation is completed successfully or an error is reported.

    -Read Operation

    -The read call can be used to read a minimum of one byte and maximum of entire flash. If the address offset specified to read is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The read is blocking in nature in that the control is returned back to user only after the read operation is completed successfully or an error is reported.

    -Erase Operation

    -The erase operations are provided to erase a Block in the Flash memory. The erase call is blocking in nature in that the control is returned back to user only after the erase operation is completed successfully or an error is reported.

    -Page Cache Write Operation

    -The page cache write call is same as write call except that it uses cache commands to write. This enhances the performance. This operation can't be performed on OnDie ECC with internal ECC enabled. There is no way to disable internal ECC for OnDie ECC flash parts in current driver. This operation is tested with Spansion S34ML04G100TFI00 flash. We have to use this operation only on the flash parts which supports program page cache command.

    -Page Cache Read Operation

    -The page cache read call is same as read call except that it uses cache commands to read. This enhances the performance. The read cache random command is used since the HW ECC block doesn't support commands without address for starting ECC. This operation can't be performed on OnDie ECC with internal ECC enabled. There is no way to disable internal ECC for OnDie ECC flash parts in current driver. This operation is tested with Spansion S34ML04G100TFI00 flash. We have to use this operation only on the flash parts which supports read page cache command (random).

    -Write Spare Bytes Operation

    -This call writes to user specified buffer into spare bytes of a page.

    -Read Spare Bytes Operation

    -This call reads spare bytes of a page into user specified buffer.

    -

    Note:
    -This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads, mutual exclusion, virtual memory, cache control, or HW write protection management must be satisfied by the layer above this driver.

    + + +

    +
    +

    nandps v2_1

    This file implements a driver for the NAND flash controller.

    +

    Driver Initialization

    +

    The function call XNandPs_CfgInitialize() should be called by the application before any other function in the driver. The initialization function takes device specific data (like device id, instance id, and base address) and initializes the XNandPs instance with the device specific data.

    +

    Device Geometry

    +

    NAND flash device is memory device and it is segmented into areas called Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device can have multiple LUN. LUN is sequential raw of multiple blocks of the same size. A block is the smallest erasable unit of data within the Flash array of a LUN. The size of each block is based on a power of 2. There is no restriction on the number of blocks within the LUN. A block contains a number of pages. A page is the smallest addressable unit for read and program operations. The arrangement of LUN, blocks, and pages is referred to by this module as the part's geometry.

    +

    The cells within the part can be programmed from a logic 1 to a logic 0 and not the other way around. To change a cell back to a logic 1, the entire block containing that cell must be erased. When a block is erased all bytes contain the value 0xFF. The number of times a block can be erased is finite. Eventually the block will wear out and will no longer be capable of erasure. As of this writing, the typical flash block can be erased 100,000 or more times.

    +

    The jobs done by this driver typically are:

    +
      +
    • 8/16 bit operational mode
      • +
    • Read, Write, and Erase operation
      • +
    • Read, Write cache operation
      • +
    • Read, Write Spare area operation
      • +
    • HW Error Check and Correction (ECC)
      • +
    +

    Write Operation

    +

    The write call can be used to write a minimum of one byte and a maximum entire flash. If the address offset specified to write is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The write is blocking in nature in that the control is returned back to user only after the write operation is completed successfully or an error is reported.

    +

    Read Operation

    +

    The read call can be used to read a minimum of one byte and maximum of entire flash. If the address offset specified to read is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The read is blocking in nature in that the control is returned back to user only after the read operation is completed successfully or an error is reported.

    +

    Erase Operation

    +

    The erase operations are provided to erase a Block in the Flash memory. The erase call is blocking in nature in that the control is returned back to user only after the erase operation is completed successfully or an error is reported.

    +

    Page Cache Write Operation

    +

    The page cache write call is same as write call except that it uses cache commands to write. This enhances the performance. This operation can't be performed on OnDie ECC with internal ECC enabled. There is no way to disable internal ECC for OnDie ECC flash parts in current driver. This operation is tested with Spansion S34ML04G100TFI00 flash. We have to use this operation only on the flash parts which supports program page cache command.

    +

    Page Cache Read Operation

    +

    The page cache read call is same as read call except that it uses cache commands to read. This enhances the performance. The read cache random command is used since the HW ECC block doesn't support commands without address for starting ECC. This operation can't be performed on OnDie ECC with internal ECC enabled. There is no way to disable internal ECC for OnDie ECC flash parts in current driver. This operation is tested with Spansion S34ML04G100TFI00 flash. We have to use this operation only on the flash parts which supports read page cache command (random).

    +

    Write Spare Bytes Operation

    +

    This call writes to user specified buffer into spare bytes of a page.

    +

    Read Spare Bytes Operation

    +

    This call reads spare bytes of a page into user specified buffer.

    +
    Note:
    +

    This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads, mutual exclusion, virtual memory, cache control, or HW write protection management must be satisfied by the layer above this driver.

    - MODIFICATION HISTORY:

    -

     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
  	nm     29/09/2011  Added support for On-Die ECC NAND and Clean NAND
@@ -75,4 +82,11 @@ This driver is intended to be RTOS and processor independent. It works with phys
 			   Added function prototypes for Page cache read/write
 			   and spare byte read/write API's.
  2.0   adk    12/10/13    Updated as per the New Tcl API's
-
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + 2.1 kpc 07/24/13 Fixed CR#808770. Update command register twice only + if flash device requires >= four address cycles. +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____-members.html index cfd40ac0..443fdf19 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____-members.html @@ -2,78 +2,89 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    __attribute__ Member List

    This is the complete list of members for __attribute__, including all inherited members.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    AddrCycles__attribute__
    BitsPerCell__attribute__
    BlockEndurance__attribute__
    BlockEnduranceGvb__attribute__
    BlocksPerLun__attribute__
    BytesPerPage__attribute__
    BytesPerPartialPage__attribute__
    ClkInputPinCap__attribute__
    Crc__attribute__
    DateCode__attribute__
    DeviceManufacturer__attribute__
    DeviceModel__attribute__
    DrvStrength__attribute__
    EccBits__attribute__
    ExtParamPageLen__attribute__
    EzNandSupport__attribute__
    Features__attribute__
    GuaranteedValidBlock__attribute__
    InputPinCap__attribute__
    InputPinCapMax__attribute__
    InterleavedAddrBits__attribute__
    InterleavedOperation__attribute__
    IOPinCap__attribute__
    IOPinCapacitance__attribute__
    JedecManufacturerId__attribute__
    MaxBadBlocksPerLun__attribute__
    NumLuns__attribute__
    NumOfParamPages__attribute__
    OptionalCmds__attribute__
    PagecacheTimingMode__attribute__
    PagesPerBlock__attribute__
    PartialProgAttr__attribute__
    ProgramsPerPage__attribute__
    Reserved0__attribute__
    Reserved1__attribute__
    Reserved2__attribute__
    Reserved3__attribute__
    Reserved4__attribute__
    Revision__attribute__
    Signature__attribute__
    SpareBytesPerPage__attribute__
    SpareBytesPerPartialPage__attribute__
    SynFeatures__attribute__
    SynTimingMode__attribute__
    TAdl__attribute__
    TBers__attribute__
    TCcs__attribute__
    TEr__attribute__
    TimingMode__attribute__
    TMr__attribute__
    TProg__attribute__
    TR__attribute__
    VendorRevisionNum__attribute__
    VendorSpecific__attribute__
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    __attribute__ Member List

    This is the complete list of members for __attribute__, including all inherited members. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AddrCycles__attribute__
    BitsPerCell__attribute__
    BlockEndurance__attribute__
    BlockEnduranceGvb__attribute__
    BlocksPerLun__attribute__
    BytesPerPage__attribute__
    BytesPerPartialPage__attribute__
    ClkInputPinCap__attribute__
    Crc__attribute__
    DateCode__attribute__
    DeviceManufacturer__attribute__
    DeviceModel__attribute__
    DrvStrength__attribute__
    EccBits__attribute__
    ExtParamPageLen__attribute__
    EzNandSupport__attribute__
    Features__attribute__
    GuaranteedValidBlock__attribute__
    InputPinCap__attribute__
    InputPinCapMax__attribute__
    InterleavedAddrBits__attribute__
    InterleavedOperation__attribute__
    IOPinCap__attribute__
    IOPinCapacitance__attribute__
    JedecManufacturerId__attribute__
    MaxBadBlocksPerLun__attribute__
    NumLuns__attribute__
    NumOfParamPages__attribute__
    OptionalCmds__attribute__
    PagecacheTimingMode__attribute__
    PagesPerBlock__attribute__
    PartialProgAttr__attribute__
    ProgramsPerPage__attribute__
    Reserved0__attribute__
    Reserved1__attribute__
    Reserved2__attribute__
    Reserved3__attribute__
    Reserved4__attribute__
    Revision__attribute__
    Signature__attribute__
    SpareBytesPerPage__attribute__
    SpareBytesPerPartialPage__attribute__
    SynFeatures__attribute__
    SynTimingMode__attribute__
    TAdl__attribute__
    TBers__attribute__
    TCcs__attribute__
    TEr__attribute__
    TimingMode__attribute__
    TMr__attribute__
    TProg__attribute__
    TR__attribute__
    VendorRevisionNum__attribute__
    VendorSpecific__attribute__
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____.html index 53e154fc..f4fbf786 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct____attribute____.html @@ -2,1385 +2,858 @@ - __attribute__ Struct Reference + Xilinx Driver nandps v2_1: __attribute__ Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    __attribute__ Struct Reference

    #include <xnandps_onfi.h> -

    -List of all members.

    Detailed Description

    -ONFI 1.0 support -

    + + +

    +
    +

    __attribute__ Struct Reference

    +

    #include <xnandps_onfi.h>

    + +

    List of all members.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Public Attributes

    u8 Signature [4]
    u16 Revision
    u16 Features
    u16 OptionalCmds
    u8 Reserved0 [2]
    u16 ExtParamPageLen
    u8 NumOfParamPages
    u8 Reserved1 [17]
    u8 DeviceManufacturer [12]
    u8 DeviceModel [20]
    u8 JedecManufacturerId
    u8 DateCode [2]
    u8 Reserved2 [13]
    u32 BytesPerPage
    u16 SpareBytesPerPage
    u32 BytesPerPartialPage
    u16 SpareBytesPerPartialPage
    u32 PagesPerBlock
    u32 BlocksPerLun
    u8 NumLuns
    u8 AddrCycles
    u8 BitsPerCell
    u16 MaxBadBlocksPerLun
    u16 BlockEndurance
    u8 GuaranteedValidBlock
    u16 BlockEnduranceGvb
    u8 ProgramsPerPage
    u8 PartialProgAttr
    u8 EccBits
    u8 InterleavedAddrBits
    u8 InterleavedOperation
    u8 EzNandSupport
    u8 Reserved3 [12]
    u8 IOPinCapacitance
    u16 TimingMode
    u16 PagecacheTimingMode
    u16 TProg
    u16 TBers
    u16 TR
    u16 TCcs
    u16 SynTimingMode
    u8 SynFeatures
    u16 ClkInputPinCap
    u16 IOPinCap
    u16 InputPinCap
    u8 InputPinCapMax
    u8 DrvStrength
    u16 TMr
    u16 TAdl
    u16 TEr
    u8 Reserved4 [6]
    u16 VendorRevisionNum
    u8 VendorSpecific [88]
    u16 Crc

    Public Attributes

    u8 Signature [4]
    u16 Revision
    u16 Features
    u16 OptionalCmds
    u8 Reserved0 [2]
    u16 ExtParamPageLen
    u8 NumOfParamPages
    u8 Reserved1 [17]
    u8 DeviceManufacturer [12]
    u8 DeviceModel [20]
    u8 JedecManufacturerId
    u8 DateCode [2]
    u8 Reserved2 [13]
    u32 BytesPerPage
    u16 SpareBytesPerPage
    u32 BytesPerPartialPage
    u16 SpareBytesPerPartialPage
    u32 PagesPerBlock
    u32 BlocksPerLun
    u8 NumLuns
    u8 AddrCycles
    u8 BitsPerCell
    u16 MaxBadBlocksPerLun
    u16 BlockEndurance
    u8 GuaranteedValidBlock
    u16 BlockEnduranceGvb
    u8 ProgramsPerPage
    u8 PartialProgAttr
    u8 EccBits
    u8 InterleavedAddrBits
    u8 InterleavedOperation
    u8 EzNandSupport
    u8 Reserved3 [12]
    u8 IOPinCapacitance
    u16 TimingMode
    u16 PagecacheTimingMode
    u16 TProg
    u16 TBers
    u16 TR
    u16 TCcs
    u16 SynTimingMode
    u8 SynFeatures
    u16 ClkInputPinCap
    u16 IOPinCap
    u16 InputPinCap
    u8 InputPinCapMax
    u8 DrvStrength
    u16 TMr
    u16 TAdl
    u16 TEr
    u8 Reserved4 [6]
    u16 VendorRevisionNum
    u8 VendorSpecific [88]
    u16 Crc
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    ONFI 1.0 support

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u8 __attribute__::AddrCycles u8 __attribute__::AddrCycles
    -
    - - - - - -
    -   - + +
    +

    Number of address cycles

    -

    -Number of address cycles

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::BitsPerCell u8 __attribute__::BitsPerCell
    -
    - - - - - -
    -   - + +
    +

    Number of bits per cell

    -

    -Number of bits per cell

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::BlockEndurance u16 __attribute__::BlockEndurance
    -
    - - - - - -
    -   - + +
    +

    Block endurance

    -

    -Block endurance

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::BlockEnduranceGvb u16 __attribute__::BlockEnduranceGvb
    -
    - - - - - -
    -   - + +
    +

    Block endurance for guaranteed valid block

    -

    -Block endurance for guaranteed valid block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 __attribute__::BlocksPerLun u32 __attribute__::BlocksPerLun
    -
    - - - - - -
    -   - + +
    +

    Number of blocks per logical unit (LUN)

    -

    -Number of blocks per logical unit (LUN)

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 __attribute__::BytesPerPage u32 __attribute__::BytesPerPage
    -
    - - - - - -
    -   - + +
    +

    Number of data bytes per page

    -

    -Number of data bytes per page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 __attribute__::BytesPerPartialPage u32 __attribute__::BytesPerPartialPage
    -
    - - - - - -
    -   - + +
    +

    Number of data bytes per partial page

    -

    -Number of data bytes per partial page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::ClkInputPinCap u16 __attribute__::ClkInputPinCap
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: CLK input pin capacitance

    -

    -ONFI 2.3: CLK input pin capacitance

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::Crc u16 __attribute__::Crc
    -
    - - - - - -
    -   - + +
    +

    Integrity CRC

    -

    -Integrity CRC

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::DateCode[2] u8 __attribute__::DateCode[2]
    -
    - - - - - -
    -   - + +
    +

    Date code

    -

    -Date code

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::DeviceManufacturer[12] u8 __attribute__::DeviceManufacturer[12]
    -
    - - - - - -
    -   - + +
    +

    Device manufacturer

    -

    -Device manufacturer

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::DeviceModel[20] u8 __attribute__::DeviceModel[20]
    -
    - - - - - -
    -   - + +
    +

    Device model

    -

    -Device model

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::DrvStrength u8 __attribute__::DrvStrength
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Driver strength support

    -

    -ONFI 2.3: Driver strength support

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::EccBits u8 __attribute__::EccBits
    -
    - - - - - -
    -   - + +
    +

    Number of bits ECC correctability

    -

    -Number of bits ECC correctability

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::ExtParamPageLen u16 __attribute__::ExtParamPageLen
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: extended parameter page length

    -

    -ONFI 2.3: extended parameter page length

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::EzNandSupport u8 __attribute__::EzNandSupport
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: EZ NAND support parameters

    -

    -ONFI 2.3: EZ NAND support parameters

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::Features u16 __attribute__::Features
    -
    - - - - - -
    -   - + +
    +

    Features supported

    -

    -Features supported

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::GuaranteedValidBlock u8 __attribute__::GuaranteedValidBlock
    -
    - - - - - -
    -   - + +
    +

    Guaranteed valid blocks at beginning of target

    -

    -Guaranteed valid blocks at beginning of target

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::InputPinCap u16 __attribute__::InputPinCap
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Input pin capacitance typical

    -

    -ONFI 2.3: Input pin capacitance typical

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::InputPinCapMax u8 __attribute__::InputPinCapMax
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Input pin capacitance maximum

    -

    -ONFI 2.3: Input pin capacitance maximum

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::InterleavedAddrBits u8 __attribute__::InterleavedAddrBits
    -
    - - - - - -
    -   - + +
    +

    Number of interleaved address bits

    -

    -Number of interleaved address bits

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::InterleavedOperation u8 __attribute__::InterleavedOperation
    -
    - - - - - -
    -   - + +
    +

    Interleaved operation attributes

    -

    -Interleaved operation attributes

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::IOPinCap u16 __attribute__::IOPinCap
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: I/O pin capacitance

    -

    -ONFI 2.3: I/O pin capacitance

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::IOPinCapacitance u8 __attribute__::IOPinCapacitance
    -
    - - - - - -
    -   - + +
    +

    I/O pin capacitance

    -

    -I/O pin capacitance

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::JedecManufacturerId u8 __attribute__::JedecManufacturerId
    -
    - - - - - -
    -   - + +
    +

    JEDEC Manufacturer ID

    -

    -JEDEC Manufacturer ID

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::MaxBadBlocksPerLun u16 __attribute__::MaxBadBlocksPerLun
    -
    - - - - - -
    -   - + +
    +

    Bad blocks maximum per LUN

    -

    -Bad blocks maximum per LUN

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::NumLuns u8 __attribute__::NumLuns
    -
    - - - - - -
    -   - + +
    +

    Number of LUN's

    -

    -Number of LUN's

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::NumOfParamPages u8 __attribute__::NumOfParamPages
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: No of parameter pages

    -

    -ONFI 2.3: No of parameter pages

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::OptionalCmds u16 __attribute__::OptionalCmds
    -
    - - - - - -
    -   - + +
    +

    Optional commands supported

    -

    -Optional commands supported

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::PagecacheTimingMode u16 __attribute__::PagecacheTimingMode
    -
    - - - - - -
    -   - + +
    +

    Program cache timing mode

    -

    -Program cache timing mode

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 __attribute__::PagesPerBlock u32 __attribute__::PagesPerBlock
    -
    - - - - - -
    -   - + +
    +

    Number of pages per block

    -

    -Number of pages per block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::PartialProgAttr u8 __attribute__::PartialProgAttr
    -
    - - - - - -
    -   - + +
    +

    Partial programming attributes

    -

    -Partial programming attributes

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::ProgramsPerPage u8 __attribute__::ProgramsPerPage
    -
    - - - - - -
    -   - + +
    +

    Number of programs per page

    -

    -Number of programs per page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Reserved0[2] u8 __attribute__::Reserved0[2]
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Reserved

    -

    -ONFI 2.3: Reserved

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Reserved1[17] u8 __attribute__::Reserved1[17]
    -
    - - - - - -
    -   - + +
    +

    Reserved

    -

    -Reserved

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Reserved2[13] u8 __attribute__::Reserved2[13]
    -
    - - - - - -
    -   - + +
    +

    Reserved

    -

    -Reserved

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Reserved3[12] u8 __attribute__::Reserved3[12]
    -
    - - - - - -
    -   - + +
    +

    Reserved

    -

    -Reserved

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Reserved4[6] u8 __attribute__::Reserved4[6]
    -
    - - - - - -
    -   - + +
    +

    Reserved

    -

    -Reserved

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::Revision u16 __attribute__::Revision
    -
    - - - - - -
    -   - + +
    +

    Revision Number

    -

    -Revision Number

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::Signature[4] u8 __attribute__::Signature[4]
    -
    - - - - - -
    -   - + +
    +

    Parameter page signature

    -

    -Parameter page signature

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::SpareBytesPerPage u16 __attribute__::SpareBytesPerPage
    -
    - - - - - -
    -   - + +
    +

    Number of spare bytes per page

    -

    -Number of spare bytes per page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::SpareBytesPerPartialPage u16 __attribute__::SpareBytesPerPartialPage
    -
    - - - - - -
    -   - + +
    +

    Number of spare bytes per partial page

    -

    -Number of spare bytes per partial page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::SynFeatures u8 __attribute__::SynFeatures
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Source synchronous features

    -

    -ONFI 2.3: Source synchronous features

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::SynTimingMode u16 __attribute__::SynTimingMode
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Source synchronous timing mode support

    -

    -ONFI 2.3: Source synchronous timing mode support

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TAdl u16 __attribute__::TAdl
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Program page register clear enhancement value

    -

    -ONFI 2.3: Program page register clear enhancement value

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TBers u16 __attribute__::TBers
    -
    - - - - - -
    -   - + +
    +

    Maximum block erase time

    -

    -Maximum block erase time

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TCcs u16 __attribute__::TCcs
    -
    - - - - - -
    -   - + +
    +

    Maximum change column setup time

    -

    -Maximum change column setup time

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TEr u16 __attribute__::TEr
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Typical page read time for EZ NAND

    -

    -ONFI 2.3: Typical page read time for EZ NAND

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TimingMode u16 __attribute__::TimingMode
    -
    - - - - - -
    -   - + +
    +

    Timing mode support

    -

    -Timing mode support

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TMr u16 __attribute__::TMr
    -
    - - - - - -
    -   - + +
    +

    ONFI 2.3: Maximum multi-plane read time

    -

    -ONFI 2.3: Maximum multi-plane read time

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TProg u16 __attribute__::TProg
    -
    - - - - - -
    -   - + +
    +

    Maximum page program time

    -

    -Maximum page program time

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::TR u16 __attribute__::TR
    -
    - - - - - -
    -   - + +
    +

    Maximum page read time

    -

    -Maximum page read time

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 __attribute__::VendorRevisionNum u16 __attribute__::VendorRevisionNum
    -
    - - - - - -
    -   - + +
    +

    Vendor specific revision number

    -

    -Vendor specific revision number

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 __attribute__::VendorSpecific[88] u8 __attribute__::VendorSpecific[88]
    -
    - - - - - -
    -   - + +
    +

    Vendor specific

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Vendor specific

    -

    The documentation for this struct was generated from the following file: -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern-members.html index ef65f006..442dd02b 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern-members.html @@ -2,28 +2,39 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_BadBlockPattern Member List

    This is the complete list of members for XNandPs_BadBlockPattern, including all inherited members.

    - - - - -
    LengthXNandPs_BadBlockPattern
    OffsetXNandPs_BadBlockPattern
    OptionsXNandPs_BadBlockPattern
    PatternXNandPs_BadBlockPattern
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_BadBlockPattern Member List

    This is the complete list of members for XNandPs_BadBlockPattern, including all inherited members. + + + + +
    LengthXNandPs_BadBlockPattern
    OffsetXNandPs_BadBlockPattern
    OptionsXNandPs_BadBlockPattern
    PatternXNandPs_BadBlockPattern
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern.html index 90f1762d..c707b423 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bad_block_pattern.html @@ -2,135 +2,108 @@ - XNandPs_BadBlockPattern Struct Reference + Xilinx Driver nandps v2_1: XNandPs_BadBlockPattern Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_BadBlockPattern Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -Bad block pattern -

    + + +

    +
    +

    XNandPs_BadBlockPattern Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - + + + + +

    Public Attributes

    u32 Options
    u32 Offset
    u32 Length
    u8 Pattern [2]

    Public Attributes

    u32 Options
    u32 Offset
    u32 Length
    u8 Pattern [2]
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    Bad block pattern

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u32 XNandPs_BadBlockPattern::Length u32 XNandPs_BadBlockPattern::Length
    -
    - - - - - -
    -   - + +
    +

    Number of bytes to check the pattern

    -

    -Number of bytes to check the pattern

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BadBlockPattern::Offset u32 XNandPs_BadBlockPattern::Offset
    -
    - - - - - -
    -   - + +
    +

    Offset to search for specified pattern

    -

    -Offset to search for specified pattern

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BadBlockPattern::Options u32 XNandPs_BadBlockPattern::Options
    -
    - - - - - -
    -   - + +
    +

    Options to search the bad block pattern

    -

    -Options to search the bad block pattern

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_BadBlockPattern::Pattern[2] u8 XNandPs_BadBlockPattern::Pattern[2]
    -
    - - - - - -
    -   - + +
    +

    Pattern format to search for

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Pattern format to search for

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc-members.html index de10764b..32662232 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc-members.html @@ -2,32 +2,43 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_BbtDesc Member List

    This is the complete list of members for XNandPs_BbtDesc, including all inherited members.

    - - - - - - - - -
    MaxBlocksXNandPs_BbtDesc
    PageOffsetXNandPs_BbtDesc
    SigLengthXNandPs_BbtDesc
    SignatureXNandPs_BbtDesc
    SigOffsetXNandPs_BbtDesc
    ValidXNandPs_BbtDesc
    VerOffsetXNandPs_BbtDesc
    VersionXNandPs_BbtDesc
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_BbtDesc Member List

    This is the complete list of members for XNandPs_BbtDesc, including all inherited members. + + + + + + + + +
    MaxBlocksXNandPs_BbtDesc
    PageOffsetXNandPs_BbtDesc
    SigLengthXNandPs_BbtDesc
    SignatureXNandPs_BbtDesc
    SigOffsetXNandPs_BbtDesc
    ValidXNandPs_BbtDesc
    VerOffsetXNandPs_BbtDesc
    VersionXNandPs_BbtDesc
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc.html index 4b03b24d..7c1226e7 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___bbt_desc.html @@ -2,235 +2,168 @@ - XNandPs_BbtDesc Struct Reference + Xilinx Driver nandps v2_1: XNandPs_BbtDesc Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_BbtDesc Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -Bad block table descriptor -

    + + +

    +
    +

    XNandPs_BbtDesc Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - - - - - - - - - + + + + + + + + +

    Public Attributes

    u32 PageOffset
    u32 SigOffset
    u32 VerOffset
    u32 SigLength
    u32 MaxBlocks
    char Signature [4]
    u8 Version
    u32 Valid

    Public Attributes

    u32 PageOffset
    u32 SigOffset
    u32 VerOffset
    u32 SigLength
    u32 MaxBlocks
    char Signature [4]
    u8 Version
    u32 Valid
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    Bad block table descriptor

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::MaxBlocks u32 XNandPs_BbtDesc::MaxBlocks
    -
    - - - - - -
    -   - + +
    +

    Max blocks to search for BBT

    -

    -Max blocks to search for BBT

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::PageOffset u32 XNandPs_BbtDesc::PageOffset
    -
    - - - - - -
    -   - + +
    +

    Page offset where BBT resides

    -

    -Page offset where BBT resides

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::SigLength u32 XNandPs_BbtDesc::SigLength
    -
    - - - - - -
    -   - + +
    +

    Length of the signature

    -

    -Length of the signature

    -

    - - - - -
    - + + + +
    +
    +
    - +
    char XNandPs_BbtDesc::Signature[4] char XNandPs_BbtDesc::Signature[4]
    -
    - - - - - -
    -   - + +
    +

    BBT signature

    -

    -BBT signature

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::SigOffset u32 XNandPs_BbtDesc::SigOffset
    -
    - - - - - -
    -   - + +
    +

    Signature offset in Spare area

    -

    -Signature offset in Spare area

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::Valid u32 XNandPs_BbtDesc::Valid
    -
    - - - - - -
    -   - + +
    +

    BBT descriptor is valid or not

    -

    -BBT descriptor is valid or not

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_BbtDesc::VerOffset u32 XNandPs_BbtDesc::VerOffset
    -
    - - - - - -
    -   - + +
    +

    Offset of BBT version

    -

    -Offset of BBT version

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_BbtDesc::Version u8 XNandPs_BbtDesc::Version
    -
    - - - - - -
    -   - + +
    +

    BBT version

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -BBT version

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format-members.html index ba9188d1..8ac3ef41 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format-members.html @@ -2,28 +2,39 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_CommandFormat Member List

    This is the complete list of members for XNandPs_CommandFormat, including all inherited members.

    - - - - -
    AddrCyclesXNandPs_CommandFormat
    EndCmdXNandPs_CommandFormat
    EndCmdValidXNandPs_CommandFormat
    StartCmdXNandPs_CommandFormat
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_CommandFormat Member List

    This is the complete list of members for XNandPs_CommandFormat, including all inherited members. + + + + +
    AddrCyclesXNandPs_CommandFormat
    EndCmdXNandPs_CommandFormat
    EndCmdValidXNandPs_CommandFormat
    StartCmdXNandPs_CommandFormat
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format.html index ad11bfaa..cf6d9775 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___command_format.html @@ -2,135 +2,108 @@ - XNandPs_CommandFormat Struct Reference + Xilinx Driver nandps v2_1: XNandPs_CommandFormat Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_CommandFormat Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -NAND Command format structures -

    + + +

    +
    +

    XNandPs_CommandFormat Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - + + + + +

    Public Attributes

    int StartCmd
    int EndCmd
    u8 AddrCycles
    u8 EndCmdValid

    Public Attributes

    int StartCmd
    int EndCmd
    u8 AddrCycles
    u8 EndCmdValid
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    NAND Command format structures

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u8 XNandPs_CommandFormat::AddrCycles u8 XNandPs_CommandFormat::AddrCycles
    -
    - - - - - -
    -   - + +
    +

    Number of address cycles

    -

    -Number of address cycles

    -

    - - - - -
    - + + + +
    +
    +
    - +
    int XNandPs_CommandFormat::EndCmd int XNandPs_CommandFormat::EndCmd
    -
    - - - - - -
    -   - + +
    +

    End command

    -

    -End command

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_CommandFormat::EndCmdValid u8 XNandPs_CommandFormat::EndCmdValid
    -
    - - - - - -
    -   - + +
    +

    End command valid

    -

    -End command valid

    -

    - - - - -
    - + + + +
    +
    +
    - +
    int XNandPs_CommandFormat::StartCmd int XNandPs_CommandFormat::StartCmd
    -
    - - - - - -
    -   - + +
    +

    Start command

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Start command

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config-members.html index dc07be23..f9d887c8 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config-members.html @@ -2,28 +2,39 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Config Member List

    This is the complete list of members for XNandPs_Config, including all inherited members.

    - - - - -
    DeviceIdXNandPs_Config
    FlashBaseXNandPs_Config
    FlashWidthXNandPs_Config
    SmcBaseXNandPs_Config
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_Config Member List

    This is the complete list of members for XNandPs_Config, including all inherited members. + + + + +
    DeviceIdXNandPs_Config
    FlashBaseXNandPs_Config
    FlashWidthXNandPs_Config
    SmcBaseXNandPs_Config
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config.html index 09851263..ef21da33 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___config.html @@ -2,135 +2,108 @@ - XNandPs_Config Struct Reference + Xilinx Driver nandps v2_1: XNandPs_Config Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Config Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -This typedef contains configuration information for the flash device. -

    + + +

    +
    +

    XNandPs_Config Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - + + + + +

    Public Attributes

    u16 DeviceId
    u32 SmcBase
    u32 FlashBase
    u32 FlashWidth

    Public Attributes

    u16 DeviceId
    u32 SmcBase
    u32 FlashBase
    u32 FlashWidth
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    This typedef contains configuration information for the flash device.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u16 XNandPs_Config::DeviceId u16 XNandPs_Config::DeviceId
    -
    - - - - - -
    -   - + +
    +

    Instance ID of device

    -

    -Instance ID of device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Config::FlashBase u32 XNandPs_Config::FlashBase
    -
    - - - - - -
    -   - + +
    +

    NAND base address

    -

    -NAND base address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Config::FlashWidth u32 XNandPs_Config::FlashWidth
    -
    - - - - - -
    -   - + +
    +

    Flash width

    -

    -Flash width

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Config::SmcBase u32 XNandPs_Config::SmcBase
    -
    - - - - - -
    -   - + +
    +

    SMC Base address

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -SMC Base address

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config-members.html index a056eb98..057a9607 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config-members.html @@ -2,29 +2,40 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_EccConfig Member List

    This is the complete list of members for XNandPs_EccConfig, including all inherited members.

    - - - - - -
    BlockSizeXNandPs_EccConfig
    BytesPerBlockXNandPs_EccConfig
    EccPosXNandPs_EccConfig
    NumStepsXNandPs_EccConfig
    TotalBytesXNandPs_EccConfig
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_EccConfig Member List

    This is the complete list of members for XNandPs_EccConfig, including all inherited members. + + + + + +
    BlockSizeXNandPs_EccConfig
    BytesPerBlockXNandPs_EccConfig
    EccPosXNandPs_EccConfig
    NumStepsXNandPs_EccConfig
    TotalBytesXNandPs_EccConfig
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config.html index c4e06ce3..ea3edcad 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___ecc_config.html @@ -2,160 +2,123 @@ - XNandPs_EccConfig Struct Reference + Xilinx Driver nandps v2_1: XNandPs_EccConfig Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_EccConfig Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -ECC configuration structure. Contains information related to ECC. -

    + + +

    +
    +

    XNandPs_EccConfig Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - - - + + + + + +

    Public Attributes

    u32 NumSteps
    u32 BlockSize
    u32 BytesPerBlock
    u32 TotalBytes
    u32 EccPos [XNANDPS_MAX_SPARE_SIZE]

    Public Attributes

    u32 NumSteps
    u32 BlockSize
    u32 BytesPerBlock
    u32 TotalBytes
    u32 EccPos [XNANDPS_MAX_SPARE_SIZE]
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    ECC configuration structure. Contains information related to ECC.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u32 XNandPs_EccConfig::BlockSize u32 XNandPs_EccConfig::BlockSize
    -
    - - - - - -
    -   - + +
    +

    ECC block size

    -

    -ECC block size

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_EccConfig::BytesPerBlock u32 XNandPs_EccConfig::BytesPerBlock
    -
    - - - - - -
    -   - + +
    +

    Number of ECC bytes for a block

    -

    -Number of ECC bytes for a block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_EccConfig::EccPos[XNANDPS_MAX_SPARE_SIZE] u32 XNandPs_EccConfig::EccPos[XNANDPS_MAX_SPARE_SIZE]
    -
    - - - - - -
    -   - + +
    +

    ECC position in the spare area

    -

    -ECC position in the spare area

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_EccConfig::NumSteps u32 XNandPs_EccConfig::NumSteps
    -
    - - - - - -
    -   - + +
    +

    Number of ECC steps for the flash page

    -

    -Number of ECC steps for the flash page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_EccConfig::TotalBytes u32 XNandPs_EccConfig::TotalBytes
    -
    - - - - - -
    -   - + +
    +

    Total number of ECC bytes for Page

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Total number of ECC bytes for Page

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features-members.html index 286a595a..99a3f451 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features-members.html @@ -2,24 +2,37 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Features Member List

    This is the complete list of members for XNandPs_Features, including all inherited members.

    -
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_Features Member List

    This is the complete list of members for XNandPs_Features, including all inherited members. + + +
    ProgramCacheXNandPs_Features
    ReadCacheXNandPs_Features
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features.html index 57977e18..328fcc6b 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___features.html @@ -2,33 +2,75 @@ - XNandPs_Features Struct Reference + Xilinx Driver nandps v2_1: XNandPs_Features Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Features Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -ONFI Features and Optional commands supported See parameter page byte 6-7 and 8-9 -

    + + +

    +
    +

    XNandPs_Features Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - + + +

    Public Attributes

    int ProgramCache
    int ReadCache
    -
    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +

    Detailed Description

    +

    ONFI Features and Optional commands supported See parameter page byte 6-7 and 8-9

    +

    Member Data Documentation

    + +
    +
    + + + + +
    int XNandPs_Features::ProgramCache
    +
    +
    + +
    +
    + +
    +
    + + + + +
    int XNandPs_Features::ReadCache
    +
    +
    + +
    +
    +
    The documentation for this struct was generated from the following file: +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry-members.html index 991e9e7d..4f23c531 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry-members.html @@ -2,36 +2,47 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Geometry Member List

    This is the complete list of members for XNandPs_Geometry, including all inherited members.

    - - - - - - - - - - - - -
    BlockSizeXNandPs_Geometry
    BlocksPerLunXNandPs_Geometry
    BytesPerPageXNandPs_Geometry
    ColAddrCyclesXNandPs_Geometry
    DeviceSizeXNandPs_Geometry
    FlashWidthXNandPs_Geometry
    NumBlocksXNandPs_Geometry
    NumLunXNandPs_Geometry
    NumPagesXNandPs_Geometry
    PagesPerBlockXNandPs_Geometry
    RowAddrCyclesXNandPs_Geometry
    SpareBytesPerPageXNandPs_Geometry
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPs_Geometry Member List

    This is the complete list of members for XNandPs_Geometry, including all inherited members. + + + + + + + + + + + + +
    BlockSizeXNandPs_Geometry
    BlocksPerLunXNandPs_Geometry
    BytesPerPageXNandPs_Geometry
    ColAddrCyclesXNandPs_Geometry
    DeviceSizeXNandPs_Geometry
    FlashWidthXNandPs_Geometry
    NumBlocksXNandPs_Geometry
    NumLunXNandPs_Geometry
    NumPagesXNandPs_Geometry
    PagesPerBlockXNandPs_Geometry
    RowAddrCyclesXNandPs_Geometry
    SpareBytesPerPageXNandPs_Geometry
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry.html index d34c1b6c..9d950ecc 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps___geometry.html @@ -2,335 +2,228 @@ - XNandPs_Geometry Struct Reference + Xilinx Driver nandps v2_1: XNandPs_Geometry Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPs_Geometry Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -Flash geometry -

    + + +

    +
    +

    XNandPs_Geometry Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + +

    Public Attributes

    u32 BytesPerPage
    u16 SpareBytesPerPage
    u32 PagesPerBlock
    u32 BlocksPerLun
    u8 NumLun
    u8 FlashWidth
    u64 NumPages
    u64 NumBlocks
    u64 BlockSize
    u64 DeviceSize
    u8 RowAddrCycles
    u8 ColAddrCycles

    Public Attributes

    u32 BytesPerPage
    u16 SpareBytesPerPage
    u32 PagesPerBlock
    u32 BlocksPerLun
    u8 NumLun
    u8 FlashWidth
    u64 NumPages
    u64 NumBlocks
    u64 BlockSize
    u64 DeviceSize
    u8 RowAddrCycles
    u8 ColAddrCycles
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    Flash geometry

    +

    Member Data Documentation

    + +
    +
    +
    - +
    u64 XNandPs_Geometry::BlockSize u64 XNandPs_Geometry::BlockSize
    -
    - - - - - -
    -   - + +
    +

    Size of a block in bytes

    -

    -Size of a block in bytes

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Geometry::BlocksPerLun u32 XNandPs_Geometry::BlocksPerLun
    -
    - - - - - -
    -   - + +
    +

    Bocks per LUN

    -

    -Bocks per LUN

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Geometry::BytesPerPage u32 XNandPs_Geometry::BytesPerPage
    -
    - - - - - -
    -   - + +
    +

    Bytes per page

    -

    -Bytes per page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_Geometry::ColAddrCycles u8 XNandPs_Geometry::ColAddrCycles
    -
    - - - - - -
    -   - + +
    +

    Column address cycles

    -

    -Column address cycles

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u64 XNandPs_Geometry::DeviceSize u64 XNandPs_Geometry::DeviceSize
    -
    - - - - - -
    -   - + +
    +

    Total device size in bytes

    -

    -Total device size in bytes

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_Geometry::FlashWidth u8 XNandPs_Geometry::FlashWidth
    -
    - - - - - -
    -   - + +
    +

    Data width of flash device

    -

    -Data width of flash device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u64 XNandPs_Geometry::NumBlocks u64 XNandPs_Geometry::NumBlocks
    -
    - - - - - -
    -   - + +
    +

    Total number of blocks in device

    -

    -Total number of blocks in device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_Geometry::NumLun u8 XNandPs_Geometry::NumLun
    -
    - - - - - -
    -   - + +
    +

    Total number of LUN

    -

    -Total number of LUN

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u64 XNandPs_Geometry::NumPages u64 XNandPs_Geometry::NumPages
    -
    - - - - - -
    -   - + +
    +

    Total number of pages in device

    -

    -Total number of pages in device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPs_Geometry::PagesPerBlock u32 XNandPs_Geometry::PagesPerBlock
    -
    - - - - - -
    -   - + +
    +

    Pages per block

    -

    -Pages per block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPs_Geometry::RowAddrCycles u8 XNandPs_Geometry::RowAddrCycles
    -
    - - - - - -
    -   - + +
    +

    Row address cycles

    -

    -Row address cycles

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u16 XNandPs_Geometry::SpareBytesPerPage u16 XNandPs_Geometry::SpareBytesPerPage
    -
    - - - - - -
    -   - + +
    +

    Size of spare area in bytes

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Size of spare area in bytes

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag-members.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag-members.html index 0313e116..2da56661 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag-members.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag-members.html @@ -2,42 +2,53 @@ - Member List + Xilinx Driver nandps v2_1: Member List - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPsTag Member List

    This is the complete list of members for XNandPsTag, including all inherited members.

    - - - - - - - - - - - - - - - - - - -
    BbPatternXNandPsTag
    BbtXNandPsTag
    BbtDescXNandPsTag
    BbtMirrorDescXNandPsTag
    CommandPhaseAddrXNandPsTag
    ConfigXNandPsTag
    DataBufXNandPsTag
    DataPhaseAddrXNandPsTag
    EccCalcXNandPsTag
    EccCodeXNandPsTag
    EccConfigXNandPsTag
    EccModeXNandPsTag
    FeaturesXNandPsTag
    GeometryXNandPsTag
    IsReadyXNandPsTag
    ReadPageXNandPsTag
    SpareBufPtrXNandPsTag
    WritePageXNandPsTag
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + + +

    +
    +

    XNandPsTag Member List

    This is the complete list of members for XNandPsTag, including all inherited members. + + + + + + + + + + + + + + + + + + +
    BbPatternXNandPsTag
    BbtXNandPsTag
    BbtDescXNandPsTag
    BbtMirrorDescXNandPsTag
    CommandPhaseAddrXNandPsTag
    ConfigXNandPsTag
    DataBufXNandPsTag
    DataPhaseAddrXNandPsTag
    EccCalcXNandPsTag
    EccCodeXNandPsTag
    EccConfigXNandPsTag
    EccModeXNandPsTag
    FeaturesXNandPsTag
    GeometryXNandPsTag
    IsReadyXNandPsTag
    ReadPageXNandPsTag
    SpareBufPtrXNandPsTag
    WritePageXNandPsTag
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag.html index ffbd67cc..9ce0ea5c 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/struct_x_nand_ps_tag.html @@ -2,485 +2,318 @@ - XNandPsTag Struct Reference + Xilinx Driver nandps v2_1: XNandPsTag Struct Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    XNandPsTag Struct Reference

    #include <xnandps.h> -

    -List of all members.

    Detailed Description

    -The XNandPs driver instance data. The user is required to allocate a variable of this type for every flash device in the system. A pointer to a variable of this type is then passed to the driver API functions. -

    + + +

    +
    +

    XNandPsTag Struct Reference

    +

    #include <xnandps.h>

    + +

    List of all members.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + +

    Public Attributes

    u32 IsReady
    XNandPs_Config Config
    XNandPs_Geometry Geometry
    XNandPs_Features Features
    u32 CommandPhaseAddr
    u32 DataPhaseAddr
    XNandPs_EccConfig EccConfig
    XNandPs_BbtDesc BbtDesc
    XNandPs_BbtDesc BbtMirrorDesc
    XNandPs_BadBlockPattern BbPattern
    u8 Bbt [XNANDPS_MAX_BLOCKS >> 2]
    u8 DataBuf [XNANDPS_MAX_PAGE_SIZE+XNANDPS_MAX_SPARE_SIZE]
    u8 * SpareBufPtr
    u8 EccCalc [XNANDPS_MAX_SPARE_SIZE]
    u8 EccCode [XNANDPS_MAX_SPARE_SIZE]
    XNandPs_EccMode EccMode
    int(* ReadPage )(struct XNandPsTag *InstancePtr, u8 *DstPtr)
    int(* WritePage )(struct XNandPsTag *InstancePtr, u8 *SrcPtr)

    Public Attributes

    u32 IsReady
    XNandPs_Config Config
    XNandPs_Geometry Geometry
    XNandPs_Features Features
    u32 CommandPhaseAddr
    u32 DataPhaseAddr
    XNandPs_EccConfig EccConfig
    XNandPs_BbtDesc BbtDesc
    XNandPs_BbtDesc BbtMirrorDesc
    XNandPs_BadBlockPattern BbPattern
    u8 Bbt [XNANDPS_MAX_BLOCKS >> 2]
    u8 DataBuf [XNANDPS_MAX_PAGE_SIZE+XNANDPS_MAX_SPARE_SIZE]
    u8 * SpareBufPtr
    u8 EccCalc [XNANDPS_MAX_SPARE_SIZE]
    u8 EccCode [XNANDPS_MAX_SPARE_SIZE]
    XNandPs_EccMode EccMode
    int(* ReadPage )(struct XNandPsTag *InstancePtr, u8 *DstPtr)
    int(* WritePage )(struct XNandPsTag *InstancePtr, u8 *SrcPtr)
    -

    Member Data Documentation

    -

    - - - - -
    - +

    Detailed Description

    +

    The XNandPs driver instance data. The user is required to allocate a variable of this type for every flash device in the system. A pointer to a variable of this type is then passed to the driver API functions.

    +

    Member Data Documentation

    + +
    +
    +
    - +
    XNandPs_BadBlockPattern XNandPsTag::BbPattern XNandPs_BadBlockPattern XNandPsTag::BbPattern
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern to search

    -

    -Bad block pattern to search

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPsTag::Bbt[XNANDPS_MAX_BLOCKS >> 2] u8 XNandPsTag::Bbt[XNANDPS_MAX_BLOCKS >> 2]
    -
    - - - - - -
    -   - + +
    +

    Bad block table array

    -

    -Bad block table array

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_BbtDesc XNandPsTag::BbtDesc XNandPs_BbtDesc XNandPsTag::BbtDesc
    -
    - - - - - -
    -   - + +
    +

    Bad block table descriptor

    -

    -Bad block table descriptor

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_BbtDesc XNandPsTag::BbtMirrorDesc XNandPs_BbtDesc XNandPsTag::BbtMirrorDesc
    -
    - - - - - -
    -   - + +
    +

    Mirror BBT descriptor

    -

    -Mirror BBT descriptor

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPsTag::CommandPhaseAddr u32 XNandPsTag::CommandPhaseAddr
    -
    - - - - - -
    -   - + +
    +

    NAND command phase address

    -

    -NAND command phase address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_Config XNandPsTag::Config XNandPs_Config XNandPsTag::Config
    -
    - - - - - -
    -   - + +
    +

    XNandPs_Config of current device

    -

    -XNandPs_Config of current device

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPsTag::DataBuf[XNANDPS_MAX_PAGE_SIZE+XNANDPS_MAX_SPARE_SIZE] u8 XNandPsTag::DataBuf[XNANDPS_MAX_PAGE_SIZE+XNANDPS_MAX_SPARE_SIZE]
    -
    - - - - - -
    -   - + +
    +

    Data buffer for partial read/writes

    -

    -Data buffer for partial read/writes

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPsTag::DataPhaseAddr u32 XNandPsTag::DataPhaseAddr
    -
    - - - - - -
    -   - + +
    +

    NAND Data phase address

    -

    -NAND Data phase address

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPsTag::EccCalc[XNANDPS_MAX_SPARE_SIZE] u8 XNandPsTag::EccCalc[XNANDPS_MAX_SPARE_SIZE]
    -
    - - - - - -
    -   - + +
    +

    Buffer for calculated ECC

    -

    -Buffer for calculated ECC

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8 XNandPsTag::EccCode[XNANDPS_MAX_SPARE_SIZE] u8 XNandPsTag::EccCode[XNANDPS_MAX_SPARE_SIZE]
    -
    - - - - - -
    -   - + +
    +

    Buffer for stored ECC

    -

    -Buffer for stored ECC

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_EccConfig XNandPsTag::EccConfig XNandPs_EccConfig XNandPsTag::EccConfig
    -
    - - - - - -
    -   - + +
    +

    ECC configuration parameters

    -

    -ECC configuration parameters

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_EccMode XNandPsTag::EccMode XNandPs_EccMode XNandPsTag::EccMode
    -
    - - - - - -
    -   - + +
    +

    ECC Mode

    -

    -ECC Mode

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_Features XNandPsTag::Features XNandPs_Features XNandPsTag::Features
    -
    - - - - - -
    -   - + +
    +

    Features and Optional commands

    -

    -Features and Optional commands

    -

    - - - - -
    - + + + +
    +
    +
    - +
    XNandPs_Geometry XNandPsTag::Geometry XNandPs_Geometry XNandPsTag::Geometry
    -
    - - - - - -
    -   - + +
    +

    Part geometry

    -

    -Part geometry

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 XNandPsTag::IsReady u32 XNandPsTag::IsReady
    -
    - - - - - -
    -   - + +
    +

    Device is initialized and ready

    -

    -Device is initialized and ready

    -

    - - - - -
    - + + + +
    +
    +
    - +
    int(* XNandPsTag::ReadPage)(struct XNandPsTag *InstancePtr, u8 *DstPtr) int(* XNandPsTag::ReadPage)(struct XNandPsTag *InstancePtr, u8 *DstPtr)
    -
    - - - - - -
    -   - + +
    +

    Read Page routine

    -

    -Read Page routine

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u8* XNandPsTag::SpareBufPtr u8* XNandPsTag::SpareBufPtr
    -
    - - - - - -
    -   - + +
    +

    Pointer to store spare buffer

    -

    -Pointer to store spare buffer

    -

    - - - - -
    - + + + +
    +
    +
    - +
    int(* XNandPsTag::WritePage)(struct XNandPsTag *InstancePtr, u8 *SrcPtr) int(* XNandPsTag::WritePage)(struct XNandPsTag *InstancePtr, u8 *SrcPtr)
    -
    - - - - - -
    -   - + +
    +

    Write Page routine

    + +
    + +
    The documentation for this struct was generated from the following file: + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -Write Page routine

    -

    The documentation for this struct was generated from the following file:
      -
    • xnandps.h
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/tabs.css b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/tabs.css index a61552a6..a4441634 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/tabs.css +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/tabs.css @@ -32,7 +32,7 @@ DIV.tabs A float : left; background : url("tab_r.gif") no-repeat right top; border-bottom : 1px solid #84B0C7; - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -57,7 +57,7 @@ DIV.tabs SPAN white-space : nowrap; } -DIV.tabs INPUT +DIV.tabs #MSearchBox { float : right; display : inline; @@ -66,7 +66,7 @@ DIV.tabs INPUT DIV.tabs TD { - font-size : x-small; + font-size : 80%; font-weight : bold; text-decoration : none; } @@ -82,21 +82,24 @@ DIV.tabs A:hover SPAN background-position: 0% -150px; } -DIV.tabs LI#current A +DIV.tabs LI.current A { background-position: 100% -150px; border-width : 0px; } -DIV.tabs LI#current SPAN +DIV.tabs LI.current SPAN { background-position: 0% -150px; padding-bottom : 6px; } -DIV.nav +DIV.navpath { background : none; border : none; border-bottom : 1px solid #84B0C7; + text-align : center; + margin : 2px; + padding : 2px; } diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8c.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8c.html index 2e66281e..ebff3ab5 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8c.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8c.html @@ -2,32 +2,61 @@ - xnandps.c File Reference + Xilinx Driver nandps v2_1: xnandps.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xnandps.c File Reference

    Detailed Description

    -This file contains the implementation of the interface functions for XNandPs driver. Refer to the header file xnandps.h for more detailed information.

    -This module supports for NAND flash memory devices that conform to the "Open NAND Flash Interface" (ONFI) Specification. This modules implements basic flash operations like read, write and erase.

    -

    Note:
    None
    + + + +
    +

    xnandps.c File Reference

    #include "xnandps.h"
    +#include "xnandps_bbm.h"
    +#include "xnandps_onfi.h"
    + + + + + + + + + + + + + + + + + + + + +

    Functions

    void XNandPs_SendCommand (XNandPs *InstancePtr, XNandPs_CommandFormat *Command, int Page, int Column)
    void XNandPs_InitBbtDesc (XNandPs *InstancePtr)
    int XNandPs_ScanBbt (XNandPs *InstancePtr)
    u8 Onfi_CmdReadStatus (XNandPs *InstancePtr)
    int Onfi_NandInit (XNandPs *InstancePtr)
    int XNandPs_CfgInitialize (XNandPs *InstancePtr, XNandPs_Config *ConfigPtr, u32 SmcBaseAddr, u32 FlashBaseAddr)
    int XNandPs_Read (XNandPs *InstancePtr, u64 Offset, u32 Length, void *DestPtr, u8 *UserSparePtr)
    int XNandPs_ReadCache (XNandPs *InstancePtr, u64 Offset, u32 Length, void *DestPtr, u8 *UserSparePtr)
    int XNandPs_Write (XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_WriteCache (XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_ReadSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_WriteSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_EraseBlock (XNandPs *InstancePtr, u32 BlockNum)

    Variables

    u32 NandOob16 [] = {13, 14, 15}
    u32 NandOob32 [] = {26, 27, 28, 29, 30, 31}
    u32 NandOob64 []
    XNandPs_CommandFormat OnfiCommands []
    +

    Detailed Description

    +

    This file contains the implementation of the interface functions for XNandPs driver. Refer to the header file xnandps.h for more detailed information.

    +

    This module supports for NAND flash memory devices that conform to the "Open NAND Flash Interface" (ONFI) Specification. This modules implements basic flash operations like read, write and erase.

    +
    Note:
    None
    - MODIFICATION HISTORY:

    -

     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
  1.01a nm     28/02/2012  Fixed 16-bit issue with ONFI commands like
@@ -51,326 +80,237 @@ This module supports for NAND flash memory devices that conform to the "Open NAN
 			   Disabling/Re-enabling ECC block in read/write API's
 			   of spare bytes since we don't calculate ECC for
 			   spare bytes.
-
    -

    -#include "xnandps.h"
    -#include "xnandps_bbm.h"
    -#include "xnandps_onfi.h"
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Functions

    void XNandPs_SendCommand (XNandPs *InstancePtr, XNandPs_CommandFormat *Command, int Page, int Column)
    void XNandPs_InitBbtDesc (XNandPs *InstancePtr)
    int XNandPs_ScanBbt (XNandPs *InstancePtr)
    u8 Onfi_CmdReadStatus (XNandPs *InstancePtr)
    int Onfi_NandInit (XNandPs *InstancePtr)
    int XNandPs_CfgInitialize (XNandPs *InstancePtr, XNandPs_Config *ConfigPtr, u32 SmcBaseAddr, u32 FlashBaseAddr)
    int XNandPs_Read (XNandPs *InstancePtr, u64 Offset, u32 Length, void *DestPtr, u8 *UserSparePtr)
    int XNandPs_ReadCache (XNandPs *InstancePtr, u64 Offset, u32 Length, void *DestPtr, u8 *UserSparePtr)
    int XNandPs_Write (XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_WriteCache (XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_ReadSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_WriteSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_EraseBlock (XNandPs *InstancePtr, u32 BlockNum)

    Variables

    u32 NandOob16 [] = {13, 14, 15}
    u32 NandOob32 [] = {26, 27, 28, 29, 30, 31}
    u32 NandOob64 []
    XNandPs_CommandFormat OnfiCommands []
    -

    Function Documentation

    -

    - - - - -
    - + 2.01 kpc 07/24/2014 Fixed CR#808770. Update command register twice only + if flash device requires >= four address cycles. +

    Function Documentation

    + +
    +
    +
    - - - - - - + + + + + +
    u8 Onfi_CmdReadStatus ( XNandPs *  InstancePtr  ) u8 Onfi_CmdReadStatus (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function sends read status command to the flash device.

    -

    Parameters:
    + +
    +

    This function sends read status command to the flash device.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
    flash status value read
    -
    Note:
    None
    -
    -

    - - - - -
    - +
    Returns:
    flash status value read
    +
    Note:
    None
    + + + + +
    +
    +
    - - - - - - + + + + + +
    int Onfi_NandInit ( XNandPs *  InstancePtr  ) int Onfi_NandInit (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function initializes the NAND flash and gets the geometry information.

    -

    Parameters:
    + +
    +

    This function initializes the NAND flash and gets the geometry information.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if failed.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if failed.
      • +
    -
    Note:
    None
    -
    -

    - - - - -
    - +
    Note:
    None
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_CfgInitialize ( XNandPs *  InstancePtr, int XNandPs_CfgInitialize (XNandPs *  InstancePtr,
    XNandPs_Config *  ConfigPtr, XNandPs_Config *  ConfigPtr,
    u32  SmcBaseAddr, u32  SmcBaseAddr,
    u32  FlashBaseAddru32  FlashBaseAddr 
    ) )
    -
    - - - - - -
    -   - - -

    -This function initializes a specific XNandPs device/instance. This function must be called prior to using the flash device to read or write any data.

    -

    Parameters:
    + +
    +

    This function initializes a specific XNandPs device/instance. This function must be called prior to using the flash device to read or write any data.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    ConfigPtr points to the XNandPs device configuration structure.
    SmcBaseAddr is the base address of SMC controller.
    FlashBaseAddr is the base address of NAND flash.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    The user needs to first call the XNandPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPs_CfgInitialize() API.
    -
    -

    - - - - -
    - +
    Note:
    The user needs to first call the XNandPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPs_CfgInitialize() API.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_EraseBlock ( XNandPs *  InstancePtr, int XNandPs_EraseBlock (XNandPs *  InstancePtr,
    u32  BlockNumu32  BlockNum 
    ) )
    -
    - - - - - -
    -   - - -

    -This function erases a specific block in the NAND device.

    -

    Parameters:
    + +
    +

    This function erases a specific block in the NAND device.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    BlockNum is the block number of the device.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    -
    Note:
    None
    -
    -

    - - - - -
    - +
    Note:
    None
    + + + + +
    +
    +
    - - - - - - + + + + + +
    void XNandPs_InitBbtDesc ( XNandPs *  InstancePtr  ) void XNandPs_InitBbtDesc (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

    -

    Parameters:
    + +
    +

    This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
      -
    • NONE
    +
    Returns:
      +
    • NONE
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_Read ( XNandPs *  InstancePtr, int XNandPs_Read (XNandPs *  InstancePtr,
    u64  Offset, u64  Offset,
    u32  Length, u32  Length,
    void *  DestPtr, void *  DestPtr,
    u8 *  UserSparePtru8 *  UserSparePtr 
    ) )
    -
    - - - - - -
    -   - - -

    -This function reads the data from the Flash device and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    -

    Parameters:
    + +
    +

    This function reads the data from the Flash device and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    @@ -378,68 +318,61 @@ This function reads the data from the Flash device and copies it into the specif
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to read from.
    DestPtr is the destination address to copy data to.
    UserSparePtr is the user buffer to which spare data must be copied.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    This function reads sequential pages from the Flash device.
    -
    -

    - - - - -
    - +
    Note:
    This function reads sequential pages from the Flash device.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_ReadCache ( XNandPs *  InstancePtr, int XNandPs_ReadCache (XNandPs *  InstancePtr,
    u64  Offset, u64  Offset,
    u32  Length, u32  Length,
    void *  DestPtr, void *  DestPtr,
    u8 *  UserSparePtru8 *  UserSparePtr 
    ) )
    -
    - - - - - -
    -   - - -

    -This function reads the data from the Flash device using read page cache command and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    -

    Parameters:
    + +
    +

    This function reads the data from the Flash device using read page cache command and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    @@ -447,220 +380,190 @@ This function reads the data from the Flash device using read page cache command
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to read from.
    DestPtr is the destination address to copy data to.
    UserSparePtr is the user buffer to which spare data must be copied.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    This function reads sequential pages from the Flash device.
    -
    -

    - - - - -
    - +
    Note:
    This function reads sequential pages from the Flash device.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_ReadSpareBytes ( XNandPs *  InstancePtr, int XNandPs_ReadSpareBytes (XNandPs *  InstancePtr,
    u32  Page, u32  Page,
    u8 *  Bufu8 *  Buf 
    ) )
    -
    - - - - - -
    -   - - -

    -This function reads the spare area of a page.

    -

    Parameters:
    + +
    +

    This function reads the spare area of a page.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Page is the page number from where spare data is read.
    Buf is pointer to the buffer where the spare data is filled.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    int XNandPs_ScanBbt ( XNandPs *  InstancePtr  ) int XNandPs_ScanBbt (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function reads the Bad Block Table(BBT) if present in flash. If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

    -

    Parameters:
    + +
    +

    This function reads the Bad Block Table(BBT) if present in flash. If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    void XNandPs_SendCommand ( XNandPs *  InstancePtr, void XNandPs_SendCommand (XNandPs *  InstancePtr,
    XNandPs_CommandFormat *  Command, XNandPs_CommandFormat *  Command,
    int  Page, int  Page,
    int  Columnint  Column 
    ) )
    -
    - - - - - -
    -   - - -

    -This function sends a NAND command to the flash device.

    -

    Parameters:
    + +
    +

    This function sends a NAND command to the flash device.

    +
    Parameters:
    InstancePtr is the pointer to XNandPs struture
    Command is the NAND command to send
    Page is the page offset required for specific commands
    Column the column offset required for specific commands
    +
    -
    Returns:
    None
    -
    Note:
    None
    -
    -

    - - - - -
    - +
    Returns:
    None
    +
    Note:
    None
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_Write ( XNandPs *  InstancePtr, int XNandPs_Write (XNandPs *  InstancePtr,
    u64  Offset, u64  Offset,
    u32  Length, u32  Length,
    void *  SrcPtr, void *  SrcPtr,
    u8 *  UserSparePtru8 *  UserSparePtr 
    ) )
    -
    - - - - - -
    -   - - -

    -This function programs the flash device(s) with data specified in the user buffer. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    -

    Parameters:
    + +
    +

    This function programs the flash device(s) with data specified in the user buffer. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    @@ -668,68 +571,62 @@ This function programs the flash device(s) with data specified in the user buffe
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to write to.
    SrcPtr is the source address to write the data from.
    UserSparePtr is the user buffer which contains buffer to write into spare data area.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    -
    Note:
    This function writes number of sequential pages into the Flash device.
    -
    -

    - - - - -
    - +
    Note:
    This function writes number of sequential pages into the Flash device.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_WriteCache ( XNandPs *  InstancePtr, int XNandPs_WriteCache (XNandPs *  InstancePtr,
    u64  Offset, u64  Offset,
    u32  Length, u32  Length,
    void *  SrcPtr, void *  SrcPtr,
    u8 *  UserSparePtru8 *  UserSparePtr 
    ) )
    -
    - - - - - -
    -   - - -

    -This function programs the flash device(s) with data specified in the user buffer using program cache command. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    -

    Parameters:
    + +
    +

    This function programs the flash device(s) with data specified in the user buffer using program cache command. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    @@ -737,162 +634,130 @@ This function programs the flash device(s) with data specified in the user buffe
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to write to.
    SrcPtr is the source address to write the data from.
    UserSparePtr is the user buffer which contains buffer to write into spare data area.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    -
    Note:
    This function writes number of sequential pages into the Flash device.
    -
    -

    - - - - -
    - +
    Note:
    This function writes number of sequential pages into the Flash device.
    + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_WriteSpareBytes ( XNandPs *  InstancePtr, int XNandPs_WriteSpareBytes (XNandPs *  InstancePtr,
    u32  Page, u32  Page,
    u8 *  Bufu8 *  Buf 
    ) )
    -
    - - - - - -
    -   - - -

    -This function write to the spare area of a page.

    -

    Parameters:
    + +
    +

    This function write to the spare area of a page.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Page is the page number to write.
    Buf is pointer to the buffer which holds the data.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    None.
    -
    -

    Variable Documentation

    -

    - - - - -
    - +
    Note:
    None.
    + + + +

    Variable Documentation

    + +
    +
    +
    - +
    u32 NandOob16[] = {13, 14, 15} u32 NandOob16[] = {13, 14, 15}
    -
    - - - - - -
    -   - + +
    +

    Ecc position for 16 bytes spare area

    -

    -Ecc position for 16 bytes spare area

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 NandOob32[] = {26, 27, 28, 29, 30, 31} u32 NandOob32[] = {26, 27, 28, 29, 30, 31}
    -
    - - - - - -
    -   - + +
    +

    Ecc position for 32 bytes spare area

    -

    -Ecc position for 32 bytes spare area

    -

    - - - - -
    - + + + +
    +
    +
    - +
    u32 NandOob64[] u32 NandOob64[]
    -
    - - - - - -
    -   - - -

    + +

    Initial value:
     {52, 53, 54, 55, 56, 57,
                    58, 59, 60, 61, 62, 63}
-
    Ecc position for 64 bytes spare area
    -

    - - - - -
    - +

    Ecc position for 64 bytes spare area

    + + + + +
    +
    +
    - +
    XNandPs_CommandFormat OnfiCommands[] XNandPs_CommandFormat OnfiCommands[]
    -
    - - - - - -
    -   - + +
    +

    ONFI commands

    +

    This structure defines the onfi command format sent to the flash.

    + +
    + + +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + -

    -This structure defines the onfi command format sent to the flash.

    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8h.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8h.html new file mode 100755 index 00000000..0b75e2b5 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps_8h.html @@ -0,0 +1,1286 @@ + + + + + Xilinx Driver nandps v2_1: xnandps.h File Reference + + + +

    Xilinx Processor IP Library

    +Software Drivers +
    + + + +
    +

    xnandps.h File Reference

    #include <string.h>
    +#include "xil_types.h"
    +#include "xil_assert.h"
    +#include "xil_io.h"
    +#include "xstatus.h"
    +#include "xnandps_hw.h"
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Classes

    struct  XNandPs_Config
    struct  XNandPs_Geometry
    struct  XNandPs_Features
    struct  XNandPs_BbtDesc
    struct  XNandPs_BadBlockPattern
    struct  XNandPs_EccConfig
    struct  XNandPsTag
    struct  XNandPs_CommandFormat

    Defines

    #define XNANDPS_H
    #define XNANDPS_MAX_TARGETS   1
    #define XNANDPS_MAX_BLOCKS   32768
    #define XNANDPS_MAX_PAGE_SIZE   16384
    #define XNANDPS_MAX_SPARE_SIZE   512
    #define XNANDPS_ECC_BLOCK_SIZE   512
    #define XNANDPS_ECC_BYTES   3
    #define XNANDPS_PAGE_SIZE_512   512
    #define XNANDPS_PAGE_SIZE_1024   1024
    #define XNANDPS_PAGE_SIZE_2048   2048
    #define XNANDPS_PAGE_SIZE_4096   4096
    #define XNANDPS_PAGE_SIZE_8192   8192
    #define XNANDPS_SPARE_SIZE_8   8
    #define XNANDPS_SPARE_SIZE_16   16
    #define XNANDPS_SPARE_SIZE_32   32
    #define XNANDPS_SPARE_SIZE_64   64
    #define XNANDPS_SPARE_SIZE_128   128
    #define XNANDPS_SPARE_SIZE_256   256
    #define XNANDPS_FLASH_WIDTH_8   8
    #define XNANDPS_FLASH_WIDTH_16   16
    #define XNANDPS_END_CMD_NONE   0
    #define XNANDPS_END_CMD_INVALID   0
    #define XNANDPS_CMD_PHASE   1
    #define XNANDPS_DATA_PHASE   2
    #define XNANDPS_PAGE_NOT_VALID   -1
    #define XNANDPS_COLUMN_NOT_VALID   -1
    #define XNANDPS_AXI_DATA_WIDTH   4
    #define XNANDPS_START_CMD_SHIFT   3
    #define XNANDPS_END_CMD_SHIFT   11
    #define XNANDPS_END_CMD_VALID_SHIFT   20
    #define XNANDPS_ADDR_CYCLES_SHIFT   21
    #define XNANDPS_CHIP_ADDR_SHIFT   24
    #define XNANDPS_ECC_LAST_SHIFT   10
    #define XNANDPS_CLEAR_CS_SHIFT   21
    #define XNANDPS_COMMAND_PHASE_MASK   0x00000000
    #define XNANDPS_DATA_PHASE_MASK   0x00080000
    #define XNANDPS_ECC_CORRECT_BYTE_MASK   0x1FF
    #define XNANDPS_ECC_CORRECT_BIT_MASK   0x7
    #define XNANDPS_CLR_CONFIG
    #define XNANDPS_ECC_MEMCFG
    #define XNANDPS_ECC_CMD1
    #define XNANDPS_ECC_CMD2
    #define XNANDPS_CLR_CS   (0x1 << XNANDPS_CLEAR_CS_SHIFT)
    #define XNANDPS_ECC_LAST   (0x1 << XNANDPS_ECC_LAST_SHIFT)
    #define OneHot(Value)   (!((Value) & (Value - 1)))

    Typedefs

    typedef struct XNandPsTag XNandPs

    Enumerations

    enum  XNandPs_EccMode { XNANDPS_ECC_NONE = 0, +XNANDPS_ECC_SW, +XNANDPS_ECC_HW, +XNANDPS_ECC_ONDIE + }

    Functions

    XNandPs_Config * XNandPs_LookupConfig (u16 DeviceId)
    int XNandPs_CfgInitialize (XNandPs *InstancePtr, XNandPs_Config *ConfigPtr, u32 SmcBaseAddr, u32 FlashBaseAddr)
    int XNandPs_Read (XNandPs *InstancePtr, u64 Offset, u32 Bytes, void *DestPtr, u8 *UserSparePtr)
    int XNandPs_ReadCache (XNandPs *InstancePtr, u64 Offset, u32 Bytes, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_Write (XNandPs *InstancePtr, u64 Offset, u32 Bytes, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_WriteCache (XNandPs *InstancePtr, u64 Offset, u32 Length, void *SrcPtr, u8 *UserSparePtr)
    int XNandPs_ReadSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_WriteSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    int XNandPs_EraseBlock (XNandPs *InstancePtr, u32 BlockNum)
    +

    Detailed Description

    +

    Define Documentation

    + +
    +
    + + + + + + + + + +
    #define OneHot(Value  )    (!((Value) & (Value - 1)))
    +
    +
    +

    OneHot is used to check if one and only one bit is set. This Macro returns 1 if the value passed is OneHot.

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ADDR_CYCLES_SHIFT   21
    +
    +
    +

    Address cycles shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_AXI_DATA_WIDTH   4
    +
    +
    +

    AXI Data width for last transaction while reading and writing

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_CHIP_ADDR_SHIFT   24
    +
    +
    +

    Chip address shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_CLEAR_CS_SHIFT   21
    +
    +
    +

    clear chip select shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_CLR_CONFIG
    +
    +
    +Value:
    ((XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK)    | \
+                        (XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK) | \
+                        (XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK))
+

    Interrupt settings

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_CLR_CS   (0x1 << XNANDPS_CLEAR_CS_SHIFT)
    +
    +
    +

    set Clear chip select

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_CMD_PHASE   1
    +
    +
    +

    End command in command phase

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_COLUMN_NOT_VALID   -1
    +
    +
    +

    Column is not valid in command phase

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_COMMAND_PHASE_MASK   0x00000000
    +
    +
    +

    Command phase mask

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_DATA_PHASE   2
    +
    +
    +

    End command in data phase

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_DATA_PHASE_MASK   0x00080000
    +
    +
    +

    Data phase mask

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_BLOCK_SIZE   512
    +
    +
    +

    ECC block size

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_BYTES   3
    +
    +
    +

    ECC bytes per ECC block

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_CMD1
    +
    +
    +Value:
    ((0x80 << XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT) | \
+                (0x00 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT)  | \
+                (0x30 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT) | \
+                (0x1 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT))
+

    ECC command 1 settings

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_CMD2
    +
    +
    +Value:
    ((0x85 << XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT) | \
+                (0x05 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT)  | \
+                (0xE0 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT) | \
+        (0x1 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT))
+

    ECC command 2 settings

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_CORRECT_BIT_MASK   0x7
    +
    +
    +

    ECC error correction bit position mask, bits[0:2] of error code

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_CORRECT_BYTE_MASK   0x1FF
    +
    +
    +

    ECC error correction byte position mask, bits[11:3] of error code

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_LAST   (0x1 << XNANDPS_ECC_LAST_SHIFT)
    +
    +
    +

    set Ecc last

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_LAST_SHIFT   10
    +
    +
    +

    Ecc last shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_ECC_MEMCFG
    +
    +
    +Value:
    ((0x1 << XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT) | \
+                        (0x1 << XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT)  | \
+                        (0x0 << XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT))
+

    ECC memory configuration settings

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_END_CMD_INVALID   0
    +
    +
    +

    End command invalid

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_END_CMD_NONE   0
    +
    +
    +

    No End command

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_END_CMD_SHIFT   11
    +
    +
    +

    End command shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_END_CMD_VALID_SHIFT   20
    +
    +
    +

    End command valid shift

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_FLASH_WIDTH_16   16
    +
    +
    +

    NAND Flash width 16-bit

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_FLASH_WIDTH_8   8
    +
    +
    +

    NAND Flash width 8-bit

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_H
    +
    +
    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_MAX_BLOCKS   32768
    +
    +
    +

    Max number of Blocks

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_MAX_PAGE_SIZE   16384
    +
    +
    +

    Max page size of NAND flash

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_MAX_SPARE_SIZE   512
    +
    +
    +

    Max spare bytes of a NAND flash page

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_MAX_TARGETS   1
    +
    +
    +

    Max number of targets supported

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_NOT_VALID   -1
    +
    +
    +

    Page is not valid in command phase

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_SIZE_1024   1024
    +
    +
    +

    Page size 1024

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_SIZE_2048   2048
    +
    +
    +

    Page size 2048

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_SIZE_4096   4096
    +
    +
    +

    Page size 4096

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_SIZE_512   512
    +
    +
    +

    Page size 512

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_PAGE_SIZE_8192   8192
    +
    +
    +

    Page size 8192

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_128   128
    +
    +
    +

    Spare bytes size 128

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_16   16
    +
    +
    +

    Spare bytes size 16

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_256   256
    +
    +
    +

    Spare bytes size 256

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_32   32
    +
    +
    +

    Spare bytes size 32

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_64   64
    +
    +
    +

    Spare bytes size 64

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_SPARE_SIZE_8   8
    +
    +
    +

    Spare bytes size 8

    + +
    +
    + +
    +
    + + + + +
    #define XNANDPS_START_CMD_SHIFT   3
    +
    +
    +

    Start command shift

    + +
    +
    +

    Typedef Documentation

    + +
    +
    + + + + +
    typedef struct XNandPsTag XNandPs
    +
    +
    +

    The XNandPs driver instance data. The user is required to allocate a variable of this type for every flash device in the system. A pointer to a variable of this type is then passed to the driver API functions.

    + +
    +
    +

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum XNandPs_EccMode
    +
    +
    +
    Enumerator:
    + + + + +
    XNANDPS_ECC_NONE  +

    No ECC

    +
    XNANDPS_ECC_SW  +

    Software ECC

    +
    XNANDPS_ECC_HW  +

    Hardware controller ECC

    +
    XNANDPS_ECC_ONDIE  +

    On-Die ECC

    +
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_CfgInitialize (XNandPs *  InstancePtr,
    XNandPs_Config *  ConfigPtr,
    u32  SmcBaseAddr,
    u32  FlashBaseAddr 
    )
    +
    +
    +

    This function initializes a specific XNandPs device/instance. This function must be called prior to using the flash device to read or write any data.

    +
    Parameters:
    + + + + + +
    InstancePtr is a pointer to the XNandPs instance.
    ConfigPtr points to the XNandPs device configuration structure.
    SmcBaseAddr is the base address of SMC controller.
    FlashBaseAddr is the base address of NAND flash.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    +
    +
    Note:
    The user needs to first call the XNandPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPs_CfgInitialize() API.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int XNandPs_EraseBlock (XNandPs *  InstancePtr,
    u32  BlockNum 
    )
    +
    +
    +

    This function erases a specific block in the NAND device.

    +
    Parameters:
    + + + +
    InstancePtr is a pointer to the XNandPs instance.
    BlockNum is the block number of the device.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    +
    +
    Note:
    None
    + +
    +
    + +
    +
    + + + + + + + + + +
    XNandPs_Config* XNandPs_LookupConfig (u16  DeviceId ) 
    +
    +
    +

    This function looks up the device configuration based on the unique device ID. The table XNandPs_ConfigTable contains the configuration info for each device in the system.

    +
    Parameters:
    + + +
    DeviceId contains the ID of the device for which the device configuration pointer is to be returned.
    +
    +
    +
    Returns:
      +
    • A pointer to the configuration found.
      • +
    • NULL if the specified device ID was not found.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_Read (XNandPs *  InstancePtr,
    u64  Offset,
    u32  Length,
    void *  DestPtr,
    u8 *  UserSparePtr 
    )
    +
    +
    +

    This function reads the data from the Flash device and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    + + + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to read from.
    Length is number of bytes to read.
    DestPtr is the destination address to copy data to.
    UserSparePtr is the user buffer to which spare data must be copied.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    +
    +
    Note:
    This function reads sequential pages from the Flash device.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_ReadCache (XNandPs *  InstancePtr,
    u64  Offset,
    u32  Length,
    void *  DestPtr,
    u8 *  UserSparePtr 
    )
    +
    +
    +

    This function reads the data from the Flash device using read page cache command and copies it into the specified user buffer. It doesn't check for the bad blocks while reading the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    + + + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to read from.
    Length is number of bytes to read.
    DestPtr is the destination address to copy data to.
    UserSparePtr is the user buffer to which spare data must be copied.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    +
    +
    Note:
    This function reads sequential pages from the Flash device.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_ReadSpareBytes (XNandPs *  InstancePtr,
    u32  Page,
    u8 *  Buf 
    )
    +
    +
    +

    This function reads the spare area of a page.

    +
    Parameters:
    + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Page is the page number from where spare data is read.
    Buf is pointer to the buffer where the spare data is filled.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    +
    +
    Note:
    None.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_Write (XNandPs *  InstancePtr,
    u64  Offset,
    u32  Length,
    void *  SrcPtr,
    u8 *  UserSparePtr 
    )
    +
    +
    +

    This function programs the flash device(s) with data specified in the user buffer. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    + + + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to write to.
    Length is number of bytes to write.
    SrcPtr is the source address to write the data from.
    UserSparePtr is the user buffer which contains buffer to write into spare data area.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    +
    +
    Note:
    This function writes number of sequential pages into the Flash device.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_WriteCache (XNandPs *  InstancePtr,
    u64  Offset,
    u32  Length,
    void *  SrcPtr,
    u8 *  UserSparePtr 
    )
    +
    +
    +

    This function programs the flash device(s) with data specified in the user buffer using program cache command. The source and destination address must be aligned to the width of the flash's data bus. It doesn't check for the bad blocks while writing to the flash pages that cross block boundary. User must take care of handling bad blocks.

    +
    Parameters:
    + + + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Offset is the flash data address to write to.
    Length is number of bytes to write.
    SrcPtr is the source address to write the data from.
    UserSparePtr is the user buffer which contains buffer to write into spare data area.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    • XST_NAND_WRITE_PROTECTED if the flash is write protected.
      • +
    +
    +
    Note:
    This function writes number of sequential pages into the Flash device.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    int XNandPs_WriteSpareBytes (XNandPs *  InstancePtr,
    u32  Page,
    u8 *  Buf 
    )
    +
    +
    +

    This function write to the spare area of a page.

    +
    Parameters:
    + + + + +
    InstancePtr is the pointer to the XNandPs instance.
    Page is the page number to write.
    Buf is pointer to the buffer which holds the data.
    +
    +
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    +
    +
    Note:
    None.
    + +
    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8c.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8c.html index 22dac75a..cca48ee9 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8c.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8c.html @@ -2,275 +2,241 @@ - xnandps_bbm.c File Reference + Xilinx Driver nandps v2_1: xnandps_bbm.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xnandps_bbm.c File Reference

    Detailed Description

    -This file implements the Bad Block Management (BBM) functionality. See xnandps_bbm.h for more details.

    -

    Note:
    None
    + + + +
    +

    xnandps_bbm.c File Reference

    #include <string.h>
    +#include "xil_types.h"
    +#include "xnandps_bbm.h"
    + + + + + + + +

    Functions

    int XNandPs_ReadSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    void XNandPs_InitBbtDesc (XNandPs *InstancePtr)
    int XNandPs_ScanBbt (XNandPs *InstancePtr)
    int XNandPs_IsBlockBad (XNandPs *InstancePtr, u32 Block)
    int XNandPs_MarkBlockBad (XNandPs *InstancePtr, u32 Block)
    +

    Detailed Description

    +

    This file implements the Bad Block Management (BBM) functionality. See xnandps_bbm.h for more details.

    +
    Note:
    None
    - MODIFICATION HISTORY:

    -

     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
  1.03a nm     10/22/2012  Fixed CR# 683787.
-
    -

    -#include <string.h>
    -#include "xil_types.h"
    -#include "xnandps_bbm.h"
    - - - - - - - - - - - - - -

    Functions

    int XNandPs_ReadSpareBytes (XNandPs *InstancePtr, u32 Page, u8 *Buf)
    void XNandPs_InitBbtDesc (XNandPs *InstancePtr)
    int XNandPs_ScanBbt (XNandPs *InstancePtr)
    int XNandPs_IsBlockBad (XNandPs *InstancePtr, u32 Block)
    int XNandPs_MarkBlockBad (XNandPs *InstancePtr, u32 Block)
    -

    Function Documentation

    -

    - - - - -
    - +

    Function Documentation

    + +
    +
    +
    - - - - - - + + + + + +
    void XNandPs_InitBbtDesc ( XNandPs *  InstancePtr  ) void XNandPs_InitBbtDesc (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

    -

    Parameters:
    + +
    +

    This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
      -
    • NONE
    +
    Returns:
      +
    • NONE
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_IsBlockBad ( XNandPs *  InstancePtr, int XNandPs_IsBlockBad (XNandPs *  InstancePtr,
    u32  Blocku32  Block 
    ) )
    -
    - - - - - -
    -   - - -

    -This function checks whether a block is bad or not.

    -

    Parameters:
    + +
    +

    This function checks whether a block is bad or not.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Block is the block number.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_MarkBlockBad ( XNandPs *  InstancePtr, int XNandPs_MarkBlockBad (XNandPs *  InstancePtr,
    u32  Blocku32  Block 
    ) )
    -
    - - - - - -
    -   - - -

    -This function marks a block as bad in the RAM based Bad Block Table(BBT). It also updates the Bad Block Table(BBT) in the flash.

    -

    Parameters:
    + +
    +

    This function marks a block as bad in the RAM based Bad Block Table(BBT). It also updates the Bad Block Table(BBT) in the flash.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Block is the block number.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_ReadSpareBytes ( XNandPs *  InstancePtr, int XNandPs_ReadSpareBytes (XNandPs *  InstancePtr,
    u32  Page, u32  Page,
    u8 *  Bufu8 *  Buf 
    ) )
    -
    - - - - - -
    -   - - -

    -This function reads the spare area of a page.

    -

    Parameters:
    + +
    +

    This function reads the spare area of a page.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Page is the page number from where spare data is read.
    Buf is pointer to the buffer where the spare data is filled.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Note:
    None.
    + + + + +
    +
    +
    - - - - - - + + + + + +
    int XNandPs_ScanBbt ( XNandPs *  InstancePtr  ) int XNandPs_ScanBbt (XNandPs *  InstancePtr ) 
    -
    - - - - - -
    -   - - -

    -This function reads the Bad Block Table(BBT) if present in flash. If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

    -

    Parameters:
    + +
    +

    This function reads the Bad Block Table(BBT) if present in flash. If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

    +
    Parameters:
    InstancePtr is a pointer to the XNandPs instance.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8h.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8h.html index c6f29d24..cdd16bc9 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8h.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__bbm_8h.html @@ -2,756 +2,521 @@ - xnandps_bbm.h File Reference + Xilinx Driver nandps v2_1: xnandps_bbm.h File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xnandps_bbm.h File Reference

    Detailed Description

    -This file implements the Bad Block Management(BBM) functionality. This is similar to the Bad Block Management which is a part of the MTD subsystem in Linux. The factory marked bad blocks are scanned initially and a Bad Block Table(BBT) is created in the memory. This table is also written to the flash so that upon reboot, the BBT is read back from the flash and loaded into the memory instead of scanning every time. The Bad Block Table(BBT) is written into one of the the last four blocks in the flash memory. The last four blocks are marked as Reserved so that user can't erase/program those blocks.

    -There are two bad block tables, a primary table and a mirror table. The tables are versioned and incrementing version number is used to detect and recover from interrupted updates. Each table is stored in a separate block, beginning in the first page of that block. Only two blocks would be necessary in the absence of bad blocks within the last four; the range of four provides a little slack in case one or two of those blocks is bad. These blocks are marked as reserved and cannot be programmed by the user. A NAND Flash device with 3 or more factory bad blocks in the last 4 cannot be used. The bad block table signature is written into the spare data area of the pages containing bad block table so that upon rebooting the bad block table signature is searched and the bad block table is loaded into RAM. The signature is "Bbt0" for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The version offset follows the signature offset in the spare data area. The version number increments on every update to the bad block table and the version wraps at 0xff.

    -Each block in the Bad Block Table(BBT) is represented by 2 bits. The two bits are encoded as follows in RAM BBT. 0'b00 -> Good Block 0'b01 -> Block is bad due to wear 0'b10 -> Reserved block 0'b11 -> Factory marked bad block

    -While writing to the flash the two bits are encoded as follows. 0'b00 -> Factory marked bad block 0'b01 -> Reserved block 0'b10 -> Block is bad due to wear 0'b11 -> Good Block

    -The user can check for the validity of the block using the API XNandPs_IsBlockBad and take the action based on the return value. Also user can update the bad block table using XNandPs_MarkBlockBad API.

    -

    Note:
    None
    + + + +
    +

    xnandps_bbm.h File Reference

    #include "xnandps.h"
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Defines

    #define BBM_H
    #define XNANDPS_BLOCK_GOOD   0x0
    #define XNANDPS_BLOCK_BAD   0x1
    #define XNANDPS_BLOCK_RESERVED   0x2
    #define XNANDPS_BLOCK_FACTORY_BAD   0x3
    #define XNANDPS_FLASH_BLOCK_GOOD   0x3
    #define XNANDPS_FLASH_BLOCK_BAD   0x2
    #define XNANDPS_FLASH_BLOCK_RESERVED   0x1
    #define XNANDPS_FLASH_BLOCK_FACTORY_BAD   0x0
    #define XNANDPS_BBT_SCAN_2ND_PAGE   0x00000001
    #define XNANDPS_BBT_DESC_PAGE_OFFSET   0
    #define XNANDPS_BBT_DESC_SIG_OFFSET   8
    #define XNANDPS_BBT_DESC_VER_OFFSET   12
    #define XNANDPS_BBT_DESC_SIG_LEN   4
    #define XNANDPS_BBT_DESC_MAX_BLOCKS   4
    #define XNANDPS_BBT_BLOCK_SHIFT   2
    #define XNANDPS_BBT_ENTRY_NUM_BLOCKS   4
    #define XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE   5
    #define XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE   1
    #define XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE   0
    #define XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE   2
    #define XNANDPS_BB_PATTERN   0xFF
    #define XNANDPS_BLOCK_TYPE_MASK   0x03
    #define XNANDPS_BLOCK_SHIFT_MASK   0x06
    #define XNandPs_BbtBlockShift(Block)   ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)

    Functions

    int XNandPs_IsBlockBad (XNandPs *InstancePtr, u32 Block)
    int XNandPs_MarkBlockBad (XNandPs *InstancePtr, u32 Block)
    +

    Detailed Description

    +

    This file implements the Bad Block Management(BBM) functionality. This is similar to the Bad Block Management which is a part of the MTD subsystem in Linux. The factory marked bad blocks are scanned initially and a Bad Block Table(BBT) is created in the memory. This table is also written to the flash so that upon reboot, the BBT is read back from the flash and loaded into the memory instead of scanning every time. The Bad Block Table(BBT) is written into one of the the last four blocks in the flash memory. The last four blocks are marked as Reserved so that user can't erase/program those blocks.

    +

    There are two bad block tables, a primary table and a mirror table. The tables are versioned and incrementing version number is used to detect and recover from interrupted updates. Each table is stored in a separate block, beginning in the first page of that block. Only two blocks would be necessary in the absence of bad blocks within the last four; the range of four provides a little slack in case one or two of those blocks is bad. These blocks are marked as reserved and cannot be programmed by the user. A NAND Flash device with 3 or more factory bad blocks in the last 4 cannot be used. The bad block table signature is written into the spare data area of the pages containing bad block table so that upon rebooting the bad block table signature is searched and the bad block table is loaded into RAM. The signature is "Bbt0" for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The version offset follows the signature offset in the spare data area. The version number increments on every update to the bad block table and the version wraps at 0xff.

    +

    Each block in the Bad Block Table(BBT) is represented by 2 bits. The two bits are encoded as follows in RAM BBT. 0'b00 -> Good Block 0'b01 -> Block is bad due to wear 0'b10 -> Reserved block 0'b11 -> Factory marked bad block

    +

    While writing to the flash the two bits are encoded as follows. 0'b00 -> Factory marked bad block 0'b01 -> Reserved block 0'b10 -> Block is bad due to wear 0'b11 -> Good Block

    +

    The user can check for the validity of the block using the API XNandPs_IsBlockBad and take the action based on the return value. Also user can update the bad block table using XNandPs_MarkBlockBad API.

    +
    Note:
    None
    - MODIFICATION HISTORY:

    -

     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
-
    -

    -#include "xnandps.h"
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Defines

    #define XNANDPS_BLOCK_GOOD   0x0
    #define XNANDPS_BLOCK_BAD   0x1
    #define XNANDPS_BLOCK_RESERVED   0x2
    #define XNANDPS_BLOCK_FACTORY_BAD   0x3
    #define XNANDPS_FLASH_BLOCK_GOOD   0x3
    #define XNANDPS_FLASH_BLOCK_BAD   0x2
    #define XNANDPS_FLASH_BLOCK_RESERVED   0x1
    #define XNANDPS_FLASH_BLOCK_FACTORY_BAD   0x0
    #define XNANDPS_BBT_SCAN_2ND_PAGE   0x00000001
    #define XNANDPS_BBT_DESC_PAGE_OFFSET   0
    #define XNANDPS_BBT_DESC_SIG_OFFSET   8
    #define XNANDPS_BBT_DESC_VER_OFFSET   12
    #define XNANDPS_BBT_DESC_SIG_LEN   4
    #define XNANDPS_BBT_DESC_MAX_BLOCKS   4
    #define XNANDPS_BBT_BLOCK_SHIFT   2
    #define XNANDPS_BBT_ENTRY_NUM_BLOCKS   4
    #define XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE   5
    #define XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE   1
    #define XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE   0
    #define XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE   2
    #define XNANDPS_BB_PATTERN   0xFF
    #define XNANDPS_BLOCK_TYPE_MASK   0x03
    #define XNANDPS_BLOCK_SHIFT_MASK   0x06
    #define XNandPs_BbtBlockShift(Block)   ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)

    Functions

    int XNandPs_IsBlockBad (XNandPs *InstancePtr, u32 Block)
    int XNandPs_MarkBlockBad (XNandPs *InstancePtr, u32 Block)
    -

    Define Documentation

    -

    - - - - -
    - +

    Define Documentation

    + +
    +
    +
    - +
    #define XNANDPS_BB_PATTERN   0xFF #define BBM_H
    -
    - - - - - -
    -   - + +
    -

    -Bad block pattern to search in a page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE   2 #define XNANDPS_BB_PATTERN   0xFF
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern to search in a page

    -

    -Bad block pattern length

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE   1 #define XNANDPS_BB_PATTERN_LENGTH_LARGE_PAGE   2
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern length

    -

    -Bad block pattern length

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE   0 #define XNANDPS_BB_PATTERN_LENGTH_SMALL_PAGE   1
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern length

    -

    -Bad block pattern offset in a large page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE   5 #define XNANDPS_BB_PATTERN_OFFSET_LARGE_PAGE   0
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern offset in a large page

    -

    -Bad block pattern offset in a page

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_BLOCK_SHIFT   2 #define XNANDPS_BB_PATTERN_OFFSET_SMALL_PAGE   5
    -
    - - - - - -
    -   - + +
    +

    Bad block pattern offset in a page

    -

    -Block shift value for a block in BBT

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_DESC_MAX_BLOCKS   4 #define XNANDPS_BBT_BLOCK_SHIFT   2
    -
    - - - - - -
    -   - + +
    +

    Block shift value for a block in BBT

    -

    -Bad block Table max blocks

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_DESC_PAGE_OFFSET   0 #define XNANDPS_BBT_DESC_MAX_BLOCKS   4
    -
    - - - - - -
    -   - + +
    +

    Bad block Table max blocks

    -

    -Page offset of Bad Block Table Desc

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_DESC_SIG_LEN   4 #define XNANDPS_BBT_DESC_PAGE_OFFSET   0
    -
    - - - - - -
    -   - + +
    +

    Page offset of Bad Block Table Desc

    -

    -Bad block Table signature length

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_DESC_SIG_OFFSET   8 #define XNANDPS_BBT_DESC_SIG_LEN   4
    -
    - - - - - -
    -   - + +
    +

    Bad block Table signature length

    -

    -Bad Block Table signature offset

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_DESC_VER_OFFSET   12 #define XNANDPS_BBT_DESC_SIG_OFFSET   8
    -
    - - - - - -
    -   - + +
    +

    Bad Block Table signature offset

    -

    -Bad block Table version offset

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_ENTRY_NUM_BLOCKS   4 #define XNANDPS_BBT_DESC_VER_OFFSET   12
    -
    - - - - - -
    -   - + +
    +

    Bad block Table version offset

    -

    -Num of blocks in one BBT entry

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BBT_SCAN_2ND_PAGE   0x00000001 #define XNANDPS_BBT_ENTRY_NUM_BLOCKS   4
    -
    - - - - - -
    -   - + +
    +

    Num of blocks in one BBT entry

    -

    -Scan the second page for bad block information

    -

    - - - - -
    - + + + +
    +
    +
    - - - - - - +
    #define XNandPs_BbtBlockShift ( Block   )    ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)#define XNANDPS_BBT_SCAN_2ND_PAGE   0x00000001
    -
    - - - - - -
    -   - + +
    +

    Scan the second page for bad block information

    -

    -This macro returns the Block shift value corresponding to a Block.

    -

    Parameters:
    +
    + + +
    +
    + + + + + + + + + +
    #define XNandPs_BbtBlockShift(Block  )    ((Block * 2) & XNANDPS_BLOCK_SHIFT_MASK)
    +
    +
    +

    This macro returns the Block shift value corresponding to a Block.

    +
    Parameters:
    Block is the block number.
    +
    -
    Returns:
    Block shift value
    -
    Note:
    None.
    -
    -

    - - - - -
    - +
    Returns:
    Block shift value
    +
    Note:
    None.
    + + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_BAD   0x1 #define XNANDPS_BLOCK_BAD   0x1
    -
    - - - - - -
    -   - + +
    +

    Block is bad

    -

    -Block is bad

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_FACTORY_BAD   0x3 #define XNANDPS_BLOCK_FACTORY_BAD   0x3
    -
    - - - - - -
    -   - + +
    +

    Factory marked bad block

    -

    -Factory marked bad block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_GOOD   0x0 #define XNANDPS_BLOCK_GOOD   0x0
    -
    - - - - - -
    -   - + +
    +

    Block is good

    -

    -Block is good

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_RESERVED   0x2 #define XNANDPS_BLOCK_RESERVED   0x2
    -
    - - - - - -
    -   - + +
    +

    Reserved block

    -

    -Reserved block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_SHIFT_MASK   0x06 #define XNANDPS_BLOCK_SHIFT_MASK   0x06
    -
    - - - - - -
    -   - + +
    +

    Block shift mask for a Bad Block Table entry byte

    -

    -Block shift mask for a Bad Block Table entry byte

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_BLOCK_TYPE_MASK   0x03 #define XNANDPS_BLOCK_TYPE_MASK   0x03
    -
    - - - - - -
    -   - + +
    +

    Block type mask

    -

    -Block type mask

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_FLASH_BLOCK_BAD   0x2 #define XNANDPS_FLASH_BLOCK_BAD   0x2
    -
    - - - - - -
    -   - + +
    +

    Block is bad

    -

    -Block is bad

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_FLASH_BLOCK_FACTORY_BAD   0x0 #define XNANDPS_FLASH_BLOCK_FACTORY_BAD   0x0
    -
    - - - - - -
    -   - + +
    +

    Factory marked bad block

    -

    -Factory marked bad block

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_FLASH_BLOCK_GOOD   0x3 #define XNANDPS_FLASH_BLOCK_GOOD   0x3
    -
    - - - - - -
    -   - + +
    +

    Block is good

    -

    -Block is good

    -

    - - - - -
    - + + + +
    +
    +
    - +
    #define XNANDPS_FLASH_BLOCK_RESERVED   0x1 #define XNANDPS_FLASH_BLOCK_RESERVED   0x1
    -
    - - - - - -
    -   - + +
    +

    Reserved block

    -

    -Reserved block

    -

    Function Documentation

    -

    - - - - -
    - + + +

    Function Documentation

    + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_IsBlockBad ( XNandPs *  InstancePtr, int XNandPs_IsBlockBad (XNandPs *  InstancePtr,
    u32  Blocku32  Block 
    ) )
    -
    - - - - - -
    -   - - -

    -This function checks whether a block is bad or not.

    -

    Parameters:
    + +
    +

    This function checks whether a block is bad or not.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Block is the block number.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -

    - - - - -
    - + + + + +
    +
    +
    - - - - + + + + - - - - + + + + - - - + + +
    int XNandPs_MarkBlockBad ( XNandPs *  InstancePtr, int XNandPs_MarkBlockBad (XNandPs *  InstancePtr,
    u32  Blocku32  Block 
    ) )
    -
    - - - - - -
    -   - - -

    -This function marks a block as bad in the RAM based Bad Block Table(BBT). It also updates the Bad Block Table(BBT) in the flash.

    -

    Parameters:
    + +
    +

    This function marks a block as bad in the RAM based Bad Block Table(BBT). It also updates the Bad Block Table(BBT) in the flash.

    +
    Parameters:
    InstancePtr is the pointer to the XNandPs instance.
    Block is the block number.
    +
    -
    Returns:
      -
    • XST_SUCCESS if successful.
    • XST_FAILURE if fail.
    +
    Returns:
      +
    • XST_SUCCESS if successful.
      • +
    • XST_FAILURE if fail.
      • +
    -
    -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. + +

    +
    +
    +

    +Copyright © 1995-2014 Xilinx, Inc. All rights reserved. +

    + + diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__g_8c.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__g_8c.html index be9609e4..769675ac 100755 --- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__g_8c.html +++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__g_8c.html @@ -2,65 +2,55 @@ - xnandps_g.c File Reference + Xilinx Driver nandps v2_1: xnandps_g.c File Reference - +

    Xilinx Processor IP Library

    Software Drivers
    - -
    -
    -
    -
    -

    xnandps_g.c File Reference

    Detailed Description

    -This file contains a configuration table that specifies the configuration of NAND flash devices in the system.

    -See xnandps.h for more information about this driver.

    -

    Note:
    None.
    -
    
-
     MODIFICATION HISTORY:
    
-
     Ver   Who    Date    	   Changes
+
+
+
+
    
+
    xnandps_g.c File Reference
    #include "xnandps.h"
    
+#include "xparameters.h"
    
+
+
+
+
    Variables
    XNandPs_Config XNandPs_ConfigTable [XPAR_XNANDPS_NUM_INSTANCES]
    
+
    Detailed Description
    
+
    This file contains a configuration table that specifies the configuration of NAND flash devices in the system.
    
+
    See xnandps.h for more information about this driver.
    
+
    Note:
    None.
    
+
     MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
- 
     
-
    
-#include "xnandps.h"
    
-#include "xparameters.h"
    
-
-
-
-
-
-

    Variables
    XNandPs_Config XNandPs_ConfigTable [XPAR_XNANDPS_NUM_INSTANCES]
    
-
    Variable Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+ 
    Variable Documentation
    
+
+
    
+
    
+      
     
    
-          
+          
    
         
    XNandPs_Config XNandPs_ConfigTable[XPAR_XNANDPS_NUM_INSTANCES]          XNandPs_Config XNandPs_ConfigTable[XPAR_XNANDPS_NUM_INSTANCES]
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
+
+
    
 Initial value:
     {
         {
@@ -70,7 +60,13 @@ See xnandps.h for more information about this driver.
    
                 XPAR_XNANDPS_0_FLASH_WIDTH      
         }
 }
-
    This table contains configuration information for each System Monitor/ADC device in the system.     
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
+
    This table contains configuration information for each System Monitor/ADC device in the system. 
    
+
+
    
+
    
+
    
+
    
+Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
+
    
+
+
diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__hw_8h.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__hw_8h.html
index c8f69719..a25e3403 100755
--- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__hw_8h.html
+++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__hw_8h.html
@@ -2,4671 +2,2919 @@
 
    
 
-   xnandps_hw.h File Reference
+   Xilinx Driver nandps v2_1: xnandps_hw.h File Reference
 
-
+
 
 
    Xilinx Processor IP Library
    
 Software Drivers
 
    
-
-
    
-  
    
-
    
-  
    
-
    xnandps_hw.h File Reference
    Detailed Description
    
-This file contains identifiers and low-level macros/functions for the NAND Flash controller driver. See xnandps.h for more information.
    
-
    Note:
    None
    
+
+
+
+
    
+
    xnandps_hw.h File Reference
    
+
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    Defines
    #define XNANDPS_HW_H
    #define XNANDPS_MEMC_STATUS_OFFSET   0x000
    #define XNANDPS_MEMC_IF_CONFIG_OFFSET   0x004
    #define XNANDPS_MEMC_SET_CONFIG_OFFSET   0x008
    #define XNANDPS_MEMC_CLR_CONFIG_OFFSET   0x00C
    #define XNANDPS_DIRECT_CMD_OFFSET   0x010
    #define XNANDPS_SET_CYCLES_OFFSET   0x014
    #define XNANDPS_SET_OPMODE_OFFSET   0x018
    #define XNANDPS_REFRESH_PERIOD_0_OFFSET   0x020
    #define XNANDPS_REFRESH_PERIOD_1_OFFSET   0x024
    #define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET   0x100
    #define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET   0x120
    #define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET   0x140
    #define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET   0x160
    #define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET   0x180
    #define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET   0x1A0
    #define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET   0x1C0
    #define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET   0x1E0
    #define XNANDPS_FLASH_CYCLES(addr)   (0x000 + addr)
    #define XNANDPS_OPMODE(addr)   (0x004 + addr)
    #define XNANDPS_USER_STATUS_OFFSET   0x200
    #define XNANDPS_USER_CONFIG_OFFSET   0x204
    #define XNANDPS_IF0_ECC_OFFSET   0x300
    #define XNANDPS_IF1_ECC_OFFSET   0x400
    #define XNANDPS_ECC_STATUS_OFFSET(addr)   (0x000 + addr)
    #define XNANDPS_ECC_MEMCFG_OFFSET(addr)   (0x004 + addr)
    #define XNANDPS_ECC_MEMCMD1_OFFSET(addr)   (0x008 + addr)
    #define XNANDPS_ECC_MEMCMD2_OFFSET(addr)   (0x00C + addr)
    #define XNANDPS_ECC_ADDR0_OFFSET(addr)   (0x010 + addr)
    #define XNANDPS_ECC_ADDR1_OFFSET(addr)   (0x014 + addr)
    #define XNANDPS_ECC_VALUE0_OFFSET(addr)   (0x018 + addr)
    #define XNANDPS_ECC_VALUE1_OFFSET(addr)   (0x01C + addr)
    #define XNANDPS_ECC_VALUE2_OFFSET(addr)   (0x020 + addr)
    #define XNANDPS_ECC_VALUE3_OFFSET(addr)   (0x024 + addr)
    #define XNANDPS_ECC_VALUE4_OFFSET(addr)   (0x028 + addr)
    #define XNANDPS_INTGTEST_OFFSET   0xE00
    #define XNANDPS_PERIPH_ID0_OFFSET   0xFE0
    #define XNANDPS_PERIPH_ID1_OFFSET   0xFE4
    #define XNANDPS_PERIPH_ID2_OFFSET   0xFE8
    #define XNANDPS_PERIPH_ID3_OFFSET   0xFEC
    #define XNANDPS_PCELL_ID0_OFFSET   0xFF0
    #define XNANDPS_PCELL_ID1_OFFSET   0xFF4
    #define XNANDPS_PCELL_ID2_OFFSET   0xFF8
    #define XNANDPS_PCELL_ID3_OFFSET   0xFFC
    #define XNandPs_ReadReg   Xil_In32
    #define XNandPs_WriteReg   Xil_Out32
    Memory controller status register bit definitions and masks
     
    
+

    #define XNANDPS_MEMC_STATUS_STATE_MASK   0x00000001
    #define XNANDPS_MEMC_STATUS_INT_EN0_MASK   0x00000002
    #define XNANDPS_MEMC_STATUS_INT_EN1_MASK   0x00000004
    #define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK   0x00000008
    #define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK   0x00000010
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK   0x00000020
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK   0x00000040
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK   0x00000080
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK   0x00000100
    #define XNANDPS_MEMC_STATUS_ECC_INT0_MASK   0x00000200
    #define XNANDPS_MEMC_STATUS_ECC_INT1_MASK   0x00000400
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK   0x00000800
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK   0x00001000
    Memory interface configurartion register bit definitions and masks
     
    
+

    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK   0x00000003
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK   0x0000000C
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK   0x00000030
    #define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK   0x00000040
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK   0x00000300
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK   0x00000C00
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK   0x00003000
    #define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK   0x00004000
    #define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK   0x00030000
    Set configuration register bit definitions and masks
     
    
+

    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK   0x00000001
    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK   0x00000002
    #define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK   0x00000004
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK   0x00000020
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK   0x00000040
    Clear configuration register bit definitions and masks
     
    
+

    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK   0x00000001
    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK   0x00000002
    #define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK   0x00000004
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK   0x00000008
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK   0x00000010
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK   0x00000020
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK   0x00000040
    Clear configuration register bit definitions and masks and shift
     
    
+

    #define XNANDPS_DIRECT_CMD_ADDR_MASK   0x000FFFFF
    #define XNANDPS_DIRECT_CMD_SET_CRE_MASK   0x00100000
    #define XNANDPS_DIRECT_CMD_TYPE_MASK   0x00600000
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK   0x03800000
    #define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT   20
    #define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT   21
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT   23
    Set cycles register bit definitions and masks and shift
     
    
+

    #define XNANDPS_SET_CYCLES_SET_T0_MASK   0x0000000F
    #define XNANDPS_SET_CYCLES_SET_T1_MASK   0x000000F0
    #define XNANDPS_SET_CYCLES_SET_T2_MASK   0x00000700
    #define XNANDPS_SET_CYCLES_SET_T3_MASK   0x00003800
    #define XNANDPS_SET_CYCLES_SET_T4_MASK   0x0001C000
    #define XNANDPS_SET_CYCLES_SET_T5_MASK   0x000E0000
    #define XNANDPS_SET_CYCLES_SET_T6_MASK   0x00F00000
    #define XNANDPS_SET_CYCLES_SET_T0_SHIFT   0
    #define XNANDPS_SET_CYCLES_SET_T1_SHIFT   4
    #define XNANDPS_SET_CYCLES_SET_T2_SHIFT   8
    #define XNANDPS_SET_CYCLES_SET_T3_SHIFT   11
    #define XNANDPS_SET_CYCLES_SET_T4_SHIFT   14
    #define XNANDPS_SET_CYCLES_SET_T5_SHIFT   17
    #define XNANDPS_SET_CYCLES_SET_T6_SHIFT   20
    Set opmode register bit definitions and masks
     
    
+

    #define XNANDPS_SET_OPMODE_SET_MW_MASK   0x00000003
    #define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK   0x00000004
    #define XNANDPS_SET_OPMODE_SET_RD_BL_MASK   0x00000038
    #define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK   0x00000040
    #define XNANDPS_SET_OPMODE_SET_WR_BL_MASK   0x00000380
    #define XNANDPS_SET_OPMODE_SET_BAA_MASK   0x00000400
    #define XNANDPS_SET_OPMODE_SET_ADV_MASK   0x00000800
    #define XNANDPS_SET_OPMODE_SET_BLS_MASK   0x00001000
    #define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK   0x0000E000
    #define XNANDPS_SET_OPMODE_MW_8_BITS   0x0
    #define XNANDPS_SET_OPMODE_MW_16_BITS   0x1
    #define XNANDPS_SET_OPMODE_MW_32_BITS   0x2
    Refresh period register bit definitions and masks
     
    
+

    #define XNANDPS_REFRESH_PERIOD_0_MASK   0x0000000F
    #define XNANDPS_REFRESH_PERIOD_1_MASK   0x0000000F
    Opmode register bit definitions and masks
     
    
+

    #define XNANDPS_OPMODE_MW_MASK   0x00000003
    #define XNANDPS_OPMODE_RD_SYNC_MASK   0x00000004
    #define XNANDPS_OPMODE_RD_BL_MASK   0x00000038
    #define XNANDPS_OPMODE_WR_SYNC_MASK   0x00000040
    #define XNANDPS_OPMODE_WR_BL_MASK   0x00000380
    #define XNANDPS_OPMODE_BAA_MASK   0x00000400
    #define XNANDPS_OPMODE_ADV_MASK   0x00000800
    #define XNANDPS_OPMODE_BLS_MASK   0x00001000
    #define XNANDPS_OPMODE_BURST_ALIGN_MASK   0x0000E000
    #define XNANDPS_OPMODE_ADDRESS_MASK   0x00FF0000
    #define XNANDPS_OPMODE_ADDRESS_MATCH_MASK   0xFF000000
    User status register bit definitions and masks
     
    
+

    #define XNANDPS_USER_STATUS_MASK   0x000000FF
    User config register bit definitions and masks
     
    
+

    #define XNANDPS_USER_CONFIG_MASK   0x000000FF
    ECC status register bit definitions and masks
     
    
+

    #define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK   0x0000003F
    #define XNANDPS_ECC_STATUS_MASK   0x00000040
    #define XNANDPS_ECC_LAST_MASK   0x00000180
    #define XNANDPS_ECC_READ_NOT_WRITE_MASK   0x00000200
    #define XNANDPS_ECC_VALID_MASK   0x00007C00
    #define XNANDPS_ECC_FAIL_MASK   0x000F8000
    #define XNANDPS_ECC_CAN_CORRECT_MASK   0x01F00000
    #define XNANDPS_ECC_READ_MASK   0x37000000
    ECC mem config register bit definitions and masks and shifts
     
    
+

    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK   0x00000003
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK   0x0000000C
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK   0x00000010
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK   0x00000060
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK   0x00000080
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK   0x00000100
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK   0x00000200
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK   0x00000400
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK   0x00001800
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT   0
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT   2
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT   4
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT   5
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT   7
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT   8
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT   9
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT   10
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT   11
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512   0x1
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024   0x2
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048   0x3
    ECC mem command1 register bit definitions and masks and shifts
     
    
+

    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK   0x000000FF
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK   0x0000FF00
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK   0x00FF0000
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK   0x01000000
    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT   0
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT   8
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT   16
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT   24
    ECC mem command2 register bit definitions and masks
     
    
+

    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK   0x000000FF
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK   0x0000FF00
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK   0x00FF0000
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK   0x00FF0000
    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT   0
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT   8
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT   16
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT   24
    ECC value register bit definitions and masks
     
    
+

    #define XNANDPS_ECC_VALUE_MASK   0x00FFFFFF
    #define XNANDPS_ECC_VALUE_CORRECT_MASK   0x08000000
    #define XNANDPS_ECC_VALUE_FAIL_MASK   0x10000000
    #define XNANDPS_ECC_VALUE_READ_MASK   0x20000000
    #define XNANDPS_ECC_VALUE_VALID_MASK   0x40000000
    #define XNANDPS_ECC_VALUE_INT_MASK   0x80000000
    Peripheral ID register bit definitions and masks
     
    
+

    #define XNANDPS_PERIPH_ID_PART_NUM_MASK   0x00000FFF
    #define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK   0x000FF000
    #define XNANDPS_PERIPH_ID_REVISION_MASK   0x00F00000
    #define XNANDPS_PERIPH_ID_INTG_CFG_MASK   0x01000000
    #define XNANDPS_PCELL_ID_MASK   0x000000FF
    
+
    Detailed Description
    
+
    This file contains identifiers and low-level macros/functions for the NAND Flash controller driver. See xnandps.h for more information.
    
+
    Note:
    None
    
 
    - MODIFICATION HISTORY:
    
-
     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
- 
     
-
    
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+ 
    Define Documentation
    
+
+
    
+
    
+      

    Memory controller status register bit definitions and masks
    #define XNANDPS_MEMC_STATUS_STATE_MASK   0x00000001
    #define XNANDPS_MEMC_STATUS_INT_EN0_MASK   0x00000002
    #define XNANDPS_MEMC_STATUS_INT_EN1_MASK   0x00000004
    #define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK   0x00000008
    #define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK   0x00000010
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK   0x00000020
     
    
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_ADDR_MASK   0x000FFFFF
    
+
    
+
    
+
    Direct command address mask 
    
 
-#define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK   0x03800000
    
+
    
+
    
+
    Direct command chip select mask 
    
 
-#define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK   0x00000080
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT   23
    
+
    
+
    
+
    Direct command chip select shift 
    
 
-#define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK   0x00000100
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT   21
    
+
    
+
    
+
    Direct command cmd_type shift 
    
 
-#define XNANDPS_MEMC_STATUS_ECC_INT0_MASK   0x00000200
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_OFFSET   0x010
    
+
    
+
    
+
    Direct command reg, WO 
    
 
-#define XNANDPS_MEMC_STATUS_ECC_INT1_MASK   0x00000400
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_SET_CRE_MASK   0x00100000
    
+
    
+
    
+
    Direct command set cre mask 
    
 
-#define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK   0x00000800
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT   20
    
+
    
+
    
+
    Direct command set_cre shift 
    
 
-#define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK   0x00001000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_DIRECT_CMD_TYPE_MASK   0x00600000
    
+
    
+
    
+
    Direct command type mask 
    
 
-
    Memory interface configurartion register bit definitions and masks
    
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK   0x00000003
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_ADDR0_OFFSET(addr  )    (0x010 + addr)
    
+
    
+
    
+
    ECC address0 reg 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK   0x0000000C
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_ADDR1_OFFSET(addr  )    (0x014 + addr)
    
+
    
+
    
+
    ECC address1 reg 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK   0x00000030
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_CAN_CORRECT_MASK   0x01F00000
    
+
    
+
    
+
    Ecc status ecc_can_correct mask 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_FAIL_MASK   0x000F8000
    
+
    
+
    
+
    Ecc status ecc_fail mask 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK   0x00000300
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_LAST_MASK   0x00000180
    
+
    
+
    
+
    Ecc status ecc_last mask 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK   0x00000C00
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK   0x00000400
    
+
    
+
    
+
    Ecc cfg ecc_extra_block mask 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK   0x00003000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT   10
    
+
    
+
    
+
    Ecc cfg ecc_extra_block shift 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK   0x00004000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK   0x00001800
    
+
    
+
    
+
    Ecc cfg ecc_extra_block_size mask 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK   0x00030000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT   11
    
+
    
+
    
+
    Ecc cfg ecc_extra_block_size shift 
    
 
-
    Set configuration register bit definitions and masks
    
-#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK   0x00000001
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK   0x00000200
    
+
    
+
    
+
    Ecc cfg ecc_int_abort mask 
    
 
-#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK   0x00000002
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT   9
    
+
    
+
    
+
    Ecc cfg ecc_int_abort shift 
    
 
-#define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK   0x00000004
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK   0x00000100
    
+
    
+
    
+
    Ecc cfg ecc_int_pass mask 
    
 
-#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK   0x00000020
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT   8
    
+
    
+
    
+
    Ecc cfg ecc_int_pass shift 
    
 
-#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK   0x00000060
    
+
    
+
    
+
    Ecc cfg ecc_jump mask 
    
 
-
    Clear configuration register bit definitions and masks
    
-#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK   0x00000001
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT   5
    
+
    
+
    
+
    Ecc cfg ecc_jump shift 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK   0x00000002
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK   0x0000000C
    
+
    
+
    
+
    Ecc cfg ecc_mode mask 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK   0x00000004
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT   2
    
+
    
+
    
+
    Ecc cfg ecc_mode shift 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK   0x00000008
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK   0x00000010
    
+
    
+
    
+
    Ecc cfg ecc_read_end mask 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK   0x00000010
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT   4
    
+
    
+
    
+
    Ecc cfg ecc_read_end shift 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK   0x00000020
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK   0x00000080
    
+
    
+
    
+
    Ecc cfg ecc_ignore_add_eight mask 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT   7
    
+
    
+
    
+
    Ecc cfg ecc_ignore_add_eight shift 
    
 
-
    Clear configuration register bit definitions and masks and shift
    
-#define XNANDPS_DIRECT_CMD_ADDR_MASK   0x000FFFFF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_OFFSET(addr  )    (0x004 + addr)
    
+
    
+
    
+
    ECC mem config reg 
    
 
-#define XNANDPS_DIRECT_CMD_SET_CRE_MASK   0x00100000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024   0x2
    
+
    
+
    
+
    ECC cfg page size value for 1024 byte page 
    
 
-#define XNANDPS_DIRECT_CMD_TYPE_MASK   0x00600000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048   0x3
    
+
    
+
    
+
    ECC cfg page size value for 2048 byte page 
    
 
-#define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK   0x03800000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512   0x1
    
+
    
+
    
+
    ECC cfg page size value for 512 byte page 
    
 
-#define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT   20
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK   0x00000003
    
+
    
+
    
+
    Ecc cfg page_size mask 
    
 
-#define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT   21
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT   0
    
+
    
+
    
+
    Ecc cfg page_size shift 
    
 
-#define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT   23
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_MEMCMD1_OFFSET(addr  )    (0x008 + addr)
    
+
    
+
    
+
    ECC mem com1 reg 
    
 
-
    Set cycles register bit definitions and masks and shift
    
-#define XNANDPS_SET_CYCLES_SET_T0_MASK   0x0000000F
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_MEMCMD2_OFFSET(addr  )    (0x00C + addr)
    
+
    
+
    
+
    ECC mem com2 reg 
    
 
-#define XNANDPS_SET_CYCLES_SET_T1_MASK   0x000000F0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK   0x00FF0000
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd_end mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T2_MASK   0x00000700
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT   16
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd_end shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T3_MASK   0x00003800
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK   0x01000000
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd_end_valid mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T4_MASK   0x0001C000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT   24
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd_end_valid shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T5_MASK   0x000E0000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK   0x0000FF00
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T6_MASK   0x00F00000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT   8
    
+
    
+
    
+
    Ecc command 1 nand_rd_cmd shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T0_SHIFT   0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK   0x000000FF
    
+
    
+
    
+
    Ecc command 1 nand_wr_cmd mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T1_SHIFT   4
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT   0
    
+
    
+
    
+
    Ecc command 1 nand_wr_cmd shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T2_SHIFT   8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK   0x00FF0000
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change_end mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T3_SHIFT   11
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT   16
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change_end shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T4_SHIFT   14
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK   0x00FF0000
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change_end_valid mask 
    
 
-#define XNANDPS_SET_CYCLES_SET_T5_SHIFT   17
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT   24
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change_end_valid shift 
    
 
-#define XNANDPS_SET_CYCLES_SET_T6_SHIFT   20
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK   0x0000FF00
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change mask 
    
 
-
    Set opmode register bit definitions and masks
    
-#define XNANDPS_SET_OPMODE_SET_MW_MASK   0x00000003
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT   8
    
+
    
+
    
+
    Ecc command2 nand_rd_col_change shift 
    
 
-#define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK   0x00000004
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK   0x000000FF
    
+
    
+
    
+
    Ecc command2 nand_wr_col_change mask 
    
 
-#define XNANDPS_SET_OPMODE_SET_RD_BL_MASK   0x00000038
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT   0
    
+
    
+
    
+
    Ecc command2 nand_wr_col_change shift 
    
 
-#define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_READ_MASK   0x37000000
    
+
    
+
    
+
    Ecc status ecc_read mask 
    
 
-#define XNANDPS_SET_OPMODE_SET_WR_BL_MASK   0x00000380
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_READ_NOT_WRITE_MASK   0x00000200
    
+
    
+
    
+
    Ecc status ecc_read_not_write mask 
    
 
-#define XNANDPS_SET_OPMODE_SET_BAA_MASK   0x00000400
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_STATUS_MASK   0x00000040
    
+
    
+
    
+
    Ecc status ecc_status mask 
    
 
-#define XNANDPS_SET_OPMODE_SET_ADV_MASK   0x00000800
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_STATUS_OFFSET(addr  )    (0x000 + addr)
    
+
    
+
    
+
    ECC status register 
    
 
-#define XNANDPS_SET_OPMODE_SET_BLS_MASK   0x00001000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK   0x0000003F
    
+
    
+
    
+
    Ecc status raw_int_status mask 
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALID_MASK   0x00007C00
    
+
    
+
    
+
    Ecc status ecc_valid mask 
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_VALUE0_OFFSET(addr  )    (0x018 + addr)
    
+
    
+
    
+
    ECC value 0 reg 
    
 
-#define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK   0x0000E000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_VALUE1_OFFSET(addr  )    (0x01C + addr)
    
+
    
+
    
+
    ECC value 1 reg 
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_VALUE2_OFFSET(addr  )    (0x020 + addr)
    
+
    
+
    
+
    ECC value 2 reg 
    
+
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_VALUE3_OFFSET(addr  )    (0x024 + addr)
    
+
    
+
    
+
    ECC value 3 reg 
    
 
-#define XNANDPS_SET_OPMODE_MW_8_BITS   0x0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_ECC_VALUE4_OFFSET(addr  )    (0x028 + addr)
    
+
    
+
    
+
    ECC value 4 reg 
    
 
-#define XNANDPS_SET_OPMODE_MW_16_BITS   0x1
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_CORRECT_MASK   0x08000000
    
+
    
+
    
+
    Ecc value ecc_correct mask 
    
 
-#define XNANDPS_SET_OPMODE_MW_32_BITS   0x2
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_FAIL_MASK   0x10000000
    
+
    
+
    
+
    Ecc value ecc_fail mask 
    
 
-
    Refresh period register bit definitions and masks
    
-#define XNANDPS_REFRESH_PERIOD_0_MASK   0x0000000F
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_INT_MASK   0x80000000
    
+
    
+
    
+
    Ecc value ecc_int mask 
    
 
-#define XNANDPS_REFRESH_PERIOD_1_MASK   0x0000000F
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_MASK   0x00FFFFFF
    
+
    
+
    
+
    Ecc value ecc_value mask 
    
 
-
    Opmode register bit definitions and masks
    
-#define XNANDPS_OPMODE_MW_MASK   0x00000003
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_READ_MASK   0x20000000
    
+
    
+
    
+
    Ecc value ecc_read mask 
    
 
-#define XNANDPS_OPMODE_RD_SYNC_MASK   0x00000004
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_ECC_VALUE_VALID_MASK   0x40000000
    
+
    
+
    
+
    Ecc value ecc_valid mask 
    
 
-#define XNANDPS_OPMODE_RD_BL_MASK   0x00000038
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_FLASH_CYCLES(addr  )    (0x000 + addr)
    
+
    
+
    
+
    NAND & SRAM cycle,RO 
    
 
-#define XNANDPS_OPMODE_WR_SYNC_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_HW_H
    
+
    
+
    
 
-#define XNANDPS_OPMODE_WR_BL_MASK   0x00000380
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET   0x100
    
+
    
+
    
+
    Interface 0 chip 0 config 
    
 
-#define XNANDPS_OPMODE_BAA_MASK   0x00000400
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET   0x120
    
+
    
+
    
+
    Interface 0 chip 1 config 
    
 
-#define XNANDPS_OPMODE_ADV_MASK   0x00000800
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET   0x140
    
+
    
+
    
+
    Interface 0 chip 2 config 
    
 
-#define XNANDPS_OPMODE_BLS_MASK   0x00001000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET   0x160
    
+
    
+
    
+
    Interface 0 chip 3 config 
    
 
-#define XNANDPS_OPMODE_BURST_ALIGN_MASK   0x0000E000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF0_ECC_OFFSET   0x300
    
+
    
+
    
+
    Interface 0 ECC register 
    
 
-#define XNANDPS_OPMODE_ADDRESS_MASK   0x00FF0000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET   0x180
    
+
    
+
    
+
    Interface 1 chip 0 config 
    
 
-
    User status register bit definitions and masks
    
-#define XNANDPS_USER_STATUS_MASK   0x000000FF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET   0x1A0
    
+
    
+
    
+
    Interface 1 chip 1 config 
    
 
-
    User config register bit definitions and masks
    
-#define XNANDPS_USER_CONFIG_MASK   0x000000FF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET   0x1C0
    
+
    
+
    
+
    Interface 1 chip 2 config 
    
 
-
    ECC status register bit definitions and masks
    
-#define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK   0x0000003F
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET   0x1E0
    
+
    
+
    
+
    Interface 1 chip 3 config 
    
 
-#define XNANDPS_ECC_STATUS_MASK   0x00000040
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_IF1_ECC_OFFSET   0x400
    
+
    
+
    
+
    Interface 1 ECC register 
    
 
-#define XNANDPS_ECC_LAST_MASK   0x00000180
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_INTGTEST_OFFSET   0xE00
    
+
    
+
    
+
    Integration test offset 
    
 
-#define XNANDPS_ECC_READ_NOT_WRITE_MASK   0x00000200
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK   0x00000020
    
+
    
+
    
+
    Memory controller interface0 ECC interrupt disable mask 
    
 
-#define XNANDPS_ECC_VALID_MASK   0x00007C00
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK   0x00000040
    
+
    
+
    
+
    Memory controller interface1 ECC interrupt disable mask 
    
 
-#define XNANDPS_ECC_FAIL_MASK   0x000F8000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK   0x00000008
    
+
    
+
    
+
    Memory controller interface0 interrupt clear mask 
    
 
-#define XNANDPS_ECC_CAN_CORRECT_MASK   0x01F00000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK   0x00000010
    
+
    
+
    
+
    Memory controller interface1 interrupt clear mask 
    
 
-#define XNANDPS_ECC_READ_MASK   0x37000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK   0x00000001
    
+
    
+
    
+
    Memory controller interface 0 interrupt disable mask 
    
 
-
    ECC mem config register bit definitions and masks and shifts
    
-#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK   0x00000003
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK   0x00000002
    
+
    
+
    
+
    Memory controller interface 1 interrupt disable mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK   0x0000000C
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK   0x00000004
    
+
    
+
    
+
    Memory controller low power exit mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK   0x00000010
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_CLR_CONFIG_OFFSET   0x00C
    
+
    
+
    
+
    Clear config reg, WO 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK   0x00000060
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK   0x00030000
    
+
    
+
    
+
    Memory controller interface exclusive masks mask 
    
 
-#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK   0x00000080
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK   0x0000000C
    
+
    
+
    
+
    Memory controller interface 0 chip select mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK   0x00000100
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK   0x00000C00
    
+
    
+
    
+
    Memory controller interface 1 chip select mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK   0x00000200
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK   0x00000003
    
+
    
+
    
+
    Memory controller interface 0 type mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK   0x00000400
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK   0x00000300
    
+
    
+
    
+
    Memory controller interface 1 type mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK   0x00001800
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK   0x00000030
    
+
    
+
    
+
    Memory controller interface 0 data width mask 
    
 
-#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT   0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK   0x00003000
    
+
    
+
    
+
    Memory controller interface 1 data width mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT   2
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_OFFSET   0x004
    
+
    
+
    
+
    Interface config reg, RO 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT   4
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK   0x00000040
    
+
    
+
    
+
    Memory controller interface 0 remap0 mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT   5
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK   0x00004000
    
+
    
+
    
+
    Memory controller interface 1 remap0 mask 
    
 
-#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT   7
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK   0x00000020
    
+
    
+
    
+
    Memory controller interfce0 ECC interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT   8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK   0x00000040
    
+
    
+
    
+
    Memory controller interfce1 ECC interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT   9
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK   0x00000001
    
+
    
+
    
+
    Memory controller interfce0 interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT   10
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK   0x00000002
    
+
    
+
    
+
    Memory controller interfce1 interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT   11
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK   0x00000004
    
+
    
+
    
+
    Memory controller low power state mask 
    
 
-#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512   0x1
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_SET_CONFIG_OFFSET   0x008
    
+
    
+
    
+
    Set configuration reg, WO 
    
 
-#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024   0x2
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_ECC_INT0_MASK   0x00000200
    
+
    
+
    
+
    Memory controller interface 0 ECC interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048   0x3
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_ECC_INT1_MASK   0x00000400
    
+
    
+
    
+
    Memory controller interface 1 ECC interrupt status mask 
    
 
-
    ECC mem command1 register bit definitions and masks and shifts
    
-#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK   0x000000FF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK   0x00000080
    
+
    
+
    
+
    Memory controller interface 0 ECC interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK   0x0000FF00
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK   0x00000100
    
+
    
+
    
+
    Memory controller interface 1 ECC interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK   0x00FF0000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_INT_EN0_MASK   0x00000002
    
+
    
+
    
+
    Memory controller interface 0 interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK   0x01000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_INT_EN1_MASK   0x00000004
    
+
    
+
    
+
    Memory controller interface 1 interrupt enable mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT   0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK   0x00000008
    
+
    
+
    
+
    Memory controller interface 0 interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT   8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK   0x00000010
    
+
    
+
    
+
    Memory controller interface 1 interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT   16
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_OFFSET   0x000
    
+
    
+
    
+
    Controller status reg, RO 
    
 
-#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT   24
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK   0x00000800
    
+
    
+
    
+
    Memory controller interface 0 raw ECC interrupt status mask 
    
 
-
    ECC mem command2 register bit definitions and masks
    
-#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK   0x000000FF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK   0x00001000
    
+
    
+
    
+
    Memory controller interface 1 raw ECC interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK   0x0000FF00
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK   0x00000020
    
+
    
+
    
+
    Memory controller interface 0 raw interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK   0x00FF0000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK   0x00000040
    
+
    
+
    
+
    Memory controller interface 1 raw interrupt status mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK   0x00FF0000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_MEMC_STATUS_STATE_MASK   0x00000001
    
+
    
+
    
+
    Memory controller operating state mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT   0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+          
+          
+          
+          
+          
+        
+      
    #define XNANDPS_OPMODE(addr  )    (0x004 + addr)
    
+
    
+
    
+
    Chip opmode reg, RO 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT   8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_ADDRESS_MASK   0x00FF0000
    
+
    
+
    
+
    Opmode Address match mask 
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT   16
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_ADDRESS_MATCH_MASK   0xFF000000
    
+
    
+
    
 
-#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT   24
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_ADV_MASK   0x00000800
    
+
    
+
    
+
    Opmode BLS mask 
    
 
-
    ECC value register bit definitions and masks
    
-#define XNANDPS_ECC_VALUE_MASK   0x00FFFFFF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_BAA_MASK   0x00000400
    
+
    
+
    
+
    Opmode ADV mask 
    
 
-#define XNANDPS_ECC_VALUE_CORRECT_MASK   0x08000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_BLS_MASK   0x00001000
    
+
    
+
    
+
    Opmode Burst align mask 
    
 
-#define XNANDPS_ECC_VALUE_FAIL_MASK   0x10000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_BURST_ALIGN_MASK   0x0000E000
    
+
    
+
    
+
    Opmode Address mask 
    
 
-#define XNANDPS_ECC_VALUE_READ_MASK   0x20000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_MW_MASK   0x00000003
    
+
    
+
    
+
    Opmode Memory width mask 
    
 
-#define XNANDPS_ECC_VALUE_VALID_MASK   0x40000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_RD_BL_MASK   0x00000038
    
+
    
+
    
+
    Opmode rd_bl mask 
    
 
-#define XNANDPS_ECC_VALUE_INT_MASK   0x80000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_RD_SYNC_MASK   0x00000004
    
+
    
+
    
+
    Opmode rd_sync mask 
    
 
-
    Peripheral ID register bit definitions and masks
    
-#define XNANDPS_PERIPH_ID_PART_NUM_MASK   0x00000FFF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_WR_BL_MASK   0x00000380
    
+
    
+
    
+
    Opmode BAA mask 
    
 
-#define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK   0x000FF000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_OPMODE_WR_SYNC_MASK   0x00000040
    
+
    
+
    
+
    Opmode wr_sync mask 
    
 
-#define XNANDPS_PERIPH_ID_REVISION_MASK   0x00F00000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PCELL_ID0_OFFSET   0xFF0
    
+
    
+
    
+
    Primecell id0 register 
    
 
-#define XNANDPS_PERIPH_ID_INTG_CFG_MASK   0x01000000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PCELL_ID1_OFFSET   0xFF4
    
+
    
+
    
+
    Primecell id1 register 
    
 
-
    Peripheral ID register bit definitions and masks
    
-#define XNANDPS_PCELL_ID_MASK   0x000000FF
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PCELL_ID2_OFFSET   0xFF8
    
+
    
+
    
+
    Primecell id2 register 
    
 
-
    Defines
    
-#define XNANDPS_MEMC_STATUS_OFFSET   0x000
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PCELL_ID3_OFFSET   0xFFC
    
+
    
+
    
+
    Primecell id3 register 
    
 
-#define XNANDPS_MEMC_IF_CONFIG_OFFSET   0x004
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PCELL_ID_MASK   0x000000FF
    
+
    
+
    
+
    Primecell identification register mask 
    
 
-#define XNANDPS_MEMC_SET_CONFIG_OFFSET   0x008
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID0_OFFSET   0xFE0
    
+
    
+
    
+
    Peripheral id0 register 
    
 
-#define XNANDPS_MEMC_CLR_CONFIG_OFFSET   0x00C
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID1_OFFSET   0xFE4
    
+
    
+
    
+
    Peripheral id1 register 
    
 
-#define XNANDPS_DIRECT_CMD_OFFSET   0x010
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID2_OFFSET   0xFE8
    
+
    
+
    
+
    Peripheral id2 register 
    
 
-#define XNANDPS_SET_CYCLES_OFFSET   0x014
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID3_OFFSET   0xFEC
    
+
    
+
    
+
    Peripheral id3 register 
    
 
-#define XNANDPS_SET_OPMODE_OFFSET   0x018
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK   0x000FF000
    
+
    
+
    
+
    Peripheral ID designed id mask 
    
 
-#define XNANDPS_REFRESH_PERIOD_0_OFFSET   0x020
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID_INTG_CFG_MASK   0x01000000
    
+
    
+
    
+
    Peripheral ID integration_cfg mask 
    
 
-#define XNANDPS_REFRESH_PERIOD_1_OFFSET   0x024
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID_PART_NUM_MASK   0x00000FFF
    
+
    
+
    
+
    Peripheral ID part_num mask 
    
 
-#define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET   0x100
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_PERIPH_ID_REVISION_MASK   0x00F00000
    
+
    
+
    
+
    Peripheral ID revision mask 
    
 
-#define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET   0x120
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNandPs_ReadReg   Xil_In32
    
+
    
+
    
+
    XNandPs Register register 
    
 
-#define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET   0x140
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_REFRESH_PERIOD_0_MASK   0x0000000F
    
+
    
+
    
+
    Interface 0 refresh period mask 
    
 
-#define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET   0x160
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_REFRESH_PERIOD_0_OFFSET   0x020
    
+
    
+
    
+
    Refresh period_0 reg, RW 
    
 
-#define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET   0x180
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_REFRESH_PERIOD_1_MASK   0x0000000F
    
+
    
+
    
+
    Interface 1 refresh period mask 
    
 
-#define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET   0x1A0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_REFRESH_PERIOD_1_OFFSET   0x024
    
+
    
+
    
+
    Refresh period_1 reg, RW 
    
 
-#define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET   0x1C0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_OFFSET   0x014
    
+
    
+
    
+
    Set cycles register, WO 
    
 
-#define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET   0x1E0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T0_MASK   0x0000000F
    
+
    
+
    
+
    Set cycles set_t0 mask 
    
 
-#define XNANDPS_FLASH_CYCLES(addr)   (0x000 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T0_SHIFT   0
    
+
    
+
    
+
    Set cycles set_t0 shift 
    
 
-#define XNANDPS_OPMODE(addr)   (0x004 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T1_MASK   0x000000F0
    
+
    
+
    
+
    Set cycles set_t1 mask 
    
 
-#define XNANDPS_USER_STATUS_OFFSET   0x200
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T1_SHIFT   4
    
+
    
+
    
+
    Set cycles set_t1 shift 
    
 
-#define XNANDPS_USER_CONFIG_OFFSET   0x204
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T2_MASK   0x00000700
    
+
    
+
    
+
    Set cycles set_t2 mask 
    
 
-#define XNANDPS_IF0_ECC_OFFSET   0x300
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T2_SHIFT   8
    
+
    
+
    
+
    Set cycles set_t2 shift 
    
 
-#define XNANDPS_IF1_ECC_OFFSET   0x400
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T3_MASK   0x00003800
    
+
    
+
    
+
    Set cycles set_t3 mask 
    
 
-#define XNANDPS_ECC_STATUS_OFFSET(addr)   (0x000 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T3_SHIFT   11
    
+
    
+
    
+
    Set cycles set_t3 shift 
    
 
-#define XNANDPS_ECC_MEMCFG_OFFSET(addr)   (0x004 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T4_MASK   0x0001C000
    
+
    
+
    
+
    Set cycles set_t4 mask 
    
 
-#define XNANDPS_ECC_MEMCMD1_OFFSET(addr)   (0x008 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T4_SHIFT   14
    
+
    
+
    
+
    Set cycles set_t4 shift 
    
 
-#define XNANDPS_ECC_MEMCMD2_OFFSET(addr)   (0x00C + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T5_MASK   0x000E0000
    
+
    
+
    
+
    Set cycles set_t5 mask 
    
 
-#define XNANDPS_ECC_ADDR0_OFFSET(addr)   (0x010 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T5_SHIFT   17
    
+
    
+
    
+
    Set cycles set_t5 shift 
    
 
-#define XNANDPS_ECC_ADDR1_OFFSET(addr)   (0x014 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T6_MASK   0x00F00000
    
+
    
+
    
+
    Set cycles set_t6 mask 
    
 
-#define XNANDPS_ECC_VALUE0_OFFSET(addr)   (0x018 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_CYCLES_SET_T6_SHIFT   20
    
+
    
+
    
+
    Set cycles set_t6 shift 
    
 
-#define XNANDPS_ECC_VALUE1_OFFSET(addr)   (0x01C + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_MW_16_BITS   0x1
    
+
    
+
    
+
    Set opmode memory width value for 16-bit flash 
    
 
-#define XNANDPS_ECC_VALUE2_OFFSET(addr)   (0x020 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_MW_32_BITS   0x2
    
+
    
+
    
+
    Set opmode memory width value for 32-bit flash 
    
 
-#define XNANDPS_ECC_VALUE3_OFFSET(addr)   (0x024 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_MW_8_BITS   0x0
    
+
    
+
    
+
    Set opmode memory width value for 8-bit flash 
    
 
-#define XNANDPS_ECC_VALUE4_OFFSET(addr)   (0x028 + addr)
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_OFFSET   0x018
    
+
    
+
    
+
    Set opmode register, WO 
    
 
-#define XNANDPS_INTGTEST_OFFSET   0xE00
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_ADV_MASK   0x00000800
    
+
    
+
    
+
    Set opmode set adv mask 
    
 
-#define XNANDPS_PERIPH_ID0_OFFSET   0xFE0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_BAA_MASK   0x00000400
    
+
    
+
    
+
    Set opmode set baa mask 
    
 
-#define XNANDPS_PERIPH_ID1_OFFSET   0xFE4
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_BLS_MASK   0x00001000
    
+
    
+
    
+
    Set opmode set bls mask 
    
 
-#define XNANDPS_PERIPH_ID2_OFFSET   0xFE8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK   0x0000E000
    
+
    
+
    
+
    Set opmode set burst align mask 
    
 
-#define XNANDPS_PERIPH_ID3_OFFSET   0xFEC
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_MW_MASK   0x00000003
    
+
    
+
    
+
    Set opmode set memory width mask 
    
 
-#define XNANDPS_PCELL_ID0_OFFSET   0xFF0
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_RD_BL_MASK   0x00000038
    
+
    
+
    
+
    Set opmode set rd_bl mask 
    
 
-#define XNANDPS_PCELL_ID1_OFFSET   0xFF4
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK   0x00000004
    
+
    
+
    
+
    Set opmode set rd_sync mask 
    
 
-#define XNANDPS_PCELL_ID2_OFFSET   0xFF8
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_WR_BL_MASK   0x00000380
    
+
    
+
    
+
    Set opmode set wr_bl mask 
    
 
-#define XNANDPS_PCELL_ID3_OFFSET   0xFFC
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK   0x00000040
    
+
    
+
    
+
    Set opmode set wr_sync mask 
    
 
-#define XNandPs_ReadReg   Xil_In32
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_USER_CONFIG_MASK   0x000000FF
    
+
    
+
    
+
    User config mask 
    
 
-#define XNandPs_WriteReg   Xil_Out32
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    #define XNANDPS_USER_CONFIG_OFFSET   0x204
    
+
    
+
    
+
    User config reg, WO 
    
 
-
-
    Define Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define XNANDPS_DIRECT_CMD_ADDR_MASK   0x000FFFFF          #define XNANDPS_USER_STATUS_MASK   0x000000FF
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    User status mask 
    
 
-
    
-Direct command address mask     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK   0x03800000          #define XNANDPS_USER_STATUS_OFFSET   0x200
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    User status reg, RO 
    
 
-
    
-Direct command chip select mask     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
-      
    
         
    #define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT   23          #define XNandPs_WriteReg   Xil_Out32
         
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command chip select shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT   21          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command cmd_type shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_DIRECT_CMD_OFFSET   0x010          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command reg, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_DIRECT_CMD_SET_CRE_MASK   0x00100000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command set cre mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT   20          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command set_cre shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_DIRECT_CMD_TYPE_MASK   0x00600000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Direct command type mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_ADDR0_OFFSET          ( addr            )    (0x010 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC address0 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_ADDR1_OFFSET          ( addr            )    (0x014 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC address1 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_CAN_CORRECT_MASK   0x01F00000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_can_correct mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_FAIL_MASK   0x000F8000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_fail mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_LAST_MASK   0x00000180          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_last mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK   0x00000400          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_extra_block mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT   10          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_extra_block shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK   0x00001800          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_extra_block_size mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT   11          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_extra_block_size shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK   0x00000200          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_int_abort mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT   9          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_int_abort shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK   0x00000100          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_int_pass mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT   8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_int_pass shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK   0x00000060          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_jump mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT   5          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_jump shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK   0x0000000C          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_mode mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT   2          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_mode shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK   0x00000010          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_read_end mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT   4          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_read_end shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK   0x00000080          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_ignore_add_eight mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT   7          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg ecc_ignore_add_eight shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_OFFSET          ( addr            )    (0x004 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC mem config reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024   0x2          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC cfg page size value for 1024 byte page     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048   0x3          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC cfg page size value for 2048 byte page     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512   0x1          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC cfg page size value for 512 byte page     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK   0x00000003          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg page_size mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT   0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc cfg page_size shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_MEMCMD1_OFFSET          ( addr            )    (0x008 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC mem com1 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_MEMCMD2_OFFSET          ( addr            )    (0x00C + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC mem com2 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK   0x00FF0000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd_end mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT   16          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd_end shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK   0x01000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd_end_valid mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT   24          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd_end_valid shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK   0x0000FF00          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT   8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_rd_cmd shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK   0x000000FF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_wr_cmd mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT   0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command 1 nand_wr_cmd shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK   0x00FF0000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change_end mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT   16          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change_end shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK   0x00FF0000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change_end_valid mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT   24          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change_end_valid shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK   0x0000FF00          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT   8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_rd_col_change shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK   0x000000FF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_wr_col_change mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT   0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc command2 nand_wr_col_change shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_READ_MASK   0x37000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_read mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_READ_NOT_WRITE_MASK   0x00000200          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_read_not_write mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_STATUS_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_STATUS_OFFSET          ( addr            )    (0x000 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC status register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK   0x0000003F          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status raw_int_status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALID_MASK   0x00007C00          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc status ecc_valid mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_VALUE0_OFFSET          ( addr            )    (0x018 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC value 0 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_VALUE1_OFFSET          ( addr            )    (0x01C + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC value 1 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_VALUE2_OFFSET          ( addr            )    (0x020 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC value 2 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_VALUE3_OFFSET          ( addr            )    (0x024 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC value 3 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_ECC_VALUE4_OFFSET          ( addr            )    (0x028 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-ECC value 4 reg     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_CORRECT_MASK   0x08000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_correct mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_FAIL_MASK   0x10000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_fail mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_INT_MASK   0x80000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_int mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_MASK   0x00FFFFFF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_value mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_READ_MASK   0x20000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_read mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_ECC_VALUE_VALID_MASK   0x40000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Ecc value ecc_valid mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_FLASH_CYCLES          ( addr            )    (0x000 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-NAND & SRAM cycle,RO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET   0x100          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 chip 0 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET   0x120          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 chip 1 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET   0x140          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 chip 2 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET   0x160          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 chip 3 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF0_ECC_OFFSET   0x300          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 ECC register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET   0x180          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 chip 0 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET   0x1A0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 chip 1 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET   0x1C0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 chip 2 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET   0x1E0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 chip 3 config     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_IF1_ECC_OFFSET   0x400          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 ECC register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_INTGTEST_OFFSET   0xE00          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Integration test offset     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK   0x00000020          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface0 ECC interrupt disable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface1 ECC interrupt disable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK   0x00000008          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface0 interrupt clear mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK   0x00000010          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface1 interrupt clear mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK   0x00000001          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 interrupt disable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK   0x00000002          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 interrupt disable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK   0x00000004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller low power exit mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_CLR_CONFIG_OFFSET   0x00C          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Clear config reg, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK   0x00030000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface exclusive masks mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK   0x0000000C          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 chip select mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK   0x00000C00          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 chip select mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK   0x00000003          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 type mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK   0x00000300          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 type mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK   0x00000030          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 data width mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK   0x00003000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 data width mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_OFFSET   0x004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface config reg, RO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 remap0 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK   0x00004000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 remap0 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK   0x00000020          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interfce0 ECC interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interfce1 ECC interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK   0x00000001          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interfce0 interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK   0x00000002          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interfce1 interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK   0x00000004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller low power state mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_SET_CONFIG_OFFSET   0x008          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set configuration reg, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_ECC_INT0_MASK   0x00000200          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 ECC interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_ECC_INT1_MASK   0x00000400          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 ECC interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK   0x00000080          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 ECC interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK   0x00000100          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 ECC interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_INT_EN0_MASK   0x00000002          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_INT_EN1_MASK   0x00000004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 interrupt enable mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK   0x00000008          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK   0x00000010          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_OFFSET   0x000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Controller status reg, RO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK   0x00000800          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 raw ECC interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK   0x00001000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 raw ECC interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK   0x00000020          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 0 raw interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller interface 1 raw interrupt status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_MEMC_STATUS_STATE_MASK   0x00000001          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Memory controller operating state mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-          
-          
-          
-          
-          
-        
-      
    #define XNANDPS_OPMODE          ( addr            )    (0x004 + addr)
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Chip opmode reg, RO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_ADDRESS_MASK   0x00FF0000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode Address match mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_ADV_MASK   0x00000800          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode BLS mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_BAA_MASK   0x00000400          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode ADV mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_BLS_MASK   0x00001000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode Burst align mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_BURST_ALIGN_MASK   0x0000E000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode Address mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_MW_MASK   0x00000003          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode Memory width mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_RD_BL_MASK   0x00000038          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode rd_bl mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_RD_SYNC_MASK   0x00000004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode rd_sync mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_WR_BL_MASK   0x00000380          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode BAA mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_OPMODE_WR_SYNC_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Opmode wr_sync mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PCELL_ID0_OFFSET   0xFF0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Primecell id0 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PCELL_ID1_OFFSET   0xFF4          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Primecell id1 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PCELL_ID2_OFFSET   0xFF8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Primecell id2 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PCELL_ID3_OFFSET   0xFFC          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Primecell id3 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PCELL_ID_MASK   0x000000FF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Primecell identification register mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID0_OFFSET   0xFE0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral id0 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID1_OFFSET   0xFE4          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral id1 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID2_OFFSET   0xFE8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral id2 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID3_OFFSET   0xFEC          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral id3 register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK   0x000FF000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral ID designed id mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID_INTG_CFG_MASK   0x01000000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral ID integration_cfg mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID_PART_NUM_MASK   0x00000FFF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral ID part_num mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_PERIPH_ID_REVISION_MASK   0x00F00000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Peripheral ID revision mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNandPs_ReadReg   Xil_In32          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-XNandPs Register register     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_REFRESH_PERIOD_0_MASK   0x0000000F          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 0 refresh period mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_REFRESH_PERIOD_0_OFFSET   0x020          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Refresh period_0 reg, RW     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_REFRESH_PERIOD_1_MASK   0x0000000F          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Interface 1 refresh period mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_REFRESH_PERIOD_1_OFFSET   0x024          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Refresh period_1 reg, RW     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_OFFSET   0x014          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles register, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T0_MASK   0x0000000F          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t0 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T0_SHIFT   0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t0 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T1_MASK   0x000000F0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t1 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T1_SHIFT   4          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t1 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T2_MASK   0x00000700          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t2 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T2_SHIFT   8          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t2 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T3_MASK   0x00003800          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t3 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T3_SHIFT   11          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t3 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T4_MASK   0x0001C000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t4 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T4_SHIFT   14          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t4 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T5_MASK   0x000E0000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t5 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T5_SHIFT   17          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t5 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T6_MASK   0x00F00000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t6 mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_CYCLES_SET_T6_SHIFT   20          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set cycles set_t6 shift     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_MW_16_BITS   0x1          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode memory width value for 16-bit flash     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_MW_32_BITS   0x2          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode memory width value for 32-bit flash     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_MW_8_BITS   0x0          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode memory width value for 8-bit flash     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_OFFSET   0x018          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode register, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_ADV_MASK   0x00000800          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set adv mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_BAA_MASK   0x00000400          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set baa mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_BLS_MASK   0x00001000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set bls mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK   0x0000E000          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set burst align mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_MW_MASK   0x00000003          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set memory width mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_RD_BL_MASK   0x00000038          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set rd_bl mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK   0x00000004          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set rd_sync mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_WR_BL_MASK   0x00000380          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set wr_bl mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK   0x00000040          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-Set opmode set wr_sync mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_USER_CONFIG_MASK   0x000000FF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-User config mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_USER_CONFIG_OFFSET   0x204          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-User config reg, WO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_USER_STATUS_MASK   0x000000FF          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-User status mask     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNANDPS_USER_STATUS_OFFSET   0x200          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-User status reg, RO     
    
-
    
-
-  
-    
-  
-
    
-      
-        
-          
-        
-      
    #define XNandPs_WriteReg   Xil_Out32          
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-XNandPs register write     
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
+      
+
    
+
    
+
    XNandPs register write 
    
+
+
    
+
    
+
    
+
    
+Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
+
    
+
+
diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8c.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8c.html
index bd88d6d7..485413c5 100755
--- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8c.html
+++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8c.html
@@ -2,31 +2,45 @@
 
    
 
-   xnandps_onfi.c File Reference
+   Xilinx Driver nandps v2_1: xnandps_onfi.c File Reference
 
-
+
 
 
    Xilinx Processor IP Library
    
 Software Drivers
 
    
-
-
    
-  
    
-
    
-  
    
-
    xnandps_onfi.c File Reference
    Detailed Description
    
-This module implements the ONFI specific commands. See xnandps_onfi.h for more information.
    
-
    Note:
    None
    
+
+
+
+
    
+
    xnandps_onfi.c File Reference
    #include "xnandps_onfi.h"
    
+
+
+
+
+
+
+
+
    Functions
    void XNandPs_SendCommand (XNandPs *InstancePtr, XNandPs_CommandFormat *Command, int Page, int Column)
    u8 Onfi_CmdReadStatus (XNandPs *InstancePtr)
    int Onfi_NandInit (XNandPs *InstancePtr)
    Variables
    XNandPs_CommandFormat OnfiCommands []
    
+
    Detailed Description
    
+
    This module implements the ONFI specific commands. See xnandps_onfi.h for more information.
    
+
    Note:
    None
    
 
    - MODIFICATION HISTORY:
    
-
     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
  1.01a nm     28/02/2012  Added support for 8Gb On-Die ECC NAND flash
@@ -37,117 +51,135 @@ This module implements the ONFI specific commands. See xnandps_onfi.h"
    
-
-
-
-
-
-
-
-
-
-
-

    Functions
    u8 Onfi_CmdReadStatus (XNandPs *InstancePtr)
    int Onfi_NandInit (XNandPs *InstancePtr)

    Variables
    XNandPs_CommandFormat OnfiCommands []
    
-
    Function Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+ 
    Function Documentation
    
+
+
    
+
    
+      
     
    
-          
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
+          
    
         
    u8 Onfi_CmdReadStatus           ( XNandPs *  InstancePtr           ) u8 Onfi_CmdReadStatus (XNandPs *  InstancePtr ) 
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-This function sends read status command to the flash device.
    
-
    Parameters:
    
+
+
    
+
    This function sends read status command to the flash device.
    
+
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XNandPs instance.
    
   
    
+  
    
 
    
-
    Returns:
    flash status value read
    
-
    Note:
    None 
    
-    
    
-
    
-
-  
-    
-  
-
    
-      
+
    Returns:
    flash status value read
    
+
    Note:
    None 
    
+
+
+
+
+
    
+
    
+      
    
-          
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
+          
    
         
    int Onfi_NandInit           ( XNandPs *  InstancePtr           ) int Onfi_NandInit (XNandPs *  InstancePtr ) 
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-This function initializes the NAND flash and gets the geometry information.
    
-
    Parameters:
    
+
+
    
+
    This function initializes the NAND flash and gets the geometry information.
    
+
    Parameters:
    
   
    
     
    InstancePtr is a pointer to the XNandPs instance.
    
   
    
+  
    
 
    
-
    Returns:
      
-
    • XST_SUCCESS if successful.
    • XST_FAILURE if failed.
    
+
    Returns:
      
+
    • XST_SUCCESS if successful.
      • 
+
    • XST_FAILURE if failed.
      • 
+
    
 
    
-
    Note:
    None 
    
-    
    
-
    Variable Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+
    Note:
    None 
    
+
+
+
+
+
    
+
    
+      
    
-          
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
    
         
    XNandPs_CommandFormat OnfiCommands[]          void XNandPs_SendCommand (XNandPs *  InstancePtr, 
    XNandPs_CommandFormat *  Command, 
    int  Page, 
    int  Column 
    )
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    This function sends a NAND command to the flash device.
    
+
    Parameters:
    
+  
+    
+    
+    
+    
+  
    InstancePtr is the pointer to XNandPs struture 
    Command is the NAND command to send 
    Page is the page offset required for specific commands 
    Column the column offset required for specific commands
    
+  
    
+
    
+
    Returns:
    None
    
+
    Note:
    None 
    
+
+
    
+
+
    Variable Documentation
    
+
+
    
+
    
+      
+        
+          
+        
+      
    XNandPs_CommandFormat OnfiCommands[]
    
+
    
+
    
+
    This structure defines the onfi command format sent to the flash. 
    
+
+
    
+
    
+
+
    
+Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
+
    
+
+
 
-
    
-This structure defines the onfi command format sent to the flash.     
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8h.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8h.html
index dabcf2fe..4bbb3c6f 100755
--- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8h.html
+++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__onfi_8h.html
@@ -2,1175 +2,787 @@
 
    
 
-   xnandps_onfi.h File Reference
+   Xilinx Driver nandps v2_1: xnandps_onfi.h File Reference
 
-
+
 
 
    Xilinx Processor IP Library
    
 Software Drivers
 
    
-
-
    
-  
    
-
    
-  
    
-
    xnandps_onfi.h File Reference
    Detailed Description
    
-This file implements ONFI specific commands which are used to get the parameter page information.
    
-The following commands are supported currently.
      
-
    • Reset
    • Read ID
    • READ Parameter Page
    • Read Status
    • Change Read Column
    • Get Features
    • Set Features
    
-
    
-
    Note:
    None
    
+
+
+
+
    
+
    xnandps_onfi.h File Reference
    #include "xnandps.h"
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    Classes
    struct  __attribute__
    Defines
    #define ONFI_H
    #define ONFI_CMD_READ1   0x00
    #define ONFI_CMD_READ2   0x30
    #define ONFI_CMD_CHANGE_READ_COLUMN1   0x05
    #define ONFI_CMD_CHANGE_READ_COLUMN2   0xE0
    #define ONFI_CMD_BLOCK_ERASE1   0x60
    #define ONFI_CMD_BLOCK_ERASE2   0xD0
    #define ONFI_CMD_READ_STATUS   0x70
    #define ONFI_CMD_PAGE_PROG1   0x80
    #define ONFI_CMD_PAGE_PROG2   0x10
    #define ONFI_CMD_CHANGE_WRITE_COLUMN   0x85
    #define ONFI_CMD_READ_ID   0x90
    #define ONFI_CMD_READ_PARAM_PAGE   0xEC
    #define ONFI_CMD_RESET   0xFF
    #define ONFI_CMD_COPYBACK_READ1   0x00
    #define ONFI_CMD_COPYBACK_READ2   0x35
    #define ONFI_CMD_READ_CACHE_ENHANCED1   0x00
    #define ONFI_CMD_READ_CACHE_ENHANCED2   0x31
    #define ONFI_CMD_READ_CACHE   0x31
    #define ONFI_CMD_READ_CACHE_END   0x3F
    #define ONFI_CMD_BLOCK_ERASE_INTERLEAVED2   0xD1
    #define ONFI_CMD_READ_STATUS_ENHANCED   0x78
    #define ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2   0x11
    #define ONFI_CMD_PAGE_CACHE_PROGRAM1   0x80
    #define ONFI_CMD_PAGE_CACHE_PROGRAM2   0x15
    #define ONFI_CMD_COPYBACK_PROGRAM1   0x85
    #define ONFI_CMD_COPYBACK_PROGRAM2   0x10
    #define ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2   0x11
    #define ONFI_CMD_READ_UNIQUEID   0xED
    #define ONFI_CMD_GET_FEATURES   0xEE
    #define ONFI_CMD_SET_FEATURES   0xEF
    #define ONFI_STATUS_FAIL   0x01
    #define ONFI_STATUS_FAILC   0x02
    #define ONFI_STATUS_ARDY   0x20
    #define ONFI_STATUS_RDY   0x40
    #define ONFI_STATUS_WP   0x80
    #define ONFI_ID_LEN   4
    #define ONFI_CRC_INIT   0x4F4E
    #define ONFI_CRC_POLYNOM   0x8005
    #define ONFI_CRC_ORDER   16
    #define ONFI_PARAM_PAGE_LEN   256
    #define ONFI_CRC_LEN   254
    #define ONFI_SIGNATURE_LEN   4
    Enumerations
    enum  OnfiCommandsEnum { 
    
+  READ = 0,
+CHANGE_READ_COLUMN,
+BLOCK_ERASE,
+READ_STATUS,
+
    
+  PAGE_PROGRAM,
+CHANGE_WRITE_COLUMN,
+READ_ID,
+READ_PARAM_PAGE,
+
    
+  RESET,
+GET_FEATURES,
+SET_FEATURES,
+READ_CACHE_RANDOM,
+
    
+  READ_CACHE_END_SEQ,
+PAGE_CACHE_PROGRAM
+
    
+ }
    
+
    Detailed Description
    
+
    This file implements ONFI specific commands which are used to get the parameter page information.
    
+
    The following commands are supported currently.
    
+
      
+
    • Reset
      • 
+
    • Read ID
      • 
+
    • READ Parameter Page
      • 
+
    • Read Status
      • 
+
    • Change Read Column
      • 
+
    • Get Features
      • 
+
    • Set Features
      • 
+
    
+
    Note:
    None
    
 
    - MODIFICATION HISTORY:
    
-
     Ver   Who    Date    	   Changes
+ MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ----   ----------  -----------------------------------------------
  1.00a nm     12/10/2010  First release
  1.04a nm     04/25/2013  Implemented PR# 699544. Added page cache read
 			   and program commands to ONFI command list.
- 
     
-
    
-#include "xnandps.h"
    
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

    Classes
    struct  __attribute__

    Defines
    #define ONFI_CMD_READ1   0x00
    #define ONFI_CMD_READ2   0x30
    #define ONFI_CMD_CHANGE_READ_COLUMN1   0x05
    #define ONFI_CMD_CHANGE_READ_COLUMN2   0xE0
    #define ONFI_CMD_BLOCK_ERASE1   0x60
    #define ONFI_CMD_BLOCK_ERASE2   0xD0
    #define ONFI_CMD_READ_STATUS   0x70
    #define ONFI_CMD_PAGE_PROG1   0x80
    #define ONFI_CMD_PAGE_PROG2   0x10
    #define ONFI_CMD_CHANGE_WRITE_COLUMN   0x85
    #define ONFI_CMD_READ_ID   0x90
    #define ONFI_CMD_READ_PARAM_PAGE   0xEC
    #define ONFI_CMD_RESET   0xFF
    #define ONFI_CMD_COPYBACK_READ1   0x00
    #define ONFI_CMD_COPYBACK_READ2   0x35
    #define ONFI_CMD_READ_CACHE_ENHANCED1   0x00
    #define ONFI_CMD_READ_CACHE_ENHANCED2   0x31
    #define ONFI_CMD_READ_CACHE   0x31
    #define ONFI_CMD_READ_CACHE_END   0x3F
    #define ONFI_CMD_BLOCK_ERASE_INTERLEAVED2   0xD1
    #define ONFI_CMD_READ_STATUS_ENHANCED   0x78
    #define ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2   0x11
    #define ONFI_CMD_PAGE_CACHE_PROGRAM1   0x80
    #define ONFI_CMD_PAGE_CACHE_PROGRAM2   0x15
    #define ONFI_CMD_COPYBACK_PROGRAM1   0x85
    #define ONFI_CMD_COPYBACK_PROGRAM2   0x10
    #define ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2   0x11
    #define ONFI_CMD_READ_UNIQUEID   0xED
    #define ONFI_CMD_GET_FEATURES   0xEE
    #define ONFI_CMD_SET_FEATURES   0xEF
    #define ONFI_STATUS_FAIL   0x01
    #define ONFI_STATUS_FAILC   0x02
    #define ONFI_STATUS_ARDY   0x20
    #define ONFI_STATUS_RDY   0x40
    #define ONFI_STATUS_WP   0x80
    #define ONFI_ID_LEN   4
    #define ONFI_CRC_INIT   0x4F4E
    #define ONFI_CRC_POLYNOM   0x8005
    #define ONFI_CRC_ORDER   16
    #define ONFI_PARAM_PAGE_LEN   256
    #define ONFI_CRC_LEN   254
    #define ONFI_SIGNATURE_LEN   4

    Enumerations
    enum  OnfiCommandsEnum { 
    
-  READ = 0, 
-CHANGE_READ_COLUMN, 
-BLOCK_ERASE, 
-READ_STATUS, 
-
    
-  PAGE_PROGRAM, 
-CHANGE_WRITE_COLUMN, 
-READ_ID, 
-READ_PARAM_PAGE, 
-
    
-  RESET, 
-GET_FEATURES, 
-SET_FEATURES, 
-READ_CACHE_RANDOM, 
-
    
-  READ_CACHE_END_SEQ, 
-PAGE_CACHE_PROGRAM
-
    
- }
    
-
    Define Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+ 
    Define Documentation
    
+
+
    
+
    
+      
     
    
-          
+          
    
         
    #define ONFI_CMD_BLOCK_ERASE1   0x60          #define ONFI_CMD_BLOCK_ERASE1   0x60
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Block Erase (1st cycle) 
    
 
-
    
-ONFI Block Erase (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_BLOCK_ERASE2   0xD0          #define ONFI_CMD_BLOCK_ERASE2   0xD0
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Block Erase (2nd cycle) 
    
 
-
    
-ONFI Block Erase (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_BLOCK_ERASE_INTERLEAVED2   0xD1          #define ONFI_CMD_BLOCK_ERASE_INTERLEAVED2   0xD1
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Block Erase interleaved command (2nd cycle) 
    
 
-
    
-ONFI Block Erase interleaved command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_CHANGE_READ_COLUMN1   0x05          #define ONFI_CMD_CHANGE_READ_COLUMN1   0x05
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Change Read Column command (1st cycle) 
    
 
-
    
-ONFI Change Read Column command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_CHANGE_READ_COLUMN2   0xE0          #define ONFI_CMD_CHANGE_READ_COLUMN2   0xE0
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Change Read Column command (2nd cycle) 
    
 
-
    
-ONFI Change Read Column command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_CHANGE_WRITE_COLUMN   0x85          #define ONFI_CMD_CHANGE_WRITE_COLUMN   0x85
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Change Write Column command 
    
 
-
    
-ONFI Change Write Column command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_COPYBACK_PROGRAM1   0x85          #define ONFI_CMD_COPYBACK_PROGRAM1   0x85
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Copyback program command (1st cycle) 
    
 
-
    
-ONFI Copyback program command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_COPYBACK_PROGRAM2   0x10          #define ONFI_CMD_COPYBACK_PROGRAM2   0x10
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Copyback program command (2nd cycle) 
    
 
-
    
-ONFI Copyback program command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2   0x11          #define ONFI_CMD_COPYBACK_PROGRAM_INTERLEAVED2   0x11
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Copyback program interleaved command (2nd cycle) 
    
 
-
    
-ONFI Copyback program interleaved command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_COPYBACK_READ1   0x00          #define ONFI_CMD_COPYBACK_READ1   0x00
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Copyback Read command (1st cycle) 
    
 
-
    
-ONFI Copyback Read command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_COPYBACK_READ2   0x35          #define ONFI_CMD_COPYBACK_READ2   0x35
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Copyback Read command (2nd cycle) 
    
 
-
    
-ONFI Copyback Read command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_GET_FEATURES   0xEE          #define ONFI_CMD_GET_FEATURES   0xEE
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Get features command 
    
 
-
    
-ONFI Get features command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_PAGE_CACHE_PROGRAM1   0x80          #define ONFI_CMD_PAGE_CACHE_PROGRAM1   0x80
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Page cache program (1st cycle) 
    
 
-
    
-ONFI Page cache program (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_PAGE_CACHE_PROGRAM2   0x15          #define ONFI_CMD_PAGE_CACHE_PROGRAM2   0x15
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Page cache program (2nd cycle) 
    
 
-
    
-ONFI Page cache program (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_PAGE_PROG1   0x80          #define ONFI_CMD_PAGE_PROG1   0x80
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Page Program command (1st cycle) 
    
 
-
    
-ONFI Page Program command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_PAGE_PROG2   0x10          #define ONFI_CMD_PAGE_PROG2   0x10
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Page Program command (2nd cycle) 
    
 
-
    
-ONFI Page Program command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2   0x11          #define ONFI_CMD_PAGE_PROGRAM_INTERLEAVED2   0x11
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Page Program interleaved command (2nd cycle) 
    
 
-
    
-ONFI Page Program interleaved command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ1   0x00          #define ONFI_CMD_READ1   0x00
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read command (1st cycle) 
    
 
-
    
-ONFI Read command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ2   0x30          #define ONFI_CMD_READ2   0x30
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read command (2nd cycle) 
    
 
-
    
-ONFI Read command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_CACHE   0x31          #define ONFI_CMD_READ_CACHE   0x31
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read cache command 
    
 
-
    
-ONFI Read cache command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_CACHE_END   0x3F          #define ONFI_CMD_READ_CACHE_END   0x3F
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read cache end command 
    
 
-
    
-ONFI Read cache end command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_CACHE_ENHANCED1   0x00          #define ONFI_CMD_READ_CACHE_ENHANCED1   0x00
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read cache enhanced command (1st cycle) 
    
 
-
    
-ONFI Read cache enhanced command (1st cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_CACHE_ENHANCED2   0x31          #define ONFI_CMD_READ_CACHE_ENHANCED2   0x31
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read cache enhanced command (2nd cycle) 
    
 
-
    
-ONFI Read cache enhanced command (2nd cycle)     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_ID   0x90          #define ONFI_CMD_READ_ID   0x90
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read ID command 
    
 
-
    
-ONFI Read ID command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_PARAM_PAGE   0xEC          #define ONFI_CMD_READ_PARAM_PAGE   0xEC
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read Parameter Page command 
    
 
-
    
-ONFI Read Parameter Page command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_STATUS   0x70          #define ONFI_CMD_READ_STATUS   0x70
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read status command 
    
 
-
    
-ONFI Read status command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_STATUS_ENHANCED   0x78          #define ONFI_CMD_READ_STATUS_ENHANCED   0x78
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read Status enhanced command 
    
 
-
    
-ONFI Read Status enhanced command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_READ_UNIQUEID   0xED          #define ONFI_CMD_READ_UNIQUEID   0xED
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Read Unique ID command 
    
 
-
    
-ONFI Read Unique ID command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_RESET   0xFF          #define ONFI_CMD_RESET   0xFF
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Reset command 
    
 
-
    
-ONFI Reset command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CMD_SET_FEATURES   0xEF          #define ONFI_CMD_SET_FEATURES   0xEF
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Set features command 
    
 
-
    
-ONFI Set features command     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CRC_INIT   0x4F4E          #define ONFI_CRC_INIT   0x4F4E
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI CRC16 Inititialization constant 
    
 
-
    
-ONFI CRC16 Inititialization constant     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CRC_LEN   254          #define ONFI_CRC_LEN   254
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI CRC16 length 
    
 
-
    
-ONFI CRC16 length     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CRC_ORDER   16          #define ONFI_CRC_ORDER   16
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI CRC16 order 
    
 
-
    
-ONFI CRC16 order     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_CRC_POLYNOM   0x8005          #define ONFI_CRC_POLYNOM   0x8005
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI CRC16 polynomial 
    
 
-
    
-ONFI CRC16 polynomial     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_ID_LEN   4          #define ONFI_H
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
 
-
    
-ONFI ID Length     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_PARAM_PAGE_LEN   256          #define ONFI_ID_LEN   4
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI ID Length 
    
 
-
    
-ONFI Parameter page length     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_SIGNATURE_LEN   4          #define ONFI_PARAM_PAGE_LEN   256
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Parameter page length 
    
 
-
    
-ONFI Signature Length     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_STATUS_ARDY   0x20          #define ONFI_SIGNATURE_LEN   4
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Signature Length 
    
 
-
    
-ONFI Status Register : ARDY     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_STATUS_FAIL   0x01          #define ONFI_STATUS_ARDY   0x20
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Status Register : ARDY 
    
 
-
    
-ONFI Status Register : FAIL     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_STATUS_FAILC   0x02          #define ONFI_STATUS_FAIL   0x01
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Status Register : FAIL 
    
 
-
    
-ONFI Status Register : FAILC     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_STATUS_RDY   0x40          #define ONFI_STATUS_FAILC   0x02
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Status Register : FAILC 
    
 
-
    
-ONFI Status Register : RDY     
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    #define ONFI_STATUS_WP   0x80          #define ONFI_STATUS_RDY   0x40
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Status Register : RDY 
    
 
-
    
-ONFI Status Register : WR     
    
-
    Enumeration Type Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+
+
+
+
    
+
    
+      
    
-          
+          
    
         
    enum OnfiCommandsEnum          #define ONFI_STATUS_WP   0x80
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    ONFI Status Register : WR 
    
 
-
    
-This enum defines the onfi commands. 
    Enumerator: 
    
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
    Enumeration Type Documentation
    
+
+
    
+
    
+      
    READ 
-ONFI Read 
    CHANGE_READ_COLUMN 
-ONFI Change Read Column 
    BLOCK_ERASE 
-ONFI Block Erase 
    READ_STATUS 
-ONFI Read Status 
    PAGE_PROGRAM 
-ONFI Page Program 
    CHANGE_WRITE_COLUMN 
-ONFI Change Write Column 
    READ_ID 
-ONFI Read ID 
    READ_PARAM_PAGE 
-ONFI Read Parameter Page 
    RESET 
-ONFI Reset 
    GET_FEATURES 
-ONFI Get Features 
    SET_FEATURES 
-ONFI Set Features 
    READ_CACHE_RANDOM 
-ONFI Read page cache random 
    READ_CACHE_END_SEQ 
-ONFI Read page cache end 
    PAGE_CACHE_PROGRAM 
-ONFI Program page cache 
    
+        
+          
+        
+      
    enum OnfiCommandsEnum
    
+
    
+
    
+
    This enum defines the onfi commands. 
    
+
    Enumerator: 
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    READ 
+
    ONFI Read 
    
+
    CHANGE_READ_COLUMN 
+
    ONFI Change Read Column 
    
+
    BLOCK_ERASE 
+
    ONFI Block Erase 
    
+
    READ_STATUS 
+
    ONFI Read Status 
    
+
    PAGE_PROGRAM 
+
    ONFI Page Program 
    
+
    CHANGE_WRITE_COLUMN 
+
    ONFI Change Write Column 
    
+
    READ_ID 
+
    ONFI Read ID 
    
+
    READ_PARAM_PAGE 
+
    ONFI Read Parameter Page 
    
+
    RESET 
+
    ONFI Reset 
    
+
    GET_FEATURES 
+
    ONFI Get Features 
    
+
    SET_FEATURES 
+
    ONFI Set Features 
    
+
    READ_CACHE_RANDOM 
+
    ONFI Read page cache random 
    
+
    READ_CACHE_END_SEQ 
+
    ONFI Read page cache end 
    
+
    PAGE_CACHE_PROGRAM 
+
    ONFI Program page cache 
    
+
    
 
    
+
    
 
    
-    
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
+
+
    
+
    
+
+
    
+Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
+
    
+
+
+
diff --git a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__sinit_8c.html b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__sinit_8c.html
index f9154e87..023d1b22 100755
--- a/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__sinit_8c.html
+++ b/XilinxProcessorIPLib/drivers/nandps/doc/html/api/xnandps__sinit_8c.html
@@ -2,107 +2,96 @@
 
    
 
-   xnandps_sinit.c File Reference
+   Xilinx Driver nandps v2_1: xnandps_sinit.c File Reference
 
-
+
 
 
    Xilinx Processor IP Library
    
 Software Drivers
 
    
-
-
    
-  
    
-
    
-  
    
-
    xnandps_sinit.c File Reference
    Detailed Description
    
-This file contains the implementation of the XNand driver's static initialization functionality.
    
-
    Note:
    None.
    
-
    
-
     MODIFICATION HISTORY:
    
-
     Ver   Who    Date    	   Changes
+
+
+
+
    
+
    xnandps_sinit.c File Reference
    #include "xparameters.h"
    
+#include "xnandps.h"
    
+
+
+
+
+
+
    Functions
    XNandPs_Config * XNandPs_LookupConfig (u16 DeviceId)
    Variables
    XNandPs_Config XNandPs_ConfigTable []
    
+
    Detailed Description
    
+
    This file contains the implementation of the XNand driver's static initialization functionality.
    
+
    Note:
    None.
    
+
     MODIFICATION HISTORY:
     Ver   Who    Date    	   Changes
  ----- ---- ----------  -----------------------------------------------
  1.00a nm   12/10/2010  First release
- 
     
-
    
-#include "xparameters.h"
    
-#include "xnandps.h"
    
-
-
-
-
-
-
-
-
-

    Functions
    XNandPs_Config * XNandPs_LookupConfig (u16 DeviceId)

    Variables
    XNandPs_Config XNandPs_ConfigTable []
    
-
    Function Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+ 
    Function Documentation
    
+
+
    
+
    
+      
     
    
-          
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
+          
    
         
    XNandPs_Config* XNandPs_LookupConfig           ( u16  DeviceId           ) XNandPs_Config* XNandPs_LookupConfig (u16  DeviceId ) 
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
-
-
    
-This function looks up the device configuration based on the unique device ID. The table XNandPs_ConfigTable contains the configuration info for each device in the system.
    
-
    Parameters:
    
+
+
    
+
    This function looks up the device configuration based on the unique device ID. The table XNandPs_ConfigTable contains the configuration info for each device in the system.
    
+
    Parameters:
    
   
    
     
    DeviceId contains the ID of the device for which the device configuration pointer is to be returned.
    
   
    
+  
    
 
    
-
    Returns:
      
-
    • A pointer to the configuration found.
    • NULL if the specified device ID was not found.
    
+
    Returns:
      
+
    • A pointer to the configuration found.
      • 
+
    • NULL if the specified device ID was not found.
      • 
+
    
 
    
-
    Note:
    None. 
    
-    
    
-
    Variable Documentation
    
-
    
-
-  
-    
-  
-
    
-      
+
    Note:
    None. 
    
+
+
+
+
    Variable Documentation
    
+
+
    
+
    
+      
    
-          
+          
    
         
    XNandPs_Config XNandPs_ConfigTable[]          XNandPs_Config XNandPs_ConfigTable[]
         
    
       
    
-    
    
-
-  
-    
-    
-  
-
    
-       
-    
+
+
    
+
    This table contains configuration information for each System Monitor/ADC device in the system. 
    
+
+
    
+
+
+
    
+Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
+
    
+
+
 
-
    
-This table contains configuration information for each System Monitor/ADC device in the system.     
    
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.