diff --git a/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.mdd b/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.mdd
index e8ff05f9..69a7be51 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.mdd
+++ b/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.mdd
@@ -36,6 +36,6 @@ BEGIN driver dprxss
 	OPTION driver_state = ACTIVE;
 	OPTION depends = (video_common_v2_0);
 	OPTION copyfiles = all;
-	OPTION VERSION = 1.0;
+	OPTION VERSION = 2.0;
 	OPTION NAME = dprxss;
 END driver
diff --git a/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.tcl b/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.tcl
index af20ba9e..83e60425 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.tcl
+++ b/XilinxProcessorIPLib/drivers/dprxss/data/dprxss.tcl
@@ -27,6 +27,11 @@
 # Except as contained in this notice, the name of the Xilinx shall not be used
 # in advertising or otherwise to promote the sale, use or other dealings in
 # this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver  Who Date     Changes
+# ---- --- -------- -----------------------------------------------------------
+# 2.00 sha 10/05/15 Added Timer Counter support.
 ###############################################################################
 
 proc generate {drv_handle} {
@@ -50,6 +55,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} {
 	set sub_core_params(displayport) "BASEADDR S_AXI_ACLK LANE_COUNT LINK_RATE MAX_BITS_PER_COLOR QUAD_PIXEL_ENABLE DUAL_PIXEL_ENABLE YCRCB_ENABLE YONLY_ENABLE GT_DATAWIDTH SECONDARY_SUPPORT AUDIO_CHANNELS MST_ENABLE NUMBER_OF_MST_STREAMS PROTOCOL_SELECTION FLOW_DIRECTION"
 	set sub_core_params(axi_iic) "BASEADDR TEN_BIT_ADR GPO_WIDTH"
 	set sub_core_params(hdcp) "BASEADDR S_AXI_FREQUENCY IS_RX IS_HDMI"
+	set sub_core_params(axi_timer) "BASEADDR CLOCK_FREQ_HZ"
 	set total_subcores [array size sub_core_params]
 
 	set filename [file join "src" $file_name]
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.h b/XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.h
index 55c278f7..21b7a4c7 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.h
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/hdcp1x/xdprxss_hdcp1x.h
@@ -41,8 +41,10 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- -----------------------------------------------------
+* ---- --- -------- ----------------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Protected HDCP, Timer Counter header file under macro
+*                    number of instances.
 * </pre>
 *
 ******************************************************************************/
@@ -56,7 +58,11 @@ extern "C" {
 
 /***************************** Include Files *********************************/
 
+#include "xparameters.h"
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
 #include "xhdcp1x.h"
+#include "xtmrctr.h"
+#endif
 
 /************************** Constant Definitions *****************************/
 
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c
index 63c6e734..137f74ca 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss.c
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This is the main file for Xilinx DisplayPort Receiver Subsystem driver.
@@ -45,8 +45,10 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- -----------------------------------------------------
+* ---- --- -------- ----------------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Added HDCP and Timer Counter support.
+*                   Protected HDCP under macro number of instances.
 * </pre>
 *
 ******************************************************************************/
@@ -70,6 +72,10 @@
 typedef struct {
 	XDp DpInst;
 	XIic IicInst;
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x Hdcp1xInst;
+	XTmrCtr TmrCtrInst;
+#endif
 } XDpRxSs_SubCores;
 
 /************************** Function Prototypes ******************************/
@@ -80,6 +86,10 @@ static void StubTp1Callback(void *InstancePtr);
 static void StubTp2Callback(void *InstancePtr);
 static void StubUnplugCallback(void *InstancePtr);
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+static void DpRxSs_TimeOutCallback(void *InstancePtr, u8 TmrCtrNumber);
+#endif
+
 /************************** Variable Definitions *****************************/
 
 /* A generic EDID structure. */
@@ -139,6 +149,9 @@ XDpRxSs_SubCores DpRxSsSubCores;
 u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
 				u32 EffectiveAddr)
 {
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x_Config Hdcp1xConfig;
+#endif
 	XIic_Config IicConfig;
 	XDp_Config DpConfig;
 	u32 Status;
@@ -238,13 +251,13 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
 		XVidC_Dp159Reset(InstancePtr->IicPtr, FALSE);
 
 		/* Wait for us */
-		XDp_WaitUs(InstancePtr->DpPtr, 800);
+		XDp_WaitUs(InstancePtr->DpPtr, 1000);
 
 		/* Initialize DP159 */
 		XVidC_Dp159Initialize(InstancePtr->IicPtr);
 
 		/* Wait for us */
-		XDp_WaitUs(InstancePtr->DpPtr, 900);
+		XDp_WaitUs(InstancePtr->DpPtr, 1000);
 
 		/* Initialize default training pattern callbacks in DP RX
 		 * Subsystem
@@ -271,6 +284,74 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
 		DpRxSs_PopulateDpRxPorts(InstancePtr);
 	}
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	/* Check for Timer Counter availability */
+	if (InstancePtr->TmrCtrPtr != NULL) {
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing Timer "
+			"Counter IP \n\r");
+
+		/* Calculate absolute base address of Timer Counter sub-core */
+		InstancePtr->Config.TmrCtrSubCore.TmrCtrConfig.BaseAddress +=
+					InstancePtr->Config.BaseAddress;
+
+		/* Timer Counter config initialize */
+		Status = XTmrCtr_Initialize(InstancePtr->TmrCtrPtr,
+		InstancePtr->Config.TmrCtrSubCore.TmrCtrConfig.DeviceId);
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: Timer "
+				"Counter initialization failed\n\r");
+			return XST_FAILURE;
+		}
+
+		/* Calculate absolute base address of Timer Counter sub-core */
+		InstancePtr->TmrCtrPtr->Config.BaseAddress +=
+					InstancePtr->Config.BaseAddress;
+		InstancePtr->TmrCtrPtr->BaseAddress +=
+					InstancePtr->Config.BaseAddress;
+
+		/* Configure the callback */
+		XTmrCtr_SetHandler(InstancePtr->TmrCtrPtr,
+				(XTmrCtr_Handler)DpRxSs_TimeOutCallback,
+					InstancePtr);
+
+		/* Enable the specified options for Timer Counter zero */
+		XTmrCtr_SetOptions (InstancePtr->TmrCtrPtr, 0,
+			XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION);
+
+		/* Set the reset value to Timer Counter zero */
+		XTmrCtr_SetResetValue (InstancePtr->TmrCtrPtr, 0,
+					XDPRXSS_TMRCTR_RST_VAL);
+	}
+
+	/* Check for HDCP availability */
+	if ((InstancePtr->Hdcp1xPtr != NULL) &&
+					(InstancePtr->Config.HdcpEnable)) {
+		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing HDCP IP "
+				"\n\r");
+
+		/* Calculate absolute base address of HDCP sub-core */
+		InstancePtr->Config.Hdcp1xSubCore.Hdcp1xConfig.BaseAddress +=
+					InstancePtr->Config.BaseAddress;
+		(void)memcpy((void *)&(Hdcp1xConfig),
+			(const void *)&CfgPtr->Hdcp1xSubCore.Hdcp1xConfig,
+				sizeof(XHdcp1x_Config));
+
+		/* HDCP config initialize */
+		Hdcp1xConfig.BaseAddress += InstancePtr->Config.BaseAddress;
+		Status = XHdcp1x_CfgInitialize(InstancePtr->Hdcp1xPtr,
+				&Hdcp1xConfig, (void *)InstancePtr->DpPtr,
+				Hdcp1xConfig.BaseAddress);
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: HDCP "
+				"initialization failed\n\r");
+			return XST_FAILURE;
+		}
+
+		/* Set key selection value for RX */
+		XHdcp1x_SetKeySelect(InstancePtr->Hdcp1xPtr, 0x1);
+	}
+#endif
+
 	/* Set the flag to indicate the subsystem is ready */
 	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
 
@@ -295,6 +376,17 @@ void XDpRxSs_Reset(XDpRxSs *InstancePtr)
 	/* Verify argument. */
 	Xil_AssertVoid(InstancePtr != NULL);
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	/* Reset HDCP interface */
+	if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) {
+		XHdcp1x_Reset(InstancePtr->Hdcp1xPtr);
+	}
+
+	/* Reset Timer Counter zero */
+	if (InstancePtr->TmrCtrPtr) {
+		XTmrCtr_Reset(InstancePtr->TmrCtrPtr, 0);
+	}
+#endif
 	/* Reset the video and AUX logic from DP RX */
 	XDpRxSs_WriteReg(InstancePtr->DpPtr->Config.BaseAddr,
 			XDP_RX_SOFT_RESET, XDP_RX_SOFT_RESET_VIDEO_MASK |
@@ -588,6 +680,373 @@ u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr)
 	return Status;
 }
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+/*****************************************************************************/
+/**
+*
+* This function enables High-Bandwidth Content Protection (HDCP) interface.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- XST_SUCCESS, if HDCP i/f enabled successfully.
+*		- XST_FAILURE, otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_HdcpEnable(XDpRxSs *InstancePtr)
+{
+	u32 Status;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Enable HDCP interface */
+	Status = XHdcp1x_Enable(InstancePtr->Hdcp1xPtr);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function disables High-Bandwidth Content Protection (HDCP) interface.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- XST_SUCCESS, if HDCP i/f disabled successfully.
+*		- XST_FAILURE, otherwise.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_HdcpDisable(XDpRxSs *InstancePtr)
+{
+	u32 Status;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Enable HDCP interface */
+	Status = XHdcp1x_Disable(InstancePtr->Hdcp1xPtr);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function polls the HDCP interface, process events and sets receive
+* state machine accordingly.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- XST_SUCCESS, if polling the HDCP interface was successful.
+*		- XST_FAILURE, if polling the HDCP interface failed.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_Poll(XDpRxSs *InstancePtr)
+{
+	u32 Status;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Poll the HDCP interface */
+	Status = XHdcp1x_Poll(InstancePtr->Hdcp1xPtr);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function enables/disables the underlying physical interface.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+* @param	PhyState indicates TRUE/FALSE value to enable/disable the
+*		underlying physical interface.
+*
+* @return
+*		- XST_SUCCESS, if the underlying physical interface enabled
+*		successfully.
+*		- XST_FAILURE, if the underlying physical interface failed to
+*		enable.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_SetPhysicalState(XDpRxSs *InstancePtr, u32 PhyState)
+{
+	u32 Status;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((PhyState == TRUE) || (PhyState == FALSE));
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Enable underlying physical interface */
+	Status = XHdcp1x_SetPhysicalState(InstancePtr->Hdcp1xPtr, PhyState);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets lane(s) of the HDCP interface.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+* @param	Lane is the number of lanes to be used.
+*		- 1 = XDPRXSS_LANE_COUNT_SET_1
+*		- 2 = XDPRXSS_LANE_COUNT_SET_2
+*		- 4 = XDPRXSS_LANE_COUNT_SET_4
+*
+* @return
+*		- XST_SUCCESS, if lane(s) into the HDCP i/f set successfully.
+*		- XST_FAILURE, if failed to set lane(s) into the HDCP i/f.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_SetLane(XDpRxSs *InstancePtr, u32 Lane)
+{
+	u32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+	Xil_AssertNonvoid((Lane == XDPRXSS_LANE_COUNT_SET_1) ||
+			(Lane == XDPRXSS_LANE_COUNT_SET_2) ||
+			(Lane == XDPRXSS_LANE_COUNT_SET_4));
+
+	/* Set lanes into the HDCP interface */
+	Status = XHdcp1x_SetLaneCount(InstancePtr->Hdcp1xPtr, Lane);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initiates authentication process.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- XST_SUCCESS, if authentication initiated successfully.
+*		- XST_FAILURE, if authentication initiated failed.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_Authenticate(XDpRxSs *InstancePtr)
+{
+	u32 Status;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Initiate authentication process */
+	Status = XHdcp1x_Authenticate(InstancePtr->Hdcp1xPtr);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the HDCP Receiver authenticated or not.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- TRUE, if HDCP Receiver is authenticated.
+*		- FALSE, if the HDCP Receiver not authenticated.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XDpRxSs_IsAuthenticated(XDpRxSs *InstancePtr)
+{
+	u32 Authenticate;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Check authentication has completed successfully */
+	Authenticate = XHdcp1x_IsAuthenticated(InstancePtr->Hdcp1xPtr);
+
+	return Authenticate;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function retrieves the current encryption map.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return
+*		- The current encryption map.
+*		- Otherwise zero.
+*
+* @note		None.
+*
+******************************************************************************/
+u64 XDpRxSs_GetEncryption(XDpRxSs *InstancePtr)
+{
+	u64 StreamMap;
+
+	/* Verify arguments.*/
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Get stream map of the stream(s) */
+	StreamMap = XHdcp1x_GetEncryption(InstancePtr->Hdcp1xPtr);
+
+	return StreamMap;
+}
+/*****************************************************************************/
+/**
+*
+* This function sets the debug printf function.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+* @param	PrintfFunc is the printf function.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_SetDebugPrintf(XDpRxSs *InstancePtr, XDpRxSs_Printf PrintfFunc)
+{
+	/* Verify arguments.*/
+	Xil_AssertVoid(InstancePtr->Config.HdcpEnable == 0x1);
+	Xil_AssertVoid(PrintfFunc != NULL);
+
+	/* Set debug printf function */
+	XHdcp1x_SetDebugPrintf(PrintfFunc);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the debug log message function.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+* @param	LogFunc is the debug logging function.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_SetDebugLogMsg(XDpRxSs *InstancePtr, XDpRxSs_LogMsg LogFunc)
+{
+	/* Verify arguments.*/
+	Xil_AssertVoid(InstancePtr->Config.HdcpEnable == 0x1);
+	Xil_AssertVoid(LogFunc != NULL);
+
+	/* Set debug log message function */
+	XHdcp1x_SetDebugLogMsg(LogFunc);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function starts the Timer Counter in count down, interrupt mode.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_StartTimer(XDpRxSs *InstancePtr)
+{
+	/* Verify arguments.*/
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Enable the specified options for Timer Counter zero */
+	XTmrCtr_SetOptions (InstancePtr->TmrCtrPtr, 0,
+		XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION);
+
+	/* Set the reset value to Timer Counter zero */
+	XTmrCtr_SetResetValue (InstancePtr->TmrCtrPtr, 0,
+				XDPRXSS_TMRCTR_RST_VAL);
+
+	/* Start Timer Counter 0 in count down mode */
+	XTmrCtr_Start(InstancePtr->TmrCtrPtr, 0);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function stops the Timer Counter.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_StopTimer(XDpRxSs *InstancePtr)
+{
+	/* Verify arguments.*/
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->Config.HdcpEnable == 0x1);
+
+	/* Stop Timer Counter 0 in count down mode */
+	XTmrCtr_Stop(InstancePtr->TmrCtrPtr, 0);
+
+	/* Reset Timer Counter reset done */
+	InstancePtr->TmrCtrResetDone = 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the callback called when the Timer Counter reset done with
+* specified reset value, assigned during initialization.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+* @param	TmrCtrNumber is the number of the timer/counter within the
+*		Timer Counter core.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void DpRxSs_TimeOutCallback(void *InstancePtr, u8 TmrCtrNumber)
+{
+	XDpRxSs *XDpRxSsPtr = (XDpRxSs *)InstancePtr;
+
+	/* Verify arguments.*/
+	Xil_AssertVoid(XDpRxSsPtr != NULL);
+	Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT);
+
+	/* Set Timer Counter reset done */
+	XDpRxSsPtr->TmrCtrResetDone = 1;
+}
+#endif
+
 /*****************************************************************************/
 /**
 *
@@ -608,6 +1067,18 @@ static void DpRxSs_GetIncludedSubCores(XDpRxSs *InstancePtr)
 	/* Assign instance of IIC core */
 	InstancePtr->IicPtr = ((InstancePtr->Config.DpSubCore.IsPresent)?
 					(&DpRxSsSubCores.IicInst): NULL);
+
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	/* Assign instance of HDCP core */
+	InstancePtr->Hdcp1xPtr =
+		((InstancePtr->Config.Hdcp1xSubCore.IsPresent)?
+				(&DpRxSsSubCores.Hdcp1xInst): NULL);
+
+	/* Assign instance of Timer Counter core */
+	InstancePtr->TmrCtrPtr =
+		((InstancePtr->Config.TmrCtrSubCore.IsPresent)?
+					(&DpRxSsSubCores.TmrCtrInst): NULL);
+#endif
 }
 
 /*****************************************************************************/
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.h b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.h
index e83167aa..e42fadaa 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.h
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss.h
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss.h
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 * @details
 *
@@ -58,11 +58,13 @@
 *
 * <b>Interrupts</b>
 *
-* The DisplayPort RX Subsystem driver provides an interrupt handler
-* XDpRxSs_DpIntrHandler for handling the interrupt from the DisplayPort
-* sub-core. The users of this driver have to register this handler with
-* the interrupt system and provide the callback functions by using
-* XDpRxSs_SetCallBack API.
+* The DisplayPort RX Subsystem driver provides the interrupt handlers
+* - XDpRxSs_DpIntrHandler
+* - XDpRxSs_HdcpIntrHandler
+* - XDpRxSs_TmrCtrIntrHandler, for handling the interrupt from the DisplayPort,
+* optional HDCP and Timer Counter sub-cores respectively. The users of this
+* driver have to register this handler with the interrupt system and provide
+* the callback functions by using XDpRxSs_SetCallBack API.
 *
 * <b>Virtual Memory</b>
 *
@@ -91,8 +93,10 @@
 * MODIFICATION HISTORY:
 *
 * Ver  Who Date     Changes
-* ---- --- -------- -----------------------------------------------------
+* ---- --- -------- ----------------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Removed HDCP interrupt handler types.
+*                   Added HDCP and Timer Counter support.
 * </pre>
 *
 ******************************************************************************/
@@ -175,48 +179,13 @@ typedef enum {
 	XDPRXSS_HANDLER_DP_CRC_TEST_EVENT = 16,	/**< CRC test start event
 						  *  interrupt type for
 						  *  DisplayPort core */
-	XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT = 17,	/**< HDCP debug
-							  *  register write
-							  *  event interrupt
-							  *  type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT = 18,	/**< HDCP AKSV MSB
-							  *  register write
-							  *  event interrupt
-							  *  type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT = 19,	/**< HDCP AN MSB
-							  *  register write
-							  *  event interrupt
-							  *  type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT = 20,	/**< HDCP A info
-							  *  register write
-							  *  event interrupt
-							  *  type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT = 21,	/**< HDCP RO register
-							  *  read event
-							  *  interrupt type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT = 22,	/**< HDCP B info
-							  *  register read
-							  *  event interrupt
-							  *  type for
-							  *  DisplayPort
-							  *  core */
-	XDPRXSS_HANDLER_UNPLUG_EVENT = 23,	/**< Unplug event type for
+	XDPRXSS_HANDLER_UNPLUG_EVENT = 17,	/**< Unplug event type for
 						  *  DisplayPort RX
 						  *  Subsystem */
-	XDPRXSS_HANDLER_LINKBW_EVENT = 24,	/**< Link BW event type for
+	XDPRXSS_HANDLER_LINKBW_EVENT = 18,	/**< Link BW event type for
 						  *  DisplayPort RX Subsystem
 						  */
-	XDPRXSS_HANDLER_PLL_RESET_EVENT = 25	/**< PLL reset event type for
+	XDPRXSS_HANDLER_PLL_RESET_EVENT = 19	/**< PLL reset event type for
 						  *  DisplayPort RX Subsystem
 						  */
 } XDpRxSs_HandlerType;
@@ -252,6 +221,7 @@ typedef struct {
 				  *  information */
 } XDpRxSs_IicSubCore;
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
 /**
 * High-Bandwidth Content Protection (HDCP) Sub-core structure.
 */
@@ -261,6 +231,17 @@ typedef struct {
 					  *  information */
 } XDpRxSs_Hdcp1xSubCore;
 
+/**
+* Timer Counter Sub-core structure.
+*/
+typedef struct {
+	u16 IsPresent;		/**< Flag to hold the presence of Timer
+				  *  Counter core */
+	XTmrCtr_Config TmrCtrConfig;	/**< Timer Counter core
+					  * configuration information */
+} XDpRxSs_TmrCtrSubCore;
+#endif
+
 /**
 * This typedef contains configuration information for the DisplayPort
 * Receiver Subsystem core. Each DisplayPort RX Subsystem core should have
@@ -288,8 +269,14 @@ typedef struct {
 	u8 ColorFormat;		/**< Type of color format supported by this
 				  *  core instance. */
 	XDpRxSs_DpSubCore DpSubCore;	/**< DisplayPort Configuration */
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
 	XDpRxSs_Hdcp1xSubCore Hdcp1xSubCore;	/**< HDCP Configuration */
+#endif
 	XDpRxSs_IicSubCore IicSubCore;	/**< IIC Configuration */
+#if ((XPAR_XHDCP_NUM_INSTANCES > 0) && (XPAR_XTMRCTR_NUM_INSTANCES > 0))
+	XDpRxSs_TmrCtrSubCore TmrCtrSubCore;	/**< Timer Counter
+						  *  Configuration */
+#endif
 } XDpRxSs_Config;
 
 /*****************************************************************************/
@@ -315,6 +302,16 @@ typedef struct {
 	/* Sub-core instances */
 	XDp *DpPtr;			/**< DisplayPort sub-core instance */
 	XIic *IicPtr;			/**< IIC sub-core instance */
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x *Hdcp1xPtr;		/**< HDCP sub-core instance */
+	XTmrCtr *TmrCtrPtr;		/**< Timer Counter sub-core instance */
+	u8 TmrCtrResetDone;		/**< Timer reset done. This is used for
+					  *  MacBook which authenticates just
+					  *  after training is done. This
+					  *  ensures that system does not do
+					  *  anything until this variable set
+					  *  to one.*/
+#endif
 
 	/* Callback */
 	XDpRxSs_Callback PllResetCallback;	/**< Callback function for PLL
@@ -444,6 +441,11 @@ typedef struct {
 #define XDpRxSs_WaitUs(InstancePtr, MicroSeconds) \
 	XDp_WaitUs((InstancePtr)->DpPtr, MicroSeconds)
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+#define XDpRxSs_Printf		XHdcp1x_Printf	/**< Debug printf */
+#define XDpRxSs_LogMsg		XHdcp1x_LogMsg	/**< Debug log message */
+#endif
+
 /************************** Function Prototypes ******************************/
 
 /* Initialization function in xdprxss_sinit.c */
@@ -461,15 +463,36 @@ u32 XDpRxSs_CheckLinkStatus(XDpRxSs *InstancePtr);
 u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr);
 void XDpRxSs_SetUserPixelWidth(XDpRxSs *InstancePtr, u8 UserPixelWidth);
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+/* Optional HDCP related functions */
+u32 XDpRxSs_HdcpEnable(XDpRxSs *InstancePtr);
+u32 XDpRxSs_HdcpDisable(XDpRxSs *InstancePtr);
+u32 XDpRxSs_Poll(XDpRxSs *InstancePtr);
+u32 XDpRxSs_SetPhysicalState(XDpRxSs *InstancePtr, u32 PhyState);
+u32 XDpRxSs_SetLane(XDpRxSs *InstancePtr, u32 Lane);
+u32 XDpRxSs_Authenticate(XDpRxSs *InstancePtr);
+u32 XDpRxSs_IsAuthenticated(XDpRxSs *InstancePtr);
+u64 XDpRxSs_GetEncryption(XDpRxSs *InstancePtr);
+void XDpRxSs_SetDebugPrintf(XDpRxSs *InstancePtr, XDpRxSs_Printf PrintfFunc);
+void XDpRxSs_SetDebugLogMsg(XDpRxSs *InstancePtr, XDpRxSs_LogMsg LogFunc);
+void XDpRxSs_StartTimer(XDpRxSs *InstancePtr);
+void XDpRxSs_StopTimer(XDpRxSs *InstancePtr);
+#endif
+
 void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr);
 void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr);
 void XDpRxSs_ReportMsaInfo(XDpRxSs *InstancePtr);
 void XDpRxSs_ReportDp159BitErrCount(XDpRxSs *InstancePtr);
+void XDpRxSs_ReportHdcpInfo(XDpRxSs *InstancePtr);
 
 /* Self test function in xdprxss_selftest.c */
 u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr);
 
 /* Interrupt functions in xdprxss_intr.c */
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+void XDpRxSs_HdcpIntrHandler(void *InstancePtr);
+void XDpRxSs_TmrCtrIntrHandler(void *InstancePtr);
+#endif
 void XDpRxSs_DpIntrHandler(void *InstancePtr);
 u32 XDpRxSs_SetCallBack(XDpRxSs *InstancePtr, u32 HandlerType,
 			void *CallbackFunc, void *CallbackRef);
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_dbg.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_dbg.c
index 40e50dbd..896caf13 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_dbg.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_dbg.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss_dbg.c
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This file contains functions to report debug information of DisplayPort RX
@@ -45,6 +45,9 @@
 * Ver  Who Date     Changes
 * ---- --- -------- -----------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Added HDCP support.
+*                   Removed DP159 bit error count code. Used DP159 bit error
+*                   count function from Video Common library.
 * </pre>
 *
 ******************************************************************************/
@@ -91,6 +94,15 @@ void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr)
 	xil_printf("\n\rDisplayPort RX Subsystem info:\n\r");
 
 	/* Report all the included cores in the subsystem instance */
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	if (InstancePtr->Hdcp1xPtr) {
+		xil_printf("High-Bandwidth Content protection (HDCP):Yes\n\r");
+	}
+	if (InstancePtr->TmrCtrPtr) {
+		xil_printf("Timer Counter(0):Yes\n\r");
+	}
+#endif
+
 	if (InstancePtr->DpPtr) {
 		xil_printf("DisplayPort Receiver(DPRX):Yes\n\r");
 	}
@@ -140,36 +152,46 @@ void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr)
 void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr)
 {
 	XDp_Config *RxConfig = &InstancePtr->DpPtr->Config;
+	u32 RegValue;
+	u32 Index;
 
 	/* Verify argument. */
 	Xil_AssertVoid(InstancePtr != NULL);
 
 	/* Read link rate and lane count */
-	xil_printf("\n\rLINK_BW_SET (0x09C) status in DPCD = 0x%x\n\r",
+	xil_printf("\n\rLINK_BW_SET (0x400) status in DPCD = 0x%x\n\r",
 			XDpRxSs_ReadReg(RxConfig->BaseAddr,
-				XDP_RX_OVER_LINK_BW_SET));
-	xil_printf("\n\rLANE_COUNT_SET (0x0A0) status in DPCD = 0x%x\n\r",
+					XDP_RX_DPCD_LINK_BW_SET));
+	xil_printf("LANE_COUNT_SET (0x404) status in DPCD = 0x%x\n\r",
 			XDpRxSs_ReadReg(RxConfig->BaseAddr,
-				XDP_RX_OVER_LANE_COUNT_SET));
+					XDP_RX_DPCD_LANE_COUNT_SET));
 
 	/* Read lanes status */
-	xil_printf("LANE0_1_STATUS (0x043C) in DPCD = 0x%x\n\r",
+	xil_printf("\n\rLANE0_1_STATUS (0x043C) in DPCD = 0x%x\n\r",
 			XDpRxSs_ReadReg(RxConfig->BaseAddr,
 				XDP_RX_DPCD_LANE01_STATUS));
 	xil_printf("LANE2_3_STATUS (0x440) in DPCD = 0x%x\n\r",
 			XDpRxSs_ReadReg(RxConfig->BaseAddr,
 				XDP_RX_DPCD_LANE23_STATUS));
 
-	/* Read symbol error */
-	xil_printf("SYM_ERR_CNT01 (0x448) = 0x%x\n\r"
-		"SYM_ERR_CNT23 (0x44C) = 0x%x\n\r",
-			XDpRxSs_ReadReg(RxConfig->BaseAddr,
-				XDP_RX_DPCD_SYM_ERR_CNT01),
-			XDpRxSs_ReadReg(RxConfig->BaseAddr,
-				XDP_RX_DPCD_SYM_ERR_CNT23));
+	/* Read symbol error which is RC register. Two times read is required
+	 * due to during training if this register is read it gives all F's,
+	 * second time read it gives proper value.
+	 */
+	for (Index = 0; Index < 2; Index++) {
+		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
+				XDP_RX_DPCD_SYM_ERR_CNT01);
+	}
+	xil_printf("\n\rSYM_ERR_CNT01 (0x448) = 0x%x\n\r", RegValue);
+
+	for (Index = 0; Index < 2; Index++) {
+		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
+				XDP_RX_DPCD_SYM_ERR_CNT23);
+	}
+	xil_printf("SYM_ERR_CNT23 (0x44C) = 0x%x\n\r", RegValue);
 
 	/* PHY status */
-	xil_printf("PHY_STATUS (0x208) = 0x%x\n\r",
+	xil_printf("\n\rPHY_STATUS (0x208) = 0x%x\n\r",
 		XDpRxSs_ReadReg(RxConfig->BaseAddr, XDP_RX_PHY_STATUS));
 
 	xil_printf("\n\r");
@@ -246,66 +268,34 @@ void XDpRxSs_ReportMsaInfo(XDpRxSs *InstancePtr)
 ******************************************************************************/
 void XDpRxSs_ReportDp159BitErrCount(XDpRxSs *InstancePtr)
 {
-	u8 Data;
-
 	/* Verify argument. */
 	Xil_AssertVoid(InstancePtr != NULL);
 
-	/* Select page 0 */
-	XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0xFF, 0x00);
+	/* Print bit error count */
+	XVidC_Dp159BitErrCount(InstancePtr->IicPtr);
+}
 
-	/* Read TST_INT/Q */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x17, &Data);
-	xil_printf("TST_INT/Q : %d\n\r", Data);
+/*****************************************************************************/
+/**
+*
+* This function prints the debug display info of the HDCP interface.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_ReportHdcpInfo(XDpRxSs *InstancePtr)
+{
+	/* Verify argument. */
+	Xil_AssertVoid(InstancePtr != NULL);
 
-	/* BERT counter0[7:0] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x18, &Data);
-	xil_printf("BERT counter0[7:0] : %d\n\r", Data);
-
-	/* BERT counter0[11:8] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x19, &Data);
-	xil_printf("BERT counter0[11:8] : %d\n\r", Data);
-
-	/* BERT counter1[7:0] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1A, &Data);
-	xil_printf("BERT counter0[7:0] : %d\n\r", Data);
-
-	/* BERT counter1[11:8] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1B, &Data);
-	xil_printf("BERT counter0[11:8] : %d\n\r", Data);
-
-	/* BERT counter2[7:0] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1C, &Data);
-	xil_printf("BERT counter2[7:0] : %d\n\r", Data);
-
-	/* BERT counter2[11:8] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1D, &Data);
-	xil_printf("BERT counter2[11:8] : %d\n\r", Data);
-
-	/* BERT counter3[7:0] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1E, &Data);
-	xil_printf("BERT counter3[7:0] : %d\n\r", Data);
-
-	/* BERT counter3[11:8] */
-	XVidC_Dp159Read(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0x1F, &Data);
-	xil_printf("BERT counter3[11:8] : %d\n\r", Data);
-
-	/* Clear BERT counters and TST_INTQ latches - Self-clearing in DP159 */
-	XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0xFF, 0x00);
-
-	/* Select page 1 */
-	XVidC_Dp159Write(InstancePtr->IicPtr, XVIDC_DP159_IIC_SLAVE,
-			0xFF, 0x01);
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	XHdcp1x_Info(InstancePtr->Hdcp1xPtr);
+#else
+	xil_printf("HDCP is not supported in this design.\n\r");
+#endif
 }
 /** @} */
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_g.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_g.c
index a001ecea..0582d83b 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_g.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_g.c
@@ -47,6 +47,7 @@
 #define XPAR_DP_RX_SUBSYSTEM_0_DP_PRESENT	1
 #define XPAR_DP_RX_SUBSYSTEM_0_DP_RX_HDCP_PRESENT	1
 #define XPAR_DP_RX_SUBSYSTEM_0_IIC_PRESENT	1
+#define XPAR_DP_RX_SUBSYSTEM_0_TIMER_PRESENT	1
 
 
 XDpRxSs_Config XDpRxSs_ConfigTable[] =
@@ -103,6 +104,14 @@ XDpRxSs_Config XDpRxSs_ConfigTable[] =
 				XPAR_DP_RX_SUBSYSTEM_0_IIC_TEN_BIT_ADR,
 				XPAR_DP_RX_SUBSYSTEM_0_IIC_GPO_WIDTH
 			}
+		},
+		{
+			XPAR_DP_RX_SUBSYSTEM_0_TIMER_PRESENT,
+			{
+				XPAR_DP_RX_SUBSYSTEM_0_TIMER_DEVICE_ID,
+				XPAR_DP_RX_SUBSYSTEM_0_TIMER_BASEADDR,
+				XPAR_DP_RX_SUBSYSTEM_0_TIMER_CLOCK_FREQ_HZ
+			}
 		}
 	}
 };
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_hw.h b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_hw.h
index ec0e93aa..f36f295c 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_hw.h
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_hw.h
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss_hw.h
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This header file contains identifiers and register-level core functions (or
@@ -48,6 +48,7 @@
 * Ver  Who Date     Changes
 * ---- --- -------- -----------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Added Timer Counter reset value macro.
 * </pre>
 *
 ******************************************************************************/
@@ -123,6 +124,9 @@ extern "C" {
 #define XDPRXSS_GUID_NBYTES		XDP_GUID_NBYTES	/**< Number of bytes
 							  *  for GUID */
 
+#define XDPRXSS_TMRCTR_RST_VAL		100000000	/**< Timer Counter
+							  *  reset value */
+
 /**************************** Type Definitions *******************************/
 
 
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_intr.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_intr.c
index a5493165..c0c763e1 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_intr.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_intr.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss_intr.c
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This file contains interrupt related functions of Xilinx DisplayPort RX
@@ -45,6 +45,8 @@
 * Ver  Who Date     Changes
 * ---- --- -------- -----------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Removed setting HDCP callbacks.
+*                   Added HDCP and Timer Counter interrupt handler.
 * </pre>
 *
 ******************************************************************************/
@@ -101,6 +103,64 @@ void XDpRxSs_DpIntrHandler(void *InstancePtr)
 	XDp_InterruptHandler(XDpRxSsPtr->DpPtr);
 }
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the HDCP Cipher core.
+*
+* The application is responsible for connecting this function to the interrupt
+* system.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance that
+*		just interrupted.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_HdcpIntrHandler(void *InstancePtr)
+{
+	XDpRxSs *XDpRxSsPtr = (XDpRxSs *)InstancePtr;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(XDpRxSsPtr != NULL);
+	Xil_AssertVoid(XDpRxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* HDCP Cipher interrupt handler */
+	XHdcp1x_CipherIntrHandler(XDpRxSsPtr->Hdcp1xPtr);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the Timer Counter core.
+*
+* The application is responsible for connecting this function to the interrupt
+* system.
+*
+* @param	InstancePtr is a pointer to the XDpRxSs core instance that
+*		just interrupted.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDpRxSs_TmrCtrIntrHandler(void *InstancePtr)
+{
+	XDpRxSs *XDpRxSsPtr = (XDpRxSs *)InstancePtr;
+
+	/* Verify arguments. */
+	Xil_AssertVoid(XDpRxSsPtr != NULL);
+	Xil_AssertVoid(XDpRxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Timer Counter interrupt handler */
+	XTmrCtr_InterruptHandler(XDpRxSsPtr->TmrCtrPtr);
+}
+#endif
+
 /*****************************************************************************/
 /**
 *
@@ -126,12 +186,6 @@ void XDpRxSs_DpIntrHandler(void *InstancePtr)
 * XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT   XDp_RxSetIntrPayloadAllocHandler
 * XDPRXSS_HANDLER_DP_ACT_RX_EVENT          XDp_RxSetIntrActRxHandler
 * XDPRXSS_HANDLER_DP_CRC_TEST_EVENT        XDp_RxSetIntrCrcTestHandler
-* XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT     XDp_RxSetIntrHdcpDebugWriteHandler
-* XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT    XDp_RxSetIntrHdcpAksvWriteHandler
-* XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT      XDp_RxSetIntrHdcpAnWriteHandler
-* XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT  XDp_RxSetIntrHdcpAinfoWriteHandler
-* XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT      XDp_RxSetIntrHdcpRoReadHandler
-* XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT  XDp_RxSetIntrHdcpBinfoReadHandler
 * XDPRXSS_HANDLER_UNPLUG_EVENT             UnplugCallback
 * XDPRXSS_HANDLER_LINKBW_EVENT             LinkBwCallback
 * XDPRXSS_HANDLER_PLL_RESET_EVENT          PllResetCallback
@@ -261,42 +315,6 @@ u32 XDpRxSs_SetCallBack(XDpRxSs *InstancePtr, u32 HandlerType,
 			Status = XST_SUCCESS;
 			break;
 
-		case XDPRXSS_HANDLER_DP_HDCP_DBG_WR_EVENT:
-			XDp_RxSetIntrHdcpDebugWriteHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
-		case XDPRXSS_HANDLER_DP_HDCP_AKSV_WR_EVENT:
-			XDp_RxSetIntrHdcpAksvWriteHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
-		case XDPRXSS_HANDLER_DP_HDCP_AN_WR_EVENT:
-			XDp_RxSetIntrHdcpAnWriteHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
-		case XDPRXSS_HANDLER_DP_HDCP_A_INFO_WR_EVENT:
-			XDp_RxSetIntrHdcpAinfoWriteHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
-		case XDPRXSS_HANDLER_DP_HDCP_RO_RD_EVENT:
-			XDp_RxSetIntrHdcpRoReadHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
-		case XDPRXSS_HANDLER_DP_HDCP_B_INFO_RD_EVENT:
-			XDp_RxSetIntrHdcpBinfoReadHandler(InstancePtr->DpPtr,
-				CallbackFunc, CallbackRef);
-			Status = XST_SUCCESS;
-			break;
-
 		case XDPRXSS_HANDLER_UNPLUG_EVENT:
 			InstancePtr->UnplugCallback =
 				(XDpRxSs_Callback)((void *)CallbackFunc);
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_selftest.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_selftest.c
index d619d8f1..7162a96f 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_selftest.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_selftest.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss_selftest.c
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This file contains self test function for the DisplayPort Receiver
@@ -45,6 +45,7 @@
 * Ver  Who Date     Changes
 * ---- --- -------- -----------------------------------------------------
 * 1.00 sha 05/18/15 Initial release.
+* 2.00 sha 10/05/15 Added HDCP and Timer Counter self test.
 * </pre>
 *
 ******************************************************************************/
@@ -102,6 +103,24 @@ u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr)
 		}
 	}
 
+#if (XPAR_XHDCP_NUM_INSTANCES > 0)
+	if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) {
+		Status = XHdcp1x_SelfTest(InstancePtr->Hdcp1xPtr);
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::HDCP Self test "
+				"failed\r\n");
+		}
+	}
+
+	if (InstancePtr->TmrCtrPtr) {
+		Status = XTmrCtr_SelfTest(InstancePtr->TmrCtrPtr, 0);
+		if (Status != XST_SUCCESS) {
+			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::Timer Counter "
+				"Self test failed\r\n");
+		}
+	}
+#endif
+
 	/* Check IIC availability */
 	if (InstancePtr->IicPtr) {
 		Status = (u32)XIic_SelfTest(InstancePtr->IicPtr);
diff --git a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_sinit.c b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_sinit.c
index cc835fd5..18febb45 100644
--- a/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_sinit.c
+++ b/XilinxProcessorIPLib/drivers/dprxss/src/xdprxss_sinit.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xdprxss_sinit.c
-* @addtogroup dprxss_v1_0
+* @addtogroup dprxss_v2_0
 * @{
 *
 * This file contains static initialization method for Xilinx DisplayPort