From 8a5fe55ba2a0e5edcec585bbb30c1c5aa9102dce Mon Sep 17 00:00:00 2001
From: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Date: Tue, 29 Jul 2014 23:08:06 -0700
Subject: [PATCH] dptx: Using tabs instead of 8 spaces.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
---
.../dptx/examples/xdptx_audio_example.c | 238 +-
.../dptx/examples/xdptx_example_common.c | 354 +-
.../dptx/examples/xdptx_example_common.h | 16 +-
.../dptx/examples/xdptx_intr_example.c | 302 +-
.../dptx/examples/xdptx_poll_example.c | 164 +-
.../dptx/examples/xdptx_selftest_example.c | 44 +-
.../dptx/examples/xdptx_timer_example.c | 148 +-
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c | 3111 ++++++++---------
XilinxProcessorIPLib/drivers/dptx/src/xdptx.h | 581 +--
.../drivers/dptx/src/xdptx_hw.h | 1590 ++++-----
.../drivers/dptx/src/xdptx_intr.c | 110 +-
.../drivers/dptx/src/xdptx_selftest.c | 238 +-
.../drivers/dptx/src/xdptx_sinit.c | 28 +-
.../drivers/dptx/src/xdptx_spm.c | 720 ++--
.../drivers/dptx/src/xdptx_vidmodetable.c | 346 +-
15 files changed, 3999 insertions(+), 3991 deletions(-)
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
index 8dc407ea..ed54f23b 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
@@ -38,27 +38,27 @@
* to display video. In this example application, the sequence to enable audio
* is illustrated.
*
- * @note This example requires an audio source such as an S/PDIF instance
- * to be part of the hardware system. See XAPP1178 for reference.
- * @note This example requires that the audio enable configuration
- * parameter for DisplayPort be turned on when creating the
- * hardware design.
- * @note For this example to output audio, the user will need to
- * implement initialization of the system (Dptx_PlatformInit),
- * configuration of the audio source (Dptx_ConfigureAudioSrc) and,
- * depending on the hardware system, will need to implement sending
- * of an info frame (Dptx_AudioSendInfoFrame). See XAPP1178 and the
- * IP documentation for reference.
- * @note For this example to display output, after training is complete,
- * the user will need to implement configuration of the video
- * stream source in order to provide the DisplayPort core with
- * input (Dptx_ConfigureStreamSrc - called in
- * xdptx_example_common.c). See XAPP1178 for reference.
- * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
- * declared extern in xdptx_example_common.h and are left up to the
- * user to implement. The functions Dptx_ConfigureAudioSrc and
- * Dptx_AudioSendInfoFrame are present in this file and are also
- * left for the user to implement.
+ * @note This example requires an audio source such as an S/PDIF instance
+ * to be part of the hardware system. See XAPP1178 for reference.
+ * @note This example requires that the audio enable configuration
+ * parameter for DisplayPort be turned on when creating the
+ * hardware design.
+ * @note For this example to output audio, the user will need to
+ * implement initialization of the system (Dptx_PlatformInit),
+ * configuration of the audio source (Dptx_ConfigureAudioSrc) and,
+ * depending on the hardware system, will need to implement sending
+ * of an info frame (Dptx_AudioSendInfoFrame). See XAPP1178 and the
+ * IP documentation for reference.
+ * @note For this example to display output, after training is complete,
+ * the user will need to implement configuration of the video
+ * stream source in order to provide the DisplayPort core with
+ * input (Dptx_ConfigureStreamSrc - called in
+ * xdptx_example_common.c). See XAPP1178 for reference.
+ * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
+ * declared extern in xdptx_example_common.h and are left up to the
+ * user to implement. The functions Dptx_ConfigureAudioSrc and
+ * Dptx_AudioSendInfoFrame are present in this file and are also
+ * left for the user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@@ -87,26 +87,26 @@ static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr);
/**
* This function is the main function of the XDptx audio example.
*
- * @param None.
+ * @param None.
*
* @return
- * - XST_SUCCESS if the audio example finished successfully.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the audio example finished successfully.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
int main(void)
{
- int Status;
+ u32 Status;
- /* Run the XDptx audio example. */
- Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Run the XDptx audio example. */
+ Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -115,46 +115,46 @@ int main(void)
* function will set up audio, initiate link training, and a video stream will
* start being sent over the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param DeviceId is the unique device ID of the DisplayPort TX core
- * instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param DeviceId is the unique device ID of the DisplayPort TX core
+ * instance.
*
* @return
- * - XST_SUCCESS if the system was set up correctly and link
- * training was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the system was set up correctly and link
+ * training was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId)
{
- u32 Status;
+ u32 Status;
- /* Do platform initialization here. This is hardware system specific -
- * it is up to the user to implement this function. */
- Dptx_PlatformInit();
- /*******************/
+ /* Do platform initialization here. This is hardware system specific -
+ * it is up to the user to implement this function. */
+ Dptx_PlatformInit();
+ /*******************/
- Status = Dptx_SetupExample(InstancePtr, DeviceId);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = Dptx_SetupExample(InstancePtr, DeviceId);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Initialize DisplayPort audio. */
- Dptx_AudioInit(InstancePtr);
+ /* Initialize DisplayPort audio. */
+ Dptx_AudioInit(InstancePtr);
- XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
- XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
+ XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
+ XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
- /* A sink monitor must be connected at this point. See the polling or
- * interrupt examples for how to wait for a connection event. */
- Status = Dptx_Run(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* A sink monitor must be connected at this point. See the polling or
+ * interrupt examples for how to wait for a connection event. */
+ Status = Dptx_Run(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -163,102 +163,102 @@ u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId)
* to implement configuration of the audio stream and, if needed, sending of
* the info frame.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note The user needs to implement the Dptx_ConfigureAudioSrc and
- * the Dptx_AudioSendInfoFrame functions to fulfill audio
- * initialization.
+ * @note The user needs to implement the Dptx_ConfigureAudioSrc and
+ * the Dptx_AudioSendInfoFrame functions to fulfill audio
+ * initialization.
*
*******************************************************************************/
static void Dptx_AudioInit(XDptx *InstancePtr)
{
- u32 Fs;
- u32 MAud;
- u32 NAud;
- u32 NumChs;
+ u32 Fs;
+ u32 MAud;
+ u32 NAud;
+ u32 NumChs;
- /* Disable audio in the DisplayPort TX. This will also flush the buffers
- * in the DisplayPort TX and set MUTE bit in VB-ID. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
- 0x0);
+ /* Disable audio in the DisplayPort TX. This will also flush the buffers
+ * in the DisplayPort TX and set MUTE bit in VB-ID. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
+ 0x0);
- /* Configure the audio source (the S/PDIF controller). It is up to the
- * user to implement this function. */
- Dptx_ConfigureAudioSrc(InstancePtr);
- /*******************/
+ /* Configure the audio source (the S/PDIF controller). It is up to the
+ * user to implement this function. */
+ Dptx_ConfigureAudioSrc(InstancePtr);
+ /*******************/
- /* Write audio info frame as per user requirements. This may be optional
- * for some systems. 8 writes are required to register
- * XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this
- * function. */
- Dptx_AudioSendInfoFrame(InstancePtr);
- /*******************/
+ /* Write audio info frame as per user requirements. This may be optional
+ * for some systems. 8 writes are required to register
+ * XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this
+ * function. */
+ Dptx_AudioSendInfoFrame(InstancePtr);
+ /*******************/
- Fs = 48; /* KHz (32 | 44.1 | 48) */
- if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) {
- MAud = 512 * Fs;
- }
- else if (InstancePtr->LinkConfig.LinkRate ==
- XDPTX_LINK_BW_SET_270GBPS) {
- MAud = 512 * Fs;
- }
- else if (InstancePtr->LinkConfig.LinkRate ==
- XDPTX_LINK_BW_SET_162GBPS) {
- MAud = 512 * Fs;
- }
+ Fs = 48; /* KHz (32 | 44.1 | 48) */
+ if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) {
+ MAud = 512 * Fs;
+ }
+ else if (InstancePtr->LinkConfig.LinkRate ==
+ XDPTX_LINK_BW_SET_270GBPS) {
+ MAud = 512 * Fs;
+ }
+ else if (InstancePtr->LinkConfig.LinkRate ==
+ XDPTX_LINK_BW_SET_162GBPS) {
+ MAud = 512 * Fs;
+ }
- /* Write the channel count. The value is (actual count - 1). */
- NumChs = 2;
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS,
- NumChs - 1);
+ /* Write the channel count. The value is (actual count - 1). */
+ NumChs = 2;
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS,
+ NumChs - 1);
- /* NAud = 540000 | 270000 | 162000 */
- NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000;
+ /* NAud = 540000 | 270000 | 162000 */
+ NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000;
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud);
- /* Enable audio in the DisplayPort TX. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
- 0x1);
+ /* Enable audio in the DisplayPort TX. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
+ 0x1);
}
/******************************************************************************/
/**
* This function needs to configure the audio source.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note The user needs to implement this. See XAPP1178 and the IP
- * documentation for reference.
+ * @note The user needs to implement this. See XAPP1178 and the IP
+ * documentation for reference.
*
*******************************************************************************/
static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr)
{
- xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n");
+ xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n");
}
/******************************************************************************/
/**
* This function needs to send an info frame as per user requirements.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note The user needs to implement this. See XAPP1178 and the IP
- * documentation for reference.
- * @note This may be optional for some systems.
- * @note A sequence of 8 writes are required to register
- * XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation
- * for reference.
+ * @note The user needs to implement this. See XAPP1178 and the IP
+ * documentation for reference.
+ * @note This may be optional for some systems.
+ * @note A sequence of 8 writes are required to register
+ * XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation
+ * for reference.
*
*******************************************************************************/
static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr)
{
- xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n");
+ xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n");
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c
index cc95080b..04788aea 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c
@@ -38,13 +38,13 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
- * @note The DisplayPort TX core does not work alone - video/audio
- * sources need to be set up in the system correctly, as well as
- * setting up the output path (for example, configuring the
- * hardware system with the DisplayPort TX core output to an FMC
- * card with DisplayPort output capabilities. Some platform
- * initialization will need to happen prior to calling XDptx driver
- * functions. See XAPP1178 as a reference.
+ * @note The DisplayPort TX core does not work alone - video/audio
+ * sources need to be set up in the system correctly, as well as
+ * setting up the output path (for example, configuring the
+ * hardware system with the DisplayPort TX core output to an FMC
+ * card with DisplayPort output capabilities. Some platform
+ * initialization will need to happen prior to calling XDptx driver
+ * functions. See XAPP1178 as a reference.
*
* <pre>
* MODIFICATION HISTORY:
@@ -73,32 +73,32 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr);
* This function will configure and establish a link with the receiver device,
* afterwards, a video stream will start to be sent over the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LaneCount is the number of lanes to use over the main link.
- * @param LinkRate is the link rate to use over the main link.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LaneCount is the number of lanes to use over the main link.
+ * @param LinkRate is the link rate to use over the main link.
*
* @return
- * - XST_SUCCESS if main link was successfully established.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if main link was successfully established.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 Dptx_Run(XDptx *InstancePtr)
{
- u32 Status;
+ u32 Status;
- /* Configure and establish a link. */
- Status = Dptx_StartLink(InstancePtr);
- if (Status == XST_SUCCESS) {
- /* Start the video stream. */
- Dptx_StartVideoStream(InstancePtr);
- } else {
- xil_printf("<-- Failed to establish/train the link.\n");
- return XST_FAILURE;
- }
+ /* Configure and establish a link. */
+ Status = Dptx_StartLink(InstancePtr);
+ if (Status == XST_SUCCESS) {
+ /* Start the video stream. */
+ Dptx_StartVideoStream(InstancePtr);
+ } else {
+ xil_printf("<-- Failed to establish/train the link.\n");
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -107,221 +107,221 @@ u32 Dptx_Run(XDptx *InstancePtr)
* configuration parameters will be retrieved based on the configuration
* to the DisplayPort TX core instance with the specified device ID.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param DeviceId is the unique device ID of the DisplayPort TX core
- * instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param DeviceId is the unique device ID of the DisplayPort TX core
+ * instance.
*
* @return
- * - XST_SUCCESS if the device configuration was found and obtained
- * and if the main link was successfully established.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the device configuration was found and obtained
+ * and if the main link was successfully established.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
{
- XDptx_Config *ConfigPtr;
- u32 Status;
+ XDptx_Config *ConfigPtr;
+ u32 Status;
- /* Obtain the device configuration for the DisplayPort TX core. */
- ConfigPtr = XDptx_LookupConfig(DeviceId);
- if (!ConfigPtr) {
- return XST_FAILURE;
- }
- /* Copy the device configuration into the InstancePtr's Config
- * structure. */
- XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
+ /* Obtain the device configuration for the DisplayPort TX core. */
+ ConfigPtr = XDptx_LookupConfig(DeviceId);
+ if (!ConfigPtr) {
+ return XST_FAILURE;
+ }
+ /* Copy the device configuration into the InstancePtr's Config
+ * structure. */
+ XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
- /* Initialize the DisplayPort TX core. */
- Status = XDptx_InitializeTx(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Initialize the DisplayPort TX core. */
+ Status = XDptx_InitializeTx(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will configure and establish a link with the receiver device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS the if main link was successfully established.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS the if main link was successfully established.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 Dptx_StartLink(XDptx *InstancePtr)
{
- u32 VsLevelTx;
- u32 PeLevelTx;
- u32 Status;
- u8 LaneCount;
- u8 LinkRate;
+ u32 VsLevelTx;
+ u32 PeLevelTx;
+ u32 Status;
+ u8 LaneCount;
+ u8 LinkRate;
- /* Obtain the capabilities of the RX device by reading the monitor's
- * DPCD. */
- Status = XDptx_GetRxCapabilities(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Obtain the capabilities of the RX device by reading the monitor's
+ * DPCD. */
+ Status = XDptx_GetRxCapabilities(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
#if (TRAIN_USE_MAX_LINK == 1)
- LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
- LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
+ LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
+ LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
#else
- LaneCount = TRAIN_USE_LANE_COUNT;
- LinkRate = TRAIN_USE_LINK_RATE;
+ LaneCount = TRAIN_USE_LANE_COUNT;
+ LinkRate = TRAIN_USE_LINK_RATE;
#endif
- /* Check if the link is already trained */
- Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
- if (Status == XST_SUCCESS) {
- xil_printf("-> Link is already trained on %d lanes.\n",
- LaneCount);
- if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_LINK_BW_SET) == LinkRate) {
- xil_printf("-> Link needs to be re-trained %d Mbps.\n",
- (270 * LinkRate));
- }
- else {
- xil_printf("-> Link is already trained on %d Mbps.\n",
- (270 * LinkRate));
- return XST_SUCCESS;
- }
- }
- else if (Status == XST_FAILURE) {
- xil_printf("-> Needs training.\n");
- }
- else {
- /* Either a connection does not exist or the supplied lane count
- * is invalid. */
- xil_printf("-> Error checking link status.\n");
- return XST_FAILURE;
- }
+ /* Check if the link is already trained */
+ Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
+ if (Status == XST_SUCCESS) {
+ xil_printf("-> Link is already trained on %d lanes.\n",
+ LaneCount);
+ if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_LINK_BW_SET) == LinkRate) {
+ xil_printf("-> Link needs to be re-trained %d Mbps.\n",
+ (270 * LinkRate));
+ }
+ else {
+ xil_printf("-> Link is already trained at %d Mbps.\n",
+ (270 * LinkRate));
+ return XST_SUCCESS;
+ }
+ }
+ else if (Status == XST_FAILURE) {
+ xil_printf("-> Needs training.\n");
+ }
+ else {
+ /* Either a connection does not exist or the supplied lane count
+ * is invalid. */
+ xil_printf("-> Error checking link status.\n");
+ return XST_FAILURE;
+ }
- XDptx_SetEnhancedFrameMode(InstancePtr, 1);
- XDptx_SetDownspread(InstancePtr, 0);
+ XDptx_SetEnhancedFrameMode(InstancePtr, 1);
+ XDptx_SetDownspread(InstancePtr, 0);
#if (TRAIN_USE_MAX_LINK == 1)
- /* Configure the main link based on the maximum common capabilities of
- * the DisplayPort TX core and the receiver device. */
- Status = XDptx_CfgMainLinkMax(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Configure the main link based on the maximum common capabilities of
+ * the DisplayPort TX core and the receiver device. */
+ Status = XDptx_CfgMainLinkMax(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
#else
- XDptx_SetLinkRate(InstancePtr, LinkRate);
- XDptx_SetLaneCount(InstancePtr, LaneCount);
+ XDptx_SetLinkRate(InstancePtr, LinkRate);
+ XDptx_SetLaneCount(InstancePtr, LaneCount);
#endif
- /* Train the link. */
- xil_printf("******************************************\n");
- Status = XDptx_EstablishLink(InstancePtr);
- if (Status != XST_SUCCESS) {
- xil_printf("!!! Training failed !!!\n");
- xil_printf("******************************************\n");
- return XST_FAILURE;
- }
+ /* Train the link. */
+ xil_printf("******************************************\n");
+ Status = XDptx_EstablishLink(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ xil_printf("!!! Training failed !!!\n");
+ xil_printf("******************************************\n");
+ return XST_FAILURE;
+ }
- VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
- PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_POSTCURSOR_LANE_0);
- xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
- InstancePtr->LinkConfig.LinkRate,
- InstancePtr->LinkConfig.LaneCount);
- xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
- InstancePtr->LinkConfig.VsLevel, VsLevelTx,
- InstancePtr->LinkConfig.PeLevel, PeLevelTx);
- xil_printf("******************************************\n");
+ VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
+ PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_POSTCURSOR_LANE_0);
+ xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
+ InstancePtr->LinkConfig.LinkRate,
+ InstancePtr->LinkConfig.LaneCount);
+ xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
+ InstancePtr->LinkConfig.VsLevel, VsLevelTx,
+ InstancePtr->LinkConfig.PeLevel, PeLevelTx);
+ xil_printf("******************************************\n");
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will start sending a video stream over the main link. The
* settings to be used are as follows:
- * - 8 bits per color.
- * - Video timing and screen resolution used:
- * - The connected monitor's preferred timing is used to determine the
- * video resolution (and associated timings) for the stream.
+ * - 8 bits per color.
+ * - Video timing and screen resolution used:
+ * - The connected monitor's preferred timing is used to determine the
+ * video resolution (and associated timings) for the stream.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note Dptx_ConfigureStreamSrc is intentionally left for the user to
- * implement since configuration of the stream source is
- * application-specific.
- * @note The Extended Display Identification Data (EDID) is read in order
- * to obtain the video resolution and timings. If this read fails,
- * a resolution of 640x480 is used at a refresh rate of 60Hz.
+ * @note Dptx_ConfigureStreamSrc is intentionally left for the user to
+ * implement since configuration of the stream source is
+ * application-specific.
+ * @note The Extended Display Identification Data (EDID) is read in order
+ * to obtain the video resolution and timings. If this read fails,
+ * a resolution of 640x480 is used at a refresh rate of 60Hz.
*
*******************************************************************************/
static void Dptx_StartVideoStream(XDptx *InstancePtr)
{
- u32 Status;
- u8 AuxData[1];
+ u32 Status;
+ u8 AuxData[1];
- /* Set the bits per color. If not set, the default is 6. */
- XDptx_CfgMsaSetBpc(InstancePtr, 8);
+ /* Set the bits per color. If not set, the default is 6. */
+ XDptx_CfgMsaSetBpc(InstancePtr, 8);
/* Choose a method for selecting the video mode. There are 3 ways to do this:
* 1) Use the preferred timing from the monitor's EDID:
- * XDptx_GetEdid(InstancePtr);
- * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
+ * XDptx_GetEdid(InstancePtr);
+ * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
*
* 2) Use a standard video timing mode (see mode_table.h):
- * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
+ * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
*
* 3) Use a custom configuration for the main stream attributes (MSA):
- * XDptx_MainStreamAttributes MsaConfigCustom;
- * MsaConfigCustom.MVid = 108000;
- * MsaConfigCustom.HSyncPolarity = 0;
- * MsaConfigCustom.VSyncPolarity = 0;
- * MsaConfigCustom.HSyncPulseWidth = 112;
- * MsaConfigCustom.VSyncPulseWidth = 3;
- * MsaConfigCustom.HResolution = 1280;
- * MsaConfigCustom.VResolution = 1024;
- * MsaConfigCustom.VBackPorch = 38;
- * MsaConfigCustom.VFrontPorch = 1;
- * MsaConfigCustom.HBackPorch = 248;
- * MsaConfigCustom.HFrontPorch = 48;
- * XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1);
+ * XDptx_MainStreamAttributes MsaConfigCustom;
+ * MsaConfigCustom.MVid = 108000;
+ * MsaConfigCustom.HSyncPolarity = 0;
+ * MsaConfigCustom.VSyncPolarity = 0;
+ * MsaConfigCustom.HSyncPulseWidth = 112;
+ * MsaConfigCustom.VSyncPulseWidth = 3;
+ * MsaConfigCustom.HResolution = 1280;
+ * MsaConfigCustom.VResolution = 1024;
+ * MsaConfigCustom.VBackPorch = 38;
+ * MsaConfigCustom.VFrontPorch = 1;
+ * MsaConfigCustom.HBackPorch = 248;
+ * MsaConfigCustom.HFrontPorch = 48;
+ * XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1);
*/
- Status = XDptx_GetEdid(InstancePtr);
- if (Status == XST_SUCCESS) {
- XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
- }
- else {
- XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
- XDPTX_VM_640x480_60_P);
- }
+ Status = XDptx_GetEdid(InstancePtr);
+ if (Status == XST_SUCCESS) {
+ XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
+ }
+ else {
+ XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
+ XDPTX_VM_640x480_60_P);
+ }
- /* Disable MST for this example. */
- AuxData[0] = 0;
- XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0);
+ /* Disable MST for this example. */
+ AuxData[0] = 0;
+ XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 0x1, AuxData);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0);
- /* Disable main stream to force sending of IDLE patterns. */
- XDptx_DisableMainLink(InstancePtr);
+ /* Disable main stream to force sending of IDLE patterns. */
+ XDptx_DisableMainLink(InstancePtr);
- /* Reset the transmitter. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
- XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
+ /* Reset the transmitter. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
+ XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
- /* Configure video stream source or generator here. This function needs
- * to be implemented in order for video to be displayed and is hardware
- * system specific. It is up to the user to implement this function. */
- Dptx_ConfigureStreamSrc(InstancePtr);
- /*********************************/
+ /* Configure video stream source or generator here. This function needs
+ * to be implemented in order for video to be displayed and is hardware
+ * system specific. It is up to the user to implement this function. */
+ Dptx_ConfigureStreamSrc(InstancePtr);
+ /*********************************/
- XDptx_EnableMainLink(InstancePtr);
+ XDptx_EnableMainLink(InstancePtr);
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h
index ea1b4c12..924b939e 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h
@@ -38,13 +38,13 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
- * @note The DisplayPort TX core does not work alone - video/audio
- * sources need to be set up in the system correctly, as well as
- * setting up the output path (for example, configuring the
- * hardware system with the DisplayPort TX core output to an FMC
- * card with DisplayPort output capabilities. Some platform
- * initialization will need to happen prior to calling XDptx driver
- * functions. See XAPP1178 as a reference.
+ * @note The DisplayPort TX core does not work alone - video/audio
+ * sources need to be set up in the system correctly, as well as
+ * setting up the output path (for example, configuring the
+ * hardware system with the DisplayPort TX core output to an FMC
+ * card with DisplayPort output capabilities. Some platform
+ * initialization will need to happen prior to calling XDptx driver
+ * functions. See XAPP1178 as a reference.
*
* <pre>
* MODIFICATION HISTORY:
@@ -70,7 +70,7 @@
/**************************** Constant Definitions ****************************/
/* The unique device ID of the DisplayPort TX core instance to be used with the
- * examples.*/
+ * examples. */
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/* If set to 1, the link training process will continue training despite failing
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
index 455bedc4..09cc5af1 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
@@ -38,17 +38,17 @@
* Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is
* turned on/off), the main link will be trained.
*
- * @note This example requires an interrupt controller connected to the
- * processor and the DisplayPort TX core in the system.
- * @note For this example to display output, the user will need to
- * implement initialization of the system (Dptx_PlatformInit) and,
- * after training is complete, implement configuration of the video
- * stream source in order to provide the DisplayPort core with
- * input (Dptx_ConfigureStreamSrc - called in
- * xdptx_example_common.c). See XAPP1178 for reference.
- * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
- * declared extern in xdptx_example_common.h and are left up to the
- * user to implement.
+ * @note This example requires an interrupt controller connected to the
+ * processor and the DisplayPort TX core in the system.
+ * @note For this example to display output, the user will need to
+ * implement initialization of the system (Dptx_PlatformInit) and,
+ * after training is complete, implement configuration of the video
+ * stream source in order to provide the DisplayPort core with
+ * input (Dptx_ConfigureStreamSrc - called in
+ * xdptx_example_common.c). See XAPP1178 for reference.
+ * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
+ * declared extern in xdptx_example_common.h and are left up to the
+ * user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@@ -76,11 +76,11 @@
/* The following constants map to the XPAR parameters created in the
* xparameters.h file. */
#ifdef XPAR_INTC_0_DEVICE_ID
-#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
-#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
+#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
+#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#else
-#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
-#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
+#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#endif /* XPAR_INTC_0_DEVICE_ID */
/****************************** Type Definitions ******************************/
@@ -88,27 +88,27 @@
/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system,
* different drivers and associated types will be used. */
#ifdef XPAR_INTC_0_DEVICE_ID
-#define INTC XIntc
-#define INTC_HANDLER XIntc_InterruptHandler
+#define INTC XIntc
+#define INTC_HANDLER XIntc_InterruptHandler
#else
-#define INTC XScuGic
-#define INTC_HANDLER XScuGic_InterruptHandler
+#define INTC XScuGic
+#define INTC_HANDLER XScuGic_InterruptHandler
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Function Prototypes *****************************/
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
- u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
- XDptx_HpdPulseHandler HpdPulseHandler);
+ u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
+ XDptx_HpdPulseHandler HpdPulseHandler);
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
- u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
- XDptx_HpdPulseHandler HpdPulseHandler);
+ u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
+ XDptx_HpdPulseHandler HpdPulseHandler);
static void Dptx_HpdEventHandler(void *InstancePtr);
static void Dptx_HpdPulseHandler(void *InstancePtr);
/**************************** Variable Definitions ****************************/
-INTC IntcInstance; /* The interrupt controller instance. */
+INTC IntcInstance; /* The interrupt controller instance. */
/**************************** Function Definitions ****************************/
@@ -120,25 +120,25 @@ INTC IntcInstance; /* The interrupt controller instance. */
* training will commence (if needed) and a video stream will start being sent
* over the main link.
*
- * @param None.
+ * @param None.
*
* @return
- * - XST_FAILURE if the interrupt example was unsuccessful - system
- * setup failed.
+ * - XST_FAILURE if the interrupt example was unsuccessful - system
+ * setup failed.
*
- * @note Unless setup failed, main will never return since
- * DptxIntrExample is blocking (it is waiting on interrupts for
- * Hot-Plug-Detect (HPD) events.
+ * @note Unless setup failed, main will never return since
+ * DptxIntrExample is blocking (it is waiting on interrupts for
+ * Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
- /* Run the XDptx interrupt example. */
- Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
- &IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
- &Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
+ /* Run the XDptx interrupt example. */
+ Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
+ &IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
+ &Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
- return XST_FAILURE;
+ return XST_FAILURE;
}
/******************************************************************************/
@@ -147,59 +147,59 @@ int main(void)
* function will set up the system with interrupts and set up the Hot-Plug-Event
* (HPD) handlers.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param DeviceId is the unique device ID of the DisplayPort TX core
- * instance.
- * @param IntcPtr is a pointer to the interrupt instance.
- * @param IntrId is the unique device ID of the interrupt controller.
- * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
- * the interrupt controller.
- * @param HpdEventHandler is a pointer to the handler called when an HPD
- * event occurs.
- * @param HpdPulseHandler is a pointer to the handler called when an HPD
- * pulse occurs.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param DeviceId is the unique device ID of the DisplayPort TX core
+ * instance.
+ * @param IntcPtr is a pointer to the interrupt instance.
+ * @param IntrId is the unique device ID of the interrupt controller.
+ * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
+ * the interrupt controller.
+ * @param HpdEventHandler is a pointer to the handler called when an HPD
+ * event occurs.
+ * @param HpdPulseHandler is a pointer to the handler called when an HPD
+ * pulse occurs.
*
* @return
- * - XST_FAILURE if the system setup failed.
- * - XST_SUCCESS should never return since this function, if setup
- * was successful, is blocking.
+ * - XST_FAILURE if the system setup failed.
+ * - XST_SUCCESS should never return since this function, if setup
+ * was successful, is blocking.
*
- * @note If system setup was successful, this function is blocking in
- * order to illustrate interrupt handling taking place for HPD
- * events.
+ * @note If system setup was successful, this function is blocking in
+ * order to illustrate interrupt handling taking place for HPD
+ * events.
*
*******************************************************************************/
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
- u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
- XDptx_HpdPulseHandler HpdPulseHandler)
+ u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
+ XDptx_HpdPulseHandler HpdPulseHandler)
{
- u32 Status;
+ u32 Status;
- /* Do platform initialization here. This is hardware system specific -
- * it is up to the user to implement this function. */
- Dptx_PlatformInit();
- /******************/
+ /* Do platform initialization here. This is hardware system specific -
+ * it is up to the user to implement this function. */
+ Dptx_PlatformInit();
+ /******************/
- Status = Dptx_SetupExample(InstancePtr, DeviceId);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = Dptx_SetupExample(InstancePtr, DeviceId);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
- XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
+ XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
+ XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
- /* Setup interrupt handling in the system. */
- Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
- DpIntrId, HpdEventHandler, HpdPulseHandler);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Setup interrupt handling in the system. */
+ Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
+ DpIntrId, HpdEventHandler, HpdPulseHandler);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Do not return in order to allow interrupt handling to run. HPD events
- * (connect, disconnect, and pulse) will be detected and handled. */
- while (1);
+ /* Do not return in order to allow interrupt handling to run. HPD events
+ * (connect, disconnect, and pulse) will be detected and handled. */
+ while (1);
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -210,88 +210,88 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
* to the processor. The user should modify this function to fit the
* application.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param IntcPtr is a pointer to the interrupt instance.
- * @param IntrId is the unique device ID of the interrupt controller.
- * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
- * the interrupt controller.
- * @param HpdEventHandler is a pointer to the handler called when an HPD
- * event occurs.
- * @param HpdPulseHandler is a pointer to the handler called when an HPD
- * pulse occurs.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param IntcPtr is a pointer to the interrupt instance.
+ * @param IntrId is the unique device ID of the interrupt controller.
+ * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
+ * the interrupt controller.
+ * @param HpdEventHandler is a pointer to the handler called when an HPD
+ * event occurs.
+ * @param HpdPulseHandler is a pointer to the handler called when an HPD
+ * pulse occurs.
*
* @return
- * - XST_SUCCESS if the interrupt system was successfully set up.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the interrupt system was successfully set up.
+ * - XST_FAILURE otherwise.
*
- * @note An interrupt controller must be present in the system, connected
- * to the processor and the DisplayPort TX core.
+ * @note An interrupt controller must be present in the system, connected
+ * to the processor and the DisplayPort TX core.
*
*******************************************************************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
- u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
- XDptx_HpdPulseHandler HpdPulseHandler)
+ u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
+ XDptx_HpdPulseHandler HpdPulseHandler)
{
- u32 Status;
+ u32 Status;
- /* Set the HPD interrupt handlers. */
- XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
- XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
+ /* Set the HPD interrupt handlers. */
+ XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
+ XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
- /* Initialize interrupt controller driver. */
+ /* Initialize interrupt controller driver. */
#ifdef XPAR_INTC_0_DEVICE_ID
- Status = XIntc_Initialize(IntcPtr, IntrId);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = XIntc_Initialize(IntcPtr, IntrId);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
#else
- XScuGic_Config *IntcConfig;
+ XScuGic_Config *IntcConfig;
- IntcConfig = XScuGic_LookupConfig(IntrId);
- Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
- IntcConfig->CpuBaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
+ IntcConfig = XScuGic_LookupConfig(IntrId);
+ Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
+ IntcConfig->CpuBaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
#endif /* XPAR_INTC_0_DEVICE_ID */
- /* Connect the device driver handler that will be called when an
- * interrupt for the device occurs, the handler defined above performs
- * the specific interrupt processing for the device. */
+ /* Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device. */
#ifdef XPAR_INTC_0_DEVICE_ID
- Status = XIntc_Connect(IntcPtr, DpIntrId,
- (XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
+ Status = XIntc_Connect(IntcPtr, DpIntrId,
+ (XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#else
- Status = XScuGic_Connect(IntcPtr, DpIntrId,
- (Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
+ Status = XScuGic_Connect(IntcPtr, DpIntrId,
+ (Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#endif /* XPAR_INTC_0_DEVICE_ID */
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Start the interrupt controller. */
+ /* Start the interrupt controller. */
#ifdef XPAR_INTC_0_DEVICE_ID
- Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- XIntc_Enable(IntcPtr, DpIntrId);
+ Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ XIntc_Enable(IntcPtr, DpIntrId);
#else
- XScuGic_Enable(IntcPtr, DpIntrId);
+ XScuGic_Enable(IntcPtr, DpIntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */
- /* Initialize the exception table. */
- Xil_ExceptionInit();
+ /* Initialize the exception table. */
+ Xil_ExceptionInit();
- /* Register the interrupt controller handler with the exception table. */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
+ /* Register the interrupt controller handler with the exception table. */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
- /* Enable exceptions. */
- Xil_ExceptionEnable();
+ /* Enable exceptions. */
+ Xil_ExceptionEnable();
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -301,26 +301,26 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
* core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note Use the XDptx_SetHpdEventHandler driver function to set this
- * function as the handler for HPD pulses.
+ * @note Use the XDptx_SetHpdEventHandler driver function to set this
+ * function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdEventHandler(void *InstancePtr)
{
- XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
+ XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
- if (XDptx_IsConnected(XDptx_InstancePtr)) {
- xil_printf("+===> HPD connection event detected.\n");
+ if (XDptx_IsConnected(XDptx_InstancePtr)) {
+ xil_printf("+===> HPD connection event detected.\n");
- Dptx_Run(XDptx_InstancePtr);
- }
- else {
- xil_printf("+===> HPD disconnection event detected.\n\n");
- }
+ Dptx_Run(XDptx_InstancePtr);
+ }
+ else {
+ xil_printf("+===> HPD disconnection event detected.\n\n");
+ }
}
/******************************************************************************/
@@ -330,19 +330,19 @@ static void Dptx_HpdEventHandler(void *InstancePtr)
* of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note Use the XDptx_SetHpdPulseHandler driver function to set this
- * function as the handler for HPD pulses.
+ * @note Use the XDptx_SetHpdPulseHandler driver function to set this
+ * function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdPulseHandler(void *InstancePtr)
{
- XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
+ XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
- xil_printf("===> HPD pulse detected.\n");
+ xil_printf("===> HPD pulse detected.\n");
- Dptx_Run(XDptx_InstancePtr);
+ Dptx_Run(XDptx_InstancePtr);
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
index 123f1b3e..cd3e6194 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
@@ -38,15 +38,15 @@
* polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/
* unplugged or the monitor is turned on/off), the main link will be trained.
*
- * @note For this example to display output, the user will need to
- * implement initialization of the system (Dptx_PlatformInit) and,
- * after training is complete, implement configuration of the video
- * stream source in order to provide the DisplayPort core with
- * input (Dptx_ConfigureStreamSrc - called in
- * xdptx_example_common.c). See XAPP1178 for reference.
- * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
- * declared extern in xdptx_example_common.h and are left up to the
- * user to implement.
+ * @note For this example to display output, the user will need to
+ * implement initialization of the system (Dptx_PlatformInit) and,
+ * after training is complete, implement configuration of the video
+ * stream source in order to provide the DisplayPort core with
+ * input (Dptx_ConfigureStreamSrc - called in
+ * xdptx_example_common.c). See XAPP1178 for reference.
+ * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
+ * declared extern in xdptx_example_common.h and are left up to the
+ * user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@@ -73,23 +73,23 @@ static void Dptx_HpdPoll(XDptx *InstancePtr);
/**
* This function is the main function of the XDptx polling example.
*
- * @param None.
+ * @param None.
*
* @return
- * - XST_FAILURE if the polling example was unsuccessful - system
- * setup failed.
+ * - XST_FAILURE if the polling example was unsuccessful - system
+ * setup failed.
*
- * @note Unless setup failed, main will never return since
- * Dptx_PollExample is blocking (it is continuously polling for
- * Hot-Plug-Detect (HPD) events.
+ * @note Unless setup failed, main will never return since
+ * Dptx_PollExample is blocking (it is continuously polling for
+ * Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
- /* Run the XDptx polling example. */
- Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
+ /* Run the XDptx polling example. */
+ Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
- return XST_FAILURE;
+ return XST_FAILURE;
}
/******************************************************************************/
@@ -100,42 +100,42 @@ int main(void)
* a connection event or a pulse is detected, link training will commence (if
* needed) and a video stream will start being sent over the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param DeviceId is the unique device ID of the DisplayPort TX core
- * instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param DeviceId is the unique device ID of the DisplayPort TX core
+ * instance.
*
* @return
- * - XST_FAILURE if the system setup failed.
- * - XST_SUCCESS should never return since this function, if setup
- * was successful, is blocking.
+ * - XST_FAILURE if the system setup failed.
+ * - XST_SUCCESS should never return since this function, if setup
+ * was successful, is blocking.
*
- * @note If system setup was successful, this function is blocking in
- * order to illustrate polling taking place for HPD events.
+ * @note If system setup was successful, this function is blocking in
+ * order to illustrate polling taking place for HPD events.
*
*******************************************************************************/
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
{
- u32 Status;
+ u32 Status;
- /* Do platform initialization here. This is hardware system specific -
- * it is up to the user to implement this function. */
- Dptx_PlatformInit();
- /******************/
+ /* Do platform initialization here. This is hardware system specific -
+ * it is up to the user to implement this function. */
+ Dptx_PlatformInit();
+ /******************/
- Status = Dptx_SetupExample(InstancePtr, DeviceId);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = Dptx_SetupExample(InstancePtr, DeviceId);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
- XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
+ XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
+ XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
- /* Continuously poll for HPD events. */
- while (1) {
- Dptx_HpdPoll(InstancePtr);
- }
+ /* Continuously poll for HPD events. */
+ while (1) {
+ Dptx_HpdPoll(InstancePtr);
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -145,56 +145,56 @@ u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
* connection or pulse event is detected, link training will begin (if required)
* and a video stream will be initiated.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static void Dptx_HpdPoll(XDptx *InstancePtr)
{
- u32 InterruptSignalState;
- u32 InterruptStatus;
- u32 HpdState;
- u32 HpdEvent;
- u32 HpdPulseDetected;
- u32 HpdDuration;
+ u32 InterruptSignalState;
+ u32 InterruptStatus;
+ u32 HpdState;
+ u32 HpdEvent;
+ u32 HpdPulseDetected;
+ u32 HpdDuration;
- /* Read interrupt registers. */
- InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_SIG_STATE);
- InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_STATUS);
+ /* Read interrupt registers. */
+ InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_SIG_STATE);
+ InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_STATUS);
- /* Check for HPD events. */
- HpdState = InterruptSignalState &
- XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
- HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
- HpdPulseDetected = InterruptStatus &
- XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
- if (HpdPulseDetected) {
- HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_HPD_DURATION);
- }
+ /* Check for HPD events. */
+ HpdState = InterruptSignalState &
+ XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
+ HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
+ HpdPulseDetected = InterruptStatus &
+ XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
+ if (HpdPulseDetected) {
+ HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_HPD_DURATION);
+ }
- /* HPD event handling. */
- if (HpdState && HpdEvent) {
- xil_printf("+===> HPD connection event detected.\n");
+ /* HPD event handling. */
+ if (HpdState && HpdEvent) {
+ xil_printf("+===> HPD connection event detected.\n");
- /* Initiate link training. */
- Dptx_Run(InstancePtr);
- }
- else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
- xil_printf("===> HPD pulse detected.\n");
+ /* Initiate link training. */
+ Dptx_Run(InstancePtr);
+ }
+ else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
+ xil_printf("===> HPD pulse detected.\n");
- /* Re-train if needed. */
- Dptx_Run(InstancePtr);
- }
- else if (!HpdState && HpdEvent) {
- xil_printf("+===> HPD disconnection event detected.\n\n");
+ /* Re-train if needed. */
+ Dptx_Run(InstancePtr);
+ }
+ else if (!HpdState && HpdEvent) {
+ xil_printf("+===> HPD disconnection event detected.\n\n");
- /* Disable main link. */
- XDptx_DisableMainLink(InstancePtr);
- }
+ /* Disable main link. */
+ XDptx_DisableMainLink(InstancePtr);
+ }
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c
index 3235746c..4f231df0 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c
@@ -38,7 +38,7 @@
* the DisplayPort TX core that will compare many of the DisplayPort TX core's
* registers against their default reset values.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -62,32 +62,32 @@ u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId);
int main(void)
{
- u32 Status;
+ u32 Status;
- Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID);
- if (Status != XST_SUCCESS) {
- xil_printf("XDptx_SelfTest failed, check register values.\n");
- return XST_FAILURE;
- }
- xil_printf("XDptx_SelfTest passed.\n");
- return Status;
+ Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID);
+ if (Status != XST_SUCCESS) {
+ xil_printf("XDptx_SelfTest failed, check register values.\n");
+ return XST_FAILURE;
+ }
+ xil_printf("XDptx_SelfTest passed.\n");
+ return Status;
}
u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId)
{
- u32 Status;
- XDptx_Config *ConfigPtr;
+ u32 Status;
+ XDptx_Config *ConfigPtr;
- /* Obtain the device configuration for the DisplayPort TX core. */
- ConfigPtr = XDptx_LookupConfig(DeviceId);
- if (!ConfigPtr) {
- return XST_FAILURE;
- }
- /* Copy the device configuration into the InstancePtr's Config
- * structure. */
- XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
+ /* Obtain the device configuration for the DisplayPort TX core. */
+ ConfigPtr = XDptx_LookupConfig(DeviceId);
+ if (!ConfigPtr) {
+ return XST_FAILURE;
+ }
+ /* Copy the device configuration into the InstancePtr's Config
+ * structure. */
+ XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
- /* Run the self test. */
- Status = XDptx_SelfTest(InstancePtr);
- return Status;
+ /* Run the self test. */
+ Status = XDptx_SelfTest(InstancePtr);
+ return Status;
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
index f64577da..a311465a 100644
--- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
+++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
@@ -40,16 +40,16 @@
* the user may override the default MicroBlaze sleep with a function that will
* use the hardware timer.
*
- * @note This example requires an AXI timer in the system.
- * @note For this example to display output, the user will need to
- * implement initialization of the system (Dptx_PlatformInit) and,
- * after training is complete, implement configuration of the video
- * stream source in order to provide the DisplayPort core with
- * input (Dptx_ConfigureStreamSrc - called in
- * xdptx_example_common.c). See XAPP1178 for reference.
- * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
- * declared extern in xdptx_example_common.h and are left up to the
- * user to implement.
+ * @note This example requires an AXI timer in the system.
+ * @note For this example to display output, the user will need to
+ * implement initialization of the system (Dptx_PlatformInit) and,
+ * after training is complete, implement configuration of the video
+ * stream source in order to provide the DisplayPort core with
+ * input (Dptx_ConfigureStreamSrc - called in
+ * xdptx_example_common.c). See XAPP1178 for reference.
+ * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
+ * declared extern in xdptx_example_common.h and are left up to the
+ * user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@@ -69,12 +69,12 @@
/**************************** Function Prototypes *****************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
- XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
+ XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds);
/*************************** Variable Declarations ****************************/
-XTmrCtr TimerCounterInst; /* The timer counter instance. */
+XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**************************** Function Definitions ****************************/
@@ -82,27 +82,27 @@ XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**
* This function is the main function of the XDptx timer example.
*
- * @param None.
+ * @param None.
*
* @return
- * - XST_SUCCESS if the timer example finished successfully.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the timer example finished successfully.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
int main(void)
{
- int Status;
+ u32 Status;
- /* Run the XDptx timer example. */
- Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
- &TimerCounterInst, &Dptx_CustomWaitUs);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Run the XDptx timer example. */
+ Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
+ &TimerCounterInst, &Dptx_CustomWaitUs);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -112,54 +112,54 @@ int main(void)
* successful, link training will commence and a video stream will start being
* sent over the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param DeviceId is the unique device ID of the DisplayPort TX core
- * instance.
- * @param TimerCounterPtr is a pointer to the timer instance.
- * @param UserSleepFunc is a pointer to the custom handler for sleep.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param DeviceId is the unique device ID of the DisplayPort TX core
+ * instance.
+ * @param TimerCounterPtr is a pointer to the timer instance.
+ * @param UserSleepFunc is a pointer to the custom handler for sleep.
*
* @return
- * - XST_SUCCESS if the system was set up correctly and link
- * training was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the system was set up correctly and link
+ * training was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
- XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
+ XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
{
- u32 Status;
+ u32 Status;
- /* Do platform initialization here. This is hardware system specific -
- * it is up to the user to implement this function. */
- Dptx_PlatformInit();
- /*******************/
+ /* Do platform initialization here. This is hardware system specific -
+ * it is up to the user to implement this function. */
+ Dptx_PlatformInit();
+ /*******************/
- /* Set a custom timer handler for improved delay accuracy on MicroBlaze
- * systems since the driver does not assume/have a dependency on the
- * system having a timer in the FPGA.
- * Note: This only has an affect for MicroBlaze systems since the Zynq
- * ARM SoC contains a timer, which is used when the driver calls the
- * delay function. */
- XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
+ /* Set a custom timer handler for improved delay accuracy on MicroBlaze
+ * systems since the driver does not assume/have a dependency on the
+ * system having a timer in the FPGA.
+ * Note: This only has an affect for MicroBlaze systems since the Zynq
+ * ARM SoC contains a timer, which is used when the driver calls the
+ * delay function. */
+ XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
- Status = Dptx_SetupExample(InstancePtr, DeviceId);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = Dptx_SetupExample(InstancePtr, DeviceId);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
- XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
+ XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
+ XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
- /* A sink monitor must be connected at this point. See the polling or
- * interrupt examples for how to wait for a connection event. */
- Status = Dptx_Run(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* A sink monitor must be connected at this point. See the polling or
+ * interrupt examples for how to wait for a connection event. */
+ Status = Dptx_Run(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -171,28 +171,28 @@ u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
* hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is
* used - XDptx_WaitUs will ignore this custom timer handler.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note Use the XDptx_SetUserTimerHandler driver function to set this
- * function as the handler for when the XDptx_WaitUs driver
- * function is called.
+ * @note Use the XDptx_SetUserTimerHandler driver function to set this
+ * function as the handler for when the XDptx_WaitUs driver
+ * function is called.
*
*******************************************************************************/
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
{
- XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
- u32 TimerVal;
+ XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
+ u32 TimerVal;
- XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0);
+ XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0);
- /* Wait specified number of useconds. */
- do {
- TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
- }
- while (TimerVal < (MicroSeconds *
- (XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
+ /* Wait specified number of useconds. */
+ do {
+ TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
+ }
+ while (TimerVal < (MicroSeconds *
+ (XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
- XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
+ XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
index 421578c2..a63d6017 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
@@ -38,7 +38,7 @@
* to all of the DisplayPort TX core's functionality. See xdptx.h for a detailed
* description of the driver.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -82,22 +82,22 @@
* during the link training process.
*/
typedef enum {
- XDPTX_TS_CLOCK_RECOVERY,
- XDPTX_TS_CHANNEL_EQUALIZATION,
- XDPTX_TS_ADJUST_LINK_RATE,
- XDPTX_TS_ADJUST_LANE_COUNT,
- XDPTX_TS_FAILURE,
- XDPTX_TS_SUCCESS
+ XDPTX_TS_CLOCK_RECOVERY,
+ XDPTX_TS_CHANNEL_EQUALIZATION,
+ XDPTX_TS_ADJUST_LINK_RATE,
+ XDPTX_TS_ADJUST_LANE_COUNT,
+ XDPTX_TS_FAILURE,
+ XDPTX_TS_SUCCESS
} XDptx_TrainingState;
/**
* This typedef describes an AUX transaction.
*/
typedef struct {
- u16 CmdCode;
- u8 NumBytes;
- u32 Address;
- u8 *Data;
+ u16 CmdCode;
+ u8 NumBytes;
+ u32 Address;
+ u8 *Data;
} XDptx_AuxTransaction;
/**************************** Function Prototypes *****************************/
@@ -106,11 +106,11 @@ typedef struct {
static u32 XDptx_RunTraining(XDptx *InstancePtr);
static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr);
static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
- XDptx *InstancePtr, u32 MaxIterations);
+ XDptx *InstancePtr, u32 MaxIterations);
static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(
- XDptx *InstancePtr);
+ XDptx *InstancePtr);
static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount(
- XDptx *InstancePtr);
+ XDptx *InstancePtr);
static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr);
static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount);
static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount);
@@ -118,13 +118,13 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr);
static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr);
static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern);
static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr,
- XDptx_TrainingState TrainingState);
+ XDptx_TrainingState TrainingState);
/* AUX transaction functions. */
static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
- u32 NumBytes, u8 *Data);
+ u32 NumBytes, u8 *Data);
static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request);
static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
- XDptx_AuxTransaction *Request);
+ XDptx_AuxTransaction *Request);
static u32 XDptx_AuxWaitReply(XDptx *InstancePtr);
static u32 XDptx_AuxWaitReady(XDptx *InstancePtr);
/* Miscellaneous functions. */
@@ -137,77 +137,77 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr);
/**
* This function prepares the DisplayPort TX core for use.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the DisplayPort TX core was successfully
- * initialized.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the DisplayPort TX core was successfully
+ * initialized.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_InitializeTx(XDptx *InstancePtr)
{
- u32 Status;
- u32 RegVal;
- XDptx_Config *Config = &InstancePtr->Config;
+ u32 Status;
+ u32 RegVal;
+ XDptx_Config *Config = &InstancePtr->Config;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /* Place the PHY (and GTTXRESET) into reset. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
- XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK);
+ /* Place the PHY (and GTTXRESET) into reset. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
+ XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK);
- /* Disable the DisplayPort TX core. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 0);
+ /* Disable the DisplayPort TX core. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 0);
- /* Set the clock divider. */
- RegVal = (XDptx_ReadReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER) &
- ~XDPTX_AUX_CLK_DIVIDER_VAL_MASK) |
- (Config->SAxiClkHz / 1000000);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal);
+ /* Set the clock divider. */
+ RegVal = (XDptx_ReadReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER) &
+ ~XDPTX_AUX_CLK_DIVIDER_VAL_MASK) |
+ (Config->SAxiClkHz / 1000000);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal);
- /* Set the DisplayPort TX core's clock speed. */
- switch (Config->MaxLinkRate) {
- case XDPTX_LINK_BW_SET_540GBPS:
- XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
- XDPTX_PHY_CLOCK_SELECT_540GBPS);
- break;
- case XDPTX_LINK_BW_SET_270GBPS:
- XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
- XDPTX_PHY_CLOCK_SELECT_270GBPS);
- break;
- case XDPTX_LINK_BW_SET_162GBPS:
- XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
- XDPTX_PHY_CLOCK_SELECT_162GBPS);
- break;
- default:
- break;
- }
+ /* Set the DisplayPort TX core's clock speed. */
+ switch (Config->MaxLinkRate) {
+ case XDPTX_LINK_BW_SET_540GBPS:
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+ XDPTX_PHY_CLOCK_SELECT_540GBPS);
+ break;
+ case XDPTX_LINK_BW_SET_270GBPS:
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+ XDPTX_PHY_CLOCK_SELECT_270GBPS);
+ break;
+ case XDPTX_LINK_BW_SET_162GBPS:
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+ XDPTX_PHY_CLOCK_SELECT_162GBPS);
+ break;
+ default:
+ break;
+ }
- /* Bring the PHY (and GTTXRESET) out of reset. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
- XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
+ /* Bring the PHY (and GTTXRESET) out of reset. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
+ XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
- /* Wait for the PHY to be ready. */
- Status = XDptx_WaitPhyReady(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Wait for the PHY to be ready. */
+ Status = XDptx_WaitPhyReady(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Enable the DisplayPort TX core. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 1);
+ /* Enable the DisplayPort TX core. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 1);
- /* Unmask Hot-Plug-Detect (HPD) interrupts. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_INTERRUPT_MASK,
- ~XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
- ~XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK &
- ~XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK);
+ /* Unmask Hot-Plug-Detect (HPD) interrupts. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_INTERRUPT_MASK,
+ ~XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
+ ~XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK &
+ ~XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK);
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -215,37 +215,37 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
* This function retrieves the configuration for this DisplayPort TX instance
* and fills in the InstancePtr->Config structure.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param ConfigPtr is a pointer to the configuration structure that will
- * be used to copy the settings from.
- * @param EffectiveAddr is the device base address in the virtual memory
- * space. If the address translation is not used, then the physical
- * address is passed.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param ConfigPtr is a pointer to the configuration structure that will
+ * be used to copy the settings from.
+ * @param EffectiveAddr is the device base address in the virtual memory
+ * space. If the address translation is not used, then the physical
+ * address is passed.
*
- * @return None.
+ * @return None.
*
- * @note Unexpected errors may occur if the address mapping is changed
- * after this function is invoked.
+ * @note Unexpected errors may occur if the address mapping is changed
+ * after this function is invoked.
*
*******************************************************************************/
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
- u32 EffectiveAddr)
+ u32 EffectiveAddr)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(ConfigPtr != NULL);
- Xil_AssertVoid(EffectiveAddr != 0x0);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(ConfigPtr != NULL);
+ Xil_AssertVoid(EffectiveAddr != 0x0);
- InstancePtr->IsReady = 0;
+ InstancePtr->IsReady = 0;
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddr = EffectiveAddr;
- InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz;
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddr = EffectiveAddr;
+ InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz;
- InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate;
- InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount;
+ InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate;
+ InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
}
/******************************************************************************/
@@ -253,59 +253,59 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
* This function retrieves the RX device's capabilities from the RX device's
* DisplayPort Configuration Data (DPCD).
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the DisplayPort Configuration Data was read
- * successfully.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the DisplayPort Configuration Data was read
+ * successfully.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr)
{
- u32 Status;
- u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- XDptx_Config *Config = &InstancePtr->Config;
- u8 RxMaxLinkRate;
- u8 RxMaxLaneCount;
+ u32 Status;
+ u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ XDptx_Config *Config = &InstancePtr->Config;
+ u8 RxMaxLinkRate;
+ u8 RxMaxLaneCount;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Dpcd != NULL);
- Xil_AssertNonvoid(LinkConfig != NULL);
- Xil_AssertNonvoid(Config != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Dpcd != NULL);
+ Xil_AssertNonvoid(LinkConfig != NULL);
+ Xil_AssertNonvoid(Config != NULL);
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_RECEIVER_CAP_FIELD_START,
- XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE, Dpcd);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_RECEIVER_CAP_FIELD_START,
+ XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE, Dpcd);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- RxMaxLinkRate = Dpcd[XDPTX_DPCD_MAX_LINK_RATE];
- RxMaxLaneCount = Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
- XDPTX_DPCD_MAX_LANE_COUNT_MASK;
- LinkConfig->MaxLinkRate = (RxMaxLinkRate > Config->MaxLinkRate) ?
- Config->MaxLinkRate : RxMaxLinkRate;
- LinkConfig->MaxLaneCount = (RxMaxLaneCount > Config->MaxLaneCount) ?
- Config->MaxLaneCount : RxMaxLaneCount;
+ RxMaxLinkRate = Dpcd[XDPTX_DPCD_MAX_LINK_RATE];
+ RxMaxLaneCount = Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
+ XDPTX_DPCD_MAX_LANE_COUNT_MASK;
+ LinkConfig->MaxLinkRate = (RxMaxLinkRate > Config->MaxLinkRate) ?
+ Config->MaxLinkRate : RxMaxLinkRate;
+ LinkConfig->MaxLaneCount = (RxMaxLaneCount > Config->MaxLaneCount) ?
+ Config->MaxLaneCount : RxMaxLaneCount;
- LinkConfig->SupportEnhancedFramingMode =
- Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
- XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
- LinkConfig->SupportDownspreadControl =
- Dpcd[XDPTX_DPCD_MAX_DOWNSPREAD] &
- XDPTX_DPCD_MAX_DOWNSPREAD_MASK;
+ LinkConfig->SupportEnhancedFramingMode =
+ Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
+ XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
+ LinkConfig->SupportDownspreadControl =
+ Dpcd[XDPTX_DPCD_MAX_DOWNSPREAD] &
+ XDPTX_DPCD_MAX_DOWNSPREAD_MASK;
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -313,34 +313,34 @@ u32 XDptx_GetRxCapabilities(XDptx *InstancePtr)
* This function retrieves the RX device's Extended Display Identification Data
* (EDID).
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the I2C transactions to read the EDID were
- * successful.
- * - XST_ERROR_COUNT_MAX if the EDID read request timed out.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the I2C transactions to read the EDID were
+ * successful.
+ * - XST_ERROR_COUNT_MAX if the EDID read request timed out.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_GetEdid(XDptx *InstancePtr)
{
- u32 Status;
+ u32 Status;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->RxConfig.Edid != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->RxConfig.Edid != NULL);
- Status = XDptx_IicRead(InstancePtr, XDPTX_EDID_ADDR, 0, XDPTX_EDID_SIZE,
- InstancePtr->RxConfig.Edid);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ Status = XDptx_IicRead(InstancePtr, XDPTX_EDID_ADDR, 0, XDPTX_EDID_SIZE,
+ InstancePtr->RxConfig.Edid);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -348,46 +348,46 @@ u32 XDptx_GetEdid(XDptx *InstancePtr)
* This function determines the common capabilities between the DisplayPort TX
* core and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if main link settings were successfully set.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if main link settings were successfully set.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr)
{
- u32 Status;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ u32 Status;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /* The link rate and lane count will be checked in XDptx_SetLinkRate and
- * XDptx_SetLaneCount. */
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* The link rate and lane count will be checked in XDptx_SetLinkRate and
+ * XDptx_SetLaneCount. */
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Configure the main link to the maximum common link rate between the
- * DisplayPort TX core and the RX device. */
- Status = XDptx_SetLinkRate(InstancePtr, LinkConfig->MaxLinkRate);
- if (Status != XST_SUCCESS) {
- return Status;
- }
+ /* Configure the main link to the maximum common link rate between the
+ * DisplayPort TX core and the RX device. */
+ Status = XDptx_SetLinkRate(InstancePtr, LinkConfig->MaxLinkRate);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
- /* Configure the main link to the maximum common lane count between the
- * DisplayPort TX core and the RX device. */
- Status = XDptx_SetLaneCount(InstancePtr, LinkConfig->MaxLaneCount);
- if (Status != XST_SUCCESS) {
- return Status;
- }
+ /* Configure the main link to the maximum common lane count between the
+ * DisplayPort TX core and the RX device. */
+ Status = XDptx_SetLaneCount(InstancePtr, LinkConfig->MaxLaneCount);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -395,53 +395,53 @@ u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr)
* This function checks if the link needs training and runs the training
* sequence if training is required.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS was either already trained, or has been
- * trained successfully.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS was either already trained, or has been
+ * trained successfully.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_EstablishLink(XDptx *InstancePtr)
{
- u32 Status;
+ u32 Status;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((InstancePtr->LinkConfig.LinkRate ==
- XDPTX_LINK_BW_SET_162GBPS) ||
- (InstancePtr->LinkConfig.LinkRate ==
- XDPTX_LINK_BW_SET_270GBPS) ||
- (InstancePtr->LinkConfig.LinkRate ==
- XDPTX_LINK_BW_SET_540GBPS));
- /* The lane count will be checked in XDptx_CheckLinkStatus. */
- Xil_AssertNonvoid(InstancePtr->RxConfig.LaneStatusAdjReqs != NULL);
- Xil_AssertNonvoid(InstancePtr->RxConfig.DpcdRxCapsField != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((InstancePtr->LinkConfig.LinkRate ==
+ XDPTX_LINK_BW_SET_162GBPS) ||
+ (InstancePtr->LinkConfig.LinkRate ==
+ XDPTX_LINK_BW_SET_270GBPS) ||
+ (InstancePtr->LinkConfig.LinkRate ==
+ XDPTX_LINK_BW_SET_540GBPS));
+ /* The lane count will be checked in XDptx_CheckLinkStatus. */
+ Xil_AssertNonvoid(InstancePtr->RxConfig.LaneStatusAdjReqs != NULL);
+ Xil_AssertNonvoid(InstancePtr->RxConfig.DpcdRxCapsField != NULL);
- Status = XDptx_CheckLinkStatus(InstancePtr,
- InstancePtr->LinkConfig.LaneCount);
- if (Status != XST_FAILURE) {
- return Status;
- }
+ Status = XDptx_CheckLinkStatus(InstancePtr,
+ InstancePtr->LinkConfig.LaneCount);
+ if (Status != XST_FAILURE) {
+ return Status;
+ }
- XDptx_ResetPhy(InstancePtr, XDPTX_PHY_CONFIG_PHY_RESET_MASK);
+ XDptx_ResetPhy(InstancePtr, XDPTX_PHY_CONFIG_PHY_RESET_MASK);
- XDptx_DisableMainLink(InstancePtr);
+ XDptx_DisableMainLink(InstancePtr);
- /* Train main link. */
- Status = XDptx_RunTraining(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Train main link. */
+ Status = XDptx_RunTraining(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- XDptx_EnableMainLink(InstancePtr);
+ XDptx_EnableMainLink(InstancePtr);
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -451,78 +451,78 @@ u32 XDptx_EstablishLink(XDptx *InstancePtr)
* equalization, symbol lock, and interlane alignment for all lanes currently in
* use.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LaneCount is the number of lanes to check.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LaneCount is the number of lanes to check.
*
* @return
- * - XST_SUCCESS if the RX device has maintained clock recovery,
- * channel equalization, symbol lock, and interlane alignment.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the RX device has maintained clock recovery,
+ * channel equalization, symbol lock, and interlane alignment.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount)
{
- u8 RetryCount = 0;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- u32 Status;
+ u32 Status;
+ u8 RetryCount = 0;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
- (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
- (LaneCount == XDPTX_LANE_COUNT_SET_4));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+ (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+ (LaneCount == XDPTX_LANE_COUNT_SET_4));
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Retrieve AUX info. */
- do {
- /* Get lane and adjustment requests. */
- Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The AUX read failed. */
- return XST_FAILURE;
- }
+ /* Retrieve AUX info. */
+ do {
+ /* Get lane and adjustment requests. */
+ Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The AUX read failed. */
+ return XST_FAILURE;
+ }
- /* Check if the link needs training. */
- if ((XDptx_CheckClockRecovery(
- InstancePtr, LaneCount) == XST_SUCCESS) &&
- (XDptx_CheckChannelEqualization(
- InstancePtr, LaneCount) == XST_SUCCESS)) {
- return XST_SUCCESS;
- }
+ /* Check if the link needs training. */
+ if ((XDptx_CheckClockRecovery(
+ InstancePtr, LaneCount) == XST_SUCCESS) &&
+ (XDptx_CheckChannelEqualization(
+ InstancePtr, LaneCount) == XST_SUCCESS)) {
+ return XST_SUCCESS;
+ }
- RetryCount++;
- }
- while (RetryCount < 5); /* Retry up to 5 times. */
+ RetryCount++;
+ }
+ while (RetryCount < 5); /* Retry up to 5 times. */
- return XST_FAILURE;
+ return XST_FAILURE;
}
/******************************************************************************/
/**
* This function enables or disables downshifting during the training process.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Enable controls the downshift feature in the training process.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Enable controls the downshift feature in the training process.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((Enable == 1) || (Enable == 0));
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((Enable == 1) || (Enable == 0));
- InstancePtr->TrainAdaptive = Enable;
+ InstancePtr->TrainAdaptive = Enable;
}
/******************************************************************************/
@@ -532,228 +532,228 @@ void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable)
* to determine which set of voltage swing and pre-emphasis values to use in the
* TX core.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Set establishes that a redriver exists in the DisplayPort output
- * path.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Set establishes that a redriver exists in the DisplayPort output
+ * path.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((Set == 1) || (Set == 0));
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((Set == 1) || (Set == 0));
- InstancePtr->HasRedriverInPath = Set;
+ InstancePtr->HasRedriverInPath = Set;
}
/******************************************************************************/
/**
* This function issues a read request over the AUX channel.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Address is the starting address to read from the RX device.
- * @param NumBytes is the number of bytes to read from the RX device.
- * @param Data is a pointer to the data buffer that will be filled with
- * read data.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Address is the starting address to read from the RX device.
+ * @param NumBytes is the number of bytes to read from the RX device.
+ * @param Data is a pointer to the data buffer that will be filled with
+ * read data.
*
* @return
- * - XST_SUCCESS if the AUX read request was successfully
- * acknowledged.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_ERROR_COUNT_MAX if the AUX request timed out.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the AUX read request was successfully
+ * acknowledged.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
{
- u32 Status;
- XDptx_AuxTransaction Request;
+ u32 Status;
+ XDptx_AuxTransaction Request;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Address <= 0xFFFFF);
- Xil_AssertNonvoid(NumBytes <= 0xFFFFF);
- Xil_AssertNonvoid(Data != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Address <= 0xFFFFF);
+ Xil_AssertNonvoid(NumBytes <= 0xFFFFF);
+ Xil_AssertNonvoid(Data != NULL);
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Send AUX read transaction. */
- Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_READ, Address,
- NumBytes, (u8 *)Data);
+ /* Send AUX read transaction. */
+ Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_READ, Address,
+ NumBytes, (u8 *)Data);
- return Status;
+ return Status;
}
/******************************************************************************/
/**
* This function issues a write request over the AUX channel.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Address is the starting address to write to the RX device.
- * @param NumBytes is the number of bytes to write to the RX device.
- * @param Data is a pointer to the data buffer that contains the data
- * to be written to the RX device.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Address is the starting address to write to the RX device.
+ * @param NumBytes is the number of bytes to write to the RX device.
+ * @param Data is a pointer to the data buffer that contains the data
+ * to be written to the RX device.
*
* @return
- * - XST_SUCCESS if AUX write request was successfully
- * acknowledged.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_ERROR_COUNT_MAX if the AUX request timed out.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if AUX write request was successfully
+ * acknowledged.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
{
- u32 Status;
- XDptx_AuxTransaction Request;
+ u32 Status;
+ XDptx_AuxTransaction Request;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Address <= 0xFFFFF);
- Xil_AssertNonvoid(NumBytes <= 0xFFFFF);
- Xil_AssertNonvoid(Data != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Address <= 0xFFFFF);
+ Xil_AssertNonvoid(NumBytes <= 0xFFFFF);
+ Xil_AssertNonvoid(Data != NULL);
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Send AUX write transaction. */
- Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_WRITE, Address,
- NumBytes, (u8 *)Data);
+ /* Send AUX write transaction. */
+ Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_WRITE, Address,
+ NumBytes, (u8 *)Data);
- return Status;
+ return Status;
}
/******************************************************************************/
/**
* This function performs an I2C read over the AUX channel.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param IicAddress is the address on the I2C bus of the target device.
- * @param RegStartAddress is the subaddress of the targeted I2C device
- * that the read will start from.
- * @param NumBytes is the number of bytes to read.
- * @param Data is a pointer to a buffer that will be filled with the I2C
- * read data.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param IicAddress is the address on the I2C bus of the target device.
+ * @param RegStartAddress is the subaddress of the targeted I2C device
+ * that the read will start from.
+ * @param NumBytes is the number of bytes to read.
+ * @param Data is a pointer to a buffer that will be filled with the I2C
+ * read data.
*
* @return
- * - XST_SUCCESS if the I2C read has successfully completed with no
- * errors.
- * - XST_ERROR_COUNT_MAX if the AUX request timed out.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the I2C read has successfully completed with no
+ * errors.
+ * - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
- u8 NumBytes, void *Data)
+ u8 NumBytes, void *Data)
{
- u32 Status;
- XDptx_AuxTransaction Request;
- u8 AuxData[2];
+ u32 Status;
+ XDptx_AuxTransaction Request;
+ u8 AuxData[2];
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(IicAddress <= 0xFFFFF);
- Xil_AssertNonvoid(RegStartAddress <= 256);
- Xil_AssertNonvoid(NumBytes <= 256);
- Xil_AssertNonvoid(Data != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(IicAddress <= 0xFFFFF);
+ Xil_AssertNonvoid(RegStartAddress <= 256);
+ Xil_AssertNonvoid(NumBytes <= 256);
+ Xil_AssertNonvoid(Data != NULL);
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Setup the I2C-over-AUX read transaction with the address. */
- Request.Address = IicAddress;
- Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
- Request.NumBytes = 2;
- AuxData[0] = RegStartAddress;
- AuxData[1] = 0;
- Request.Data = AuxData;
- Status = XDptx_AuxRequest(InstancePtr, &Request);
- if (Status != XST_SUCCESS) {
- return Status;
- }
+ /* Setup the I2C-over-AUX read transaction with the address. */
+ Request.Address = IicAddress;
+ Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
+ Request.NumBytes = 2;
+ AuxData[0] = RegStartAddress;
+ AuxData[1] = 0;
+ Request.Data = AuxData;
+ Status = XDptx_AuxRequest(InstancePtr, &Request);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
- /* Send I2C-over-AUX read transaction. */
- Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_READ,
- IicAddress, NumBytes, (u8 *)Data);
+ /* Send I2C-over-AUX read transaction. */
+ Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_READ,
+ IicAddress, NumBytes, (u8 *)Data);
- return Status;
+ return Status;
}
/******************************************************************************/
/**
* This function performs an I2C write over the AUX channel.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param IicAddress is the address on the I2C bus of the target device.
- * @param RegStartAddress is the sub-address of the targeted I2C device
- * that the write will start at.
- * @param NumBytes is the number of bytes to write.
- * @param Data is a pointer to a buffer which will be used as the data
- * source for the write.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param IicAddress is the address on the I2C bus of the target device.
+ * @param RegStartAddress is the sub-address of the targeted I2C device
+ * that the write will start at.
+ * @param NumBytes is the number of bytes to write.
+ * @param Data is a pointer to a buffer which will be used as the data
+ * source for the write.
*
* @return
- * - XST_SUCCESS if the I2C write has successfully completed with
- * no errors.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_ERROR_COUNT_MAX if the AUX request timed out.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the I2C write has successfully completed with
+ * no errors.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
- u8 NumBytes, void *Data)
+ u8 NumBytes, void *Data)
{
- u32 Status;
- XDptx_AuxTransaction Request;
- u8 AuxData[2];
+ u32 Status;
+ XDptx_AuxTransaction Request;
+ u8 AuxData[2];
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(IicAddress <= 0xFFFFF);
- Xil_AssertNonvoid(RegStartAddress <= 256);
- Xil_AssertNonvoid(NumBytes <= 256);
- Xil_AssertNonvoid(Data != NULL);
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(IicAddress <= 0xFFFFF);
+ Xil_AssertNonvoid(RegStartAddress <= 256);
+ Xil_AssertNonvoid(NumBytes <= 256);
+ Xil_AssertNonvoid(Data != NULL);
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Setup the I2C-over-AUX write transaction with the address. */
- Request.Address = IicAddress;
- Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
- Request.NumBytes = 2;
- AuxData[0] = RegStartAddress;
- AuxData[1] = 0;
- Request.Data = AuxData;
- Status = XDptx_AuxRequest(InstancePtr, &Request);
- if (Status != XST_SUCCESS) {
- return Status;
- }
+ /* Setup the I2C-over-AUX write transaction with the address. */
+ Request.Address = IicAddress;
+ Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
+ Request.NumBytes = 2;
+ AuxData[0] = RegStartAddress;
+ AuxData[1] = 0;
+ Request.Data = AuxData;
+ Status = XDptx_AuxRequest(InstancePtr, &Request);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
- /* Send I2C-over-AUX read transaction. */
- Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_READ,
- IicAddress, NumBytes, (u8 *)Data);
+ /* Send I2C-over-AUX read transaction. */
+ Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_I2C_READ,
+ IicAddress, NumBytes, (u8 *)Data);
- return Status;
+ return Status;
}
/******************************************************************************/
@@ -761,60 +761,60 @@ u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
* This function enables or disables 0.5% spreading of the clock for both the
* DisplayPort and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Enable will downspread the main link signal if set to 1 and
- * disable downspreading if set to 0.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Enable will downspread the main link signal if set to 1 and
+ * disable downspreading if set to 0.
*
* @return
- * - XST_SUCCESS if setting the downspread control enable was
- * successful.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the downspread control enable was
+ * successful.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
{
- u32 Status;
- u8 RegVal;
+ u32 Status;
+ u8 RegVal;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- InstancePtr->LinkConfig.DownspreadControl = Enable;
+ InstancePtr->LinkConfig.DownspreadControl = Enable;
- /* Write downspread enable to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_DOWNSPREAD_CTRL,
- InstancePtr->LinkConfig.DownspreadControl);
+ /* Write downspread enable to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_DOWNSPREAD_CTRL,
+ InstancePtr->LinkConfig.DownspreadControl);
- /* Preserve the current RX device settings. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- if (InstancePtr->LinkConfig.DownspreadControl) {
- RegVal |= XDPTX_DPCD_SPREAD_AMP_MASK;
- }
- else {
- RegVal &= ~XDPTX_DPCD_SPREAD_AMP_MASK;
- }
+ /* Preserve the current RX device settings. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ if (InstancePtr->LinkConfig.DownspreadControl) {
+ RegVal |= XDPTX_DPCD_SPREAD_AMP_MASK;
+ }
+ else {
+ RegVal &= ~XDPTX_DPCD_SPREAD_AMP_MASK;
+ }
- /* Write downspread enable to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write downspread enable to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -822,60 +822,60 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
* This function enables or disables the enhanced framing symbol sequence for
* both the DisplayPort TX core and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Enable will enable enhanced frame mode if set to 1 and disable
- * it if set to 0.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Enable will enable enhanced frame mode if set to 1 and disable
+ * it if set to 0.
*
* @return
- * - XST_SUCCESS if setting the enhanced frame mode enable was
- * successful.
- * - XST_DEVICE_NOT_FOUND if no RX is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the enhanced frame mode enable was
+ * successful.
+ * - XST_DEVICE_NOT_FOUND if no RX is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
{
- u32 Status;
- u8 RegVal;
+ u32 Status;
+ u8 RegVal;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- InstancePtr->LinkConfig.EnhancedFramingMode = Enable;
+ InstancePtr->LinkConfig.EnhancedFramingMode = Enable;
- /* Write enhanced frame mode enable to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENHANCED_FRAME_EN,
- InstancePtr->LinkConfig.EnhancedFramingMode);
+ /* Write enhanced frame mode enable to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENHANCED_FRAME_EN,
+ InstancePtr->LinkConfig.EnhancedFramingMode);
- /* Preserve the current RX device settings. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- if (InstancePtr->LinkConfig.EnhancedFramingMode) {
- RegVal |= XDPTX_DPCD_ENHANCED_FRAME_EN_MASK;
- }
- else {
- RegVal &= ~XDPTX_DPCD_ENHANCED_FRAME_EN_MASK;
- }
+ /* Preserve the current RX device settings. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ if (InstancePtr->LinkConfig.EnhancedFramingMode) {
+ RegVal |= XDPTX_DPCD_ENHANCED_FRAME_EN_MASK;
+ }
+ else {
+ RegVal &= ~XDPTX_DPCD_ENHANCED_FRAME_EN_MASK;
+ }
- /* Write enhanced frame mode enable to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write enhanced frame mode enable to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -883,56 +883,56 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
* This function sets the number of lanes to be used by the main link for both
* the DisplayPort TX core and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LaneCount is the number of lanes to be used over the main link.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LaneCount is the number of lanes to be used over the main link.
*
* @return
- * - XST_SUCCESS if setting the new lane count was successful.
- * - XST_DEVICE_NOT_FOUND if no RX is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the new lane count was successful.
+ * - XST_DEVICE_NOT_FOUND if no RX is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
{
- u32 Status;
- u8 RegVal;
+ u32 Status;
+ u8 RegVal;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
- (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
- (LaneCount == XDPTX_LANE_COUNT_SET_4));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+ (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+ (LaneCount == XDPTX_LANE_COUNT_SET_4));
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- InstancePtr->LinkConfig.LaneCount = LaneCount;
+ InstancePtr->LinkConfig.LaneCount = LaneCount;
- /* Write the new lane count to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LANE_COUNT_SET,
- InstancePtr->LinkConfig.LaneCount);
+ /* Write the new lane count to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LANE_COUNT_SET,
+ InstancePtr->LinkConfig.LaneCount);
- /* Preserve the current RX device settings. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- RegVal &= ~XDPTX_DPCD_LANE_COUNT_SET_MASK;
- RegVal |= InstancePtr->LinkConfig.LaneCount;
+ /* Preserve the current RX device settings. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ RegVal &= ~XDPTX_DPCD_LANE_COUNT_SET_MASK;
+ RegVal |= InstancePtr->LinkConfig.LaneCount;
- /* Write the new lane count to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write the new lane count to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 0x1,
+ &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -940,71 +940,71 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
* This function sets the data rate to be used by the main link for both the
* DisplayPort TX core and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LinkRate is the link rate to be used over the main link based on
- * one of the following selects:
- * - XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
- * - XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
- * - XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LinkRate is the link rate to be used over the main link based on
+ * one of the following selects:
+ * - XDPTX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
+ * - XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
+ * - XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
*
* @return
- * - XST_SUCCESS if setting the new link rate was successful.
- * - XST_DEVICE_NOT_FOUND if no RX device is connected.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the new link rate was successful.
+ * - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
{
- u32 Status;
+ u32 Status;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
- (LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
- (LinkRate == XDPTX_LINK_BW_SET_540GBPS));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
+ (LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
+ (LinkRate == XDPTX_LINK_BW_SET_540GBPS));
- if (!XDptx_IsConnected(InstancePtr)) {
- return XST_DEVICE_NOT_FOUND;
- }
+ if (!XDptx_IsConnected(InstancePtr)) {
+ return XST_DEVICE_NOT_FOUND;
+ }
- /* Write a corresponding clock frequency to the DisplayPort TX core. */
- switch (LinkRate) {
- case XDPTX_LINK_BW_SET_162GBPS:
- Status = XDptx_SetClkSpeed(InstancePtr,
- XDPTX_PHY_CLOCK_SELECT_162GBPS);
- break;
- case XDPTX_LINK_BW_SET_270GBPS:
- Status = XDptx_SetClkSpeed(InstancePtr,
- XDPTX_PHY_CLOCK_SELECT_270GBPS);
- break;
- case XDPTX_LINK_BW_SET_540GBPS:
- Status = XDptx_SetClkSpeed(InstancePtr,
- XDPTX_PHY_CLOCK_SELECT_540GBPS);
- break;
- default:
- break;
- }
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write a corresponding clock frequency to the DisplayPort TX core. */
+ switch (LinkRate) {
+ case XDPTX_LINK_BW_SET_162GBPS:
+ Status = XDptx_SetClkSpeed(InstancePtr,
+ XDPTX_PHY_CLOCK_SELECT_162GBPS);
+ break;
+ case XDPTX_LINK_BW_SET_270GBPS:
+ Status = XDptx_SetClkSpeed(InstancePtr,
+ XDPTX_PHY_CLOCK_SELECT_270GBPS);
+ break;
+ case XDPTX_LINK_BW_SET_540GBPS:
+ Status = XDptx_SetClkSpeed(InstancePtr,
+ XDPTX_PHY_CLOCK_SELECT_540GBPS);
+ break;
+ default:
+ break;
+ }
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- InstancePtr->LinkConfig.LinkRate = LinkRate;
+ InstancePtr->LinkConfig.LinkRate = LinkRate;
- /* Write new link rate to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LINK_BW_SET,
- InstancePtr->LinkConfig.LinkRate);
+ /* Write new link rate to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LINK_BW_SET,
+ InstancePtr->LinkConfig.LinkRate);
- /* Write new link rate to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LINK_BW_SET, 1,
- &InstancePtr->LinkConfig.LinkRate);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write new link rate to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LINK_BW_SET, 0x1,
+ &InstancePtr->LinkConfig.LinkRate);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -1012,131 +1012,131 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
* This function enables or disables scrambling of symbols for both the
* DisplayPort and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Enable will enable or disable scrambling.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Enable will enable or disable scrambling.
*
* @return
- * - XST_SUCCESS if setting the scrambling enable was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the scrambling enable was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable)
{
- u32 Status;
- u8 RegVal;
+ u32 Status;
+ u8 RegVal;
- /* Verify arguments. */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
+ /* Verify arguments. */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
- InstancePtr->LinkConfig.ScramblerEn = Enable;
+ InstancePtr->LinkConfig.ScramblerEn = Enable;
- /* Write scrambler disable to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SCRAMBLING_DISABLE,
- Enable ? 0 : 1);
+ /* Write scrambler disable to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SCRAMBLING_DISABLE,
+ Enable ? 0x0 : 0x1);
- /* Preserve the current RX device settings. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- if (Enable) {
- RegVal &= ~XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK;
- }
- else {
- RegVal |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK;
- }
+ /* Preserve the current RX device settings. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 0x1, &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ if (Enable) {
+ RegVal &= ~XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK;
+ }
+ else {
+ RegVal |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK;
+ }
- /* Write scrambler disable to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write scrambler disable to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 0x1, &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function enables the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_EnableMainLink(XDptx *InstancePtr)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /* Reset the scrambler. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_FORCE_SCRAMBLER_RESET, 1);
+ /* Reset the scrambler. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_FORCE_SCRAMBLER_RESET, 0x1);
- /* Enable the main stream. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_ENABLE_MAIN_STREAM, 1);
+ /* Enable the main stream. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_ENABLE_MAIN_STREAM, 0x1);
}
/******************************************************************************/
/**
* This function disables the main link.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_DisableMainLink(XDptx *InstancePtr)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /* Reset the scrambler. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_FORCE_SCRAMBLER_RESET, 1);
+ /* Reset the scrambler. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_FORCE_SCRAMBLER_RESET, 0x1);
- /* Disable the main stream. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_ENABLE_MAIN_STREAM, 0);
+ /* Disable the main stream. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_ENABLE_MAIN_STREAM, 0x0);
}
/******************************************************************************/
/**
* This function does a PHY reset.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Reset is the type of reset to assert.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Reset is the type of reset to assert.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x0);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, Reset);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG,
- XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
- XDptx_WaitPhyReady(InstancePtr);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, Reset);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG,
+ XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
+ XDptx_WaitPhyReady(InstancePtr);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 1);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x1);
}
/******************************************************************************/
@@ -1144,27 +1144,27 @@ void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset)
* This function installs a custom delay/sleep function to be used by the XDdptx
* driver.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param CallbackFunc is the address to the callback function.
- * @param CallbackRef is the user data item (microseconds to delay) that
- * will be passed to the custom sleep/delay function when it is
- * invoked.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param CallbackFunc is the address to the callback function.
+ * @param CallbackRef is the user data item (microseconds to delay) that
+ * will be passed to the custom sleep/delay function when it is
+ * invoked.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
- XDptx_TimerHandler CallbackFunc, void *CallbackRef)
+ XDptx_TimerHandler CallbackFunc, void *CallbackRef)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallbackFunc != NULL);
- Xil_AssertVoid(CallbackRef != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallbackFunc != NULL);
+ Xil_AssertVoid(CallbackRef != NULL);
- InstancePtr->UserTimerWaitUs = CallbackFunc;
- InstancePtr->UserTimerPtr = CallbackRef;
+ InstancePtr->UserTimerWaitUs = CallbackFunc;
+ InstancePtr->UserTimerPtr = CallbackRef;
}
/******************************************************************************/
@@ -1178,34 +1178,34 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
* to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a
* hardware timer is used.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param MicroSeconds is the number of microseconds to delay/sleep for.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param MicroSeconds is the number of microseconds to delay/sleep for.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#if defined(__MICROBLAZE__)
- if (InstancePtr->UserTimerWaitUs != NULL) {
- /* Use the timer handler specified by the user for better
- * accuracy. */
- InstancePtr->UserTimerWaitUs(InstancePtr, MicroSeconds);
- }
- else {
- /* MicroBlaze sleep only has millisecond accuracy. Round up. */
- u32 MilliSeconds = (MicroSeconds + 999) / 1000;
- MB_Sleep(MilliSeconds);
- }
+ if (InstancePtr->UserTimerWaitUs != NULL) {
+ /* Use the timer handler specified by the user for better
+ * accuracy. */
+ InstancePtr->UserTimerWaitUs(InstancePtr, MicroSeconds);
+ }
+ else {
+ /* MicroBlaze sleep only has millisecond accuracy. Round up. */
+ u32 MilliSeconds = (MicroSeconds + 999) / 1000;
+ MB_Sleep(MilliSeconds);
+ }
#elif defined(__arm__)
- /* Wait the requested amount of time. */
- usleep(MicroSeconds);
+ /* Wait the requested amount of time. */
+ usleep(MicroSeconds);
#endif
}
@@ -1219,320 +1219,320 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds)
* be re-attempted. If training fails at the minimal data rate, 1.62 Gbps with
* a single lane, training will no longer re-attempt and fail.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the training process succeeded.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the training process succeeded.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_RunTraining(XDptx *InstancePtr)
{
- u32 Status;
- XDptx_TrainingState TrainingState = XDPTX_TS_CLOCK_RECOVERY;
+ u32 Status;
+ XDptx_TrainingState TrainingState = XDPTX_TS_CLOCK_RECOVERY;
- /* Disable scrambler. */
- Status = XDptx_SetScrambler(InstancePtr, 0);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Disable scrambler. */
+ Status = XDptx_SetScrambler(InstancePtr, 0);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- while (1) {
- switch (TrainingState) {
- case XDPTX_TS_CLOCK_RECOVERY:
- TrainingState = XDptx_TrainingStateClockRecovery(
- InstancePtr);
- break;
- case XDPTX_TS_CHANNEL_EQUALIZATION:
- TrainingState = XDptx_TrainingStateChannelEqualization(
- InstancePtr, 5);
- break;
- case XDPTX_TS_ADJUST_LINK_RATE:
- TrainingState = XDptx_TrainingStateAdjustLinkRate(
- InstancePtr);
- break;
- case XDPTX_TS_ADJUST_LANE_COUNT:
- TrainingState = XDptx_TrainingStateAdjustLaneCount(
- InstancePtr);
- break;
- default:
- break;
- }
+ while (1) {
+ switch (TrainingState) {
+ case XDPTX_TS_CLOCK_RECOVERY:
+ TrainingState = XDptx_TrainingStateClockRecovery(
+ InstancePtr);
+ break;
+ case XDPTX_TS_CHANNEL_EQUALIZATION:
+ TrainingState = XDptx_TrainingStateChannelEqualization(
+ InstancePtr, 5);
+ break;
+ case XDPTX_TS_ADJUST_LINK_RATE:
+ TrainingState = XDptx_TrainingStateAdjustLinkRate(
+ InstancePtr);
+ break;
+ case XDPTX_TS_ADJUST_LANE_COUNT:
+ TrainingState = XDptx_TrainingStateAdjustLaneCount(
+ InstancePtr);
+ break;
+ default:
+ break;
+ }
- if (TrainingState == XDPTX_TS_SUCCESS) {
- break;
- }
- else if (TrainingState == XDPTX_TS_FAILURE) {
- return XST_FAILURE;
- }
+ if (TrainingState == XDPTX_TS_SUCCESS) {
+ break;
+ }
+ else if (TrainingState == XDPTX_TS_FAILURE) {
+ return XST_FAILURE;
+ }
- if ((InstancePtr->TrainAdaptive == 0) &&
- ((TrainingState == XDPTX_TS_ADJUST_LANE_COUNT) ||
- (TrainingState == XDPTX_TS_ADJUST_LINK_RATE))) {
- return XST_FAILURE;
- }
- }
+ if ((InstancePtr->TrainAdaptive == 0) &&
+ ((TrainingState == XDPTX_TS_ADJUST_LANE_COUNT) ||
+ (TrainingState == XDPTX_TS_ADJUST_LINK_RATE))) {
+ return XST_FAILURE;
+ }
+ }
- /* Turn off the training pattern. */
- Status = XDptx_SetTrainingPattern(InstancePtr,
- XDPTX_TRAINING_PATTERN_SET_OFF);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Turn off the training pattern. */
+ Status = XDptx_SetTrainingPattern(InstancePtr,
+ XDPTX_TRAINING_PATTERN_SET_OFF);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Enable scrambler. */
- Status = XDptx_SetScrambler(InstancePtr, 1);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Enable scrambler. */
+ Status = XDptx_SetScrambler(InstancePtr, 1);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Final status check. */
- Status = XDptx_CheckLinkStatus(InstancePtr,
- InstancePtr->LinkConfig.LaneCount);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Final status check. */
+ Status = XDptx_CheckLinkStatus(InstancePtr,
+ InstancePtr->LinkConfig.LaneCount);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function runs the clock recovery sequence as part of link training. The
* sequence is as follows:
- * 0) Start signaling at the minimum voltage swing, pre-emphasis, and post-
- * cursor levels.
- * 1) Transmit training pattern 1 over the main link with symbol scrambling
- * disabled.
- * 2) The clock recovery loop. If clock recovery is unsuccessful after
- * MaxIterations loop iterations, return.
- * 2a) Wait for at least the period of time specified in the RX device's
- * DisplayPort Configuration Data (DPCD) register,
- * TRAINING_AUX_RD_INTERVAL.
- * 2b) Check if all lanes have achieved clock recovery lock. If so, return.
- * 2c) Check if the same voltage swing level has been used 5 consecutive
- * times or if the maximum level has been reached. If so, return.
- * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
- * requested by the RX device.
- * 2e) Loop back to 2a.
+ * 0) Start signaling at the minimum voltage swing, pre-emphasis, and post-
+ * cursor levels.
+ * 1) Transmit training pattern 1 over the main link with symbol scrambling
+ * disabled.
+ * 2) The clock recovery loop. If clock recovery is unsuccessful after
+ * MaxIterations loop iterations, return.
+ * 2a) Wait for at least the period of time specified in the RX device's
+ * DisplayPort Configuration Data (DPCD) register,
+ * TRAINING_AUX_RD_INTERVAL.
+ * 2b) Check if all lanes have achieved clock recovery lock. If so, return.
+ * 2c) Check if the same voltage swing level has been used 5 consecutive
+ * times or if the maximum level has been reached. If so, return.
+ * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ * requested by the RX device.
+ * 2e) Loop back to 2a.
* For a more detailed description of the clock recovery sequence, see section
* 3.5.1.2.1 of the DisplayPort 1.2a specification document.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return The next training state:
- * - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence
- * completed successfully.
- * - XDPTX_TS_FAILURE if writing the drive settings to the RX
- * device was unsuccesful.
- * - XDPTX_TS_ADJUST_LINK_RATE if the clock recovery sequence
- * did not complete successfully.
+ * @return The next training state:
+ * - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence
+ * completed successfully.
+ * - XDPTX_TS_FAILURE if writing the drive settings to the RX
+ * device was unsuccesful.
+ * - XDPTX_TS_ADJUST_LINK_RATE if the clock recovery sequence
+ * did not complete successfully.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
{
- u32 Status;
- u32 DelayUs;
- u8 PrevVsLevel = 0;
- u8 SameVsLevelCount = 0;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ u32 Status;
+ u32 DelayUs;
+ u8 PrevVsLevel = 0;
+ u8 SameVsLevelCount = 0;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- /* Obtain the required delay for clock recovery as specified by the
- * RX device. */
- DelayUs = XDptx_GetTrainingDelay(InstancePtr, XDPTX_TS_CLOCK_RECOVERY);
+ /* Obtain the required delay for clock recovery as specified by the
+ * RX device. */
+ DelayUs = XDptx_GetTrainingDelay(InstancePtr, XDPTX_TS_CLOCK_RECOVERY);
- /* Start CRLock. */
+ /* Start CRLock. */
- /* Transmit training pattern 1. */
- Status = XDptx_SetTrainingPattern(InstancePtr,
- XDPTX_TRAINING_PATTERN_SET_TP1);
- if (Status != XST_SUCCESS) {
- return XDPTX_TS_FAILURE;
- }
+ /* Transmit training pattern 1. */
+ Status = XDptx_SetTrainingPattern(InstancePtr,
+ XDPTX_TRAINING_PATTERN_SET_TP1);
+ if (Status != XST_SUCCESS) {
+ return XDPTX_TS_FAILURE;
+ }
- /* Start from minimal voltage swing and pre-emphasis levels. */
- LinkConfig->VsLevel = 0;
- LinkConfig->PeLevel = 0;
- Status = XDptx_SetVswingPreemp(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XDPTX_TS_FAILURE;
- }
+ /* Start from minimal voltage swing and pre-emphasis levels. */
+ LinkConfig->VsLevel = 0;
+ LinkConfig->PeLevel = 0;
+ Status = XDptx_SetVswingPreemp(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XDPTX_TS_FAILURE;
+ }
- while (1) {
- /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
- XDptx_WaitUs(InstancePtr, DelayUs);
+ while (1) {
+ /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+ XDptx_WaitUs(InstancePtr, DelayUs);
- /* Get lane and adjustment requests. */
- Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The AUX read failed. */
- return XDPTX_TS_FAILURE;
- }
+ /* Get lane and adjustment requests. */
+ Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The AUX read failed. */
+ return XDPTX_TS_FAILURE;
+ }
- /* Check if all lanes have realized and maintained the frequency
- * loc and get adjustment requests. */
- Status = XDptx_CheckClockRecovery(InstancePtr,
- InstancePtr->LinkConfig.LaneCount);
- if (Status == XST_SUCCESS) {
- return XDPTX_TS_CHANNEL_EQUALIZATION;
- }
+ /* Check if all lanes have realized and maintained the frequency
+ * lock and get adjustment requests. */
+ Status = XDptx_CheckClockRecovery(InstancePtr,
+ InstancePtr->LinkConfig.LaneCount);
+ if (Status == XST_SUCCESS) {
+ return XDPTX_TS_CHANNEL_EQUALIZATION;
+ }
- /* Check if the same voltage swing for each lane has been used 5
- * consecutive times. */
- if (PrevVsLevel == LinkConfig->VsLevel) {
- SameVsLevelCount++;
- }
- else {
- SameVsLevelCount = 0;
- PrevVsLevel = LinkConfig->VsLevel;
- }
- if (SameVsLevelCount >= 5) {
- break;
- }
+ /* Check if the same voltage swing for each lane has been used 5
+ * consecutive times. */
+ if (PrevVsLevel == LinkConfig->VsLevel) {
+ SameVsLevelCount++;
+ }
+ else {
+ SameVsLevelCount = 0;
+ PrevVsLevel = LinkConfig->VsLevel;
+ }
+ if (SameVsLevelCount >= 5) {
+ break;
+ }
- /* Adjust the drive settings as requested by the RX device. */
- Status = XDptx_AdjVswingPreemp(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The AUX write failed. */
- return XDPTX_TS_FAILURE;
- }
- }
+ /* Adjust the drive settings as requested by the RX device. */
+ Status = XDptx_AdjVswingPreemp(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The AUX write failed. */
+ return XDPTX_TS_FAILURE;
+ }
+ }
- return XDPTX_TS_ADJUST_LINK_RATE;
+ return XDPTX_TS_ADJUST_LINK_RATE;
}
/******************************************************************************/
/**
* This function runs the channel equalization sequence as part of link
* training. The sequence is as follows:
- * 0) Start signaling with the same drive settings used at the end of the
- * clock recovery sequence.
- * 1) Transmit training pattern 2 (or 3) over the main link with symbol
- * scrambling disabled.
- * 2) The channel equalization loop. If channel equalization is
- * unsuccessful after MaxIterations loop iterations, return.
- * 2a) Wait for at least the period of time specified in the RX device's
- * DisplayPort Configuration Data (DPCD) register,
- * TRAINING_AUX_RD_INTERVAL.
- * 2b) Check if all lanes have achieved channel equalization, symbol lock,
- * and interlane alignment. If so, return.
- * 2c) Check if the same voltage swing level has been used 5 consecutive
- * times or if the maximum level has been reached. If so, return.
- * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
- * requested by the RX device.
- * 2e) Loop back to 2a.
+ * 0) Start signaling with the same drive settings used at the end of the
+ * clock recovery sequence.
+ * 1) Transmit training pattern 2 (or 3) over the main link with symbol
+ * scrambling disabled.
+ * 2) The channel equalization loop. If channel equalization is
+ * unsuccessful after MaxIterations loop iterations, return.
+ * 2a) Wait for at least the period of time specified in the RX device's
+ * DisplayPort Configuration Data (DPCD) register,
+ * TRAINING_AUX_RD_INTERVAL.
+ * 2b) Check if all lanes have achieved channel equalization, symbol lock,
+ * and interlane alignment. If so, return.
+ * 2c) Check if the same voltage swing level has been used 5 consecutive
+ * times or if the maximum level has been reached. If so, return.
+ * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
+ * requested by the RX device.
+ * 2e) Loop back to 2a.
* For a more detailed description of the channel equalization sequence, see
* section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param MaxIterations is the maximum number of times to loop through the
- * clock recovery sequence before down-shifting to a reduced data
- * rate or a reduced number of lanes.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param MaxIterations is the maximum number of times to loop through the
+ * clock recovery sequence before down-shifting to a reduced data
+ * rate or a reduced number of lanes.
*
- * @return The next training state:
- * - XDPTX_TS_SUCCESS if training succeeded.
- * - XDPTX_TS_FAILURE if writing the drive settings to the RX
- * device was unsuccesful.
- * - XDPTX_TS_ADJUST_LINK_RATE if, after MaxIterations loop
- * iterations, the channel equalization sequence did not complete
- * successfully.
+ * @return The next training state:
+ * - XDPTX_TS_SUCCESS if training succeeded.
+ * - XDPTX_TS_FAILURE if writing the drive settings to the RX
+ * device was unsuccesful.
+ * - XDPTX_TS_ADJUST_LINK_RATE if, after MaxIterations loop
+ * iterations, the channel equalization sequence did not complete
+ * successfully.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
- XDptx *InstancePtr, u32 MaxIterations)
+ XDptx *InstancePtr, u32 MaxIterations)
{
- u32 Status;
- u32 DelayUs;
- u32 IterationCount = 0;
- u8 PrevVsLevel = 0;
- u8 SameVsLevelCount = 0;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ u32 Status;
+ u32 DelayUs;
+ u32 IterationCount = 0;
+ u8 PrevVsLevel = 0;
+ u8 SameVsLevelCount = 0;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- /* Obtain the required delay for channel equalization as specified by
- * the RX device. */
- DelayUs = XDptx_GetTrainingDelay(InstancePtr,
- XDPTX_TS_CHANNEL_EQUALIZATION);
+ /* Obtain the required delay for channel equalization as specified by
+ * the RX device. */
+ DelayUs = XDptx_GetTrainingDelay(InstancePtr,
+ XDPTX_TS_CHANNEL_EQUALIZATION);
- /* Start channel equalization. */
+ /* Start channel equalization. */
- /* Write the current drive settings to the RX device. */
- Status = XDptx_SetVswingPreemp(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XDPTX_TS_FAILURE;
- }
+ /* Write the current drive settings to the RX device. */
+ Status = XDptx_SetVswingPreemp(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XDPTX_TS_FAILURE;
+ }
- /* Transmit training pattern 2/3. */
- if (InstancePtr->RxConfig.DpcdRxCapsField[XDPTX_DPCD_MAX_LANE_COUNT] &
- XDPTX_DPCD_TPS3_SUPPORT_MASK) {
- Status = XDptx_SetTrainingPattern(InstancePtr,
- XDPTX_TRAINING_PATTERN_SET_TP3);
- }
- else {
- Status = XDptx_SetTrainingPattern(InstancePtr,
- XDPTX_TRAINING_PATTERN_SET_TP2);
- }
- if (Status != XST_SUCCESS) {
- return XDPTX_TS_FAILURE;
- }
+ /* Transmit training pattern 2/3. */
+ if (InstancePtr->RxConfig.DpcdRxCapsField[XDPTX_DPCD_MAX_LANE_COUNT] &
+ XDPTX_DPCD_TPS3_SUPPORT_MASK) {
+ Status = XDptx_SetTrainingPattern(InstancePtr,
+ XDPTX_TRAINING_PATTERN_SET_TP3);
+ }
+ else {
+ Status = XDptx_SetTrainingPattern(InstancePtr,
+ XDPTX_TRAINING_PATTERN_SET_TP2);
+ }
+ if (Status != XST_SUCCESS) {
+ return XDPTX_TS_FAILURE;
+ }
- while (IterationCount < MaxIterations) {
- /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
- XDptx_WaitUs(InstancePtr, DelayUs);
+ while (IterationCount < MaxIterations) {
+ /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
+ XDptx_WaitUs(InstancePtr, DelayUs);
- /* Get lane and adjustment requests. */
- Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The AUX read failed. */
- return XDPTX_TS_FAILURE;
- }
+ /* Get lane and adjustment requests. */
+ Status = XDptx_GetLaneStatusAdjReqs(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The AUX read failed. */
+ return XDPTX_TS_FAILURE;
+ }
- /* Check that all lanes still have their clocks locked. */
- Status = XDptx_CheckClockRecovery(InstancePtr,
- InstancePtr->LinkConfig.LaneCount);
- if (Status != XST_SUCCESS) {
- break;
- }
+ /* Check that all lanes still have their clocks locked. */
+ Status = XDptx_CheckClockRecovery(InstancePtr,
+ InstancePtr->LinkConfig.LaneCount);
+ if (Status != XST_SUCCESS) {
+ break;
+ }
- /* Check that all lanes stihave accomplished channel equalization,
- * symbol lock, and interlane alignment. */
- Status = XDptx_CheckChannelEqualization(InstancePtr,
- InstancePtr->LinkConfig.LaneCount);
- if (Status == XST_SUCCESS) {
- return XDPTX_TS_SUCCESS;
- }
+ /* Check that all lanes stihave accomplished channel
+ * equalization, symbol lock, and interlane alignment. */
+ Status = XDptx_CheckChannelEqualization(InstancePtr,
+ InstancePtr->LinkConfig.LaneCount);
+ if (Status == XST_SUCCESS) {
+ return XDPTX_TS_SUCCESS;
+ }
- /* Check if the same voltage swing for each lane has been used 5
- * consecutive times. */
- if (PrevVsLevel == LinkConfig->VsLevel) {
- SameVsLevelCount++;
- }
- else {
- SameVsLevelCount = 0;
- PrevVsLevel = LinkConfig->VsLevel;
- }
- if (SameVsLevelCount >= 5) {
- break;
- }
+ /* Check if the same voltage swing for each lane has been used 5
+ * consecutive times. */
+ if (PrevVsLevel == LinkConfig->VsLevel) {
+ SameVsLevelCount++;
+ }
+ else {
+ SameVsLevelCount = 0;
+ PrevVsLevel = LinkConfig->VsLevel;
+ }
+ if (SameVsLevelCount >= 5) {
+ break;
+ }
- /* Adjust the drive settings as requested by the RX device. */
- Status = XDptx_AdjVswingPreemp(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The AUX write failed. */
- return XDPTX_TS_FAILURE;
- }
+ /* Adjust the drive settings as requested by the RX device. */
+ Status = XDptx_AdjVswingPreemp(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The AUX write failed. */
+ return XDPTX_TS_FAILURE;
+ }
- IterationCount++;
- }
+ IterationCount++;
+ }
- /* Tried MaxIteration times with no success. Try a reduced bitrate
- * first, then reduce the number of lanes. */
- return XDPTX_TS_ADJUST_LINK_RATE;
+ /* Tried MaxIteration times with no success. Try a reduced bitrate
+ * first, then reduce the number of lanes. */
+ return XDPTX_TS_ADJUST_LINK_RATE;
}
/******************************************************************************/
@@ -1543,47 +1543,47 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
* recovery) at the reduced data rate. If the data rate is already at 1.62 Gbps,
* a downshift in lane count will be attempted.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return The next training state:
- * - XDPTX_TS_ADJUST_LANE_COUNT if the minimal data rate is already
- * in use. Re-attempt training at a reduced lane count.
- * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
+ * @return The next training state:
+ * - XDPTX_TS_ADJUST_LANE_COUNT if the minimal data rate is already
+ * in use. Re-attempt training at a reduced lane count.
+ * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr)
{
- u32 Status;
+ u32 Status;
- switch (InstancePtr->LinkConfig.LinkRate) {
- case XDPTX_LINK_BW_SET_540GBPS:
- Status = XDptx_SetLinkRate(InstancePtr,
- XDPTX_LINK_BW_SET_270GBPS);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
- Status = XDPTX_TS_CLOCK_RECOVERY;
- break;
- case XDPTX_LINK_BW_SET_270GBPS:
- Status = XDptx_SetLinkRate(InstancePtr,
- XDPTX_LINK_BW_SET_162GBPS);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
- Status = XDPTX_TS_CLOCK_RECOVERY;
- break;
- default:
- /* Already at the lowest link rate. Try reducing the lane
- * count next. */
- Status = XDPTX_TS_ADJUST_LANE_COUNT;
- break;
- }
+ switch (InstancePtr->LinkConfig.LinkRate) {
+ case XDPTX_LINK_BW_SET_540GBPS:
+ Status = XDptx_SetLinkRate(InstancePtr,
+ XDPTX_LINK_BW_SET_270GBPS);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
+ Status = XDPTX_TS_CLOCK_RECOVERY;
+ break;
+ case XDPTX_LINK_BW_SET_270GBPS:
+ Status = XDptx_SetLinkRate(InstancePtr,
+ XDPTX_LINK_BW_SET_162GBPS);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
+ Status = XDPTX_TS_CLOCK_RECOVERY;
+ break;
+ default:
+ /* Already at the lowest link rate. Try reducing the lane
+ * count next. */
+ Status = XDPTX_TS_ADJUST_LANE_COUNT;
+ break;
+ }
- return Status;
+ return Status;
}
/******************************************************************************/
@@ -1594,66 +1594,66 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr)
* and training will be re-attempted (starting with clock recovery) at this
* lower lane count.
*
- * @note Training will be re-attempted with the maximum data rate being
- * used with the reduced lane count to train at the main link at
- * the maximum bandwidth possible.
+ * @note Training will be re-attempted with the maximum data rate being
+ * used with the reduced lane count to train at the main link at
+ * the maximum bandwidth possible.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return The next training state:
- * - XDPTX_TS_FAILURE if only one lane is already in use.
- * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
+ * @return The next training state:
+ * - XDPTX_TS_FAILURE if only one lane is already in use.
+ * - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount(
- XDptx *InstancePtr)
+ XDptx *InstancePtr)
{
- u32 Status;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ u32 Status;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- switch (LinkConfig->LaneCount) {
- case XDPTX_LANE_COUNT_SET_4:
- Status = XDptx_SetLaneCount(InstancePtr,
- XDPTX_LANE_COUNT_SET_2);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
+ switch (LinkConfig->LaneCount) {
+ case XDPTX_LANE_COUNT_SET_4:
+ Status = XDptx_SetLaneCount(InstancePtr,
+ XDPTX_LANE_COUNT_SET_2);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
- Status = XDptx_SetLinkRate(InstancePtr,
- LinkConfig->MaxLinkRate);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
- Status = XDPTX_TS_CLOCK_RECOVERY;
- break;
- case XDPTX_LANE_COUNT_SET_2:
- Status = XDptx_SetLaneCount(InstancePtr,
- XDPTX_LANE_COUNT_SET_1);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
+ Status = XDptx_SetLinkRate(InstancePtr,
+ LinkConfig->MaxLinkRate);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
+ Status = XDPTX_TS_CLOCK_RECOVERY;
+ break;
+ case XDPTX_LANE_COUNT_SET_2:
+ Status = XDptx_SetLaneCount(InstancePtr,
+ XDPTX_LANE_COUNT_SET_1);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
- Status = XDptx_SetLinkRate(InstancePtr,
- LinkConfig->MaxLinkRate);
- if (Status != XST_SUCCESS) {
- Status = XDPTX_TS_FAILURE;
- break;
- }
- Status = XDPTX_TS_CLOCK_RECOVERY;
- break;
- default:
- /* Already at the lowest lane count. Training has failed at the
- * lowest lane count and link rate. */
- Status = XDPTX_TS_FAILURE;
- break;
- }
+ Status = XDptx_SetLinkRate(InstancePtr,
+ LinkConfig->MaxLinkRate);
+ if (Status != XST_SUCCESS) {
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
+ Status = XDPTX_TS_CLOCK_RECOVERY;
+ break;
+ default:
+ /* Already at the lowest lane count. Training has failed at the
+ * lowest lane count and link rate. */
+ Status = XDPTX_TS_FAILURE;
+ break;
+ }
- return Status;
+ return Status;
}
/******************************************************************************/
@@ -1663,28 +1663,28 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount(
* XDptx_CheckClockRecovery, XDptx_CheckChannelEqualization, and
* XDptx_AdjVswingPreemp.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the AUX read was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the AUX read was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr)
{
- u32 Status;
+ u32 Status;
- /* Read and store 4 bytes of lane status and 2 bytes of adjustment
- * requests. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_STATUS_LANE_0_1,
- 6, InstancePtr->RxConfig.LaneStatusAdjReqs);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Read and store 4 bytes of lane status and 2 bytes of adjustment
+ * requests. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_STATUS_LANE_0_1,
+ 6, InstancePtr->RxConfig.LaneStatusAdjReqs);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -1694,53 +1694,53 @@ static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr)
* successful - the RX device's link clock and data recovery unit has realized
* and maintained the frequency lock for all lanes currently in use.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LaneCount is the number of lanes to check.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LaneCount is the number of lanes to check.
*
* @return
- * - XST_SUCCESS if the RX device's clock recovery PLL has
- * achieved frequency lock for all lanes in use.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the RX device's clock recovery PLL has
+ * achieved frequency lock for all lanes in use.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
{
- u32 Status;
- u8 AuxData[6];
+ u32 Status;
+ u8 AuxData[6];
- u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
+ u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
- /* Check that all LANEx_CR_DONE bits are set. */
- switch (LaneCount) {
- case XDPTX_LANE_COUNT_SET_4:
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK)) {
- return XST_FAILURE;
- }
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 1. */
- case XDPTX_LANE_COUNT_SET_2:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 0. */
- case XDPTX_LANE_COUNT_SET_1:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK)) {
- return XST_FAILURE;
- }
- default:
- /* All (LaneCount) lanes have achieved clock recovery. */
- break;
- }
+ /* Check that all LANEx_CR_DONE bits are set. */
+ switch (LaneCount) {
+ case XDPTX_LANE_COUNT_SET_4:
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 1. */
+ case XDPTX_LANE_COUNT_SET_2:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 0. */
+ case XDPTX_LANE_COUNT_SET_1:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ default:
+ /* All (LaneCount) lanes have achieved clock recovery. */
+ break;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -1750,87 +1750,87 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
* successful - the RX device has achieved channel equalization, symbol lock,
* and interlane alignment for all lanes currently in use.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param LaneCount is the number of lanes to check.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param LaneCount is the number of lanes to check.
*
* @return
- * - XST_SUCCESS if the RX device has achieved channel
- * equalization symbol lock, and interlane alignment for all
- * lanes in use.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the RX device has achieved channel
+ * equalization symbol lock, and interlane alignment for all
+ * lanes in use.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
{
- u32 Status;
- u8 AuxData[6];
- u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
+ u32 Status;
+ u8 AuxData[6];
+ u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
- /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
- switch (LaneCount) {
- case XDPTX_LANE_COUNT_SET_4:
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK)) {
- return XST_FAILURE;
- }
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 1. */
- case XDPTX_LANE_COUNT_SET_2:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 0. */
- case XDPTX_LANE_COUNT_SET_1:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK)) {
- return XST_FAILURE;
- }
- default:
- /* All (LaneCount) lanes have achieved channel equalization. */
- break;
- }
+ /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
+ switch (LaneCount) {
+ case XDPTX_LANE_COUNT_SET_4:
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 1. */
+ case XDPTX_LANE_COUNT_SET_2:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 0. */
+ case XDPTX_LANE_COUNT_SET_1:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ default:
+ /* All (LaneCount) lanes have achieved channel equalization. */
+ break;
+ }
- /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
- switch (LaneCount) {
- case XDPTX_LANE_COUNT_SET_4:
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK)) {
- return XST_FAILURE;
- }
- if (!(LaneStatus[1] &
- XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 1. */
- case XDPTX_LANE_COUNT_SET_2:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK)) {
- return XST_FAILURE;
- }
- /* Drop through and check lane 0. */
- case XDPTX_LANE_COUNT_SET_1:
- if (!(LaneStatus[0] &
- XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK)) {
- return XST_FAILURE;
- }
- default:
- /* All (LaneCount) lanes have achieved symbol lock. */
- break;
- }
+ /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
+ switch (LaneCount) {
+ case XDPTX_LANE_COUNT_SET_4:
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ if (!(LaneStatus[1] &
+ XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 1. */
+ case XDPTX_LANE_COUNT_SET_2:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ /* Drop through and check lane 0. */
+ case XDPTX_LANE_COUNT_SET_1:
+ if (!(LaneStatus[0] &
+ XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK)) {
+ return XST_FAILURE;
+ }
+ default:
+ /* All (LaneCount) lanes have achieved symbol lock. */
+ break;
+ }
- /* Check that interlane alignment is done. */
- if (!(LaneStatus[2] &
- XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) {
- return XST_FAILURE;
- }
+ /* Check that interlane alignment is done. */
+ if (!(LaneStatus[2] &
+ XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -1838,87 +1838,88 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
* This function sets current voltage swing and pre-emphasis level settings from
* the LinkConfig structure to hardware.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if writing the settings was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if writing the settings was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note 7-series FPGAs registers use the terminology POSTCURSOR(1) to
+ * represent the DisplayPort pre-emphasis levels.
*
*******************************************************************************/
static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
{
- u32 Status;
- u8 Data;
- u8 AuxData[4];
- u8 Index;
- u8 VsLevelRx = InstancePtr->LinkConfig.VsLevel;
- u8 PeLevelRx = InstancePtr->LinkConfig.PeLevel;
- u32 VsLevel;
- u32 PeLevel;
- u32 VsLevels[4] = {XDPTX_VS_LEVEL_0, XDPTX_VS_LEVEL_1,
- XDPTX_VS_LEVEL_2, XDPTX_VS_LEVEL_3};
- u32 PeLevels[4] = {XDPTX_PE_LEVEL_0, XDPTX_PE_LEVEL_1,
- XDPTX_PE_LEVEL_2, XDPTX_PE_LEVEL_3};
+ u32 Status;
+ u8 Data;
+ u8 AuxData[4];
+ u8 Index;
+ u8 VsLevelRx = InstancePtr->LinkConfig.VsLevel;
+ u8 PeLevelRx = InstancePtr->LinkConfig.PeLevel;
+ u32 VsLevel;
+ u32 PeLevel;
+ u32 VsLevels[4] = {XDPTX_VS_LEVEL_0, XDPTX_VS_LEVEL_1,
+ XDPTX_VS_LEVEL_2, XDPTX_VS_LEVEL_3};
+ u32 PeLevels[4] = {XDPTX_PE_LEVEL_0, XDPTX_PE_LEVEL_1,
+ XDPTX_PE_LEVEL_2, XDPTX_PE_LEVEL_3};
- if (InstancePtr->HasRedriverInPath == 0) {
- PeLevel = PeLevels[PeLevelRx];
- VsLevel = VsLevels[VsLevelRx];
+ if (InstancePtr->HasRedriverInPath == 0) {
+ PeLevel = PeLevels[PeLevelRx];
+ VsLevel = VsLevels[VsLevelRx];
- /* Need to compensate due to no redriver in the path. */
- if (PeLevelRx != 0) {
- VsLevel += XDPTX_VS_LEVEL_OFFSET;
- }
- }
- else {
- /* No need to compensate since redriver does that. Can evenly
- * disperse the voltage swing and pre-emphasis levels. */
+ /* Need to compensate due to no redriver in the path. */
+ if (PeLevelRx != 0) {
+ VsLevel += XDPTX_VS_LEVEL_OFFSET;
+ }
+ }
+ else {
+ /* No need to compensate since redriver does that. Can evenly
+ * disperse the voltage swing and pre-emphasis levels. */
- /* Map 16 possible voltage swing levels in the DisplayPort TX
- * core to 4 possible in the RX device. */
- VsLevel = VsLevelRx * 4 + 2;
- /* Map 32 possible pre-emphasis levels in the DisplayPort TX
- * core to 4 possible in the RX device. */
- PeLevel = PeLevelRx * 8 + 4;
- }
+ /* Map 16 possible voltage swing levels in the DisplayPort TX
+ * core to 4 possible in the RX device. */
+ VsLevel = VsLevelRx * 4 + 2;
+ /* Map 32 possible pre-emphasis levels in the DisplayPort TX
+ * core to 4 possible in the RX device. */
+ PeLevel = PeLevelRx * 8 + 4;
+ }
- /* Set up the data buffer for writing to the RX device. */
- Data = (PeLevelRx << XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
- VsLevelRx;
- /* The maximum voltage swing has been reached. */
- if (VsLevelRx == XDPTX_MAXIMUM_VS_LEVEL) {
- Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
- }
- /* The maximum pre-emphasis level has been reached. */
- if (PeLevelRx == XDPTX_MAXIMUM_PE_LEVEL) {
- Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
- }
- memset(AuxData, Data, InstancePtr->LinkConfig.LaneCount);
+ /* Set up the data buffer for writing to the RX device. */
+ Data = (PeLevelRx << XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
+ VsLevelRx;
+ /* The maximum voltage swing has been reached. */
+ if (VsLevelRx == XDPTX_MAXIMUM_VS_LEVEL) {
+ Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
+ }
+ /* The maximum pre-emphasis level has been reached. */
+ if (PeLevelRx == XDPTX_MAXIMUM_PE_LEVEL) {
+ Data |= XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
+ }
+ memset(AuxData, Data, InstancePtr->LinkConfig.LaneCount);
- for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) {
- /* Disable pre-cursor levels. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0);
+ for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) {
+ /* Disable pre-cursor levels. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0x0);
- /* Write new voltage swing levels to the TX registers. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel);
+ /* Write new voltage swing levels to the TX registers. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel);
- /* Write new pre-emphasis levels to the TX registers. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel);
- }
+ /* Write new pre-emphasis levels to the TX registers. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel);
+ }
- /* Write the voltage swing and pre-emphasis levels for each lane to the
- * RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TRAINING_LANE0_SET,
- InstancePtr->LinkConfig.LaneCount, AuxData);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write the voltage swing and pre-emphasis levels for each lane to the
+ * RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TRAINING_LANE0_SET,
+ InstancePtr->LinkConfig.LaneCount, AuxData);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -1926,78 +1927,78 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
* This function sets new voltage swing and pre-emphasis levels using the
* adjustment requests obtained from the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the new levels were written successfully.
- * - XST_FAILURE otherwise (an AUX transaction failed).
+ * - XST_SUCCESS if the new levels were written successfully.
+ * - XST_FAILURE otherwise (an AUX transaction failed).
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
{
- u32 Status;
- u8 Index;
- u8 VsLevelAdjReq[4];
- u8 PeLevelAdjReq[4];
- u8 *AdjReqs = &InstancePtr->RxConfig.LaneStatusAdjReqs[4];
+ u32 Status;
+ u8 Index;
+ u8 VsLevelAdjReq[4];
+ u8 PeLevelAdjReq[4];
+ u8 *AdjReqs = &InstancePtr->RxConfig.LaneStatusAdjReqs[4];
- /* Analyze the adjustment requests for changes in voltage swing and
- * pre-emphasis levels. */
- VsLevelAdjReq[0] = AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
- VsLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
- VsLevelAdjReq[2] = AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
- VsLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
- PeLevelAdjReq[0] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
- PeLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
- PeLevelAdjReq[2] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
- PeLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
- XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
+ /* Analyze the adjustment requests for changes in voltage swing and
+ * pre-emphasis levels. */
+ VsLevelAdjReq[0] = AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
+ VsLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
+ VsLevelAdjReq[2] = AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
+ VsLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
+ PeLevelAdjReq[0] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
+ PeLevelAdjReq[1] = (AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
+ PeLevelAdjReq[2] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
+ PeLevelAdjReq[3] = (AdjReqs[1] & XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
+ XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
- /* Change the drive settings to match the adjustment requests. Use the
- * greatest level requested. */
- InstancePtr->LinkConfig.VsLevel = 0;
- InstancePtr->LinkConfig.PeLevel = 0;
- for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) {
- if (VsLevelAdjReq[Index] >InstancePtr->LinkConfig.VsLevel) {
- InstancePtr->LinkConfig.VsLevel = VsLevelAdjReq[Index];
- }
- if (PeLevelAdjReq[Index] >InstancePtr->LinkConfig.PeLevel) {
- InstancePtr->LinkConfig.PeLevel = PeLevelAdjReq[Index];
- }
- }
+ /* Change the drive settings to match the adjustment requests. Use the
+ * greatest level requested. */
+ InstancePtr->LinkConfig.VsLevel = 0;
+ InstancePtr->LinkConfig.PeLevel = 0;
+ for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) {
+ if (VsLevelAdjReq[Index] >InstancePtr->LinkConfig.VsLevel) {
+ InstancePtr->LinkConfig.VsLevel = VsLevelAdjReq[Index];
+ }
+ if (PeLevelAdjReq[Index] >InstancePtr->LinkConfig.PeLevel) {
+ InstancePtr->LinkConfig.PeLevel = PeLevelAdjReq[Index];
+ }
+ }
- /* Verify that the voltage swing and pre-emphasis combination is
- * allowed. Some combinations will result in a differential peak-to-peak
- * voltage that is outside the permissable range. See the VESA
- * DisplayPort v1.2 Specification, section 3.1.5.2.
- * The valid combinations are:
- * PE=0 PE=1 PE=2 PE=3
- * VS=0 Valid Valid Valid Valid
- * VS=1 Valid Valid Valid
- * VS=2 Valid Valid
- * VS=3 Valid
- */
- if (InstancePtr->LinkConfig.PeLevel >
- (4 - InstancePtr->LinkConfig.VsLevel)) {
- InstancePtr->LinkConfig.PeLevel =
- 4 - InstancePtr->LinkConfig.VsLevel;
- }
+ /* Verify that the voltage swing and pre-emphasis combination is
+ * allowed. Some combinations will result in a differential peak-to-peak
+ * voltage that is outside the permissable range. See the VESA
+ * DisplayPort v1.2 Specification, section 3.1.5.2.
+ * The valid combinations are:
+ * PE=0 PE=1 PE=2 PE=3
+ * VS=0 Valid Valid Valid Valid
+ * VS=1 Valid Valid Valid
+ * VS=2 Valid Valid
+ * VS=3 Valid
+ */
+ if (InstancePtr->LinkConfig.PeLevel >
+ (4 - InstancePtr->LinkConfig.VsLevel)) {
+ InstancePtr->LinkConfig.PeLevel =
+ 4 - InstancePtr->LinkConfig.VsLevel;
+ }
- /* Make the adjustments to both the DisplayPort TX core and the RX
- * device. */
- Status = XDptx_SetVswingPreemp(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Make the adjustments to both the DisplayPort TX core and the RX
+ * device. */
+ Status = XDptx_SetVswingPreemp(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -2005,45 +2006,44 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
* This function sets the training pattern to be used during link training for
* both the DisplayPort TX core and the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Pattern selects the pattern to be used. One of the following:
- * - XDPTX_TRAINING_PATTERN_SET_OFF
- * - XDPTX_TRAINING_PATTERN_SET_TP1
- * - XDPTX_TRAINING_PATTERN_SET_TP2
- * - XDPTX_TRAINING_PATTERN_SET_TP3
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Pattern selects the pattern to be used. One of the following:
+ * - XDPTX_TRAINING_PATTERN_SET_OFF
+ * - XDPTX_TRAINING_PATTERN_SET_TP1
+ * - XDPTX_TRAINING_PATTERN_SET_TP2
+ * - XDPTX_TRAINING_PATTERN_SET_TP3
*
* @return
- * - XST_SUCCESS if setting the pattern was successful.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if setting the pattern was successful.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern)
{
- u32 Status;
- u8 RegVal;
+ u32 Status;
+ u8 RegVal;
- /* Write to the DisplayPort TX core. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_TRAINING_PATTERN_SET, Pattern);
+ /* Write to the DisplayPort TX core. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_TRAINING_PATTERN_SET, Pattern);
- /* Preserve the current RX device settings. */
- Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
- RegVal &= ~XDPTX_DPCD_TP_SEL_MASK;
- RegVal |= (Pattern & XDPTX_DPCD_TP_SEL_MASK);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Preserve the current RX device settings. */
+ Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
+ RegVal &= ~XDPTX_DPCD_TP_SEL_MASK;
+ RegVal |= (Pattern & XDPTX_DPCD_TP_SEL_MASK);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- /* Write to the RX device. */
- Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1,
- &RegVal);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Write to the RX device. */
+ Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -2051,53 +2051,53 @@ static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern)
* This function determines what the RX device's required training delay is for
* link training.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param TrainingState is the current training state; either clock
- * recovery or channel equalization.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param TrainingState is the current training state; either clock
+ * recovery or channel equalization.
*
- * @return The training delay specified in the RX device's DisplayPort
- * Configuration Data (DPCD) register,
- * XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL.
+ * @return The training delay specified in the RX device's DisplayPort
+ * Configuration Data (DPCD) register,
+ * XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr,
- XDptx_TrainingState TrainingState)
+ XDptx_TrainingState TrainingState)
{
- u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
- u16 Delay;
+ u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
+ u16 Delay;
- switch (Dpcd[XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL]) {
- case XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US:
- if (TrainingState == XDPTX_TS_CLOCK_RECOVERY) {
- /* Delay for the clock recovery phase. */
- Delay = 100;
- }
- else {
- /* Delay for the channel equalization phase. */
- Delay = 400;
- }
- break;
- case XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS:
- Delay = 4000;
- break;
- case XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS:
- Delay = 8000;
- break;
- case XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS:
- Delay = 12000;
- break;
- case XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS:
- Delay = 16000;
- break;
- default:
- /* Default to 20 ms. */
- Delay = 20000;
- break;
- }
+ switch (Dpcd[XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL]) {
+ case XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US:
+ if (TrainingState == XDPTX_TS_CLOCK_RECOVERY) {
+ /* Delay for the clock recovery phase. */
+ Delay = 100;
+ }
+ else {
+ /* Delay for the channel equalization phase. */
+ Delay = 400;
+ }
+ break;
+ case XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS:
+ Delay = 4000;
+ break;
+ case XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS:
+ Delay = 8000;
+ break;
+ case XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS:
+ Delay = 12000;
+ break;
+ case XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS:
+ Delay = 16000;
+ break;
+ default:
+ /* Default to 20 ms. */
+ Delay = 20000;
+ break;
+ }
- return Delay;
+ return Delay;
}
/******************************************************************************/
@@ -2105,77 +2105,77 @@ static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr,
* This function contains the common sequence of submitting an AUX command for
* AUX read, AUX write, I2C-over-AUX read, and I2C-over-AUX write transactions.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param CmdType is the type of AUX command (one of: XDPTX_AUX_CMD_READ,
- * XDPTX_AUX_CMD_WRITE, XDPTX_AUX_CMD_I2C_READ, or
- * XDPTX_AUX_CMD_I2C_WRITE.
- * @param Address is the starting address that the AUX transaction will
- * read/write from/to the RX device.
- * @param NumBytes is the number of bytes to read/write from/to the RX
- * device.
- * @param Data is a pointer to the data buffer that contains the data
- * to be read/written from/to the RX device.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param CmdType is the type of AUX command (one of: XDPTX_AUX_CMD_READ,
+ * XDPTX_AUX_CMD_WRITE, XDPTX_AUX_CMD_I2C_READ, or
+ * XDPTX_AUX_CMD_I2C_WRITE.
+ * @param Address is the starting address that the AUX transaction will
+ * read/write from/to the RX device.
+ * @param NumBytes is the number of bytes to read/write from/to the RX
+ * device.
+ * @param Data is a pointer to the data buffer that contains the data
+ * to be read/written from/to the RX device.
*
* @return
- * - XST_SUCCESS if the AUX transaction request was acknowledged.
- * - XST_ERROR_COUNT_MAX if the AUX request timed out.
- * - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
- * reply code or if the AUX transaction failed).
+ * - XST_SUCCESS if the AUX transaction request was acknowledged.
+ * - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ * - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
+ * reply code or if the AUX transaction failed).
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
- u32 NumBytes, u8 *Data)
+ u32 NumBytes, u8 *Data)
{
- u32 Status;
- XDptx_AuxTransaction Request;
- u32 BytesLeft;
+ u32 Status;
+ XDptx_AuxTransaction Request;
+ u32 BytesLeft;
- /* Set the start address for AUX transactions. For I2C transactions,
- * this is the address of the I2C bus. */
- Request.Address = Address;
+ /* Set the start address for AUX transactions. For I2C transactions,
+ * this is the address of the I2C bus. */
+ Request.Address = Address;
- BytesLeft = NumBytes;
- while (BytesLeft > 0) {
- Request.CmdCode = CmdType;
+ BytesLeft = NumBytes;
+ while (BytesLeft > 0) {
+ Request.CmdCode = CmdType;
- if ((CmdType == XDPTX_AUX_CMD_READ) ||
- (CmdType == XDPTX_AUX_CMD_WRITE)) {
- /* Increment address for normal AUX transactions. */
- Request.Address = Address + (NumBytes - BytesLeft);
- }
+ if ((CmdType == XDPTX_AUX_CMD_READ) ||
+ (CmdType == XDPTX_AUX_CMD_WRITE)) {
+ /* Increment address for normal AUX transactions. */
+ Request.Address = Address + (NumBytes - BytesLeft);
+ }
- /* Increment the pointer to the supplied data buffer. */
- Request.Data = &Data[NumBytes - BytesLeft];
+ /* Increment the pointer to the supplied data buffer. */
+ Request.Data = &Data[NumBytes - BytesLeft];
- if (BytesLeft > 16) {
- Request.NumBytes = 16;
- }
- else {
- Request.NumBytes = BytesLeft;
- }
- BytesLeft -= Request.NumBytes;
+ if (BytesLeft > 16) {
+ Request.NumBytes = 16;
+ }
+ else {
+ Request.NumBytes = BytesLeft;
+ }
+ BytesLeft -= Request.NumBytes;
- if ((CmdType == XDPTX_AUX_CMD_I2C_READ) && (BytesLeft > 0)) {
- /* Middle of a transaction I2C read request. Override
- * the command code that was set to CmdType. */
- Request.CmdCode = XDPTX_AUX_CMD_I2C_READ_MOT;
- }
- else if ((CmdType == XDPTX_AUX_CMD_I2C_WRITE) &&
- (BytesLeft > 0)) {
- /* Middle of a transaction I2C write request. Override
- * the command code that was set to CmdType. */
- Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
- }
+ if ((CmdType == XDPTX_AUX_CMD_I2C_READ) && (BytesLeft > 0)) {
+ /* Middle of a transaction I2C read request. Override
+ * the command code that was set to CmdType. */
+ Request.CmdCode = XDPTX_AUX_CMD_I2C_READ_MOT;
+ }
+ else if ((CmdType == XDPTX_AUX_CMD_I2C_WRITE) &&
+ (BytesLeft > 0)) {
+ /* Middle of a transaction I2C write request. Override
+ * the command code that was set to CmdType. */
+ Request.CmdCode = XDPTX_AUX_CMD_I2C_WRITE_MOT;
+ }
- Status = XDptx_AuxRequest(InstancePtr, &Request);
- if (Status != XST_SUCCESS) {
- return Status;
- }
- }
+ Status = XDptx_AuxRequest(InstancePtr, &Request);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -2185,58 +2185,58 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
* indicates that the request was deferred, the request is sent again (up to a
* maximum specified by XDPTX_AUX_MAX_DEFER_COUNT|XDPTX_AUX_MAX_TIMEOUT_COUNT).
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Request is a pointer to an initialized XDptx_AuxTransaction
- * structure containing the required information for issuing an
- * AUX command, as well as a write buffer used for write commands,
- * and a read buffer for read commands.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Request is a pointer to an initialized XDptx_AuxTransaction
+ * structure containing the required information for issuing an
+ * AUX command, as well as a write buffer used for write commands,
+ * and a read buffer for read commands.
*
* @return
- * - XST_SUCCESS if the request was acknowledged.
- * - XST_ERROR_COUNT_MAX if resending the request exceeded the
- * maximum for deferral and timeout.
- * - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
- * reply code or if the AUX transaction failed).
+ * - XST_SUCCESS if the request was acknowledged.
+ * - XST_ERROR_COUNT_MAX if resending the request exceeded the
+ * maximum for deferral and timeout.
+ * - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
+ * reply code or if the AUX transaction failed).
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request)
{
- u32 Status;
- u32 DeferCount = 0;
- u32 TimeoutCount = 0;
+ u32 Status;
+ u32 DeferCount = 0;
+ u32 TimeoutCount = 0;
- while ((DeferCount < XDPTX_AUX_MAX_DEFER_COUNT) &&
- (TimeoutCount < XDPTX_AUX_MAX_TIMEOUT_COUNT)) {
- Status = XDptx_AuxWaitReady(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* The RX device isn't ready yet. */
- TimeoutCount++;
- continue;
- }
+ while ((DeferCount < XDPTX_AUX_MAX_DEFER_COUNT) &&
+ (TimeoutCount < XDPTX_AUX_MAX_TIMEOUT_COUNT)) {
+ Status = XDptx_AuxWaitReady(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* The RX device isn't ready yet. */
+ TimeoutCount++;
+ continue;
+ }
- /* Send the request. */
- Status = XDptx_AuxRequestSend(InstancePtr, Request);
- if (Status == XST_SEND_ERROR) {
- /* The request was deferred. */
- DeferCount++;
- }
- else if (Status == XST_ERROR_COUNT_MAX) {
- /* Waiting for a reply timed out. */
- TimeoutCount++;
- }
- else {
- /* XST_FAILURE indicates that the request was NACK'ed,
- * XST_SUCCESS indicates that the request was ACK'ed. */
- return Status;
- }
+ /* Send the request. */
+ Status = XDptx_AuxRequestSend(InstancePtr, Request);
+ if (Status == XST_SEND_ERROR) {
+ /* The request was deferred. */
+ DeferCount++;
+ }
+ else if (Status == XST_ERROR_COUNT_MAX) {
+ /* Waiting for a reply timed out. */
+ TimeoutCount++;
+ }
+ else {
+ /* XST_FAILURE indicates that the request was NACK'ed,
+ * XST_SUCCESS indicates that the request was ACK'ed. */
+ return Status;
+ }
- XDptx_WaitUs(InstancePtr, 100);
- }
+ XDptx_WaitUs(InstancePtr, 100);
+ }
- /* The request was not successfully received by the RX device. */
- return XST_ERROR_COUNT_MAX;
+ /* The request was not successfully received by the RX device. */
+ return XST_ERROR_COUNT_MAX;
}
/******************************************************************************/
@@ -2245,82 +2245,81 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request)
* channel by writing the command, the destination address, (the write buffer
* for write commands), and the data size to the DisplayPort TX core.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Request is a pointer to an initialized XDptx_AuxTransaction
- * structure containing the required information for issuing an AUX
- * command.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Request is a pointer to an initialized XDptx_AuxTransaction
+ * structure containing the required information for issuing an AUX
+ * command.
*
* @return
- * - XST_SUCCESS if the request was acknowledged.
- * - XST_ERROR_COUNT_MAX if waiting for a reply timed out.
- * - XST_SEND_ERROR if the request was deferred.
- * - XST_FAILURE otherwise, if the request was NACK'ed.
+ * - XST_SUCCESS if the request was acknowledged.
+ * - XST_ERROR_COUNT_MAX if waiting for a reply timed out.
+ * - XST_SEND_ERROR if the request was deferred.
+ * - XST_FAILURE otherwise, if the request was NACK'ed.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
- XDptx_AuxTransaction *Request)
+ XDptx_AuxTransaction *Request)
{
- u32 Status;
- u8 Index;
+ u32 Status;
+ u8 Index;
- /* Set the address for the request. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_ADDRESS,
- Request->Address);
+ /* Set the address for the request. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_ADDRESS,
+ Request->Address);
- if ((Request->CmdCode == XDPTX_AUX_CMD_WRITE) ||
- (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE) ||
- (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE_MOT)) {
- /* Feed write data into the DisplayPort TX core's write FIFO. */
- for (Index = 0; Index < Request->NumBytes; Index++) {
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_AUX_WRITE_FIFO,
- Request->Data[Index]);
- }
- }
+ if ((Request->CmdCode == XDPTX_AUX_CMD_WRITE) ||
+ (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE) ||
+ (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE_MOT)) {
+ /* Feed write data into the DisplayPort TX core's write FIFO. */
+ for (Index = 0; Index < Request->NumBytes; Index++) {
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_AUX_WRITE_FIFO, Request->Data[Index]);
+ }
+ }
- /* Submit the command and the data size. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_CMD,
- ((Request->CmdCode << XDPTX_AUX_CMD_SHIFT) |
- ((Request->NumBytes - 1) &
- XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK)));
+ /* Submit the command and the data size. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_CMD,
+ ((Request->CmdCode << XDPTX_AUX_CMD_SHIFT) |
+ ((Request->NumBytes - 1) &
+ XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK)));
- /* Check for a reply from the RX device to the submitted request. */
- Status = XDptx_AuxWaitReply(InstancePtr);
- if (Status != XST_SUCCESS) {
- /* Waiting for a reply timed out. */
- return XST_ERROR_COUNT_MAX;
- }
+ /* Check for a reply from the RX device to the submitted request. */
+ Status = XDptx_AuxWaitReply(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ /* Waiting for a reply timed out. */
+ return XST_ERROR_COUNT_MAX;
+ }
- /* Analyze the reply. */
- Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_AUX_REPLY_CODE);
- if ((Status == XDPTX_AUX_REPLY_CODE_DEFER) ||
- (Status == XDPTX_AUX_REPLY_CODE_I2C_DEFER)) {
- /* The request was deferred. */
- return XST_SEND_ERROR;
- }
- else if ((Status == XDPTX_AUX_REPLY_CODE_NACK) ||
- (Status == XDPTX_AUX_REPLY_CODE_I2C_NACK)) {
- /* The request was not acknowledged. */
- return XST_FAILURE;
- }
+ /* Analyze the reply. */
+ Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_AUX_REPLY_CODE);
+ if ((Status == XDPTX_AUX_REPLY_CODE_DEFER) ||
+ (Status == XDPTX_AUX_REPLY_CODE_I2C_DEFER)) {
+ /* The request was deferred. */
+ return XST_SEND_ERROR;
+ }
+ else if ((Status == XDPTX_AUX_REPLY_CODE_NACK) ||
+ (Status == XDPTX_AUX_REPLY_CODE_I2C_NACK)) {
+ /* The request was not acknowledged. */
+ return XST_FAILURE;
+ }
- /* The request was acknowledged. */
+ /* The request was acknowledged. */
- if ((Request->CmdCode == XDPTX_AUX_CMD_READ) ||
- (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ) ||
- (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ_MOT)) {
- /* Obtain the read data from the reply FIFO. */
- for (Index = 0; Index < Request->NumBytes; Index++) {
- Request->Data[Index] = XDptx_ReadReg(
- InstancePtr->Config.BaseAddr,
- XDPTX_AUX_REPLY_DATA);
- }
- }
+ if ((Request->CmdCode == XDPTX_AUX_CMD_READ) ||
+ (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ) ||
+ (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ_MOT)) {
+ /* Obtain the read data from the reply FIFO. */
+ for (Index = 0; Index < Request->NumBytes; Index++) {
+ Request->Data[Index] = XDptx_ReadReg(
+ InstancePtr->Config.BaseAddr,
+ XDPTX_AUX_REPLY_DATA);
+ }
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -2328,73 +2327,73 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
* This function waits for a reply indicating that the most recent AUX request
* has been received by the RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if a reply was sent from the RX device.
- * - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
+ * - XST_SUCCESS if a reply was sent from the RX device.
+ * - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AuxWaitReply(XDptx *InstancePtr)
{
- u32 Timeout = 100;
- u32 Status;
+ u32 Timeout = 100;
+ u32 Status;
- while (0 < Timeout) {
- Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_STATUS);
+ while (0 < Timeout) {
+ Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_STATUS);
- /* Check for a timeout. */
- if (Status & XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) {
- return XST_ERROR_COUNT_MAX;
- }
+ /* Check for a timeout. */
+ if (Status & XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) {
+ return XST_ERROR_COUNT_MAX;
+ }
- /* Check for a reply. */
- if (Status & XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK) {
- return XST_SUCCESS;
- }
+ /* Check for a reply. */
+ if (Status & XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK) {
+ return XST_SUCCESS;
+ }
- Timeout--;
- XDptx_WaitUs(InstancePtr, 20);
- }
+ Timeout--;
+ XDptx_WaitUs(InstancePtr, 20);
+ }
- return XST_ERROR_COUNT_MAX;
+ return XST_ERROR_COUNT_MAX;
}
/******************************************************************************/
/**
* This function waits until another request is no longer in progress.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the the RX device is no longer busy.
- * - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
+ * - XST_SUCCESS if the the RX device is no longer busy.
+ * - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_AuxWaitReady(XDptx *InstancePtr)
{
- u32 Status;
- u32 Timeout = 100;
+ u32 Status;
+ u32 Timeout = 100;
- /* Wait until the DisplayPort TX core is ready. */
- do {
- Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_SIG_STATE);
+ /* Wait until the DisplayPort TX core is ready. */
+ do {
+ Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_SIG_STATE);
- /* Protect against an infinite loop. */
- if (!Timeout--) {
- return XST_ERROR_COUNT_MAX;
- }
- XDptx_WaitUs(InstancePtr, 20);
- }
- while (Status & XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
+ /* Protect against an infinite loop. */
+ if (!Timeout--) {
+ return XST_ERROR_COUNT_MAX;
+ }
+ XDptx_WaitUs(InstancePtr, 20);
+ }
+ while (Status & XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
@@ -2402,79 +2401,79 @@ static u32 XDptx_AuxWaitReady(XDptx *InstancePtr)
* This function sets the clock frequency for the DisplayPort PHY corresponding
* to a desired data rate.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param Speed determines what clock frequency will be used based on one
- * of the following selects:
- * - XDPTX_PHY_CLOCK_SELECT_162GBPS = 0x01
- * - XDPTX_PHY_CLOCK_SELECT_270GBPS = 0x03
- * - XDPTX_PHY_CLOCK_SELECT_540GBPS = 0x05
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param Speed determines what clock frequency will be used based on one
+ * of the following selects:
+ * - XDPTX_PHY_CLOCK_SELECT_162GBPS = 0x01
+ * - XDPTX_PHY_CLOCK_SELECT_270GBPS = 0x03
+ * - XDPTX_PHY_CLOCK_SELECT_540GBPS = 0x05
*
* @return
- * - XST_SUCCESS if the reset for each lane is done after the clock
- * frequency has been set.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the reset for each lane is done after the clock
+ * frequency has been set.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed)
{
- u32 Status;
- u32 RegVal;
+ u32 Status;
+ u32 RegVal;
- /* Disable the DisplayPort TX core first. */
- RegVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE);
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0);
+ /* Disable the DisplayPort TX core first. */
+ RegVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE);
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x0);
- /* Change speed of the feedback clock. */
- XDptx_WriteReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_CLOCK_SELECT, Speed);
+ /* Change speed of the feedback clock. */
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_CLOCK_SELECT, Speed);
- /* Re-enable the DisplayPort TX core if it was previously enabled. */
- if (RegVal != 0) {
- XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 1);
- }
+ /* Re-enable the DisplayPort TX core if it was previously enabled. */
+ if (RegVal != 0x0) {
+ XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0x1);
+ }
- /* Wait until the PHY is ready. */
- Status = XDptx_WaitPhyReady(InstancePtr);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
+ /* Wait until the PHY is ready. */
+ Status = XDptx_WaitPhyReady(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function waits for the DisplayPort PHY to come out of reset.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_ERROR_COUNT_MAX if the PHY failed to be ready.
- * - XST_SUCCESS otherwise.
+ * - XST_ERROR_COUNT_MAX if the PHY failed to be ready.
+ * - XST_SUCCESS otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static u32 XDptx_WaitPhyReady(XDptx *InstancePtr)
{
- u32 Timeout = 100;
- u32 PhyStatus;
+ u32 Timeout = 100;
+ u32 PhyStatus;
- /* Wait until the PHY is ready. */
- do {
- PhyStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_PHY_STATUS) &
- XDPTX_PHY_STATUS_ALL_LANES_READY_MASK;
+ /* Wait until the PHY is ready. */
+ do {
+ PhyStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_PHY_STATUS) &
+ XDPTX_PHY_STATUS_ALL_LANES_READY_MASK;
- /* Protect against an infinite loop. */
- if (!Timeout--) {
- return XST_ERROR_COUNT_MAX;
- }
- XDptx_WaitUs(InstancePtr, 20);
- }
- while (PhyStatus != XDPTX_PHY_STATUS_ALL_LANES_READY_MASK);
+ /* Protect against an infinite loop. */
+ if (!Timeout--) {
+ return XST_ERROR_COUNT_MAX;
+ }
+ XDptx_WaitUs(InstancePtr, 20);
+ }
+ while (PhyStatus != XDPTX_PHY_STATUS_ALL_LANES_READY_MASK);
- return XST_SUCCESS;
+ return XST_SUCCESS;
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
index c43184db..792008f3 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
@@ -38,39 +38,39 @@
* Xilinx DisplayPort soft IP core in source (TX) mode.
*
* The Xilinx DisplayPort soft IP supports the following features:
- * - 1, 2, or 4 lanes.
- * - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
- * - 1, 2, or 4 pixel-wide video interfaces.
- * - RGB and YCbCr color space.
- * - Up to 16 bits per component.
- * - Up to 4Kx2K monitor resolution.
- * - Auto lane rate and width negotiation.
- * - I2C over a 1Mb/s AUX channel.
- * - Secondary channel audio support (2 channels).
- * - 4 independent video multi-streams.
+ * - 1, 2, or 4 lanes.
+ * - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
+ * - 1, 2, or 4 pixel-wide video interfaces.
+ * - RGB and YCbCr color space.
+ * - Up to 16 bits per component.
+ * - Up to 4Kx2K monitor resolution.
+ * - Auto lane rate and width negotiation.
+ * - I2C over a 1Mb/s AUX channel.
+ * - Secondary channel audio support (2 channels).
+ * - 4 independent video multi-streams.
*
* The Xilinx DisplayPort soft IP does not support the following features:
- * - The automated test feature.
- * - Audio (3-8 channel).
- * - FAUX.
- * - Bridging function.
- * - MST audio.
- * - eDP optional features.
- * - iDP.
- * - GTC.
+ * - The automated test feature.
+ * - Audio (3-8 channel).
+ * - FAUX.
+ * - Bridging function.
+ * - MST audio.
+ * - eDP optional features.
+ * - iDP.
+ * - GTC.
*
* <b>DisplayPort overview</b>
*
* A DisplayPort link consists of:
- * - A unidirectional main link which is used to transport isochronous data
- * streams such as video and audio. The main link may use 1, 2, or 4
- * lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
- * needs to be trained prior to sending streams.
- * - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
- * link training, link management, and device control.
- * - A hot-plug-detect (HPD) signal line is used to determine whether a
- * DisplayPort connection exists between the DisplayPort TX connector and
- * an RX device. It is serves as an interrupt request by the RX device.
+ * - A unidirectional main link which is used to transport isochronous data
+ * streams such as video and audio. The main link may use 1, 2, or 4
+ * lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
+ * needs to be trained prior to sending streams.
+ * - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
+ * link training, link management, and device control.
+ * - A hot-plug-detect (HPD) signal line is used to determine whether a
+ * DisplayPort connection exists between the DisplayPort TX connector and
+ * an RX device. It is serves as an interrupt request by the RX device.
*
* <b>Driver description</b>
*
@@ -84,10 +84,10 @@
* - The LPM manages the main link and is responsible for keeping the link
* synchronized. It will establish a link with a downstream RX device by
* undergoing a link training sequence which consists of:
- * - Clock recovery: The clock needs to be recovered and PLLs need to be
- * locked for all lanes.
- * - Channel equalization: All lanes need to achieve channel equalization
- * and and symbol lock, as well as for interlane alignment to take place.
+ * - Clock recovery: The clock needs to be recovered and PLLs need to be
+ * locked for all lanes.
+ * - Channel equalization: All lanes need to achieve channel equalization
+ * and and symbol lock, as well as for interlane alignment to take place.
* - The SPM manages transportation of an isochronous stream. That is, it will
* initialize and maintain a video stream, establish a virtual channel to a
* sink monitor, and transmit the stream.
@@ -158,8 +158,8 @@
* - The driver does not handle audio. See the audio example in the driver
* examples directory for the required sequence for enabling audio.
*
- * @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
- * required with a speed grade of -2 or -3.
+ * @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
+ * required with a speed grade of -2 or -3.
*
* <pre>
* MODIFICATION HISTORY:
@@ -171,8 +171,8 @@
*
*******************************************************************************/
-#ifndef XDPTX_H_ /* Prevent circular inclusions */
-#define XDPTX_H_ /* by using protection macros. */
+#ifndef XDPTX_H_ /* Prevent circular inclusions */
+#define XDPTX_H_ /* by using protection macros. */
/******************************* Include Files ********************************/
@@ -186,18 +186,19 @@
/**
* This macro checks if there is a connected RX device.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return - TRUE if there is a connection.
- * - FALSE if there is no connection.
+ * @return
+ * - TRUE if there is a connection.
+ * - FALSE if there is no connection.
*
- * @note C-style signature:
- * void XDptx_IsConnected(XDptx *InstancePtr)
+ * @note C-style signature:
+ * void XDptx_IsConnected(XDptx *InstancePtr)
*
*******************************************************************************/
#define XDptx_IsConnected(InstancePtr) \
- (XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
- XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
+ (XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
+ XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
/****************************** Type Definitions ******************************/
@@ -210,116 +211,116 @@
* Where RB stands for reduced blanking.
*/
typedef enum {
- XDPTX_VM_640x480_60_P,
- XDPTX_VM_800x600_60_P,
- XDPTX_VM_848x480_60_P,
- XDPTX_VM_1024x768_60_P,
- XDPTX_VM_1280x768_60_P_RB,
- XDPTX_VM_1280x768_60_P,
- XDPTX_VM_1280x800_60_P_RB,
- XDPTX_VM_1280x800_60_P,
- XDPTX_VM_1280x960_60_P,
- XDPTX_VM_1280x1024_60_P,
- XDPTX_VM_1360x768_60_P,
- XDPTX_VM_1400x1050_60_P_RB,
- XDPTX_VM_1400x1050_60_P,
- XDPTX_VM_1440x900_60_P_RB,
- XDPTX_VM_1440x900_60_P,
- XDPTX_VM_1600x1200_60_P,
- XDPTX_VM_1680x1050_60_P_RB,
- XDPTX_VM_1680x1050_60_P,
- XDPTX_VM_1792x1344_60_P,
- XDPTX_VM_1856x1392_60_P,
- XDPTX_VM_1920x1200_60_P_RB,
- XDPTX_VM_1920x1200_60_P,
- XDPTX_VM_1920x1440_60_P,
- XDPTX_VM_2560x1600_60_P_RB,
- XDPTX_VM_2560x1600_60_P,
- XDPTX_VM_800x600_56_P,
- XDPTX_VM_1600x1200_65_P,
- XDPTX_VM_1600x1200_70_P,
- XDPTX_VM_1024x768_70_P,
- XDPTX_VM_640x480_72_P,
- XDPTX_VM_800x600_72_P,
- XDPTX_VM_640x480_75_P,
- XDPTX_VM_800x600_75_P,
- XDPTX_VM_1024x768_75_P,
- XDPTX_VM_1152x864_75_P,
- XDPTX_VM_1280x768_75_P,
- XDPTX_VM_1280x800_75_P,
- XDPTX_VM_1280x1024_75_P,
- XDPTX_VM_1400x1050_75_P,
- XDPTX_VM_1440x900_75_P,
- XDPTX_VM_1600x1200_75_P,
- XDPTX_VM_1680x1050_75_P,
- XDPTX_VM_1792x1344_75_P,
- XDPTX_VM_1856x1392_75_P,
- XDPTX_VM_1920x1200_75_P,
- XDPTX_VM_1920x1440_75_P,
- XDPTX_VM_2560x1600_75_P,
- XDPTX_VM_640x350_85_P,
- XDPTX_VM_640x400_85_P,
- XDPTX_VM_720x400_85_P,
- XDPTX_VM_640x480_85_P,
- XDPTX_VM_800x600_85_P,
- XDPTX_VM_1024x768_85_P,
- XDPTX_VM_1280x768_85_P,
- XDPTX_VM_1280x800_85_P,
- XDPTX_VM_1280x960_85_P,
- XDPTX_VM_1280x1024_85_P,
- XDPTX_VM_1400x1050_85_P,
- XDPTX_VM_1440x900_85_P,
- XDPTX_VM_1600x1200_85_P,
- XDPTX_VM_1680x1050_85_P,
- XDPTX_VM_1920x1200_85_P,
- XDPTX_VM_2560x1600_85_P,
- XDPTX_VM_800x600_120_P_RB,
- XDPTX_VM_1024x768_120_P_RB,
- XDPTX_VM_1280x768_120_P_RB,
- XDPTX_VM_1280x800_120_P_RB,
- XDPTX_VM_1280x960_120_P_RB,
- XDPTX_VM_1280x1024_120_P_RB,
- XDPTX_VM_1360x768_120_P_RB,
- XDPTX_VM_1400x1050_120_P_RB,
- XDPTX_VM_1440x900_120_P_RB,
- XDPTX_VM_1600x1200_120_P_RB,
- XDPTX_VM_1680x1050_120_P_RB,
- XDPTX_VM_1792x1344_120_P_RB,
- XDPTX_VM_1856x1392_120_P_RB,
- XDPTX_VM_1920x1200_120_P_RB,
- XDPTX_VM_1920x1440_120_P_RB,
- XDPTX_VM_2560x1600_120_P_RB,
- XDPTX_VM_1366x768_60_P,
- XDPTX_VM_1920x1080_60_P,
- XDPTX_VM_UHD_30_P,
- XDPTX_VM_720_60_P,
- XDPTX_VM_480_60_P,
- XDPTX_VM_UHD2_60_P,
- XDPTX_VM_UHD_60,
- XDPTX_VM_USE_EDID_PREFERRED,
- XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
+ XDPTX_VM_640x480_60_P,
+ XDPTX_VM_800x600_60_P,
+ XDPTX_VM_848x480_60_P,
+ XDPTX_VM_1024x768_60_P,
+ XDPTX_VM_1280x768_60_P_RB,
+ XDPTX_VM_1280x768_60_P,
+ XDPTX_VM_1280x800_60_P_RB,
+ XDPTX_VM_1280x800_60_P,
+ XDPTX_VM_1280x960_60_P,
+ XDPTX_VM_1280x1024_60_P,
+ XDPTX_VM_1360x768_60_P,
+ XDPTX_VM_1400x1050_60_P_RB,
+ XDPTX_VM_1400x1050_60_P,
+ XDPTX_VM_1440x900_60_P_RB,
+ XDPTX_VM_1440x900_60_P,
+ XDPTX_VM_1600x1200_60_P,
+ XDPTX_VM_1680x1050_60_P_RB,
+ XDPTX_VM_1680x1050_60_P,
+ XDPTX_VM_1792x1344_60_P,
+ XDPTX_VM_1856x1392_60_P,
+ XDPTX_VM_1920x1200_60_P_RB,
+ XDPTX_VM_1920x1200_60_P,
+ XDPTX_VM_1920x1440_60_P,
+ XDPTX_VM_2560x1600_60_P_RB,
+ XDPTX_VM_2560x1600_60_P,
+ XDPTX_VM_800x600_56_P,
+ XDPTX_VM_1600x1200_65_P,
+ XDPTX_VM_1600x1200_70_P,
+ XDPTX_VM_1024x768_70_P,
+ XDPTX_VM_640x480_72_P,
+ XDPTX_VM_800x600_72_P,
+ XDPTX_VM_640x480_75_P,
+ XDPTX_VM_800x600_75_P,
+ XDPTX_VM_1024x768_75_P,
+ XDPTX_VM_1152x864_75_P,
+ XDPTX_VM_1280x768_75_P,
+ XDPTX_VM_1280x800_75_P,
+ XDPTX_VM_1280x1024_75_P,
+ XDPTX_VM_1400x1050_75_P,
+ XDPTX_VM_1440x900_75_P,
+ XDPTX_VM_1600x1200_75_P,
+ XDPTX_VM_1680x1050_75_P,
+ XDPTX_VM_1792x1344_75_P,
+ XDPTX_VM_1856x1392_75_P,
+ XDPTX_VM_1920x1200_75_P,
+ XDPTX_VM_1920x1440_75_P,
+ XDPTX_VM_2560x1600_75_P,
+ XDPTX_VM_640x350_85_P,
+ XDPTX_VM_640x400_85_P,
+ XDPTX_VM_720x400_85_P,
+ XDPTX_VM_640x480_85_P,
+ XDPTX_VM_800x600_85_P,
+ XDPTX_VM_1024x768_85_P,
+ XDPTX_VM_1280x768_85_P,
+ XDPTX_VM_1280x800_85_P,
+ XDPTX_VM_1280x960_85_P,
+ XDPTX_VM_1280x1024_85_P,
+ XDPTX_VM_1400x1050_85_P,
+ XDPTX_VM_1440x900_85_P,
+ XDPTX_VM_1600x1200_85_P,
+ XDPTX_VM_1680x1050_85_P,
+ XDPTX_VM_1920x1200_85_P,
+ XDPTX_VM_2560x1600_85_P,
+ XDPTX_VM_800x600_120_P_RB,
+ XDPTX_VM_1024x768_120_P_RB,
+ XDPTX_VM_1280x768_120_P_RB,
+ XDPTX_VM_1280x800_120_P_RB,
+ XDPTX_VM_1280x960_120_P_RB,
+ XDPTX_VM_1280x1024_120_P_RB,
+ XDPTX_VM_1360x768_120_P_RB,
+ XDPTX_VM_1400x1050_120_P_RB,
+ XDPTX_VM_1440x900_120_P_RB,
+ XDPTX_VM_1600x1200_120_P_RB,
+ XDPTX_VM_1680x1050_120_P_RB,
+ XDPTX_VM_1792x1344_120_P_RB,
+ XDPTX_VM_1856x1392_120_P_RB,
+ XDPTX_VM_1920x1200_120_P_RB,
+ XDPTX_VM_1920x1440_120_P_RB,
+ XDPTX_VM_2560x1600_120_P_RB,
+ XDPTX_VM_1366x768_60_P,
+ XDPTX_VM_1920x1080_60_P,
+ XDPTX_VM_UHD_30_P,
+ XDPTX_VM_720_60_P,
+ XDPTX_VM_480_60_P,
+ XDPTX_VM_UHD2_60_P,
+ XDPTX_VM_UHD_60,
+ XDPTX_VM_USE_EDID_PREFERRED,
+ XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
} XDptx_VideoMode;
/**
* This typedef contains the display monitor timing attributes for a video mode.
*/
typedef struct {
- XDptx_VideoMode VideoMode; /**< Enumerated key. */
- u8 DmtId; /**< Standard DMT ID number. */
- u16 HResolution; /**< Horizontal resolution. */
- u16 VResolution; /**< Vertical resolution. */
- u32 PixelClkKhz; /**< Pixel frequency (in KHz). */
- u8 Scan; /**< Interlaced/non-interlaced. */
- u8 HSyncPolarity; /**< Horizontal polarity. */
- u8 VSyncPolarity; /**< Vertical polarity. */
- u32 HFrontPorch; /**< Horizontal front porch. */
- u32 HSyncPulseWidth; /**< Horizontal synchronization pulse
- width. */
- u32 HBackPorch; /**< Horizontal back porch. */
- u32 VFrontPorch; /**< Vertical front porch. */
- u32 VSyncPulseWidth; /**< Vertical synchronization pulse
- width.*/
- u32 VBackPorch; /**< Vertical back porch. */
+ XDptx_VideoMode VideoMode; /**< Enumerated key. */
+ u8 DmtId; /**< Standard DMT ID number. */
+ u16 HResolution; /**< Horizontal resolution. */
+ u16 VResolution; /**< Vertical resolution. */
+ u32 PixelClkKhz; /**< Pixel frequency (in KHz). */
+ u8 Scan; /**< Interlaced/non-interlaced. */
+ u8 HSyncPolarity; /**< Horizontal polarity. */
+ u8 VSyncPolarity; /**< Vertical polarity. */
+ u32 HFrontPorch; /**< Horizontal front porch. */
+ u32 HSyncPulseWidth; /**< Horizontal synchronization pulse
+ width. */
+ u32 HBackPorch; /**< Horizontal back porch. */
+ u32 VFrontPorch; /**< Vertical front porch. */
+ u32 VSyncPulseWidth; /**< Vertical synchronization pulse
+ width.*/
+ u32 VBackPorch; /**< Vertical back porch. */
} XDptx_DmtMode;
extern XDptx_DmtMode XDptx_DmtModes[];
@@ -328,86 +329,86 @@ extern XDptx_DmtMode XDptx_DmtModes[];
* This typedef contains configuration information for the DisplayPort TX core.
*/
typedef struct {
- u16 DeviceId; /**< Device instance ID. */
- u32 BaseAddr; /**< The base address of the core. */
- u32 SAxiClkHz; /**< The clock frequency of the core's
- S_AXI_ACLK port. */
- u8 MaxLaneCount; /**< The maximum lane count supported by this
- core's instance. */
- u8 MaxLinkRate; /**< The maximum link rate supported by this
- core's instance. */
- u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
- core's instance*/
- u8 QuadPixelEn; /**< Quad pixel support by this core's
- instance. */
- u8 DualPixelEn; /**< Dual pixel support by this core's
- instance. */
- u8 YOnlyEn; /**< YOnly format support by this core's
- instance. */
- u8 YCrCbEn; /**< YCrCb format support by this core's
- instance. */
+ u16 DeviceId; /**< Device instance ID. */
+ u32 BaseAddr; /**< The base address of the core. */
+ u32 SAxiClkHz; /**< The clock frequency of the core's
+ S_AXI_ACLK port. */
+ u8 MaxLaneCount; /**< The maximum lane count supported by this
+ core's instance. */
+ u8 MaxLinkRate; /**< The maximum link rate supported by this
+ core's instance. */
+ u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
+ core's instance*/
+ u8 QuadPixelEn; /**< Quad pixel support by this core's
+ instance. */
+ u8 DualPixelEn; /**< Dual pixel support by this core's
+ instance. */
+ u8 YOnlyEn; /**< YOnly format support by this core's
+ instance. */
+ u8 YCrCbEn; /**< YCrCb format support by this core's
+ instance. */
} XDptx_Config;
/**
* This typedef contains configuration information about the RX device.
*/
typedef struct {
- u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
- /**< The raw capabilities field
- of the RX device's DisplayPort
- Configuration Data (DPCD). */
- u8 Edid[XDPTX_EDID_SIZE]; /**< The RX device's raw Extended
- Display Identification Data
- (EDID). */
- u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
- RX device's status registers.
- The first 4 bytes correspond to
- the lane status associated with
- clock recovery, channel
- equalization, symbol lock, and
- interlane alignment. The
- remaining 2 bytes represent the
- pre-emphasis and voltage swing
- level adjustments requested by
- the RX device. */
+ u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
+ /**< The raw capabilities field
+ of the RX device's DisplayPort
+ Configuration Data (DPCD). */
+ u8 Edid[XDPTX_EDID_SIZE]; /**< The RX device's raw Extended
+ Display Identification Data
+ (EDID). */
+ u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
+ RX device's status registers.
+ The first 4 bytes correspond to
+ the lane status associated with
+ clock recovery, channel
+ equalization, symbol lock, and
+ interlane alignment. The
+ remaining 2 bytes represent the
+ pre-emphasis and voltage swing
+ level adjustments requested by
+ the RX device. */
} XDptx_SinkConfig;
/**
* This typedef contains configuration information about the main link settings.
*/
typedef struct {
- u8 LaneCount; /**< The current lane count of the main
- link. */
- u8 LinkRate; /**< The current link rate of the main
- link. */
- u8 ScramblerEn; /**< Symbol scrambling is currently in
- use over the main link. */
- u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
- use over the main link. */
- u8 DownspreadControl; /**< Downspread control is currently in
- use over the main link. */
- u8 MaxLaneCount; /**< The maximum lane count of the main
- link. */
- u8 MaxLinkRate; /**< The maximum link rate of the main
- link. */
- u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
- the RX device. */
- u8 SupportDownspreadControl; /**< Downspread control is supported by
- the RX device. */
- u8 VsLevel; /**< The current voltage swing level for
- each lane. */
- u8 PeLevel; /**< The current pre-emphasis/cursor
- level for each lane. */
- u8 ComponentFormat; /**< The component format currently in
- use over the main link. */
- u8 DynamicRange; /**< The dynamic range currently in use
- over the main link. */
- u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
- use over the main link. */
- u8 SynchronousClockMode; /**< Synchronous clock mode is currently
- in use over the main link. */
- u8 Pattern; /**< The current pattern currently in
- use over the main link. */
+ u8 LaneCount; /**< The current lane count of the main
+ link. */
+ u8 LinkRate; /**< The current link rate of the main
+ link. */
+ u8 ScramblerEn; /**< Symbol scrambling is currently in
+ use over the main link. */
+ u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
+ use over the main link. */
+ u8 DownspreadControl; /**< Downspread control is currently in
+ use over the main link. */
+ u8 MaxLaneCount; /**< The maximum lane count of the main
+ link. */
+ u8 MaxLinkRate; /**< The maximum link rate of the main
+ link. */
+ u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
+ the RX device. */
+ u8 SupportDownspreadControl; /**< Downspread control is supported by
+ the RX device. */
+ u8 VsLevel; /**< The current voltage swing level for
+ each lane. */
+ u8 PeLevel; /**< The current pre-emphasis/cursor
+ level for each lane. */
+ u8 ComponentFormat; /**< The component format currently in
+ use over the main link. */
+ u8 DynamicRange; /**< The dynamic range currently in use
+ over the main link. */
+ u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
+ use over the main link. */
+ u8 SynchronousClockMode; /**< Synchronous clock mode is currently
+ in use over the main link. */
+ u8 Pattern; /**< The current pattern currently in
+ use over the main link. */
} XDptx_LinkConfig;
/**
@@ -415,31 +416,31 @@ typedef struct {
* video will be displayed.
*/
typedef struct {
- u32 HClkTotal;
- u32 VClkTotal;
- u32 HSyncPulseWidth;
- u32 VSyncPulseWidth;
- u32 HResolution;
- u32 VResolution;
- u32 HSyncPolarity;
- u32 VSyncPolarity;
- u32 HStart;
- u32 VStart;
- u32 VBackPorch;
- u32 VFrontPorch;
- u32 HBackPorch;
- u32 HFrontPorch;
- u32 Misc0;
- u32 Misc1;
- u32 MVid;
- u32 NVid;
- u32 TransferUnitSize;
- u32 UserPixelWidth;
- u32 DataPerLane;
- u32 AvgBytesPerTU;
- u32 InitWait;
- u32 Interlaced;
- u32 BitsPerColor;
+ u32 HClkTotal;
+ u32 VClkTotal;
+ u32 HSyncPulseWidth;
+ u32 VSyncPulseWidth;
+ u32 HResolution;
+ u32 VResolution;
+ u32 HSyncPolarity;
+ u32 VSyncPolarity;
+ u32 HStart;
+ u32 VStart;
+ u32 VBackPorch;
+ u32 VFrontPorch;
+ u32 HBackPorch;
+ u32 HFrontPorch;
+ u32 Misc0;
+ u32 Misc1;
+ u32 MVid;
+ u32 NVid;
+ u32 TransferUnitSize;
+ u32 UserPixelWidth;
+ u32 DataPerLane;
+ u32 AvgBytesPerTU;
+ u32 InitWait;
+ u32 Interlaced;
+ u32 BitsPerColor;
} XDptx_MainStreamAttributes;
/******************************************************************************/
@@ -451,9 +452,11 @@ typedef struct {
* used, the user may implement their own wait implementation using a hardware
* timer (see example/) for better accuracy.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param MicroSeconds is the number of microseconds to be passed to the
- * timer function.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param MicroSeconds is the number of microseconds to be passed to the
+ * timer function.
+ *
+ * @note None.
*
*******************************************************************************/
typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
@@ -463,7 +466,9 @@ typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
* interrupt.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ *
+ * @note None.
*
*******************************************************************************/
typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
@@ -473,7 +478,9 @@ typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
* interrupt.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ *
+ * @note None.
*
*******************************************************************************/
typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
@@ -484,41 +491,41 @@ typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
* this type is then passed to the driver API functions.
*/
typedef struct {
- u32 IsReady; /**< Device is initialized and
- ready. */
- u8 TrainAdaptive; /**< Downshift lane count and
- link rate if necessary
- during training. */
- u8 HasRedriverInPath; /**< Redriver in path requires
- different voltage swing
- and pre-emphasis. */
- XDptx_Config Config; /**< Configuration structure for
- the DisplayPort TX
- core. */
- XDptx_SinkConfig RxConfig; /**< Configuration structure for
- the RX device. */
- XDptx_LinkConfig LinkConfig; /**< Configuration structure for
- the main link. */
- XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for
- the main stream
- attributes. */
- XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
- delay/sleep. */
- void *UserTimerPtr; /**< Pointer to a timer instance
- used by the custom user
- delay/sleep function. */
- XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
- Plug-Detect (HPD) event
- interrupts. */
- void *HpdEventCallbackRef; /**< A pointer to the user data
- passed to the HPD event
- callback function.*/
- XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
- Plug-Detect (HPD) pulse
- interrupts. */
- void *HpdPulseCallbackRef; /**< A pointer to the user data
- passed to the HPD pulse
- callback function.*/
+ u32 IsReady; /**< Device is initialized and
+ ready. */
+ u8 TrainAdaptive; /**< Downshift lane count and
+ link rate if necessary
+ during training. */
+ u8 HasRedriverInPath; /**< Redriver in path requires
+ different voltage swing
+ and pre-emphasis. */
+ XDptx_Config Config; /**< Configuration structure for
+ the DisplayPort TX
+ core. */
+ XDptx_SinkConfig RxConfig; /**< Configuration structure for
+ the RX device. */
+ XDptx_LinkConfig LinkConfig; /**< Configuration structure for
+ the main link. */
+ XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for
+ the main stream
+ attributes. */
+ XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
+ delay/sleep. */
+ void *UserTimerPtr; /**< Pointer to a timer instance
+ used by the custom user
+ delay/sleep function. */
+ XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
+ Plug-Detect (HPD) event
+ interrupts. */
+ void *HpdEventCallbackRef; /**< A pointer to the user data
+ passed to the HPD event
+ callback function.*/
+ XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
+ Plug-Detect (HPD) pulse
+ interrupts. */
+ void *HpdPulseCallbackRef; /**< A pointer to the user data
+ passed to the HPD pulse
+ callback function.*/
} XDptx;
/**************************** Function Prototypes *****************************/
@@ -526,7 +533,7 @@ typedef struct {
/* xdptx.c: Setup and initialization functions. */
u32 XDptx_InitializeTx(XDptx *InstancePtr);
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
- u32 EffectiveAddr);
+ u32 EffectiveAddr);
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
u32 XDptx_GetEdid(XDptx *InstancePtr);
@@ -541,9 +548,9 @@ void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set);
u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
- u8 NumBytes, void *Data);
+ u8 NumBytes, void *Data);
u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
- u8 NumBytes, void *Data);
+ u8 NumBytes, void *Data);
/* xdptx.c: Functions for controlling the link configuration. */
u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable);
@@ -558,23 +565,23 @@ void XDptx_DisableMainLink(XDptx *InstancePtr);
void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset);
void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds);
void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
- XDptx_TimerHandler CallbackFunc, void *CallbackRef);
+ XDptx_TimerHandler CallbackFunc, void *CallbackRef);
/* xdptx_spm.c: Stream policy maker functions. */
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr);
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
- XDptx_VideoMode VideoMode);
+ XDptx_VideoMode VideoMode);
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr);
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
- XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
+ XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
void XDptx_SetVideoMode(XDptx *InstancePtr);
/* xdptx_intr.c: Interrupt handling functions. */
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
- XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
+ XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
- XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
+ XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
void XDptx_HpdInterruptHandler(XDptx *InstancePtr);
/* xdptx_selftest.c: Self test function. */
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
index 02520eb7..b8e01ad9 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
@@ -38,6 +38,8 @@
* macros) that can be used to access the device. High-level driver functions
* are defined in xdptx.h.
*
+ * @note None.
+ *
* <pre>
* MODIFICATION HISTORY:
*
@@ -48,8 +50,8 @@
*
*******************************************************************************/
-#ifndef XDPTX_HW_H_
-#define XDPTX_HW_H_
+#ifndef XDPTX_HW_H_ /* Prevent circular inclusions */
+#define XDPTX_HW_H_ /* by using protection macros. */
/***************************** Include Files **********************************/
@@ -66,264 +68,264 @@
/** @name DPTX core registers: Link configuration field.
* @{
*/
-#define XDPTX_LINK_BW_SET 0x0000 /**< Set main link bandwidth
- setting. */
-#define XDPTX_LANE_COUNT_SET 0x0004 /**< Set lane count setting. */
-#define XDPTX_ENHANCED_FRAME_EN 0x0008 /**< Enable enhanced framing
- symbol sequence. */
-#define XDPTX_TRAINING_PATTERN_SET 0x000C /**< Set the link training
- pattern. */
-#define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 /**< Transmit the link quality
- pattern. */
-#define XDPTX_SCRAMBLING_DISABLE 0x0014 /**< Disable scrambler and
- transmit all symbols. */
-#define XDPTX_DOWNSPREAD_CTRL 0x0018 /**< Enable a 0.5% spreading of
- the clock. */
-#define XDPTX_SOFT_RESET 0x001C /**< Software reset. */
+#define XDPTX_LINK_BW_SET 0x0000 /**< Set main link bandwidth
+ setting. */
+#define XDPTX_LANE_COUNT_SET 0x0004 /**< Set lane count setting. */
+#define XDPTX_ENHANCED_FRAME_EN 0x0008 /**< Enable enhanced framing
+ symbol sequence. */
+#define XDPTX_TRAINING_PATTERN_SET 0x000C /**< Set the link training
+ pattern. */
+#define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 /**< Transmit the link quality
+ pattern. */
+#define XDPTX_SCRAMBLING_DISABLE 0x0014 /**< Disable scrambler and
+ transmit all symbols. */
+#define XDPTX_DOWNSPREAD_CTRL 0x0018 /**< Enable a 0.5% spreading of
+ the clock. */
+#define XDPTX_SOFT_RESET 0x001C /**< Software reset. */
/* @} */
/** @name DPTX core registers: Core enables.
* @{
*/
-#define XDPTX_ENABLE 0x0080 /**< Enable the basic operations
- of the DisplayPort TX
- core or output stuffing
- symbols if disabled. */
-#define XDPTX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main
- link video info. */
-#define XDPTX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of
- secondary link info. */
-#define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 /**< Force a scrambler reset. */
-#define XDPTX_TX_MST_CONFIG 0x00D0 /**< Enable MST. */
+#define XDPTX_ENABLE 0x0080 /**< Enable the basic operations
+ of the DisplayPort TX
+ core or output stuffing
+ symbols if disabled. */
+#define XDPTX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main
+ link video info. */
+#define XDPTX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of
+ secondary link info. */
+#define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 /**< Force a scrambler reset. */
+#define XDPTX_TX_MST_CONFIG 0x00D0 /**< Enable MST. */
/* @} */
/** @name DPTX core registers: Core ID.
* @{
*/
-#define XDPTX_VERSION 0x00F8 /**< Core version. */
-#define XDPTX_CORE_ID 0x00FC /**< DisplayPort revision. */
+#define XDPTX_VERSION 0x00F8 /**< Core version. */
+#define XDPTX_CORE_ID 0x00FC /**< DisplayPort revision. */
/* @} */
/** @name DPTX core registers: AUX channel interface.
* @{
*/
-#define XDPTX_AUX_CMD 0x0100 /**< Initiates AUX commands. */
-#define XDPTX_AUX_WRITE_FIFO 0x0104 /**< Write data for the current
- AUX command. */
-#define XDPTX_AUX_ADDRESS 0x0108 /**< Specifies the address of
- current AUX command. */
-#define XDPTX_AUX_CLK_DIVIDER 0x010C /**< Clock divider value for
- generating the internal
- 1MHz clock. */
-#define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 /**< Indicates an overflow in
- user FIFO. */
-#define XDPTX_INTERRUPT_SIG_STATE 0x0130 /**< The raw signal values for
- interupt events. */
-#define XDPTX_AUX_REPLY_DATA 0x0134 /**< Reply data received during
- the AUX reply. */
-#define XDPTX_AUX_REPLY_CODE 0x0138 /**< Reply code received from
- the most recent AUX
- command. */
-#define XDPTX_AUX_REPLY_COUNT 0x013C /**< Number of reply
- transactions receieved
- over AUX. */
-#define XDPTX_INTERRUPT_STATUS 0x0140 /**< Status for interrupt
- events. */
-#define XDPTX_INTERRUPT_MASK 0x0144 /**< Masks the specified
- interrupt sources. */
-#define XDPTX_REPLY_DATA_COUNT 0x0148 /**< Total number of data bytes
- actually received during
- a transaction. */
-#define XDPTX_REPLY_STATUS 0x014C /**< Reply status of most recent
- AUX transaction. */
-#define XDPTX_HPD_DURATION 0x0150 /**< Duration of the HPD pulse
- in microseconds. */
+#define XDPTX_AUX_CMD 0x0100 /**< Initiates AUX commands. */
+#define XDPTX_AUX_WRITE_FIFO 0x0104 /**< Write data for the current
+ AUX command. */
+#define XDPTX_AUX_ADDRESS 0x0108 /**< Specifies the address of
+ current AUX command. */
+#define XDPTX_AUX_CLK_DIVIDER 0x010C /**< Clock divider value for
+ generating the internal
+ 1MHz clock. */
+#define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 /**< Indicates an overflow in
+ user FIFO. */
+#define XDPTX_INTERRUPT_SIG_STATE 0x0130 /**< The raw signal values for
+ interupt events. */
+#define XDPTX_AUX_REPLY_DATA 0x0134 /**< Reply data received during
+ the AUX reply. */
+#define XDPTX_AUX_REPLY_CODE 0x0138 /**< Reply code received from
+ the most recent AUX
+ command. */
+#define XDPTX_AUX_REPLY_COUNT 0x013C /**< Number of reply
+ transactions receieved
+ over AUX. */
+#define XDPTX_INTERRUPT_STATUS 0x0140 /**< Status for interrupt
+ events. */
+#define XDPTX_INTERRUPT_MASK 0x0144 /**< Masks the specified
+ interrupt sources. */
+#define XDPTX_REPLY_DATA_COUNT 0x0148 /**< Total number of data bytes
+ actually received during
+ a transaction. */
+#define XDPTX_REPLY_STATUS 0x014C /**< Reply status of most recent
+ AUX transaction. */
+#define XDPTX_HPD_DURATION 0x0150 /**< Duration of the HPD pulse
+ in microseconds. */
/* @} */
/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1.
* @{
*/
-#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers
- for stream 1. */
-#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in
- the horizontal framing
- period. */
-#define XDPTX_MAIN_STREAM_VTOTAL 0x0184 /**< Total number of lines in
- the video frame. */
-#define XDPTX_MAIN_STREAM_POLARITY 0x0188 /**< Polarity for the video
- sync signals. */
-#define XDPTX_MAIN_STREAM_HSWIDTH 0x018C /**< Width of the horizontal
- sync pulse. */
-#define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 /**< Width of the vertical sync
- pulse. */
-#define XDPTX_MAIN_STREAM_HRES 0x0194 /**< Number of active pixels per
- line (the horizontal
- resolution). */
-#define XDPTX_MAIN_STREAM_VRES 0x0198 /**< Number of active lines (the
- vertical resolution). */
-#define XDPTX_MAIN_STREAM_HSTART 0x019C /**< Number of clocks between
- the leading edge of the
- horizontal sync and the
- start of active data. */
-#define XDPTX_MAIN_STREAM_VSTART 0x01A0 /**< Number of lines between the
- leading edge of the
- vertical sync and the
- first line of active
- data. */
-#define XDPTX_MAIN_STREAM_MISC0 0x01A4 /**< Miscellaneous stream
- attributes. */
-#define XDPTX_MAIN_STREAM_MISC1 0x01A8 /**< Miscellaneous stream
- attributes. */
-#define XDPTX_M_VID 0x01AC /**< M value for the video
- stream as computed by
- the source core in
- asynchronous clock
- mode. Must be written
- in synchronous mode. */
-#define XDPTX_TU_SIZE 0x01B0 /**< Size of a transfer unit in
- the framing logic. */
-#define XDPTX_N_VID 0x01B4 /**< N value for the video
- stream as computed by
- the source core in
- asynchronous clock mode.
- Must be written in
- synchronous mode. */
-#define XDPTX_USER_PIXEL_WIDTH 0x01B8 /**< Selects the width of the
- user data input port. */
-#define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC /**< Used to translate the
- number of pixels per
- line to the native
- internal 16-bit
- datapath. */
-#define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 /**< Video is interlaced. */
-#define XDPTX_MIN_BYTES_PER_TU 0x01C4 /**< The minimum number of bytes
- per transfer unit. */
-#define XDPTX_FRAC_BYTES_PER_TU 0x01C8 /**< The fractional component
- when calculated the
- XDPTX_MIN_BYTES_PER_TU
- register value. */
-#define XDPTX_INIT_WAIT 0x01CC /**< Number of initial wait
- cycles at the start of a
- new line by the framing
- logic, allowing enough
- data to be buffered in
- the input FIFO. */
-#define XDPTX_STREAM0 0x01D0 /**< Average stream symbol
- timeslots per MTP
- config. */
-#define XDPTX_STREAM1 0x01D4 /**< Average stream symbol
- timeslots per MTP
- config. */
-#define XDPTX_STREAM2 0x01D8 /**< Average stream symbol
- timeslots per MTP
- config. */
-#define XDPTX_STREAM3 0x01DC /**< Average stream symbol
- timeslots per MTP
- config. */
+#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers
+ for stream 1. */
+#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in
+ the horizontal framing
+ period. */
+#define XDPTX_MAIN_STREAM_VTOTAL 0x0184 /**< Total number of lines in
+ the video frame. */
+#define XDPTX_MAIN_STREAM_POLARITY 0x0188 /**< Polarity for the video
+ sync signals. */
+#define XDPTX_MAIN_STREAM_HSWIDTH 0x018C /**< Width of the horizontal
+ sync pulse. */
+#define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 /**< Width of the vertical sync
+ pulse. */
+#define XDPTX_MAIN_STREAM_HRES 0x0194 /**< Number of active pixels per
+ line (the horizontal
+ resolution). */
+#define XDPTX_MAIN_STREAM_VRES 0x0198 /**< Number of active lines (the
+ vertical resolution). */
+#define XDPTX_MAIN_STREAM_HSTART 0x019C /**< Number of clocks between
+ the leading edge of the
+ horizontal sync and the
+ start of active data. */
+#define XDPTX_MAIN_STREAM_VSTART 0x01A0 /**< Number of lines between the
+ leading edge of the
+ vertical sync and the
+ first line of active
+ data. */
+#define XDPTX_MAIN_STREAM_MISC0 0x01A4 /**< Miscellaneous stream
+ attributes. */
+#define XDPTX_MAIN_STREAM_MISC1 0x01A8 /**< Miscellaneous stream
+ attributes. */
+#define XDPTX_M_VID 0x01AC /**< M value for the video
+ stream as computed by
+ the source core in
+ asynchronous clock
+ mode. Must be written
+ in synchronous mode. */
+#define XDPTX_TU_SIZE 0x01B0 /**< Size of a transfer unit in
+ the framing logic. */
+#define XDPTX_N_VID 0x01B4 /**< N value for the video
+ stream as computed by
+ the source core in
+ asynchronous clock mode.
+ Must be written in
+ synchronous mode. */
+#define XDPTX_USER_PIXEL_WIDTH 0x01B8 /**< Selects the width of the
+ user data input port. */
+#define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC /**< Used to translate the
+ number of pixels per
+ line to the native
+ internal 16-bit
+ datapath. */
+#define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 /**< Video is interlaced. */
+#define XDPTX_MIN_BYTES_PER_TU 0x01C4 /**< The minimum number of bytes
+ per transfer unit. */
+#define XDPTX_FRAC_BYTES_PER_TU 0x01C8 /**< The fractional component
+ when calculated the
+ XDPTX_MIN_BYTES_PER_TU
+ register value. */
+#define XDPTX_INIT_WAIT 0x01CC /**< Number of initial wait
+ cycles at the start of a
+ new line by the framing
+ logic, allowing enough
+ data to be buffered in
+ the input FIFO. */
+#define XDPTX_STREAM0 0x01D0 /**< Average stream symbol
+ timeslots per MTP
+ config. */
+#define XDPTX_STREAM1 0x01D4 /**< Average stream symbol
+ timeslots per MTP
+ config. */
+#define XDPTX_STREAM2 0x01D8 /**< Average stream symbol
+ timeslots per MTP
+ config. */
+#define XDPTX_STREAM3 0x01DC /**< Average stream symbol
+ timeslots per MTP
+ config. */
/* @} */
/** @name DPTX core registers: PHY configuration status.
* @{
*/
-#define XDPTX_PHY_CONFIG 0x0200 /**< Transceiver PHY reset and
- configuration. */
-#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 /**< Controls the differential
- voltage swing. */
-#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 /**< Controls the differential
- voltage swing. */
-#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 /**< Controls the differential
- voltage swing. */
-#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C /**< Controls the differential
- voltage swing. */
-#define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 /**< Enable pseudo random bit
- sequence 7 pattern
- transmission for link
- quality assessment. */
-#define XDPTX_PHY_CLOCK_SELECT 0x0234 /**< Instructs the PHY PLL to
- generate the proper
- clock frequency for the
- required link rate. */
-#define XDPTX_TX_PHY_POWER_DOWN 0x0238 /**< Controls PHY power down. */
-#define XDPTX_PHY_PRECURSOR_LANE_0 0x023C /**< Controls the pre-cursor
- level. */
-#define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 /**< Controls the pre-cursor
- level. */
-#define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 /**< Controls the pre-cursor
- level. */
-#define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 /**< Controls the pre-cursor
- level. */
-#define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C /**< Controls the post-cursor
- level. */
-#define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 /**< Controls the post-cursor
- level. */
-#define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 /**< Controls the post-cursor
- level. */
-#define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 /**< Controls the post-cursor
- level. */
-#define XDPTX_PHY_STATUS 0x0280 /**< Current PHY status. */
-#define XDPTX_GT_DRP_COMMAND 0x02A0 /**< Provides acces to the GT
- DRP ports. */
-#define XDPTX_GT_DRP_READ_DATA 0x02A4 /**< Provides access to GT DRP
- read data. */
-#define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 /**< Provides access to GT DRP
- channel status. */
+#define XDPTX_PHY_CONFIG 0x0200 /**< Transceiver PHY reset and
+ configuration. */
+#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 /**< Controls the differential
+ voltage swing. */
+#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 /**< Controls the differential
+ voltage swing. */
+#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 /**< Controls the differential
+ voltage swing. */
+#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C /**< Controls the differential
+ voltage swing. */
+#define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 /**< Enable pseudo random bit
+ sequence 7 pattern
+ transmission for link
+ quality assessment. */
+#define XDPTX_PHY_CLOCK_SELECT 0x0234 /**< Instructs the PHY PLL to
+ generate the proper
+ clock frequency for the
+ required link rate. */
+#define XDPTX_TX_PHY_POWER_DOWN 0x0238 /**< Controls PHY power down. */
+#define XDPTX_PHY_PRECURSOR_LANE_0 0x023C /**< Controls the pre-cursor
+ level. */
+#define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 /**< Controls the pre-cursor
+ level. */
+#define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 /**< Controls the pre-cursor
+ level. */
+#define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 /**< Controls the pre-cursor
+ level. */
+#define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C /**< Controls the post-cursor
+ level. */
+#define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 /**< Controls the post-cursor
+ level. */
+#define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 /**< Controls the post-cursor
+ level. */
+#define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 /**< Controls the post-cursor
+ level. */
+#define XDPTX_PHY_STATUS 0x0280 /**< Current PHY status. */
+#define XDPTX_GT_DRP_COMMAND 0x02A0 /**< Provides acces to the GT
+ DRP ports. */
+#define XDPTX_GT_DRP_READ_DATA 0x02A4 /**< Provides access to GT DRP
+ read data. */
+#define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 /**< Provides access to GT DRP
+ channel status. */
/* @} */
/** @name DPTX core registers: DisplayPort audio.
* @{
*/
-#define XDPTX_TX_AUDIO_CONTROL 0x0300 /**< Enables audio stream
- packets in main link and
- buffer control. */
-#define XDPTX_TX_AUDIO_CHANNELS 0x0304 /**< Used to input active
- channel count. */
-#define XDPTX_TX_AUDIO_INFO_DATA 0x0308 /**< Word formatted as per
- CEA 861-C info frame. */
-#define XDPTX_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream
- as computed by the
- DisplayPort TX core when
- audio and link clocks
- are synchronous. */
-#define XDPTX_TX_AUDIO_NAUD 0x032C /**< N value of audio stream
- as computed by the
- DisplayPort TX core when
- audio and link clocks
- are synchronous. */
-#define XDPTX_TX_AUDIO_EXT_DATA 0x0330 /**< Word formatted as per
- extension packet. */
+#define XDPTX_TX_AUDIO_CONTROL 0x0300 /**< Enables audio stream
+ packets in main link and
+ buffer control. */
+#define XDPTX_TX_AUDIO_CHANNELS 0x0304 /**< Used to input active
+ channel count. */
+#define XDPTX_TX_AUDIO_INFO_DATA 0x0308 /**< Word formatted as per
+ CEA 861-C info frame. */
+#define XDPTX_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream
+ as computed by the
+ DisplayPort TX core when
+ audio and link clocks
+ are synchronous. */
+#define XDPTX_TX_AUDIO_NAUD 0x032C /**< N value of audio stream
+ as computed by the
+ DisplayPort TX core when
+ audio and link clocks
+ are synchronous. */
+#define XDPTX_TX_AUDIO_EXT_DATA 0x0330 /**< Word formatted as per
+ extension packet. */
/* @} */
/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.
* @{
*/
-#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers
- for stream 2. */
-#define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \
- XDPTX_STREAM1_MSA_START) /**< The MSA registers for
- stream 2 are at an
- offset from the
- corresponding registers
- of stream 1. */
-#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers
- for stream 3. */
-#define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \
- XDPTX_STREAM1_MSA_START) /**< The MSA registers for
- stream 2 are at an
- offset from the
- corresponding registers
- of stream 1. */
-#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers
- for stream 4. */
-#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \
- XDPTX_STREAM1_MSA_START) /**< The MSA registers for
- stream 2 are at an
- offset from the
- corresponding registers
- of stream 1. */
+#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers
+for stream 2. */
+#define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \
+ XDPTX_STREAM1_MSA_START) /**< The MSA registers for
+ stream 2 are at an
+ offset from the
+ corresponding registers
+ of stream 1. */
+#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers
+ for stream 3. */
+#define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \
+ XDPTX_STREAM1_MSA_START) /**< The MSA registers for
+ stream 3 are at an
+ offset from the
+ corresponding registers
+ of stream 1. */
+#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers
+ for stream 4. */
+#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \
+ XDPTX_STREAM1_MSA_START) /**< The MSA registers for
+ stream 4 are at an
+ offset from the
+ corresponding registers
+ of stream 1. */
/* @} */
-#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload
- table (0xFF bytes). */
+#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload
+ table (0xFF bytes). */
/******************************************************************************/
@@ -331,393 +333,393 @@
* @{
*/
/* 0x000: LINK_BW_SET */
-#define XDPTX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
-#define XDPTX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
-#define XDPTX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
+#define XDPTX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
+#define XDPTX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
+#define XDPTX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
/* 0x001: LANE_COUNT_SET */
-#define XDPTX_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */
-#define XDPTX_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */
-#define XDPTX_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */
+#define XDPTX_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */
+#define XDPTX_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */
+#define XDPTX_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */
/* 0x00C: TRAINING_PATTERN_SET */
-#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */
-#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for
- clock recovery. */
-#define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 /**< Training pattern 2 used for
- channel equalization. */
-#define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 /**< Training pattern 3 used for
- channel equalization for
- cores with DP v1.2. */
+#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */
+#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for
+ clock recovery. */
+#define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 /**< Training pattern 2 used for
+ channel equalization. */
+#define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 /**< Training pattern 3 used for
+ channel equalization for
+ cores with DP v1.2. */
/* 0x010: LINK_QUAL_PATTERN_SET */
-#define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 /**< Link quality test pattern
- not transmitted. */
+#define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 /**< Link quality test pattern
+ not transmitted. */
#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST \
- 0x1 /**< D10.2 unscrambled test
- pattern transmitted. */
+ 0x1 /**< D10.2 unscrambled test
+ pattern transmitted. */
#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES \
- 0x2 /**< Symbol error rate
- measurement pattern
- transmitted. */
+ 0x2 /**< Symbol error rate
+ measurement pattern
+ transmitted. */
#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 \
- 0x3 /**< Pseudo random bit sequence
- 7 transmitted. */
+ 0x3 /**< Pseudo random bit sequence
+ 7 transmitted. */
/* 0x01C: SOFTWARE_RESET */
#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \
- 0x00000001 /**< Reset video logic. */
+ 0x00000001 /**< Reset video logic. */
#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \
- 0x00000002 /**< Reset video logic. */
+ 0x00000002 /**< Reset video logic. */
#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \
- 0x00000004 /**< Reset video logic. */
+ 0x00000004 /**< Reset video logic. */
#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \
- 0x00000008 /**< Reset video logic. */
+ 0x00000008 /**< Reset video logic. */
#define XDPTX_SOFT_RESET_AUX_MASK \
- 0x00000080 /**< Reset AUX logic. */
+ 0x00000080 /**< Reset AUX logic. */
#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK \
- 0x0000000F /**< Reset video logic for all
- streams. */
+ 0x0000000F /**< Reset video logic for all
+ streams. */
/* 0x0D0: TX_MST_CONFIG */
#define XDPTX_TX_MST_CONFIG_MST_EN_MASK \
- 0x00000001 /**< Enable MST. */
+ 0x00000001 /**< Enable MST. */
#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK \
- 0x00000002 /**< The VC payload has been
- updated in the sink. */
+ 0x00000002 /**< The VC payload has been
+ updated in the sink. */
/* 0x0F8 : VERSION_REGISTER */
#define XDPTX_VERSION_INTER_REV_MASK \
- 0x0000000F /**< Internal revision. */
+ 0x0000000F /**< Internal revision. */
#define XDPTX_VERSION_CORE_PATCH_MASK \
- 0x00000030 /**< Core patch details. */
+ 0x00000030 /**< Core patch details. */
#define XDPTX_VERSION_CORE_PATCH_SHIFT \
- 8 /**< Shift bits for core patch
- details. */
+ 8 /**< Shift bits for core patch
+ details. */
#define XDPTX_VERSION_CORE_VER_REV_MASK \
- 0x000000C0 /**< Core version revision. */
+ 0x000000C0 /**< Core version revision. */
#define XDPTX_VERSION_CORE_VER_REV_SHIFT \
- 12 /**< Shift bits for core version
- revision. */
+ 12 /**< Shift bits for core version
+ revision. */
#define XDPTX_VERSION_CORE_VER_MNR_MASK \
- 0x00000F00 /**< Core minor version. */
+ 0x00000F00 /**< Core minor version. */
#define XDPTX_VERSION_CORE_VER_MNR_SHIFT \
- 16 /**< Shift bits for core minor
- version. */
+ 16 /**< Shift bits for core minor
+ version. */
#define XDPTX_VERSION_CORE_VER_MJR_MASK \
- 0x0000F000 /**< Core major version. */
+ 0x0000F000 /**< Core major version. */
#define XDPTX_VERSION_CORE_VER_MJR_SHIFT \
- 24 /**< Shift bits for core major
- version. */
+ 24 /**< Shift bits for core major
+ version. */
/* 0x0FC : CORE_ID */
-#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */
-#define XDPTX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */
-#define XDPTX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */
+#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */
+#define XDPTX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */
+#define XDPTX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */
#define XDPTX_CORE_ID_DP_REV_MASK \
- 0x000000F0 /**< DisplayPort protocol
- revision. */
+ 0x000000F0 /**< DisplayPort protocol
+ revision. */
#define XDPTX_CORE_ID_DP_REV_SHIFT \
- 8 /**< Shift bits for DisplayPort
- protocol revision. */
+ 8 /**< Shift bits for DisplayPort
+ protocol revision. */
#define XDPTX_CORE_ID_DP_MNR_VER_MASK \
- 0x00000F00 /**< DisplayPort protocol minor
- version. */
+ 0x00000F00 /**< DisplayPort protocol minor
+ version. */
#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT \
- 16 /**< Shift bits for DisplayPort
- protocol major
- version. */
+ 16 /**< Shift bits for DisplayPort
+ protocol major
+ version. */
#define XDPTX_CORE_ID_DP_MJR_VER_MASK \
- 0x0000F000 /**< DisplayPort protocol major
- version. */
+ 0x0000F000 /**< DisplayPort protocol major
+ version. */
#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT \
- 24 /**< Shift bits for DisplayPort
- protocol major
- version. */
+ 24 /**< Shift bits for DisplayPort
+ protocol major
+ version. */
/* 0x100 AUX_CMD */
#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK \
- 0x0000000F /**< Number of bytes to transfer
- with the current AUX
- command. */
-#define XDPTX_AUX_CMD_MASK 0x00000F00 /**< AUX command. */
-#define XDPTX_AUX_CMD_SHIFT 8 /**< Shift bits for command. */
-#define XDPTX_AUX_CMD_I2C_WRITE 0x0 /**< I2C-over-AUX write
- command. */
-#define XDPTX_AUX_CMD_I2C_READ 0x1 /**< I2C-over-AUX read
- command. */
-#define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 /**< I2C-over-AUX write status
- command. */
-#define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 /**< I2C-over-AUX write MOT
- (middle-of-transaction)
- command. */
-#define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 /**< I2C-over-AUX read MOT
- (middle-of-transaction)
- command. */
+ 0x0000000F /**< Number of bytes to transfer
+ with the current AUX
+ command. */
+#define XDPTX_AUX_CMD_MASK 0x00000F00 /**< AUX command. */
+#define XDPTX_AUX_CMD_SHIFT 8 /**< Shift bits for command. */
+#define XDPTX_AUX_CMD_I2C_WRITE 0x0 /**< I2C-over-AUX write
+ command. */
+#define XDPTX_AUX_CMD_I2C_READ 0x1 /**< I2C-over-AUX read
+ command. */
+#define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 /**< I2C-over-AUX write status
+ command. */
+#define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 /**< I2C-over-AUX write MOT
+ (middle-of-transaction)
+ command. */
+#define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 /**< I2C-over-AUX read MOT
+ (middle-of-transaction)
+ command. */
#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT \
- 0x6 /**< I2C-over-AUX write status
- MOT (middle-of-
- transaction) command. */
-#define XDPTX_AUX_CMD_WRITE 0x8 /**< AUX write command. */
-#define XDPTX_AUX_CMD_READ 0x9 /**< AUX read command. */
+ 0x6 /**< I2C-over-AUX write status
+ MOT (middle-of-
+ transaction) command. */
+#define XDPTX_AUX_CMD_WRITE 0x8 /**< AUX write command. */
+#define XDPTX_AUX_CMD_READ 0x9 /**< AUX read command. */
#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN \
- 0x00001000 /**< Address only transfer
- enable (STOP will be
- sent after command). */
+ 0x00001000 /**< Address only transfer
+ enable (STOP will be
+ sent after command). */
/* 0x10C: AUX_CLK_DIVIDER */
#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK \
- 0x0000000F /**< Clock divider value. */
+ 0x0000000F /**< Clock divider value. */
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \
- 0x00000F00 /**< AUX (noise) signal width
- filter. */
+ 0x00000F00 /**< AUX (noise) signal width
+ filter. */
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \
- 8 /**< Shift bits for AUX signal
- width filter. */
+ 8 /**< Shift bits for AUX signal
+ width filter. */
/* 0x130: INTERRUPT_SIG_STATE */
#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK \
- 0x00000001 /**< Raw state of the HPD pin on
- the DP connector. */
+ 0x00000001 /**< Raw state of the HPD pin on
+ the DP connector. */
#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK \
- 0x00000002 /**< A request is currently
- being sent. */
+ 0x00000002 /**< A request is currently
+ being sent. */
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK \
- 0x00000004 /**< A reply is currently being
- received. */
+ 0x00000004 /**< A reply is currently being
+ received. */
#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK \
- 0x00000008 /**< A reply timeout has
- occurred. */
+ 0x00000008 /**< A reply timeout has
+ occurred. */
/* 0x138: AUX_REPLY_CODE */
-#define XDPTX_AUX_REPLY_CODE_ACK 0x0 /**< AUX command ACKed. */
-#define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 /**< I2C-over-AUX command
- not ACKed. */
-#define XDPTX_AUX_REPLY_CODE_NACK 0x1 /**< AUX command not ACKed. */
-#define XDPTX_AUX_REPLY_CODE_DEFER 0x2 /**< AUX command deferred. */
-#define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 /**< I2C-over-AUX command not
- ACKed. */
-#define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 /**< I2C-over-AUX command
- deferred. */
+#define XDPTX_AUX_REPLY_CODE_ACK 0x0 /**< AUX command ACKed. */
+#define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 /**< I2C-over-AUX command
+ not ACKed. */
+#define XDPTX_AUX_REPLY_CODE_NACK 0x1 /**< AUX command not ACKed. */
+#define XDPTX_AUX_REPLY_CODE_DEFER 0x2 /**< AUX command deferred. */
+#define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 /**< I2C-over-AUX command not
+ ACKed. */
+#define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 /**< I2C-over-AUX command
+ deferred. */
/* 0x140: INTERRUPT_STATUS */
#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK \
- 0x00000001 /**< Detected an IRQ framed with
- the proper timing on the
- HPD signal. */
+ 0x00000001 /**< Detected an IRQ framed with
+ the proper timing on the
+ HPD signal. */
#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK \
- 0x00000002 /**< Detected the presence of
- the HPD signal. */
+ 0x00000002 /**< Detected the presence of
+ the HPD signal. */
#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK \
- 0x00000004 /**< An AUX reply transaction
- has been detected. */
+ 0x00000004 /**< An AUX reply transaction
+ has been detected. */
#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK \
- 0x00000008 /**< A reply timeout has
- occurred. */
+ 0x00000008 /**< A reply timeout has
+ occurred. */
#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK \
- 0x00000010 /**< A pulse on the HPD line was
- detected. */
+ 0x00000010 /**< A pulse on the HPD line was
+ detected. */
#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK \
- 0x00000020 /**< Extended packet has been
- transmitted and the core
- is ready to accept a new
- packet. */
+ 0x00000020 /**< Extended packet has been
+ transmitted and the core
+ is ready to accept a new
+ packet. */
/* 0x144: INTERRUPT_MASK */
#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK \
- 0x00000001 /**< Mask HPD IRQ interrupt. */
+ 0x00000001 /**< Mask HPD IRQ interrupt. */
#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK \
- 0x00000002 /**< Mask HPD event
- interrupt. */
+ 0x00000002 /**< Mask HPD event
+ interrupt. */
#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK \
- 0x00000004 /**< Mask reply received
- interrupt. */
+ 0x00000004 /**< Mask reply received
+ interrupt. */
#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK \
- 0x00000008 /**< Mask reply received
- interrupt. */
+ 0x00000008 /**< Mask reply received
+ interrupt. */
#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK \
- 0x00000010 /**< Mask HPD pulse detected
- interrupt. */
+ 0x00000010 /**< Mask HPD pulse detected
+ interrupt. */
#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK \
- 0x00000020 /**< Mask extended packet
- transmit interrupt. */
+ 0x00000020 /**< Mask extended packet
+ transmit interrupt. */
/* 0x14C: REPLY_STATUS */
#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK \
- 0x00000001 /**< AUX transaction is complete
- and a valid reply
- transaction received. */
+ 0x00000001 /**< AUX transaction is complete
+ and a valid reply
+ transaction received. */
#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK \
- 0x00000002 /**< AUX reply is currently
- being received. */
+ 0x00000002 /**< AUX reply is currently
+ being received. */
#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK \
- 0x00000004 /**< AUX request is currently
- being transmitted. */
+ 0x00000004 /**< AUX request is currently
+ being transmitted. */
#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK \
- 0x00000008 /**< Detected an error in the
- AUX reply of the most
- recent transaction. */
+ 0x00000008 /**< Detected an error in the
+ AUX reply of the most
+ recent transaction. */
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK \
- 0x00000FF0 /**< Internal AUX reply state
- machine status bits. */
+ 0x00000FF0 /**< Internal AUX reply state
+ machine status bits. */
#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT \
- 4 /**< Shift bits for the internal
- AUX reply state machine
- status. */
+ 4 /**< Shift bits for the internal
+ AUX reply state machine
+ status. */
/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[1-4]_POLARITY */
#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \
- 0x00000001 /**< Polarity of the horizontal
- sync pulse. */
+ 0x00000001 /**< Polarity of the horizontal
+ sync pulse. */
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK \
- 0x00000002 /**< Polarity of the vertical
- sync pulse. */
+ 0x00000002 /**< Polarity of the vertical
+ sync pulse. */
#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT \
- 1 /**< Shift bits for polarity of
- the vertical sync
- pulse. */
+ 1 /**< Shift bits for polarity of
+ the vertical sync
+ pulse. */
/* 0x1A4, 0x524, 0x574, 0x5C4: MAIN_STREAM[1-4]_MISC0 */
#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \
- 0x00000001 /**< Synchronous clock. */
+ 0x00000001 /**< Synchronous clock. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \
- 0x00000006 /**< Component format. */
+ 0x00000006 /**< Component format. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \
- 1 /**< Shift bits for component
- format. */
+ 1 /**< Shift bits for component
+ format. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB \
- 0x0 /**< Stream's component format
- is RGB. */
+ 0x0 /**< Stream's component format
+ is RGB. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 \
- 0x1 /**< Stream's component format
- is YcbCr 4:2:2. */
+ 0x1 /**< Stream's component format
+ is YcbCr 4:2:2. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 \
- 0x2 /**< Stream's component format
- is YcbCr 4:4:4. */
+ 0x2 /**< Stream's component format
+ is YcbCr 4:4:4. */
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \
- 0x00000008 /**< Dynamic range. */
+ 0x00000008 /**< Dynamic range. */
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \
- 3 /**< Shift bits for dynamic
- range. */
+ 3 /**< Shift bits for dynamic
+ range. */
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK \
- 0x00000010 /**< YCbCr colorimetry. */
+ 0x00000010 /**< YCbCr colorimetry. */
#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT \
- 4 /**< Shift bits for YCbCr
- colorimetry. */
+ 4 /**< Shift bits for YCbCr
+ colorimetry. */
#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK \
- 0x000000E0 /**< Bit depth per color
- component (BDC). */
+ 0x000000E0 /**< Bit depth per color
+ component (BDC). */
#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT \
- 5 /**< Shift bits for BDC.*/
+ 5 /**< Shift bits for BDC.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC \
- 0x0 /**< 6 bits per component.*/
+ 0x0 /**< 6 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC \
- 0x1 /**< 8 bits per component.*/
+ 0x1 /**< 8 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC \
- 0x2 /**< 10 bits per component.*/
+ 0x2 /**< 10 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC \
- 0x3 /**< 12 bits per component.*/
+ 0x3 /**< 12 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC \
- 0x4 /**< 16 bits per component.*/
+ 0x4 /**< 16 bits per component.*/
/* 0x1A8, 0x528, 0x578, 0x5C8: MAIN_STREAM[1-4]_MISC1 */
#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \
- 0x00000001 /**< Interlaced vertical total
- even. */
+ 0x00000001 /**< Interlaced vertical total
+ even. */
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK \
- 0x00000006 /**< Stereo video attribute. */
+ 0x00000006 /**< Stereo video attribute. */
#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT \
- 1 /**< Shift bits for stereo video
- attribute. */
+ 1 /**< Shift bits for stereo video
+ attribute. */
/* 0x200: PHY_CONFIG */
#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \
- 0x0010000 /**< Release reset. */
+ 0x0010000 /**< Release reset. */
#define XDPTX_PHY_CONFIG_PHY_RESET_MASK \
- 0x0010001 /**< Hold the PHY in reset. */
+ 0x0010001 /**< Hold the PHY in reset. */
#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK \
- 0x0010002 /**< Hold GTTXRESET in reset. */
+ 0x0010002 /**< Hold GTTXRESET in reset. */
#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \
- 0x0010100 /**< Hold TX_PHY_PMA reset. */
+ 0x0010100 /**< Hold TX_PHY_PMA reset. */
#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \
- 0x0010200 /**< HOLD TX_PHY_PCS reset. */
+ 0x0010200 /**< HOLD TX_PHY_PCS reset. */
#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \
- 0x0010400 /**< Set TX_PHY_POLARITY. */
+ 0x0010400 /**< Set TX_PHY_POLARITY. */
#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \
- 0x0011000 /**< Set TX_PHY_PRBSFORCEERR. */
+ 0x0011000 /**< Set TX_PHY_PRBSFORCEERR. */
#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \
- 0x001E000 /**< Set TX_PHY_LOOPBACK. */
+ 0x001E000 /**< Set TX_PHY_LOOPBACK. */
#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK \
- 0x0010003 /**< Rest GT and PHY. */
+ 0x0010003 /**< Rest GT and PHY. */
/* 0x234: PHY_CLOCK_SELECT */
-#define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */
-#define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */
-#define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 /**< 5.40 Gbps link. */
+#define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */
+#define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */
+#define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 /**< 5.40 Gbps link. */
/* 0x0220, 0x0224, 0x0228, 0x022C: XDPTX_PHY_VOLTAGE_DIFF_LANE_[0-3] */
-#define XDPTX_VS_LEVEL_0 0x2 /**< Voltage swing level 0. */
-#define XDPTX_VS_LEVEL_1 0x5 /**< Voltage swing level 1. */
-#define XDPTX_VS_LEVEL_2 0x8 /**< Voltage swing level 2. */
-#define XDPTX_VS_LEVEL_3 0xF /**< Voltage swing level 3. */
-#define XDPTX_VS_LEVEL_OFFSET 0x4 /**< Voltage swing compensation
- offset used when there's
- no redriver in display
- path. */
+#define XDPTX_VS_LEVEL_0 0x2 /**< Voltage swing level 0. */
+#define XDPTX_VS_LEVEL_1 0x5 /**< Voltage swing level 1. */
+#define XDPTX_VS_LEVEL_2 0x8 /**< Voltage swing level 2. */
+#define XDPTX_VS_LEVEL_3 0xF /**< Voltage swing level 3. */
+#define XDPTX_VS_LEVEL_OFFSET 0x4 /**< Voltage swing compensation
+ offset used when there's
+ no redriver in display
+ path. */
/* 0x024C, 0x0250, 0x0254, 0x0258: XDPTX_PHY_POSTCURSOR_LANE_[0-3] */
-#define XDPTX_PE_LEVEL_0 0x00 /**< Pre-emphasis level 0. */
-#define XDPTX_PE_LEVEL_1 0x0E /**< Pre-emphasis level 1. */
-#define XDPTX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */
-#define XDPTX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */
+#define XDPTX_PE_LEVEL_0 0x00 /**< Pre-emphasis level 0. */
+#define XDPTX_PE_LEVEL_1 0x0E /**< Pre-emphasis level 1. */
+#define XDPTX_PE_LEVEL_2 0x14 /**< Pre-emphasis level 2. */
+#define XDPTX_PE_LEVEL_3 0x1B /**< Pre-emphasis level 3. */
/* 0x280: PHY_STATUS */
#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \
- 0x00000003 /**< Reset done for lanes
- 0 and 1. */
+ 0x00000003 /**< Reset done for lanes
+ 0 and 1. */
#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \
- 0x0000000C /**< Reset done for lanes
- 2 and 3. */
+ 0x0000000C /**< Reset done for lanes
+ 2 and 3. */
#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \
- 0x00000010 /**< PLL locked for lanes
- 0 and 1. */
+ 0x00000010 /**< PLL locked for lanes
+ 0 and 1. */
#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \
- 0x00000020 /**< PLL locked for lanes
- 2 and 3. */
+ 0x00000020 /**< PLL locked for lanes
+ 2 and 3. */
#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \
- 0x00000020 /**< FPGA fabric clock PLL
- locked. */
+ 0x00000020 /**< FPGA fabric clock PLL
+ locked. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK \
- 0x00030000 /**< TX buffer status lane 0. */
+ 0x00030000 /**< TX buffer status lane 0. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT \
- 16 /**< Shift bits for TX buffer
- status lane 0. */
+ 16 /**< Shift bits for TX buffer
+ status lane 0. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK \
- 0x000C0000 /**< TX error on lane 0. */
+ 0x000C0000 /**< TX error on lane 0. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT \
- 18 /**< Shift bits for TX error on
- lane 0. */
+ 18 /**< Shift bits for TX error on
+ lane 0. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK \
- 0x00300000 /**< TX buffer status lane 1. */
+ 0x00300000 /**< TX buffer status lane 1. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT \
- 20 /**< Shift bits for TX buffer
- status lane 1. */
+ 20 /**< Shift bits for TX buffer
+ status lane 1. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK \
- 0x00C00000 /**< TX error on lane 1. */
+ 0x00C00000 /**< TX error on lane 1. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT \
- 22 /**< Shift bits for TX error on
- lane 1. */
+ 22 /**< Shift bits for TX error on
+ lane 1. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK \
- 0x03000000 /**< TX buffer status lane 2. */
+ 0x03000000 /**< TX buffer status lane 2. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT \
- 24 /**< Shift bits for TX buffer
- status lane 2. */
+ 24 /**< Shift bits for TX buffer
+ status lane 2. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK \
- 0x0C000000 /**< TX error on lane 2. */
+ 0x0C000000 /**< TX error on lane 2. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT \
- 26 /**< Shift bits for TX error on
- lane 2. */
+ 26 /**< Shift bits for TX error on
+ lane 2. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK \
- 0x30000000 /**< TX buffer status lane 3. */
+ 0x30000000 /**< TX buffer status lane 3. */
#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT \
- 28 /**< Shift bits for TX buffer
- status lane 3. */
+ 28 /**< Shift bits for TX buffer
+ status lane 3. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK \
- 0xC0000000 /**< TX error on lane 3. */
+ 0xC0000000 /**< TX error on lane 3. */
#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \
- 30 /**< Shift bits for TX error on
- lane 3. */
+ 30 /**< Shift bits for TX error on
+ lane 3. */
#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK \
- 0x0000003F /**< All lanes are ready. */
+ 0x0000003F /**< All lanes are ready. */
/* 0x2A0: XDPTX_GT_DRP_COMMAND */
#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK \
- 0x000F /**< DRP address. */
+ 0x000F /**< DRP address. */
#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK \
- 0x0080 /**< DRP read/write command
- (Read=0, Write=1). */
+ 0x0080 /**< DRP read/write command
+ (Read=0, Write=1). */
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK \
- 0xFF00 /**< DRP write data. */
+ 0xFF00 /**< DRP write data. */
#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT \
- 16 /**< Shift bits for DRP write
- data. */
+ 16 /**< Shift bits for DRP write
+ data. */
/* @} */
/******************************************************************************/
@@ -731,167 +733,167 @@
/** @name DisplayPort Configuration Data: Receiver capability field.
* @{
*/
-#define XDPTX_DPCD_REV 0x00000
-#define XDPTX_DPCD_MAX_LINK_RATE 0x00001
-#define XDPTX_DPCD_MAX_LANE_COUNT 0x00002
-#define XDPTX_DPCD_MAX_DOWNSPREAD 0x00003
-#define XDPTX_DPCD_NORP_PWR_V_CAP 0x00004
-#define XDPTX_DPCD_DOWNSP_PRESENT 0x00005
-#define XDPTX_DPCD_ML_CH_CODING_CAP 0x00006
-#define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
-#define XDPTX_DPCD_RX_PORT0_CAP_0 0x00008
-#define XDPTX_DPCD_RX_PORT0_CAP_1 0x00009
-#define XDPTX_DPCD_RX_PORT1_CAP_0 0x0000A
-#define XDPTX_DPCD_RX_PORT1_CAP_1 0x0000B
-#define XDPTX_DPCD_I2C_SPEED_CTL_CAP 0x0000C
-#define XDPTX_DPCD_EDP_CFG_CAP 0x0000D
-#define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
-#define XDPTX_DPCD_ADAPTER_CAP 0x0000F
-#define XDPTX_DPCD_FAUX_CAP 0x00020
-#define XDPTX_DPCD_MSTM_CAP 0x00021
-#define XDPTX_DPCD_NUM_AUDIO_EPS 0x00022
-#define XDPTX_DPCD_AV_GRANULARITY 0x00023
-#define XDPTX_DPCD_AUD_DEC_LAT_7_0 0x00024
-#define XDPTX_DPCD_AUD_DEC_LAT_15_8 0x00025
-#define XDPTX_DPCD_AUD_PP_LAT_7_0 0x00026
-#define XDPTX_DPCD_AUD_PP_LAT_15_8 0x00027
-#define XDPTX_DPCD_VID_INTER_LAT 0x00028
-#define XDPTX_DPCD_VID_PROG_LAT 0x00029
-#define XDPTX_DPCD_REP_LAT 0x0002A
-#define XDPTX_DPCD_AUD_DEL_INS_7_0 0x0002B
-#define XDPTX_DPCD_AUD_DEL_INS_15_8 0x0002C
-#define XDPTX_DPCD_AUD_DEL_INS_23_16 0x0002D
-#define XDPTX_DPCD_GUID 0x00030
-#define XDPTX_DPCD_RX_GTC_VALUE_7_0 0x00054
-#define XDPTX_DPCD_RX_GTC_VALUE_15_8 0x00055
-#define XDPTX_DPCD_RX_GTC_VALUE_23_16 0x00056
-#define XDPTX_DPCD_RX_GTC_VALUE_31_24 0x00057
-#define XDPTX_DPCD_RX_GTC_MSTR_REQ 0x00058
-#define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059
-#define XDPTX_DPCD_DOWNSP_0_CAP 0x00080
-#define XDPTX_DPCD_DOWNSP_1_CAP 0x00081
-#define XDPTX_DPCD_DOWNSP_2_CAP 0x00082
-#define XDPTX_DPCD_DOWNSP_3_CAP 0x00083
-#define XDPTX_DPCD_DOWNSP_0_DET_CAP 0x00080
-#define XDPTX_DPCD_DOWNSP_1_DET_CAP 0x00084
-#define XDPTX_DPCD_DOWNSP_2_DET_CAP 0x00088
-#define XDPTX_DPCD_DOWNSP_3_DET_CAP 0x0008C
+#define XDPTX_DPCD_REV 0x00000
+#define XDPTX_DPCD_MAX_LINK_RATE 0x00001
+#define XDPTX_DPCD_MAX_LANE_COUNT 0x00002
+#define XDPTX_DPCD_MAX_DOWNSPREAD 0x00003
+#define XDPTX_DPCD_NORP_PWR_V_CAP 0x00004
+#define XDPTX_DPCD_DOWNSP_PRESENT 0x00005
+#define XDPTX_DPCD_ML_CH_CODING_CAP 0x00006
+#define XDPTX_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
+#define XDPTX_DPCD_RX_PORT0_CAP_0 0x00008
+#define XDPTX_DPCD_RX_PORT0_CAP_1 0x00009
+#define XDPTX_DPCD_RX_PORT1_CAP_0 0x0000A
+#define XDPTX_DPCD_RX_PORT1_CAP_1 0x0000B
+#define XDPTX_DPCD_I2C_SPEED_CTL_CAP 0x0000C
+#define XDPTX_DPCD_EDP_CFG_CAP 0x0000D
+#define XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
+#define XDPTX_DPCD_ADAPTER_CAP 0x0000F
+#define XDPTX_DPCD_FAUX_CAP 0x00020
+#define XDPTX_DPCD_MSTM_CAP 0x00021
+#define XDPTX_DPCD_NUM_AUDIO_EPS 0x00022
+#define XDPTX_DPCD_AV_GRANULARITY 0x00023
+#define XDPTX_DPCD_AUD_DEC_LAT_7_0 0x00024
+#define XDPTX_DPCD_AUD_DEC_LAT_15_8 0x00025
+#define XDPTX_DPCD_AUD_PP_LAT_7_0 0x00026
+#define XDPTX_DPCD_AUD_PP_LAT_15_8 0x00027
+#define XDPTX_DPCD_VID_INTER_LAT 0x00028
+#define XDPTX_DPCD_VID_PROG_LAT 0x00029
+#define XDPTX_DPCD_REP_LAT 0x0002A
+#define XDPTX_DPCD_AUD_DEL_INS_7_0 0x0002B
+#define XDPTX_DPCD_AUD_DEL_INS_15_8 0x0002C
+#define XDPTX_DPCD_AUD_DEL_INS_23_16 0x0002D
+#define XDPTX_DPCD_GUID 0x00030
+#define XDPTX_DPCD_RX_GTC_VALUE_7_0 0x00054
+#define XDPTX_DPCD_RX_GTC_VALUE_15_8 0x00055
+#define XDPTX_DPCD_RX_GTC_VALUE_23_16 0x00056
+#define XDPTX_DPCD_RX_GTC_VALUE_31_24 0x00057
+#define XDPTX_DPCD_RX_GTC_MSTR_REQ 0x00058
+#define XDPTX_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059
+#define XDPTX_DPCD_DOWNSP_0_CAP 0x00080
+#define XDPTX_DPCD_DOWNSP_1_CAP 0x00081
+#define XDPTX_DPCD_DOWNSP_2_CAP 0x00082
+#define XDPTX_DPCD_DOWNSP_3_CAP 0x00083
+#define XDPTX_DPCD_DOWNSP_0_DET_CAP 0x00080
+#define XDPTX_DPCD_DOWNSP_1_DET_CAP 0x00084
+#define XDPTX_DPCD_DOWNSP_2_DET_CAP 0x00088
+#define XDPTX_DPCD_DOWNSP_3_DET_CAP 0x0008C
/* @} */
/** @name DisplayPort Configuration Data: Link configuration field.
* @{
*/
-#define XDPTX_DPCD_LINK_BW_SET 0x00100
-#define XDPTX_DPCD_LANE_COUNT_SET 0x00101
-#define XDPTX_DPCD_TP_SET 0x00102
-#define XDPTX_DPCD_TRAINING_LANE0_SET 0x00103
-#define XDPTX_DPCD_TRAINING_LANE1_SET 0x00104
-#define XDPTX_DPCD_TRAINING_LANE2_SET 0x00105
-#define XDPTX_DPCD_TRAINING_LANE3_SET 0x00106
-#define XDPTX_DPCD_DOWNSPREAD_CTRL 0x00107
-#define XDPTX_DPCD_ML_CH_CODING_SET 0x00108
-#define XDPTX_DPCD_I2C_SPEED_CTL_SET 0x00109
-#define XDPTX_DPCD_EDP_CFG_SET 0x0010A
-#define XDPTX_DPCD_LINK_QUAL_LANE0_SET 0x0010B
-#define XDPTX_DPCD_LINK_QUAL_LANE1_SET 0x0010C
-#define XDPTX_DPCD_LINK_QUAL_LANE2_SET 0x0010D
-#define XDPTX_DPCD_LINK_QUAL_LANE3_SET 0x0010E
-#define XDPTX_DPCD_TRAINING_LANE0_1_SET2 0x0010F
-#define XDPTX_DPCD_TRAINING_LANE2_3_SET2 0x00110
-#define XDPTX_DPCD_MSTM_CTRL 0x00111
-#define XDPTX_DPCD_AUDIO_DELAY_7_0 0x00112
-#define XDPTX_DPCD_AUDIO_DELAY_15_8 0x00113
-#define XDPTX_DPCD_AUDIO_DELAY_23_6 0x00114
-#define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
-#define XDPTX_DPCD_FAUX_MODE_CTRL 0x00120
-#define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121
-#define XDPTX_DPCD_BACK_CH_STATUS 0x00122
-#define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123
-#define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125
-#define XDPTX_DPCD_TX_GTC_VALUE_7_0 0x00154
-#define XDPTX_DPCD_TX_GTC_VALUE_15_8 0x00155
-#define XDPTX_DPCD_TX_GTC_VALUE_23_16 0x00156
-#define XDPTX_DPCD_TX_GTC_VALUE_31_24 0x00157
-#define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
-#define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159
-#define XDPTX_DPCD_ADAPTER_CTRL 0x001A0
-#define XDPTX_DPCD_BRANCH_DEVICE_CTRL 0x001A1
-#define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0
-#define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
-#define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
+#define XDPTX_DPCD_LINK_BW_SET 0x00100
+#define XDPTX_DPCD_LANE_COUNT_SET 0x00101
+#define XDPTX_DPCD_TP_SET 0x00102
+#define XDPTX_DPCD_TRAINING_LANE0_SET 0x00103
+#define XDPTX_DPCD_TRAINING_LANE1_SET 0x00104
+#define XDPTX_DPCD_TRAINING_LANE2_SET 0x00105
+#define XDPTX_DPCD_TRAINING_LANE3_SET 0x00106
+#define XDPTX_DPCD_DOWNSPREAD_CTRL 0x00107
+#define XDPTX_DPCD_ML_CH_CODING_SET 0x00108
+#define XDPTX_DPCD_I2C_SPEED_CTL_SET 0x00109
+#define XDPTX_DPCD_EDP_CFG_SET 0x0010A
+#define XDPTX_DPCD_LINK_QUAL_LANE0_SET 0x0010B
+#define XDPTX_DPCD_LINK_QUAL_LANE1_SET 0x0010C
+#define XDPTX_DPCD_LINK_QUAL_LANE2_SET 0x0010D
+#define XDPTX_DPCD_LINK_QUAL_LANE3_SET 0x0010E
+#define XDPTX_DPCD_TRAINING_LANE0_1_SET2 0x0010F
+#define XDPTX_DPCD_TRAINING_LANE2_3_SET2 0x00110
+#define XDPTX_DPCD_MSTM_CTRL 0x00111
+#define XDPTX_DPCD_AUDIO_DELAY_7_0 0x00112
+#define XDPTX_DPCD_AUDIO_DELAY_15_8 0x00113
+#define XDPTX_DPCD_AUDIO_DELAY_23_6 0x00114
+#define XDPTX_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
+#define XDPTX_DPCD_FAUX_MODE_CTRL 0x00120
+#define XDPTX_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121
+#define XDPTX_DPCD_BACK_CH_STATUS 0x00122
+#define XDPTX_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123
+#define XDPTX_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125
+#define XDPTX_DPCD_TX_GTC_VALUE_7_0 0x00154
+#define XDPTX_DPCD_TX_GTC_VALUE_15_8 0x00155
+#define XDPTX_DPCD_TX_GTC_VALUE_23_16 0x00156
+#define XDPTX_DPCD_TX_GTC_VALUE_31_24 0x00157
+#define XDPTX_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
+#define XDPTX_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159
+#define XDPTX_DPCD_ADAPTER_CTRL 0x001A0
+#define XDPTX_DPCD_BRANCH_DEVICE_CTRL 0x001A1
+#define XDPTX_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0
+#define XDPTX_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
+#define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
/* @} */
/** @name DisplayPort Configuration Data: Link/sink status field.
* @{
*/
-#define XDPTX_DPCD_SINK_COUNT 0x00200
-#define XDPTX_DPCD_DEVICE_SERVICE_IRQ 0x00201
-#define XDPTX_DPCD_STATUS_LANE_0_1 0x00202
-#define XDPTX_DPCD_STATUS_LANE_2_3 0x00203
-#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204
-#define XDPTX_DPCD_SINK_STATUS 0x00205
-#define XDPTX_DPCD_ADJ_REQ_LANE_0_1 0x00206
-#define XDPTX_DPCD_ADJ_REQ_LANE_2_3 0x00207
-#define XDPTX_DPCD_TRAINING_SCORE_LANE_0 0x00208
-#define XDPTX_DPCD_TRAINING_SCORE_LANE_1 0x00209
-#define XDPTX_DPCD_TRAINING_SCORE_LANE_2 0x0020A
-#define XDPTX_DPCD_TRAINING_SCORE_LANE_3 0x0020B
-#define XDPTX_DPCD_ADJ_REQ_PC2 0x0020C
-#define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D
-#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210
-#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212
-#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214
-#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
+#define XDPTX_DPCD_SINK_COUNT 0x00200
+#define XDPTX_DPCD_DEVICE_SERVICE_IRQ 0x00201
+#define XDPTX_DPCD_STATUS_LANE_0_1 0x00202
+#define XDPTX_DPCD_STATUS_LANE_2_3 0x00203
+#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204
+#define XDPTX_DPCD_SINK_STATUS 0x00205
+#define XDPTX_DPCD_ADJ_REQ_LANE_0_1 0x00206
+#define XDPTX_DPCD_ADJ_REQ_LANE_2_3 0x00207
+#define XDPTX_DPCD_TRAINING_SCORE_LANE_0 0x00208
+#define XDPTX_DPCD_TRAINING_SCORE_LANE_1 0x00209
+#define XDPTX_DPCD_TRAINING_SCORE_LANE_2 0x0020A
+#define XDPTX_DPCD_TRAINING_SCORE_LANE_3 0x0020B
+#define XDPTX_DPCD_ADJ_REQ_PC2 0x0020C
+#define XDPTX_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D
+#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210
+#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212
+#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214
+#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
/* @} */
/** @name DisplayPort Configuration Data: Automated testing sub-field.
* @{
*/
-#define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS 0x00280
-#define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281
-#define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282
-#define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
+#define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS 0x00280
+#define XDPTX_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281
+#define XDPTX_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282
+#define XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
#define XDPTX_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum) \
- (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
+ (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
/* @} */
/** @name DisplayPort Configuration Data: Sink control field.
* @{
*/
-#define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
+#define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
/* @} */
/** @name DisplayPort Configuration Data: Sideband message buffers.
* @{
*/
-#define XDPTX_DPCD_DOWN_REQ 0x01000
-#define XDPTX_DPCD_UP_REP 0x01200
-#define XDPTX_DPCD_DOWN_REP 0x01400
-#define XDPTX_DPCD_UP_REQ 0x01600
+#define XDPTX_DPCD_DOWN_REQ 0x01000
+#define XDPTX_DPCD_UP_REP 0x01200
+#define XDPTX_DPCD_DOWN_REP 0x01400
+#define XDPTX_DPCD_UP_REQ 0x01600
/* @} */
/** @name DisplayPort Configuration Data: Event status indicator field.
* @{
*/
-#define XDPTX_DPCD_SINK_COUNT_ESI 0x02002
-#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
-#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
-#define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
-#define XDPTX_DPCD_SINK_LANE0_1_STATUS 0x0200C
-#define XDPTX_DPCD_SINK_LANE2_3_STATUS 0x0200D
-#define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E
-#define XDPTX_DPCD_SINK_STATUS_ESI 0x0200F
+#define XDPTX_DPCD_SINK_COUNT_ESI 0x02002
+#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
+#define XDPTX_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
+#define XDPTX_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
+#define XDPTX_DPCD_SINK_LANE0_1_STATUS 0x0200C
+#define XDPTX_DPCD_SINK_LANE2_3_STATUS 0x0200D
+#define XDPTX_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E
+#define XDPTX_DPCD_SINK_STATUS_ESI 0x0200F
/* @} */
/** @name DisplayPort Configuration Data: Field addresses and sizes.
* @{
*/
-#define XDPTX_DPCD_RECEIVER_CAP_FIELD_START XDPTX_DPCD_REV
-#define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100
-#define XDPTX_DPCD_LINK_CFG_FIELD_START XDPTX_DPCD_LINK_BW_SET
-#define XDPTX_DPCD_LINK_CFG_FIELD_SIZE 0x100
-#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START XDPTX_DPCD_SINK_COUNT
-#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17
+#define XDPTX_DPCD_RECEIVER_CAP_FIELD_START XDPTX_DPCD_REV
+#define XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100
+#define XDPTX_DPCD_LINK_CFG_FIELD_START XDPTX_DPCD_LINK_BW_SET
+#define XDPTX_DPCD_LINK_CFG_FIELD_SIZE 0x100
+#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_START XDPTX_DPCD_SINK_COUNT
+#define XDPTX_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17
/* @} */
/******************************************************************************/
@@ -901,87 +903,87 @@
* @{
*/
/* 0x00000: DPCD_REV */
-#define XDPTX_DPCD_REV_MNR_MASK 0x0F
-#define XDPTX_DPCD_REV_MJR_MASK 0xF0
-#define XDPTX_DPCD_REV_MJR_SHIFT 4
+#define XDPTX_DPCD_REV_MNR_MASK 0x0F
+#define XDPTX_DPCD_REV_MJR_MASK 0xF0
+#define XDPTX_DPCD_REV_MJR_SHIFT 4
/* 0x00001: MAX_LINK_RATE */
-#define XDPTX_DPCD_MAX_LINK_RATE_162GBPS 0x06
-#define XDPTX_DPCD_MAX_LINK_RATE_270GBPS 0x0A
-#define XDPTX_DPCD_MAX_LINK_RATE_540GBPS 0x14
+#define XDPTX_DPCD_MAX_LINK_RATE_162GBPS 0x06
+#define XDPTX_DPCD_MAX_LINK_RATE_270GBPS 0x0A
+#define XDPTX_DPCD_MAX_LINK_RATE_540GBPS 0x14
/* 0x00002: MAX_LANE_COUNT */
-#define XDPTX_DPCD_MAX_LANE_COUNT_MASK 0x1F
-#define XDPTX_DPCD_MAX_LANE_COUNT_1 0x01
-#define XDPTX_DPCD_MAX_LANE_COUNT_2 0x02
-#define XDPTX_DPCD_MAX_LANE_COUNT_4 0x04
-#define XDPTX_DPCD_TPS3_SUPPORT_MASK 0x40
-#define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
+#define XDPTX_DPCD_MAX_LANE_COUNT_MASK 0x1F
+#define XDPTX_DPCD_MAX_LANE_COUNT_1 0x01
+#define XDPTX_DPCD_MAX_LANE_COUNT_2 0x02
+#define XDPTX_DPCD_MAX_LANE_COUNT_4 0x04
+#define XDPTX_DPCD_TPS3_SUPPORT_MASK 0x40
+#define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
/* 0x00003: MAX_DOWNSPREAD */
-#define XDPTX_DPCD_MAX_DOWNSPREAD_MASK 0x01
-#define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40
+#define XDPTX_DPCD_MAX_DOWNSPREAD_MASK 0x01
+#define XDPTX_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40
/* 0x00005: DOWNSP_PRESENT */
-#define XDPTX_DPCD_DOWNSP_PRESENT_MASK 0x01
-#define XDPTX_DPCD_DOWNSP_TYPE_MASK 0x06
-#define XDPTX_DPCD_DOWNSP_TYPE_SHIFT 1
-#define XDPTX_DPCD_DOWNSP_TYPE_DP 0x0
-#define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1
-#define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2
-#define XDPTX_DPCD_DOWNSP_TYPE_OTHERS 0x3
-#define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08
-#define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10
+#define XDPTX_DPCD_DOWNSP_PRESENT_MASK 0x01
+#define XDPTX_DPCD_DOWNSP_TYPE_MASK 0x06
+#define XDPTX_DPCD_DOWNSP_TYPE_SHIFT 1
+#define XDPTX_DPCD_DOWNSP_TYPE_DP 0x0
+#define XDPTX_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1
+#define XDPTX_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2
+#define XDPTX_DPCD_DOWNSP_TYPE_OTHERS 0x3
+#define XDPTX_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08
+#define XDPTX_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10
/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */
-#define XDPTX_DPCD_ML_CH_CODING_MASK 0x01
+#define XDPTX_DPCD_ML_CH_CODING_MASK 0x01
/* 0x00007: DOWNSP_COUNT_MSA_OUI */
-#define XDPTX_DPCD_DOWNSP_COUNT_MASK 0x0F
-#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40
-#define XDPTX_DPCD_OUI_SUPPORT_MASK 0x80
+#define XDPTX_DPCD_DOWNSP_COUNT_MASK 0x0F
+#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40
+#define XDPTX_DPCD_OUI_SUPPORT_MASK 0x80
/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */
-#define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02
-#define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04
+#define XDPTX_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02
+#define XDPTX_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04
/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */
-#define XDPTX_DPCD_I2C_SPEED_CTL_NONE 0x00
-#define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS 0x01
-#define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS 0x02
-#define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS 0x04
-#define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS 0x08
-#define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS 0x10
-#define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS 0x20
+#define XDPTX_DPCD_I2C_SPEED_CTL_NONE 0x00
+#define XDPTX_DPCD_I2C_SPEED_CTL_1KBIPS 0x01
+#define XDPTX_DPCD_I2C_SPEED_CTL_5KBIPS 0x02
+#define XDPTX_DPCD_I2C_SPEED_CTL_10KBIPS 0x04
+#define XDPTX_DPCD_I2C_SPEED_CTL_100KBIPS 0x08
+#define XDPTX_DPCD_I2C_SPEED_CTL_400KBIPS 0x10
+#define XDPTX_DPCD_I2C_SPEED_CTL_1MBIPS 0x20
/* 0x0000E: TRAIN_AUX_RD_INTERVAL */
-#define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00
-#define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS 0x01
-#define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS 0x02
-#define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS 0x03
-#define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS 0x04
+#define XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00
+#define XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS 0x01
+#define XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS 0x02
+#define XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS 0x03
+#define XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS 0x04
/* 0x00020: DPCD_FAUX_CAP */
-#define XDPTX_DPCD_FAUX_CAP_MASK 0x01
+#define XDPTX_DPCD_FAUX_CAP_MASK 0x01
/* 0x00021: MSTM_CAP */
-#define XDPTX_DPCD_MST_CAP_MASK 0x01
+#define XDPTX_DPCD_MST_CAP_MASK 0x01
/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4
-#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5
-#define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5
-#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4
+#define XDPTX_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5
+#define XDPTX_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5
+#define XDPTX_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7
/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
-#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03
-#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0
-#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1
-#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2
-#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3
+#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03
+#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0
+#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1
+#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2
+#define XDPTX_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3
/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
-#define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01
-#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02
-#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
+#define XDPTX_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01
+#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02
+#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
/* @} */
/** @name DisplayPort Configuration Data: Link configuration field masks,
@@ -989,55 +991,55 @@
* @{
*/
/* 0x00100: XDPTX_DPCD_LINK_BW_SET */
-#define XDPTX_DPCD_LINK_BW_SET_162GBPS 0x06
-#define XDPTX_DPCD_LINK_BW_SET_270GBPS 0x0A
-#define XDPTX_DPCD_LINK_BW_SET_540GBPS 0x14
+#define XDPTX_DPCD_LINK_BW_SET_162GBPS 0x06
+#define XDPTX_DPCD_LINK_BW_SET_270GBPS 0x0A
+#define XDPTX_DPCD_LINK_BW_SET_540GBPS 0x14
/* 0x00101: LANE_COUNT_SET */
-#define XDPTX_DPCD_LANE_COUNT_SET_MASK 0x1F
-#define XDPTX_DPCD_LANE_COUNT_SET_1 0x01
-#define XDPTX_DPCD_LANE_COUNT_SET_2 0x02
-#define XDPTX_DPCD_LANE_COUNT_SET_4 0x04
-#define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK 0x80
+#define XDPTX_DPCD_LANE_COUNT_SET_MASK 0x1F
+#define XDPTX_DPCD_LANE_COUNT_SET_1 0x01
+#define XDPTX_DPCD_LANE_COUNT_SET_2 0x02
+#define XDPTX_DPCD_LANE_COUNT_SET_4 0x04
+#define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK 0x80
/* 0x00102: TP_SET */
-#define XDPTX_DPCD_TP_SEL_MASK 0x03
-#define XDPTX_DPCD_TP_SEL_OFF 0x0
-#define XDPTX_DPCD_TP_SEL_TP1 0x1
-#define XDPTX_DPCD_TP_SEL_TP2 0x2
-#define XDPTX_DPCD_TP_SEL_TP3 0x3
-#define XDPTX_DPCD_TP_SET_LQP_MASK 0x06
-#define XDPTX_DPCD_TP_SET_LQP_SHIFT 2
-#define XDPTX_DPCD_TP_SET_LQP_OFF 0x0
-#define XDPTX_DPCD_TP_SET_LQP_D102_TEST 0x1
-#define XDPTX_DPCD_TP_SET_LQP_SER_MES 0x2
-#define XDPTX_DPCD_TP_SET_LQP_PRBS7 0x3
-#define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10
-#define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
-#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0
-#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6
-#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0
-#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1
-#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2
+#define XDPTX_DPCD_TP_SEL_MASK 0x03
+#define XDPTX_DPCD_TP_SEL_OFF 0x0
+#define XDPTX_DPCD_TP_SEL_TP1 0x1
+#define XDPTX_DPCD_TP_SEL_TP2 0x2
+#define XDPTX_DPCD_TP_SEL_TP3 0x3
+#define XDPTX_DPCD_TP_SET_LQP_MASK 0x06
+#define XDPTX_DPCD_TP_SET_LQP_SHIFT 2
+#define XDPTX_DPCD_TP_SET_LQP_OFF 0x0
+#define XDPTX_DPCD_TP_SET_LQP_D102_TEST 0x1
+#define XDPTX_DPCD_TP_SET_LQP_SER_MES 0x2
+#define XDPTX_DPCD_TP_SET_LQP_PRBS7 0x3
+#define XDPTX_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10
+#define XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
+#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0
+#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6
+#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0
+#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1
+#define XDPTX_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2
/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */
-#define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03
-#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
-#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18
-#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
-#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
+#define XDPTX_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03
+#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
+#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18
+#define XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
+#define XDPTX_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
/* 0x00107: DOWNSPREAD_CTRL */
-#define XDPTX_DPCD_SPREAD_AMP_MASK 0x10
-#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80
+#define XDPTX_DPCD_SPREAD_AMP_MASK 0x10
+#define XDPTX_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80
/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */
/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */
/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */
-#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03
-#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04
-#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30
-#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4
-#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40
+#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03
+#define XDPTX_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04
+#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30
+#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4
+#define XDPTX_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40
/* 0x00111: MSTM_CTRL */
-#define XDPTX_DPCD_MST_EN_MASK 0x01
-#define XDPTX_DPCD_UP_REQ_EN_MASK 0x02
-#define XDPTX_DPCD_UP_IS_SRC_MASK 0x03
+#define XDPTX_DPCD_MST_EN_MASK 0x01
+#define XDPTX_DPCD_UP_REQ_EN_MASK 0x02
+#define XDPTX_DPCD_UP_IS_SRC_MASK 0x03
/* @} */
/** @name DisplayPort Configuration Data: Link/sink status field masks, shifts,
@@ -1045,46 +1047,46 @@
* @{
*/
/* 0x00202: STATUS_LANE_0_1 */
-#define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
-#define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
-#define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
-#define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
-#define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
-#define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
+#define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
+#define XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
+#define XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
+#define XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
+#define XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
+#define XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
/* 0x00202: STATUS_LANE_2_3 */
-#define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01
-#define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02
-#define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04
-#define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10
-#define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20
-#define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40
+#define XDPTX_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01
+#define XDPTX_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02
+#define XDPTX_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04
+#define XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10
+#define XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20
+#define XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40
/* 0x00204: LANE_ALIGN_STATUS_UPDATED */
#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \
- 0x01
+ 0x01
#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \
- 0x40
+ 0x40
#define XDPTX_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \
- 0x80
+ 0x80
/* 0x00205: SINK_STATUS */
-#define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01
-#define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02
+#define XDPTX_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01
+#define XDPTX_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02
/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */
-#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
-#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
-#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
-#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
-#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
-#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
-#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
+#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
+#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
+#define XDPTX_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
+#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
+#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
+#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
+#define XDPTX_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
/* 0x0020C: ADJ_REQ_PC2 */
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0
-#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0
+#define XDPTX_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6
/* @} */
/******************************************************************************/
@@ -1098,59 +1100,59 @@
/** @name Extended Display Identification Data: Field addresses and sizes.
* @{
*/
-#define XDPTX_EDID_ADDR 0x50
-#define XDPTX_EDID_SIZE 128
-#define XDPTX_EDID_DTD_DD(Num) (0x36 + (18 * Num))
-#define XDPTX_EDID_PTM XDPTX_EDID_DTD_DD(0)
+#define XDPTX_EDID_ADDR 0x50
+#define XDPTX_EDID_SIZE 128
+#define XDPTX_EDID_DTD_DD(Num) (0x36 + (18 * Num))
+#define XDPTX_EDID_PTM XDPTX_EDID_DTD_DD(0)
/* @} */
/** @name Extended Display Identification Data: Register offsets for the
* Detailed Timing Descriptor (DTD).
* @{
*/
-#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00
-#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01
-#define XDPTX_EDID_DTD_HRES_LSB 0x02
-#define XDPTX_EDID_DTD_HBLANK_LSB 0x03
-#define XDPTX_EDID_DTD_HRES_HBLANK_U4 0x04
-#define XDPTX_EDID_DTD_VRES_LSB 0x05
-#define XDPTX_EDID_DTD_VBLANK_LSB 0x06
-#define XDPTX_EDID_DTD_VRES_VBLANK_U4 0x07
-#define XDPTX_EDID_DTD_HFPORCH_LSB 0x08
-#define XDPTX_EDID_DTD_HSPW_LSB 0x09
-#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4 0x0A
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2 0x0B
-#define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB 0x0C
-#define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB 0x0D
-#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4 0x0E
-#define XDPTX_EDID_DTD_HBORDER 0x0F
-#define XDPTX_EDID_DTD_VBORDER 0x10
-#define XDPTX_EDID_DTD_SIGNAL 0x11
+#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00
+#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01
+#define XDPTX_EDID_DTD_HRES_LSB 0x02
+#define XDPTX_EDID_DTD_HBLANK_LSB 0x03
+#define XDPTX_EDID_DTD_HRES_HBLANK_U4 0x04
+#define XDPTX_EDID_DTD_VRES_LSB 0x05
+#define XDPTX_EDID_DTD_VBLANK_LSB 0x06
+#define XDPTX_EDID_DTD_VRES_VBLANK_U4 0x07
+#define XDPTX_EDID_DTD_HFPORCH_LSB 0x08
+#define XDPTX_EDID_DTD_HSPW_LSB 0x09
+#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4 0x0A
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2 0x0B
+#define XDPTX_EDID_DTD_HIMGSIZE_MM_LSB 0x0C
+#define XDPTX_EDID_DTD_VIMGSIZE_MM_LSB 0x0D
+#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4 0x0E
+#define XDPTX_EDID_DTD_HBORDER 0x0F
+#define XDPTX_EDID_DTD_VBORDER 0x10
+#define XDPTX_EDID_DTD_SIGNAL 0x11
/** @name Extended Display Identification Data: Masks, shifts, and register
* values.
* @{
*/
-#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F
-#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0
-#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4
-#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F
-#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0
-#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4
-#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2
-#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F
-#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0
-#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4
-#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02
-#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04
-#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1
-#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2
+#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F
+#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0
+#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4
+#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F
+#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0
+#define XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4
+#define XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2
+#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F
+#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0
+#define XDPTX_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4
+#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02
+#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04
+#define XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1
+#define XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2
/* @} */
/******************* Macros (Inline Functions) Definitions ********************/
@@ -1166,33 +1168,33 @@
/**
* This is a low-level function that reads from the specified register.
*
- * @param BaseAddress is the base address of the device.
- * @param RegOffset is the register offset to be read from.
+ * @param BaseAddress is the base address of the device.
+ * @param RegOffset is the register offset to be read from.
*
- * @return The 32-bit value of the specified register.
+ * @return The 32-bit value of the specified register.
*
- * @note C-style signature:
- * u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)
+ * @note C-style signature:
+ * u32 XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*******************************************************************************/
#define XDptx_ReadReg(BaseAddress, RegOffset) \
- XDptx_In32((BaseAddress) + (RegOffset))
+ XDptx_In32((BaseAddress) + (RegOffset))
/******************************************************************************/
/**
* This is a low-level function that writes to the specified register.
*
- * @param BaseAddress is the base address of the device.
- * @param RegOffset is the register offset to write to.
- * @param Data is the 32-bit data to write to the specified register.
+ * @param BaseAddress is the base address of the device.
+ * @param RegOffset is the register offset to write to.
+ * @param Data is the 32-bit data to write to the specified register.
*
- * @return None.
+ * @return None.
*
- * @note C-style signature:
- * void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+ * @note C-style signature:
+ * void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*******************************************************************************/
#define XDptx_WriteReg(BaseAddress, RegOffset, Data) \
- XDptx_Out32((BaseAddress) + (RegOffset), (Data))
+ XDptx_Out32((BaseAddress) + (RegOffset), (Data))
#endif /* XDPTX_HW_H_ */
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
index 8fb61552..d7e2e6b5 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
@@ -36,7 +36,7 @@
*
* This file contains functions related to XDptx interrupt handling.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -59,26 +59,26 @@
* This function installs a callback function for when a hot-plug-detect event
* interrupt occurs.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param CallbackFunc is the address to the callback function.
- * @param CallbackRef is the user data item that will be passed to the
- * callback function when it is invoked.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param CallbackFunc is the address to the callback function.
+ * @param CallbackRef is the user data item that will be passed to the
+ * callback function when it is invoked.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
- XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
+ XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallbackFunc != NULL);
- Xil_AssertVoid(CallbackRef != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallbackFunc != NULL);
+ Xil_AssertVoid(CallbackRef != NULL);
- InstancePtr->HpdEventHandler = CallbackFunc;
- InstancePtr->HpdEventCallbackRef = CallbackRef;
+ InstancePtr->HpdEventHandler = CallbackFunc;
+ InstancePtr->HpdEventCallbackRef = CallbackRef;
}
/******************************************************************************/
@@ -86,26 +86,26 @@ void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
* This function installs a callback function for when a hot-plug-detect pulse
* interrupt occurs.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param CallbackFunc is the address to the callback function.
- * @param CallbackRef is the user data item that will be passed to the
- * callback function when it is invoked.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param CallbackFunc is the address to the callback function.
+ * @param CallbackRef is the user data item that will be passed to the
+ * callback function when it is invoked.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
- XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
+ XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallbackFunc != NULL);
- Xil_AssertVoid(CallbackRef != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallbackFunc != NULL);
+ Xil_AssertVoid(CallbackRef != NULL);
- InstancePtr->HpdPulseHandler = CallbackFunc;
- InstancePtr->HpdPulseCallbackRef = CallbackRef;
+ InstancePtr->HpdPulseHandler = CallbackFunc;
+ InstancePtr->HpdPulseCallbackRef = CallbackRef;
}
/******************************************************************************/
@@ -115,46 +115,46 @@ void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
* When an interrupt happens, it first detects what kind of interrupt happened,
* then decides which callback function to invoke.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
{
- u32 IntrStatus;
- u8 HpdEventDetected;
- u8 HpdPulseDetected;
- u32 HpdDuration;
+ u32 IntrStatus;
+ u8 HpdEventDetected;
+ u8 HpdPulseDetected;
+ u32 HpdDuration;
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
- /* Determine what kind of interrupt occurred.
- * Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
- IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_STATUS);
- IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_INTERRUPT_MASK);
+ /* Determine what kind of interrupt occurred.
+ * Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
+ IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_STATUS);
+ IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_INTERRUPT_MASK);
- HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
- HpdPulseDetected = IntrStatus &
+ HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
+ HpdPulseDetected = IntrStatus &
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
- if (HpdEventDetected) {
- InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef);
- }
+ if (HpdEventDetected) {
+ InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef);
+ }
- if (HpdPulseDetected) {
+ if (HpdPulseDetected) {
/* The source device must debounce the incoming HPD signal by
* sampling the value at an interval greater than 250 ms. */
- HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- XDPTX_HPD_DURATION);
- if (HpdDuration >= 250) {
- InstancePtr->HpdPulseHandler(
- InstancePtr->HpdPulseCallbackRef);
- }
- }
+ HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ XDPTX_HPD_DURATION);
+ if (HpdDuration >= 250) {
+ InstancePtr->HpdPulseHandler(
+ InstancePtr->HpdPulseCallbackRef);
+ }
+ }
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
index cd275ec8..dfa82931 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
@@ -38,7 +38,7 @@
* will check many of the DisplayPort TX's register values against the default
* reset values as a sanity-check that the core is ready to be used.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -63,59 +63,59 @@
*/
u32 ResetValues[53][2] =
{
- {XDPTX_LINK_BW_SET, 0},
- {XDPTX_LANE_COUNT_SET, 0},
- {XDPTX_ENHANCED_FRAME_EN, 0},
- {XDPTX_TRAINING_PATTERN_SET, 0},
- {XDPTX_LINK_QUAL_PATTERN_SET, 0},
- {XDPTX_SCRAMBLING_DISABLE, 0},
- {XDPTX_DOWNSPREAD_CTRL, 0},
- {XDPTX_SOFT_RESET, 0},
- {XDPTX_ENABLE, 0},
- {XDPTX_ENABLE_MAIN_STREAM, 0},
- {XDPTX_ENABLE_SEC_STREAM, 0},
- {XDPTX_FORCE_SCRAMBLER_RESET, 0},
- {XDPTX_TX_MST_CONFIG, 0},
- {XDPTX_AUX_CMD, 0},
- {XDPTX_AUX_WRITE_FIFO, 0},
- {XDPTX_AUX_ADDRESS, 0},
- {XDPTX_AUX_CLK_DIVIDER, 0},
- {XDPTX_TX_USER_FIFO_OVERFLOW, 0},
- {XDPTX_AUX_REPLY_DATA, 0},
- {XDPTX_AUX_REPLY_CODE, 0},
- {XDPTX_AUX_REPLY_COUNT, 0},
- {XDPTX_INTERRUPT_MASK, 0x3F},
- {XDPTX_REPLY_DATA_COUNT, 0},
- {XDPTX_REPLY_STATUS, 0x10},
- {XDPTX_STREAM0, 0},
- {XDPTX_STREAM1, 0},
- {XDPTX_STREAM2, 0},
- {XDPTX_STREAM3, 0},
- {XDPTX_PHY_CONFIG, 0x03},
- {XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0},
- {XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0},
- {XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0},
- {XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0},
- {XDPTX_PHY_TRANSMIT_PRBS7, 0},
- {XDPTX_PHY_CLOCK_SELECT, 0},
- {XDPTX_TX_PHY_POWER_DOWN, 0},
- {XDPTX_PHY_PRECURSOR_LANE_0, 0},
- {XDPTX_PHY_PRECURSOR_LANE_1, 0},
- {XDPTX_PHY_PRECURSOR_LANE_2, 0},
- {XDPTX_PHY_PRECURSOR_LANE_3, 0},
- {XDPTX_PHY_POSTCURSOR_LANE_0, 0},
- {XDPTX_PHY_POSTCURSOR_LANE_1, 0},
- {XDPTX_PHY_POSTCURSOR_LANE_2, 0},
- {XDPTX_PHY_POSTCURSOR_LANE_3, 0},
- {XDPTX_GT_DRP_COMMAND, 0},
- {XDPTX_GT_DRP_READ_DATA, 0},
- {XDPTX_GT_DRP_CHANNEL_STATUS, 0},
- {XDPTX_TX_AUDIO_CONTROL, 0},
- {XDPTX_TX_AUDIO_CHANNELS, 0},
- {XDPTX_TX_AUDIO_INFO_DATA, 0},
- {XDPTX_TX_AUDIO_MAUD, 0},
- {XDPTX_TX_AUDIO_NAUD, 0},
- {XDPTX_TX_AUDIO_EXT_DATA, 0}
+ {XDPTX_LINK_BW_SET, 0},
+ {XDPTX_LANE_COUNT_SET, 0},
+ {XDPTX_ENHANCED_FRAME_EN, 0},
+ {XDPTX_TRAINING_PATTERN_SET, 0},
+ {XDPTX_LINK_QUAL_PATTERN_SET, 0},
+ {XDPTX_SCRAMBLING_DISABLE, 0},
+ {XDPTX_DOWNSPREAD_CTRL, 0},
+ {XDPTX_SOFT_RESET, 0},
+ {XDPTX_ENABLE, 0},
+ {XDPTX_ENABLE_MAIN_STREAM, 0},
+ {XDPTX_ENABLE_SEC_STREAM, 0},
+ {XDPTX_FORCE_SCRAMBLER_RESET, 0},
+ {XDPTX_TX_MST_CONFIG, 0},
+ {XDPTX_AUX_CMD, 0},
+ {XDPTX_AUX_WRITE_FIFO, 0},
+ {XDPTX_AUX_ADDRESS, 0},
+ {XDPTX_AUX_CLK_DIVIDER, 0},
+ {XDPTX_TX_USER_FIFO_OVERFLOW, 0},
+ {XDPTX_AUX_REPLY_DATA, 0},
+ {XDPTX_AUX_REPLY_CODE, 0},
+ {XDPTX_AUX_REPLY_COUNT, 0},
+ {XDPTX_INTERRUPT_MASK, 0x3F},
+ {XDPTX_REPLY_DATA_COUNT, 0},
+ {XDPTX_REPLY_STATUS, 0x10},
+ {XDPTX_STREAM0, 0},
+ {XDPTX_STREAM1, 0},
+ {XDPTX_STREAM2, 0},
+ {XDPTX_STREAM3, 0},
+ {XDPTX_PHY_CONFIG, 0x03},
+ {XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0},
+ {XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0},
+ {XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0},
+ {XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0},
+ {XDPTX_PHY_TRANSMIT_PRBS7, 0},
+ {XDPTX_PHY_CLOCK_SELECT, 0},
+ {XDPTX_TX_PHY_POWER_DOWN, 0},
+ {XDPTX_PHY_PRECURSOR_LANE_0, 0},
+ {XDPTX_PHY_PRECURSOR_LANE_1, 0},
+ {XDPTX_PHY_PRECURSOR_LANE_2, 0},
+ {XDPTX_PHY_PRECURSOR_LANE_3, 0},
+ {XDPTX_PHY_POSTCURSOR_LANE_0, 0},
+ {XDPTX_PHY_POSTCURSOR_LANE_1, 0},
+ {XDPTX_PHY_POSTCURSOR_LANE_2, 0},
+ {XDPTX_PHY_POSTCURSOR_LANE_3, 0},
+ {XDPTX_GT_DRP_COMMAND, 0},
+ {XDPTX_GT_DRP_READ_DATA, 0},
+ {XDPTX_GT_DRP_CHANNEL_STATUS, 0},
+ {XDPTX_TX_AUDIO_CONTROL, 0},
+ {XDPTX_TX_AUDIO_CHANNELS, 0},
+ {XDPTX_TX_AUDIO_INFO_DATA, 0},
+ {XDPTX_TX_AUDIO_MAUD, 0},
+ {XDPTX_TX_AUDIO_NAUD, 0},
+ {XDPTX_TX_AUDIO_EXT_DATA, 0}
};
/**
@@ -124,26 +124,26 @@ u32 ResetValues[53][2] =
*/
u32 ResetValuesMsa[20][2] =
{
- {XDPTX_MAIN_STREAM_HTOTAL, 0},
- {XDPTX_MAIN_STREAM_VTOTAL, 0},
- {XDPTX_MAIN_STREAM_POLARITY, 0},
- {XDPTX_MAIN_STREAM_HSWIDTH, 0},
- {XDPTX_MAIN_STREAM_VSWIDTH, 0},
- {XDPTX_MAIN_STREAM_HRES, 0},
- {XDPTX_MAIN_STREAM_VRES, 0},
- {XDPTX_MAIN_STREAM_HSTART, 0},
- {XDPTX_MAIN_STREAM_VSTART, 0},
- {XDPTX_MAIN_STREAM_MISC0, 0},
- {XDPTX_MAIN_STREAM_MISC1, 0},
- {XDPTX_M_VID, 0},
- {XDPTX_TU_SIZE, 0},
- {XDPTX_N_VID, 0},
- {XDPTX_USER_PIXEL_WIDTH, 0},
- {XDPTX_USER_DATA_COUNT_PER_LANE, 0},
- {XDPTX_MAIN_STREAM_INTERLACED, 0},
- {XDPTX_MIN_BYTES_PER_TU, 0},
- {XDPTX_FRAC_BYTES_PER_TU, 0},
- {XDPTX_INIT_WAIT, 32}
+ {XDPTX_MAIN_STREAM_HTOTAL, 0},
+ {XDPTX_MAIN_STREAM_VTOTAL, 0},
+ {XDPTX_MAIN_STREAM_POLARITY, 0},
+ {XDPTX_MAIN_STREAM_HSWIDTH, 0},
+ {XDPTX_MAIN_STREAM_VSWIDTH, 0},
+ {XDPTX_MAIN_STREAM_HRES, 0},
+ {XDPTX_MAIN_STREAM_VRES, 0},
+ {XDPTX_MAIN_STREAM_HSTART, 0},
+ {XDPTX_MAIN_STREAM_VSTART, 0},
+ {XDPTX_MAIN_STREAM_MISC0, 0},
+ {XDPTX_MAIN_STREAM_MISC1, 0},
+ {XDPTX_M_VID, 0},
+ {XDPTX_TU_SIZE, 0},
+ {XDPTX_N_VID, 0},
+ {XDPTX_USER_PIXEL_WIDTH, 0},
+ {XDPTX_USER_DATA_COUNT_PER_LANE, 0},
+ {XDPTX_MAIN_STREAM_INTERLACED, 0},
+ {XDPTX_MIN_BYTES_PER_TU, 0},
+ {XDPTX_FRAC_BYTES_PER_TU, 0},
+ {XDPTX_INIT_WAIT, 32}
};
/**************************** Function Definitions ****************************/
@@ -153,60 +153,60 @@ u32 ResetValuesMsa[20][2] =
* This function runs a self-test on the XDptx driver/device. The sanity test
* checks whether or not all tested registers hold their default reset values.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
* @return
- * - XST_SUCCESS if the self-test passed - all tested registers
- * hold their default reset values.
- * - XST_FAILURE otherwise.
+ * - XST_SUCCESS if the self-test passed - all tested registers
+ * hold their default reset values.
+ * - XST_FAILURE otherwise.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
u32 XDptx_SelfTest(XDptx *InstancePtr)
{
- u8 Index;
- u8 StreamIndex;
- u32 StreamOffset;
- u32 Val;
+ u8 Index;
+ u8 StreamIndex;
+ u32 StreamOffset;
+ u32 Val;
- /* Compare general usage registers with their default values. */
- for (Index = 0; Index < 53; Index++) {
- Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- ResetValues[Index][0]);
- /* Fail if register does not hold default value. */
- if (Val != ResetValues[Index][1]) {
- return XST_FAILURE;
- }
- }
+ /* Compare general usage registers with their default values. */
+ for (Index = 0; Index < 53; Index++) {
+ Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ ResetValues[Index][0]);
+ /* Fail if register does not hold default value. */
+ if (Val != ResetValues[Index][1]) {
+ return XST_FAILURE;
+ }
+ }
- /* Compare main stream attribute (MSA) registers for all 4 streams with
- * their default values. */
- for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
- /* Determine the MSA register offset for each stream. */
- if (StreamIndex == 0) {
- StreamOffset = 0;
- }
- else if (StreamIndex == 1) {
- StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
- }
- else if (StreamIndex == 2) {
- StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
- }
- else if (StreamIndex == 3) {
- StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET;
- }
+ /* Compare main stream attribute (MSA) registers for all 4 streams with
+ * their default values. */
+ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
+ /* Determine the MSA register offset for each stream. */
+ if (StreamIndex == 0) {
+ StreamOffset = 0;
+ }
+ else if (StreamIndex == 1) {
+ StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
+ }
+ else if (StreamIndex == 2) {
+ StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
+ }
+ else if (StreamIndex == 3) {
+ StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET;
+ }
- for (Index = 0; Index < 20; Index++) {
- Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
- StreamOffset + ResetValuesMsa[Index][0]);
- /* Fail if register does not hold default value. */
- if (Val != ResetValuesMsa[Index][1]) {
- return XST_FAILURE;
- }
- }
- }
+ for (Index = 0; Index < 20; Index++) {
+ Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
+ StreamOffset + ResetValuesMsa[Index][0]);
+ /* Fail if register does not hold default value. */
+ if (Val != ResetValuesMsa[Index][1]) {
+ return XST_FAILURE;
+ }
+ }
+ }
- /* All tested registers hold their default reset values. */
- return XST_SUCCESS;
+ /* All tested registers hold their default reset values. */
+ return XST_SUCCESS;
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
index 08183a93..b29cad48 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
@@ -36,7 +36,7 @@
*
* This file contains static initialization methods for the XDptx driver.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -69,25 +69,25 @@ extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
* ID. The table XDptx_ConfigTable[] contains the configuration information for
* each device in the system.
*
- * @param DeviceId is the unique device ID of the device being looked up.
+ * @param DeviceId is the unique device ID of the device being looked up.
*
- * @return A pointer to the configuration table entry corresponding to the
- * given device ID, or NULL if no match is found.
+ * @return A pointer to the configuration table entry corresponding to the
+ * given device ID, or NULL if no match is found.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
XDptx_Config *XDptx_LookupConfig(u16 DeviceId)
{
- XDptx_Config *CfgPtr;
- u32 Index;
+ XDptx_Config *CfgPtr;
+ u32 Index;
- for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {
- if (XDptx_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XDptx_ConfigTable[Index];
- break;
- }
- }
+ for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {
+ if (XDptx_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDptx_ConfigTable[Index];
+ break;
+ }
+ }
- return CfgPtr;
+ return CfgPtr;
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
index a974a6fc..64e2e7e5 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
@@ -38,7 +38,7 @@
* These functions set up the DisplayPort TX core's main stream attributes that
* determine how a video stream will be displayed.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -60,164 +60,164 @@
static void XDptx_ClearMsaValues(XDptx *InstancePtr);
static void XDptx_SetMsaValues(XDptx *InstancePtr,
- XDptx_MainStreamAttributes *MsaConfig);
+ XDptx_MainStreamAttributes *MsaConfig);
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function calculates the following Main Stream Attributes (MSA):
- * - Transfer unit size
- * - User pixel width
- * - NVid
- * - Horizontal start
- * - Vertical start
- * - Horizontal total clock
- * - Vertical total clock
- * - Misc0
- * - Misc1
- * - Data per lane
- * - Average number of bytes per transfer unit
- * - Number of initial wait cycles
+ * - Transfer unit size
+ * - User pixel width
+ * - NVid
+ * - Horizontal start
+ * - Vertical start
+ * - Horizontal total clock
+ * - Vertical total clock
+ * - Misc0
+ * - Misc1
+ * - Data per lane
+ * - Average number of bytes per transfer unit
+ * - Number of initial wait cycles
* These values are derived from:
- * - Bits per color
- * - MVid
- * - Horizontal sync polarity
- * - Vertical sync polarity
- * - Horizontal sync pulse width
- * - Vertical sync pulse width
- * - Horizontal resolution
- * - Vertical resolution
- * - Vertical back porch
- * - Vertical front porch
- * - Horizontal back porch
- * - Horizontal front porch
+ * - Bits per color
+ * - MVid
+ * - Horizontal sync polarity
+ * - Vertical sync polarity
+ * - Horizontal sync pulse width
+ * - Vertical sync pulse width
+ * - Horizontal resolution
+ * - Vertical resolution
+ * - Vertical back porch
+ * - Vertical front porch
+ * - Horizontal back porch
+ * - Horizontal front porch
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note The MsaConfig structure is modified with the new, calculated
- * values. The main stream attributes that were used to derive the
- * calculated values are untouched in the MsaConfig structure.
+ * @note The MsaConfig structure is modified with the new, calculated
+ * values. The main stream attributes that were used to derive the
+ * calculated values are untouched in the MsaConfig structure.
*
*******************************************************************************/
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
{
- u32 VideoBw;
- u32 BitsPerPixel;
- XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
- XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
+ u32 VideoBw;
+ u32 BitsPerPixel;
+ XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
+ XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
- (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
- (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
- Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
- (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
- (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
- Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
- (LinkConfig->SynchronousClockMode == 1));
- Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
- (LinkConfig->DynamicRange == 1));
- Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
- (LinkConfig->YCbCrColorimetry == 1));
- Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
- (MsaConfig->BitsPerColor == 8) ||
- (MsaConfig->BitsPerColor == 10) ||
- (MsaConfig->BitsPerColor == 12) ||
- (MsaConfig->BitsPerColor == 16));
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
+ (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
+ (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
+ Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+ (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+ (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
+ Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
+ (LinkConfig->SynchronousClockMode == 1));
+ Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
+ (LinkConfig->DynamicRange == 1));
+ Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
+ (LinkConfig->YCbCrColorimetry == 1));
+ Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
+ (MsaConfig->BitsPerColor == 8) ||
+ (MsaConfig->BitsPerColor == 10) ||
+ (MsaConfig->BitsPerColor == 12) ||
+ (MsaConfig->BitsPerColor == 16));
- /* Fixed transfer unit size. */
- MsaConfig->TransferUnitSize = 64;
+ /* Fixed transfer unit size. */
+ MsaConfig->TransferUnitSize = 64;
- /* Set the user pixel width to handle clocks that exceed the
- * capabilities of the DisplayPort TX core. */
- if ((MsaConfig->MVid > 300000) &&
- (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
- MsaConfig->UserPixelWidth = 4;
- }
- else if ((MsaConfig->MVid > 75000) &&
- (LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
- MsaConfig->UserPixelWidth = 2;
- }
- else {
- MsaConfig->UserPixelWidth = 1;
- }
+ /* Set the user pixel width to handle clocks that exceed the
+ * capabilities of the DisplayPort TX core. */
+ if ((MsaConfig->MVid > 300000) &&
+ (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
+ MsaConfig->UserPixelWidth = 4;
+ }
+ else if ((MsaConfig->MVid > 75000) &&
+ (LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
+ MsaConfig->UserPixelWidth = 2;
+ }
+ else {
+ MsaConfig->UserPixelWidth = 1;
+ }
- /* Compute the rest of the MSA values. */
- MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
- MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
- MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
- MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
- MsaConfig->HBackPorch + MsaConfig->HFrontPorch +
- MsaConfig->HResolution);
- MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
- MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
- MsaConfig->VResolution);
+ /* Compute the rest of the MSA values. */
+ MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
+ MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
+ MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
+ MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
+ MsaConfig->HBackPorch + MsaConfig->HFrontPorch +
+ MsaConfig->HResolution);
+ MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
+ MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
+ MsaConfig->VResolution);
- /* Miscellaneous attributes. */
- if (MsaConfig->BitsPerColor == 6) {
- MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
- }
- else if (MsaConfig->BitsPerColor == 8) {
- MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
- }
- else if (MsaConfig->BitsPerColor == 10) {
- MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
- }
- else if (MsaConfig->BitsPerColor == 12) {
- MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
- }
- else if (MsaConfig->BitsPerColor == 16) {
- MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
- }
- MsaConfig->Misc0 = (MsaConfig->Misc0 <<
- XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
- (LinkConfig->YCbCrColorimetry <<
- XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
- (LinkConfig->DynamicRange <<
- XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
- (LinkConfig->ComponentFormat <<
- XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
- (LinkConfig->SynchronousClockMode);
- MsaConfig->Misc1 = 0;
+ /* Miscellaneous attributes. */
+ if (MsaConfig->BitsPerColor == 6) {
+ MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
+ }
+ else if (MsaConfig->BitsPerColor == 8) {
+ MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
+ }
+ else if (MsaConfig->BitsPerColor == 10) {
+ MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
+ }
+ else if (MsaConfig->BitsPerColor == 12) {
+ MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
+ }
+ else if (MsaConfig->BitsPerColor == 16) {
+ MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
+ }
+ MsaConfig->Misc0 = (MsaConfig->Misc0 <<
+ XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
+ (LinkConfig->YCbCrColorimetry <<
+ XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
+ (LinkConfig->DynamicRange <<
+ XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
+ (LinkConfig->ComponentFormat <<
+ XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
+ (LinkConfig->SynchronousClockMode);
+ MsaConfig->Misc1 = 0;
- MsaConfig->DataPerLane = (MsaConfig->HResolution *
- MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
+ MsaConfig->DataPerLane = (MsaConfig->HResolution *
+ MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
- /* Determine the number of bits per pixel for the specified color
- * component format. */
- if (LinkConfig->ComponentFormat ==
- XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
- /* YCbCr422 color component format. */
- BitsPerPixel = MsaConfig->BitsPerColor * 2;
- }
- else {
- /* RGB or YCbCr 4:4:4 color component format. */
- BitsPerPixel = MsaConfig->BitsPerColor * 3;
- }
+ /* Determine the number of bits per pixel for the specified color
+ * component format. */
+ if (LinkConfig->ComponentFormat ==
+ XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
+ /* YCbCr422 color component format. */
+ BitsPerPixel = MsaConfig->BitsPerColor * 2;
+ }
+ else {
+ /* RGB or YCbCr 4:4:4 color component format. */
+ BitsPerPixel = MsaConfig->BitsPerColor * 3;
+ }
- /* Calculate the transfer unit size. */
- VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
- MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
- (LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
+ /* Calculate the transfer unit size. */
+ VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
+ MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
+ (LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
- /* The number of initial wait cycles at the start of a new line by the
- * framing logic. This allows enough data to be buffered in the input
- * FIFO before video is sent. */
- MsaConfig->InitWait = (MsaConfig->TransferUnitSize -
- (MsaConfig->AvgBytesPerTU / 1000));
- if ((MsaConfig->AvgBytesPerTU / 1000) > MsaConfig->TransferUnitSize) {
- MsaConfig->InitWait = 0;
- }
- else if (MsaConfig->InitWait > 10) {
- MsaConfig->InitWait -= 10;
- }
- else {
- MsaConfig->InitWait = 0;
- }
+ /* The number of initial wait cycles at the start of a new line by the
+ * framing logic. This allows enough data to be buffered in the input
+ * FIFO before video is sent. */
+ MsaConfig->InitWait = (MsaConfig->TransferUnitSize -
+ (MsaConfig->AvgBytesPerTU / 1000));
+ if ((MsaConfig->AvgBytesPerTU / 1000) > MsaConfig->TransferUnitSize) {
+ MsaConfig->InitWait = 0;
+ }
+ else if (MsaConfig->InitWait > 10) {
+ MsaConfig->InitWait -= 10;
+ }
+ else {
+ MsaConfig->InitWait = 0;
+ }
}
/******************************************************************************/
@@ -227,41 +227,41 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
* from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The
* XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param VideoMode is one of the enumerated standard video modes that is
- * used to determine the MSA values to be used.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param VideoMode is one of the enumerated standard video modes that is
+ * used to determine the MSA values to be used.
*
- * @return None.
+ * @return None.
*
- * @note The InstancePtr->MsaConfig structure is modified to reflect the
- * MSA values associated to the specified video mode.
+ * @note The InstancePtr->MsaConfig structure is modified to reflect the
+ * MSA values associated to the specified video mode.
*
*******************************************************************************/
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
- XDptx_VideoMode VideoMode)
+ XDptx_VideoMode VideoMode)
{
- XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
+ XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsaConfig != NULL);
- Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsaConfig != NULL);
+ Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
- /* Configure the MSA values from the display monitor DMT table. */
- MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
- MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
- MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
- MsaConfig->HSyncPulseWidth = XDptx_DmtModes[VideoMode].HSyncPulseWidth;
- MsaConfig->VSyncPulseWidth = XDptx_DmtModes[VideoMode].VSyncPulseWidth;
- MsaConfig->HResolution = XDptx_DmtModes[VideoMode].HResolution;
- MsaConfig->VResolution = XDptx_DmtModes[VideoMode].VResolution;
- MsaConfig->VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch;
- MsaConfig->VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch;
- MsaConfig->HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch;
- MsaConfig->HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch;
+ /* Configure the MSA values from the display monitor DMT table. */
+ MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
+ MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
+ MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
+ MsaConfig->HSyncPulseWidth = XDptx_DmtModes[VideoMode].HSyncPulseWidth;
+ MsaConfig->VSyncPulseWidth = XDptx_DmtModes[VideoMode].VSyncPulseWidth;
+ MsaConfig->HResolution = XDptx_DmtModes[VideoMode].HResolution;
+ MsaConfig->VResolution = XDptx_DmtModes[VideoMode].VResolution;
+ MsaConfig->VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch;
+ MsaConfig->VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch;
+ MsaConfig->HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch;
+ MsaConfig->HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch;
- /* Calculate the rest of the MSA values. */
- XDptx_CfgMsaRecalculate(InstancePtr);
+ /* Calculate the rest of the MSA values. */
+ XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@@ -271,92 +271,92 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
* Timing Mode (PTM) information is stored in the sink's Extended Display
* Identification Data (EDID).
*
- * @param InstancePtr is a pointer to the XDptx instance
+ * @param InstancePtr is a pointer to the XDptx instance
*
- * @return None.
+ * @return None.
*
- * @note The InstancePtr->MsaConfig structure is modified to reflect the
- * main stream attribute values associated to the preferred timing
- * of the sink monitor.
+ * @note The InstancePtr->MsaConfig structure is modified to reflect the
+ * main stream attribute values associated to the preferred timing
+ * of the sink monitor.
*
*******************************************************************************/
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
{
- XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
- u8 *Ptm = &InstancePtr->RxConfig.Edid[XDPTX_EDID_PTM];
+ XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
+ u8 *Ptm = &InstancePtr->RxConfig.Edid[XDPTX_EDID_PTM];
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsaConfig != NULL);
- Xil_AssertVoid(Ptm != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsaConfig != NULL);
+ Xil_AssertVoid(Ptm != NULL);
- /* Configure the MSA values with the PTM information as
- * specified by the preferred Detailed Timing Descriptor (DTD) of the
- * monitor's EDID.
- * Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
- * versions may not contain this information. */
- u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
- Ptm[XDPTX_EDID_DTD_HBLANK_LSB];
+ /* Configure the MSA values with the PTM information as
+ * specified by the preferred Detailed Timing Descriptor (DTD) of the
+ * monitor's EDID.
+ * Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
+ * versions may not contain this information. */
+ u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
+ Ptm[XDPTX_EDID_DTD_HBLANK_LSB];
- u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
- Ptm[XDPTX_EDID_DTD_VBLANK_LSB];
+ u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
+ Ptm[XDPTX_EDID_DTD_VBLANK_LSB];
- MsaConfig->MVid = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << 8) |
- Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10;
+ MsaConfig->MVid = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << 8) |
+ Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10;
- MsaConfig->HSyncPulseWidth =
- (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
- Ptm[XDPTX_EDID_DTD_HSPW_LSB];
+ MsaConfig->HSyncPulseWidth =
+ (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
+ Ptm[XDPTX_EDID_DTD_HSPW_LSB];
- MsaConfig->VSyncPulseWidth =
- ((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
- (Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
- XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
+ MsaConfig->VSyncPulseWidth =
+ ((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
+ (Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
+ XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
- MsaConfig->HResolution =
- (((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
- Ptm[XDPTX_EDID_DTD_HRES_LSB];
+ MsaConfig->HResolution =
+ (((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
+ Ptm[XDPTX_EDID_DTD_HRES_LSB];
- MsaConfig->VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
- XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
- Ptm[XDPTX_EDID_DTD_VRES_LSB];
+ MsaConfig->VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
+ XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
+ Ptm[XDPTX_EDID_DTD_VRES_LSB];
- MsaConfig->VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
- ((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
- XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
- XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
+ MsaConfig->VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
+ ((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
+ XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
+ XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
- MsaConfig->HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
- XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
- Ptm[XDPTX_EDID_DTD_HFPORCH_LSB];
+ MsaConfig->HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
+ XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
+ Ptm[XDPTX_EDID_DTD_HFPORCH_LSB];
- MsaConfig->HSyncPolarity = (Ptm[XDPTX_EDID_DTD_SIGNAL] &
- XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK) >>
- XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT;
+ MsaConfig->HSyncPolarity = (Ptm[XDPTX_EDID_DTD_SIGNAL] &
+ XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK) >>
+ XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT;
- MsaConfig->VSyncPolarity = Ptm[XDPTX_EDID_DTD_SIGNAL] &
- XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK >>
- XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT;
+ MsaConfig->VSyncPolarity = Ptm[XDPTX_EDID_DTD_SIGNAL] &
+ XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK >>
+ XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT;
- MsaConfig->VBackPorch = VBlank -
- (MsaConfig->VFrontPorch + MsaConfig->VSyncPulseWidth);
+ MsaConfig->VBackPorch = VBlank -
+ (MsaConfig->VFrontPorch + MsaConfig->VSyncPulseWidth);
- MsaConfig->HBackPorch = HBlank -
- (MsaConfig->HFrontPorch + MsaConfig->HSyncPulseWidth);
+ MsaConfig->HBackPorch = HBlank -
+ (MsaConfig->HFrontPorch + MsaConfig->HSyncPulseWidth);
- /* Calculate the rest of the MSA values. */
- XDptx_CfgMsaRecalculate(InstancePtr);
+ /* Calculate the rest of the MSA values. */
+ XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@@ -366,101 +366,101 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
* attributes, the rest of the attributes may be derived. The minimal required
* main stream attributes that must be contained in the MsaConfigCustom
* structure are:
- * - MVid
- * - Horizontal sync polarity
- * - Vertical sync polarity
- * - Horizontal sync pulse width
- * - Vertical sync pulse width
- * - Horizontal resolution
- * - Vertical resolution
- * - Vertical back porch
- * - Vertical front porch
- * - Horizontal back porch
- * - Horizontal front porch
+ * - MVid
+ * - Horizontal sync polarity
+ * - Vertical sync polarity
+ * - Horizontal sync pulse width
+ * - Vertical sync pulse width
+ * - Horizontal resolution
+ * - Vertical resolution
+ * - Vertical back porch
+ * - Vertical front porch
+ * - Horizontal back porch
+ * - Horizontal front porch
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param MsaConfigCustom is the structure that will be used to copy the
- * main stream attributes from (into InstancePtr->MsaConfig).
- * @param Recalculate is a boolean enable that determines whether or not
- * the main stream attributes should be recalculated.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param MsaConfigCustom is the structure that will be used to copy the
+ * main stream attributes from (into InstancePtr->MsaConfig).
+ * @param Recalculate is a boolean enable that determines whether or not
+ * the main stream attributes should be recalculated.
*
- * @return None.
+ * @return None.
*
- * @note The InstancePtr-> MsaConfig structure is modified with the new
- * values.
+ * @note The InstancePtr-> MsaConfig structure is modified with the new
+ * values.
*
*******************************************************************************/
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
- XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
+ XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
{
- XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
+ XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(MsaConfig != NULL);
- Xil_AssertVoid(MsaConfigCustom != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsaConfig != NULL);
+ Xil_AssertVoid(MsaConfigCustom != NULL);
- /* Copy the MSA values from the user configuration structure. */
- MsaConfig->MVid = MsaConfigCustom->MVid;
- MsaConfig->HSyncPolarity = MsaConfigCustom->HSyncPolarity;
- MsaConfig->VSyncPolarity = MsaConfigCustom->VSyncPolarity;
- MsaConfig->HSyncPulseWidth = MsaConfigCustom->HSyncPulseWidth;
- MsaConfig->VSyncPulseWidth = MsaConfigCustom->VSyncPulseWidth;
- MsaConfig->HResolution = MsaConfigCustom->HResolution;
- MsaConfig->VResolution = MsaConfigCustom->VResolution;
+ /* Copy the MSA values from the user configuration structure. */
+ MsaConfig->MVid = MsaConfigCustom->MVid;
+ MsaConfig->HSyncPolarity = MsaConfigCustom->HSyncPolarity;
+ MsaConfig->VSyncPolarity = MsaConfigCustom->VSyncPolarity;
+ MsaConfig->HSyncPulseWidth = MsaConfigCustom->HSyncPulseWidth;
+ MsaConfig->VSyncPulseWidth = MsaConfigCustom->VSyncPulseWidth;
+ MsaConfig->HResolution = MsaConfigCustom->HResolution;
+ MsaConfig->VResolution = MsaConfigCustom->VResolution;
- MsaConfig->VBackPorch = MsaConfigCustom->VBackPorch;
- MsaConfig->VFrontPorch = MsaConfigCustom->VFrontPorch;
- MsaConfig->HBackPorch = MsaConfigCustom->HBackPorch;
- MsaConfig->HFrontPorch = MsaConfigCustom->HFrontPorch;
+ MsaConfig->VBackPorch = MsaConfigCustom->VBackPorch;
+ MsaConfig->VFrontPorch = MsaConfigCustom->VFrontPorch;
+ MsaConfig->HBackPorch = MsaConfigCustom->HBackPorch;
+ MsaConfig->HFrontPorch = MsaConfigCustom->HFrontPorch;
- if (Recalculate) {
- /* Calculate the rest of the MSA values. */
- XDptx_CfgMsaRecalculate(InstancePtr);
- }
- else {
- /* Use the custom values for the rest. */
- MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize;
- MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth;
- MsaConfig->NVid = MsaConfigCustom->NVid;
- MsaConfig->HStart = MsaConfigCustom->HStart;
- MsaConfig->VStart = MsaConfigCustom->VStart;
- MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
- MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
- MsaConfig->Misc0 = MsaConfigCustom->Misc0;
- MsaConfig->Misc1 = MsaConfigCustom->Misc1;
- MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
- MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU;
- MsaConfig->InitWait = MsaConfigCustom->InitWait;
- }
+ if (Recalculate) {
+ /* Calculate the rest of the MSA values. */
+ XDptx_CfgMsaRecalculate(InstancePtr);
+ }
+ else {
+ /* Use the custom values for the rest. */
+ MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize;
+ MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth;
+ MsaConfig->NVid = MsaConfigCustom->NVid;
+ MsaConfig->HStart = MsaConfigCustom->HStart;
+ MsaConfig->VStart = MsaConfigCustom->VStart;
+ MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
+ MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
+ MsaConfig->Misc0 = MsaConfigCustom->Misc0;
+ MsaConfig->Misc1 = MsaConfigCustom->Misc1;
+ MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
+ MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU;
+ MsaConfig->InitWait = MsaConfigCustom->InitWait;
+ }
}
/******************************************************************************/
/**
* This function sets the bits per color value of the video stream.
*
- * @param InstancePtr is a pointer to the XDptx instance
- * @param BitsPerColor is the new number of bits per color to use.
+ * @param InstancePtr is a pointer to the XDptx instance
+ * @param BitsPerColor is the new number of bits per color to use.
*
- * @return None.
+ * @return None.
*
- * @note The InstancePtr->MsaConfig structure is modified to reflect the
- * new main stream attributes associated with a new bits per color
- * value.
+ * @note The InstancePtr->MsaConfig structure is modified to reflect the
+ * new main stream attributes associated with a new bits per color
+ * value.
*
*******************************************************************************/
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
- (BitsPerColor == 10) || (BitsPerColor == 12) ||
- (BitsPerColor == 16));
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
+ (BitsPerColor == 10) || (BitsPerColor == 12) ||
+ (BitsPerColor == 16));
- InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
+ InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
- /* Calculate the rest of the MSA values. */
- XDptx_CfgMsaRecalculate(InstancePtr);
+ /* Calculate the rest of the MSA values. */
+ XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@@ -469,22 +469,22 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
* TX core and sets them to the values specified in the main stream attributes
* configuration structure.
*
- * @param InstancePtr is a pointer to the XDptx instance
+ * @param InstancePtr is a pointer to the XDptx instance
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
void XDptx_SetVideoMode(XDptx *InstancePtr)
{
- /* Verify arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
+ /* Verify arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
- XDptx_ClearMsaValues(InstancePtr);
- XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
+ XDptx_ClearMsaValues(InstancePtr);
+ XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
}
/******************************************************************************/
@@ -492,16 +492,16 @@ void XDptx_SetVideoMode(XDptx *InstancePtr)
* This function clears the main stream attributes registers of the DisplayPort
* TX core.
*
- * @param InstancePtr is a pointer to the XDptx instance.
+ * @param InstancePtr is a pointer to the XDptx instance.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static void XDptx_ClearMsaValues(XDptx *InstancePtr)
{
- XDptx_Config *Config = &InstancePtr->Config;
+ XDptx_Config *Config = &InstancePtr->Config;
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
@@ -530,62 +530,62 @@ static void XDptx_ClearMsaValues(XDptx *InstancePtr)
* core with the values specified in the main stream attributes configuration
* structure.
*
- * @param InstancePtr is a pointer to the XDptx instance.
- * @param MsaConfig is a pointer to the main stream attributes
- * configuration structure.
+ * @param InstancePtr is a pointer to the XDptx instance.
+ * @param MsaConfig is a pointer to the main stream attributes
+ * configuration structure.
*
- * @return None.
+ * @return None.
*
- * @note None.
+ * @note None.
*
*******************************************************************************/
static void XDptx_SetMsaValues(XDptx *InstancePtr,
- XDptx_MainStreamAttributes *MsaConfig)
+ XDptx_MainStreamAttributes *MsaConfig)
{
- XDptx_Config *Config = &InstancePtr->Config;
+ XDptx_Config *Config = &InstancePtr->Config;
- /* Set the main stream attributes to the associated DisplayPort TX core
- * registers. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
- MsaConfig->HClkTotal);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
- MsaConfig->VClkTotal);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
- MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
- XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
- MsaConfig->HSyncPulseWidth);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
- MsaConfig->VSyncPulseWidth);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
- MsaConfig->HResolution);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
- MsaConfig->VResolution);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
- MsaConfig->HStart);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
- MsaConfig->VStart);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
- MsaConfig->Misc0);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
- MsaConfig->Misc1);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
- MsaConfig->MVid);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
- MsaConfig->NVid);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
- MsaConfig->UserPixelWidth);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
- MsaConfig->DataPerLane);
+ /* Set the main stream attributes to the associated DisplayPort TX core
+ * registers. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
+ MsaConfig->HClkTotal);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
+ MsaConfig->VClkTotal);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
+ MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
+ XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
+ MsaConfig->HSyncPulseWidth);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
+ MsaConfig->VSyncPulseWidth);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
+ MsaConfig->HResolution);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
+ MsaConfig->VResolution);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
+ MsaConfig->HStart);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
+ MsaConfig->VStart);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
+ MsaConfig->Misc0);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
+ MsaConfig->Misc1);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
+ MsaConfig->MVid);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
+ MsaConfig->NVid);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
+ MsaConfig->UserPixelWidth);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
+ MsaConfig->DataPerLane);
- /* Set the transfer unit values to the associated DisplayPort TX core
- * registers. */
- XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
- MsaConfig->TransferUnitSize);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
- MsaConfig->AvgBytesPerTU / 1000);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
- MsaConfig->AvgBytesPerTU % 1000);
- XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
- MsaConfig->InitWait);
+ /* Set the transfer unit values to the associated DisplayPort TX core
+ * registers. */
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
+ MsaConfig->TransferUnitSize);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
+ MsaConfig->AvgBytesPerTU / 1000);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
+ MsaConfig->AvgBytesPerTU % 1000);
+ XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
+ MsaConfig->InitWait);
}
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
index 270ca6aa..c503ae4e 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
@@ -36,7 +36,7 @@
*
* Contains display monitor timing (DMT) modes for various standard resolutions.
*
- * @note None.
+ * @note None.
*
* <pre>
* MODIFICATION HISTORY:
@@ -61,176 +61,176 @@
*/
XDptx_DmtMode XDptx_DmtModes[] =
{
- {XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175,
- 0, 1, 1, 8, 96, 40, 2, 2, 25},
- {XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000,
- 0, 0, 0, 40, 128, 88, 1, 4, 23},
- {XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750,
- 0, 0, 0, 16, 112, 112, 6, 8, 23},
- {XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000,
- 0, 1, 1, 24, 136, 160, 3, 6, 29},
- {XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250,
- 0, 0, 1, 48, 32, 80, 3, 7, 12},
- {XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500,
- 0, 1, 0, 64, 128, 192, 3, 7, 20},
- {XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000,
- 0, 0, 1, 48, 32, 80, 3, 6, 14},
- {XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500,
- 0, 1, 0, 72, 128, 200, 3, 6, 22},
- {XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000,
- 0, 0, 0, 96, 112, 312, 1, 3, 36},
- {XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000,
- 0, 0, 0, 48, 112, 248, 1, 3, 38},
- {XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500,
- 0, 0, 0, 64, 112, 256, 3, 6, 18},
- {XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000,
- 0, 0, 1, 48, 32, 80, 3, 4, 23},
- {XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750,
- 0, 1, 0, 88, 144, 232, 3, 4, 32},
- {XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750,
- 0, 0, 1, 48, 32, 80, 3, 6, 17},
- {XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500,
- 0, 1, 0, 80, 152, 232, 3, 6, 25},
- {XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000,
- 0, 0, 0, 64, 192, 304, 1, 3, 46},
- {XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000,
- 0, 1, 0, 48, 32, 80, 3, 6, 21},
- {XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250,
- 0, 1, 0, 104, 176, 280, 3, 6, 30},
- {XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750,
- 0, 1, 0, 128, 200, 328, 1, 3, 46},
- {XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250,
- 0, 1, 0, 96, 224, 352, 1, 3, 43},
- {XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000,
- 0, 0, 1, 48, 32, 80, 3, 6, 26},
- {XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250,
- 0, 1, 0, 136, 200, 336, 3, 6, 36},
- {XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000,
- 0, 1, 0, 128, 208, 344, 1, 3, 56},
- {XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500,
- 0, 0, 1, 48, 32, 80, 3, 6, 37},
- {XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500,
- 0, 1, 0, 192, 280, 472, 3, 6, 49},
- {XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000,
- 0, 0, 0, 24, 72, 128, 1, 2, 22},
- {XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500,
- 0, 0, 0, 64, 192, 304, 1, 3, 46},
- {XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000,
- 0, 0, 0, 64, 192, 304, 1, 3, 46},
- {XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000,
- 0, 1, 1, 24, 136, 144, 3, 6, 29},
- {XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500,
- 0, 1, 1, 16, 40, 120, 1, 3, 20},
- {XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000,
- 0, 0, 0, 56, 120, 64, 37, 6, 23},
- {XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500,
- 0, 1, 1, 16, 64, 120, 1, 3, 16},
- {XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500,
- 0, 0, 0, 16, 80, 160, 1, 3, 21},
- {XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750,
- 0, 0, 0, 16, 96, 176, 1, 3, 28},
- {XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000,
- 0, 0, 0, 64, 128, 256, 1, 3, 32},
- {XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250,
- 0, 1, 0, 80, 128, 208, 3, 7, 27},
- {XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500,
- 0, 1, 0, 80, 128, 208, 3, 6, 29},
- {XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000,
- 0, 0, 0, 16, 144, 248, 1, 3, 38},
- {XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000,
- 0, 1, 0, 104, 144, 248, 3, 4, 42},
- {XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750,
- 0, 1, 0, 96, 152, 31, 3, 6, 33},
- {XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500,
- 0, 0, 0, 64, 192, 304, 1, 3, 46},
- {XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000,
- 0, 1, 0, 120, 176, 37, 3, 6, 40},
- {XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000,
- 0, 1, 0, 96, 216, 352, 1, 3, 69},
- {XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000,
- 0, 1, 0, 128, 224, 352, 1, 3, 104},
- {XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250,
- 0, 1, 0, 136, 208, 344, 3, 6, 46},
- {XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000,
- 0, 1, 0, 144, 224, 352, 1, 3, 56},
- {XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250,
- 0, 1, 0, 208, 280, 488, 3, 6, 63},
- {XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500,
- 0, 0, 1, 32, 64, 96, 32, 3, 60},
- {XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500,
- 0, 1, 0, 32, 64, 96, 1, 3, 41},
- {XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500,
- 0, 1, 0, 36, 72, 108, 1, 3, 42},
- {XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000,
- 0, 1, 1, 56, 56, 80, 1, 3, 25},
- {XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250,
- 0, 0, 0, 32, 64, 152, 1, 3, 27},
- {XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500,
- 0, 0, 0, 48, 96, 208, 1, 3, 36},
- {XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500,
- 0, 1, 0, 80, 136, 216, 3, 7, 31},
- {XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500,
- 0, 1, 0, 80, 136, 216, 3, 6, 34},
- {XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500,
- 0, 0, 0, 64, 160, 224, 1, 3, 47},
- {XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500,
- 0, 0, 0, 64, 160, 224, 1, 3, 44},
- {XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500,
- 0, 1, 0, 104, 152, 256, 3, 4, 48},
- {XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000,
- 0, 1, 0, 104, 152, 32, 3, 6, 39},
- {XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500,
- 0, 0, 0, 64, 192, 304, 1, 3, 46},
- {XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750,
- 0, 1, 0, 128, 176, 304, 3, 6, 46},
- {XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250,
- 0, 1, 0, 144, 208, 352, 3, 6, 53},
- {XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250,
- 0, 1, 0, 208, 280, 488, 3, 6, 73},
- {XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250,
- 0, 0, 1, 48, 32, 80, 3, 4, 29},
- {XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500,
- 0, 0, 1, 48, 32, 80, 3, 4, 38},
- {XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250,
- 0, 0, 1, 48, 32, 80, 3, 7, 35},
- {XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250,
- 0, 0, 1, 48, 32, 80, 3, 6, 38},
- {XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500,
- 0, 0, 1, 48, 32, 80, 3, 4, 50},
- {XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250,
- 0, 0, 1, 48, 32, 80, 3, 7, 50},
- {XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250,
- 0, 0, 1, 48, 32, 80, 3, 5, 37},
- {XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000,
- 0, 0, 1, 48, 32, 80, 3, 4, 55},
- {XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750,
- 0, 0, 1, 48, 32, 80, 3, 6, 44},
- {XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250,
- 0, 0, 1, 48, 32, 80, 3, 4, 64},
- {XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500,
- 0, 0, 1, 48, 32, 80, 3, 6, 53},
- {XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250,
- 0, 0, 1, 48, 32, 80, 3, 4, 72},
- {XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500,
- 0, 0, 1, 48, 32, 80, 3, 4, 75},
- {XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000,
- 0, 0, 1, 48, 32, 80, 3, 6, 62},
- {XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500,
- 0, 0, 1, 48, 32, 80, 3, 4, 78},
- {XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750,
- 0, 0, 1, 48, 32, 80, 3, 6, 85},
- {XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000,
- 0, 0, 0, 14, 56, 64, 1, 3, 28},
- {XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500,
- 0, 1, 1, 88, 44, 148, 4, 5, 36},
- {XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000, 0, 0, 1, 176,
- 88, 296, 20, 10, 60},
- {XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250, 0, 1, 1, 110,
- 40, 220, 5, 5, 20},
- {XDPTX_VM_480_60_P, 0x00, 720, 480, 27027, 0, 1, 1, 16, 62,
- 60, 9, 6, 30},
- {XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000, 0, 0, 1, 88,
- 44, 148, 20, 10, 60},
- {XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000, 0, 0, 1, 176,
- 88, 296, 20, 10, 60}
+ {XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175,
+ 0, 1, 1, 8, 96, 40, 2, 2, 25},
+ {XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000,
+ 0, 0, 0, 40, 128, 88, 1, 4, 23},
+ {XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750,
+ 0, 0, 0, 16, 112, 112, 6, 8, 23},
+ {XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000,
+ 0, 1, 1, 24, 136, 160, 3, 6, 29},
+ {XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250,
+ 0, 0, 1, 48, 32, 80, 3, 7, 12},
+ {XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500,
+ 0, 1, 0, 64, 128, 192, 3, 7, 20},
+ {XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000,
+ 0, 0, 1, 48, 32, 80, 3, 6, 14},
+ {XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500,
+ 0, 1, 0, 72, 128, 200, 3, 6, 22},
+ {XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000,
+ 0, 0, 0, 96, 112, 312, 1, 3, 36},
+ {XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000,
+ 0, 0, 0, 48, 112, 248, 1, 3, 38},
+ {XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500,
+ 0, 0, 0, 64, 112, 256, 3, 6, 18},
+ {XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000,
+ 0, 0, 1, 48, 32, 80, 3, 4, 23},
+ {XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750,
+ 0, 1, 0, 88, 144, 232, 3, 4, 32},
+ {XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750,
+ 0, 0, 1, 48, 32, 80, 3, 6, 17},
+ {XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500,
+ 0, 1, 0, 80, 152, 232, 3, 6, 25},
+ {XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000,
+ 0, 0, 0, 64, 192, 304, 1, 3, 46},
+ {XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000,
+ 0, 1, 0, 48, 32, 80, 3, 6, 21},
+ {XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250,
+ 0, 1, 0, 104, 176, 280, 3, 6, 30},
+ {XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750,
+ 0, 1, 0, 128, 200, 328, 1, 3, 46},
+ {XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250,
+ 0, 1, 0, 96, 224, 352, 1, 3, 43},
+ {XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000,
+ 0, 0, 1, 48, 32, 80, 3, 6, 26},
+ {XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250,
+ 0, 1, 0, 136, 200, 336, 3, 6, 36},
+ {XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000,
+ 0, 1, 0, 128, 208, 344, 1, 3, 56},
+ {XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500,
+ 0, 0, 1, 48, 32, 80, 3, 6, 37},
+ {XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500,
+ 0, 1, 0, 192, 280, 472, 3, 6, 49},
+ {XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000,
+ 0, 0, 0, 24, 72, 128, 1, 2, 22},
+ {XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500,
+ 0, 0, 0, 64, 192, 304, 1, 3, 46},
+ {XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000,
+ 0, 0, 0, 64, 192, 304, 1, 3, 46},
+ {XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000,
+ 0, 1, 1, 24, 136, 144, 3, 6, 29},
+ {XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500,
+ 0, 1, 1, 16, 40, 120, 1, 3, 20},
+ {XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000,
+ 0, 0, 0, 56, 120, 64, 37, 6, 23},
+ {XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500,
+ 0, 1, 1, 16, 64, 120, 1, 3, 16},
+ {XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500,
+ 0, 0, 0, 16, 80, 160, 1, 3, 21},
+ {XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750,
+ 0, 0, 0, 16, 96, 176, 1, 3, 28},
+ {XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000,
+ 0, 0, 0, 64, 128, 256, 1, 3, 32},
+ {XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250,
+ 0, 1, 0, 80, 128, 208, 3, 7, 27},
+ {XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500,
+ 0, 1, 0, 80, 128, 208, 3, 6, 29},
+ {XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000,
+ 0, 0, 0, 16, 144, 248, 1, 3, 38},
+ {XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000,
+ 0, 1, 0, 104, 144, 248, 3, 4, 42},
+ {XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750,
+ 0, 1, 0, 96, 152, 31, 3, 6, 33},
+ {XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500,
+ 0, 0, 0, 64, 192, 304, 1, 3, 46},
+ {XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000,
+ 0, 1, 0, 120, 176, 37, 3, 6, 40},
+ {XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000,
+ 0, 1, 0, 96, 216, 352, 1, 3, 69},
+ {XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000,
+ 0, 1, 0, 128, 224, 352, 1, 3, 104},
+ {XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250,
+ 0, 1, 0, 136, 208, 344, 3, 6, 46},
+ {XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000,
+ 0, 1, 0, 144, 224, 352, 1, 3, 56},
+ {XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250,
+ 0, 1, 0, 208, 280, 488, 3, 6, 63},
+ {XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500,
+ 0, 0, 1, 32, 64, 96, 32, 3, 60},
+ {XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500,
+ 0, 1, 0, 32, 64, 96, 1, 3, 41},
+ {XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500,
+ 0, 1, 0, 36, 72, 108, 1, 3, 42},
+ {XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000,
+ 0, 1, 1, 56, 56, 80, 1, 3, 25},
+ {XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250,
+ 0, 0, 0, 32, 64, 152, 1, 3, 27},
+ {XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500,
+ 0, 0, 0, 48, 96, 208, 1, 3, 36},
+ {XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500,
+ 0, 1, 0, 80, 136, 216, 3, 7, 31},
+ {XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500,
+ 0, 1, 0, 80, 136, 216, 3, 6, 34},
+ {XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500,
+ 0, 0, 0, 64, 160, 224, 1, 3, 47},
+ {XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500,
+ 0, 0, 0, 64, 160, 224, 1, 3, 44},
+ {XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500,
+ 0, 1, 0, 104, 152, 256, 3, 4, 48},
+ {XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000,
+ 0, 1, 0, 104, 152, 32, 3, 6, 39},
+ {XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500,
+ 0, 0, 0, 64, 192, 304, 1, 3, 46},
+ {XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750,
+ 0, 1, 0, 128, 176, 304, 3, 6, 46},
+ {XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250,
+ 0, 1, 0, 144, 208, 352, 3, 6, 53},
+ {XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250,
+ 0, 1, 0, 208, 280, 488, 3, 6, 73},
+ {XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250,
+ 0, 0, 1, 48, 32, 80, 3, 4, 29},
+ {XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500,
+ 0, 0, 1, 48, 32, 80, 3, 4, 38},
+ {XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250,
+ 0, 0, 1, 48, 32, 80, 3, 7, 35},
+ {XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250,
+ 0, 0, 1, 48, 32, 80, 3, 6, 38},
+ {XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500,
+ 0, 0, 1, 48, 32, 80, 3, 4, 50},
+ {XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250,
+ 0, 0, 1, 48, 32, 80, 3, 7, 50},
+ {XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250,
+ 0, 0, 1, 48, 32, 80, 3, 5, 37},
+ {XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000,
+ 0, 0, 1, 48, 32, 80, 3, 4, 55},
+ {XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750,
+ 0, 0, 1, 48, 32, 80, 3, 6, 44},
+ {XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250,
+ 0, 0, 1, 48, 32, 80, 3, 4, 64},
+ {XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500,
+ 0, 0, 1, 48, 32, 80, 3, 6, 53},
+ {XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250,
+ 0, 0, 1, 48, 32, 80, 3, 4, 72},
+ {XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500,
+ 0, 0, 1, 48, 32, 80, 3, 4, 75},
+ {XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000,
+ 0, 0, 1, 48, 32, 80, 3, 6, 62},
+ {XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500,
+ 0, 0, 1, 48, 32, 80, 3, 4, 78},
+ {XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750,
+ 0, 0, 1, 48, 32, 80, 3, 6, 85},
+ {XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000,
+ 0, 0, 0, 14, 56, 64, 1, 3, 28},
+ {XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500,
+ 0, 1, 1, 88, 44, 148, 4, 5, 36},
+ {XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000,
+ 0, 0, 1, 176, 88, 296, 20, 10, 60},
+ {XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250,
+ 0, 1, 1, 110, 40, 220, 5, 5, 20},
+ {XDPTX_VM_480_60_P, 0x00, 720, 480, 27027,
+ 0, 1, 1, 16, 62, 60, 9, 6, 30},
+ {XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000,
+ 0, 0, 1, 88, 44, 148, 20, 10, 60},
+ {XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000,
+ 0, 0, 1, 176, 88, 296, 20, 10, 60}
};