diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html index 232ed4da..93255c62 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/functions.html @@ -40,6 +40,7 @@
  • l
  • m
  • n
    • +
  • o
  • p
  • q
  • r
    • @@ -56,7 +57,8 @@ Here is a list of all class members with links to the classes they belong to:

    - a -

    - b -

    - e -

    +: XDptx_MstStream
  • MstSupport +: XDptx_Config

    - n -

    +

    - o -

    - p -

    - s -

    - n -

    +

    - o -

    - p -

    - s -

    Note:
    For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.
    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html
index 5071f985..ada0518e 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx-members.html
@@ -22,6 +22,7 @@
     
  • Class Members
    • 
   
 
    XDptx Member List
    This is the complete list of members for XDptx, including all inherited members.
    
+  
@@ -34,6 +35,7 @@
   
+  
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html
index 0d40a1f8..df7c2437 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx.html
@@ -49,6 +49,10 @@ The XDptx driver instance data. The
 
 
 
+
+
+
+
 
@@ -63,6 +67,21 @@ The XDptx driver instance data. The
 
 
    AuxDelayUsXDptx
    
   
    BoardCharXDptx
    
   
    ConfigXDptx
    
   
    HpdEventCallbackRefXDptx
    MstEnableXDptx
    
   
    MstStreamConfigXDptx
    
   
    RxConfigXDptx
    SbMsgDelayUsXDptx
    
   
    TopologyXDptx
    
   
    TrainAdaptiveXDptx
    
   
    UserTimerPtrXDptx
    XDptx_Topology Topology
    u32 AuxDelayUs
    u32 SbMsgDelayUs
    XDptx_TimerHandler UserTimerWaitUs
    
 
 
    void * UserTimerPtr
    
 
    Member Data Documentation
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u32 XDptx::AuxDelayUs          
    
+
    
+
    
+
+
    
+Amount of latency in micro- seconds to use between AUX transactions. 
+
    
+
    
 
 
    
 
    
@@ -243,6 +262,21 @@ Configuration structure for a multi-stream transport (MST) stream.
 Configuration structure for the RX device. 
 
    
 
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u32 XDptx::SbMsgDelayUs          
    
+
    
+
    
+
+
    
+Amount of latency in micro- seconds to use between sideband messages for multi-stream transport (MST) mode. 
+
    
+
    
 
 
    
 
    
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html
index 7dfe9cbe..2b918b86 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config-members.html
@@ -24,12 +24,18 @@
 
    XDptx_Config Member List
    This is the complete list of members for XDptx_Config, including all inherited members.
    
+  
+  
+  
+  
+  
+  
    
   
    BaseAddrXDptx_Config
    
   
    DeviceIdXDptx_Config
    DpProtocolXDptx_Config
    
   
    DualPixelEnXDptx_Config
    
   
    MaxBitsPerColorXDptx_Config
    
   
    MaxLaneCountXDptx_Config
    
   
    MaxLinkRateXDptx_Config
    MstSupportXDptx_Config
    NumAudioChsXDptx_Config
    NumMstStreamsXDptx_Config
    PayloadDataWidthXDptx_Config
    
   
    QuadPixelEnXDptx_Config
    
   
    SAxiClkHzXDptx_Config
    SecondaryChEnXDptx_Config
    
   
    YCrCbEnXDptx_Config
    
   
    YOnlyEnXDptx_Config
    
 
    Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. 
diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html
index 3b01100b..60bbddd1 100644
--- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html
+++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/struct_x_dptx___config.html
@@ -45,9 +45,21 @@ This typedef contains configuration information for the DisplayPort TX core.
 
 u8 DualPixelEn
 
+u8 YCrCbEn
+
 u8 YOnlyEn
 
-u8 YCrCbEn
+u8 PayloadDataWidth
+
+u8 SecondaryChEn
+
+u8 NumAudioChs
+
+u8 MstSupport
+
+u8 NumMstStreams
+
+u8 DpProtocol
 
 
 
    Member Data Documentation
    
@@ -63,7 +75,7 @@ This typedef contains configuration information for the DisplayPort TX core.
 
    
 
 
    
-The base address of the core. 
+The base address of the core instance. 
 
    
 
    
 
@@ -81,6 +93,21 @@ The base address of the core.
 Device instance ID. 
 
    
 
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::DpProtocol          
    
+
    
+
    
+
+
    
+The DisplayPort protocol version that this core instance is configured for. 0 = v1.1a, 1 = v1.2. 
+
    
+
    
 
 
    
 
    
@@ -93,7 +120,7 @@ Device instance ID.
 
    
 
 
    
-Dual pixel support by this core's instance. 
+Dual pixel support by this core instance. 
 
    
 
    
 
@@ -108,7 +135,7 @@ Dual pixel support by this core's instance.
 
    
 
 
    
-The maximum bits/color supported by this core's instance 
+The maximum bits/color supported by this core instance 
 
    
 
    
 
@@ -123,7 +150,7 @@ The maximum bits/color supported by this core's instance
 
    
 
 
    
-The maximum lane count supported by this core's instance. 
+The maximum lane count supported by this core instance. 
 
    
 
    
 
@@ -138,7 +165,67 @@ The maximum lane count supported by this core's instance.
 
    
 
 
    
-The maximum link rate supported by this core's instance. 
+The maximum link rate supported by this core instance. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::MstSupport          
    
+
    
+
    
+
+
    
+Multi-stream transport (MST) mode is enabled by this core instance. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::NumAudioChs          
    
+
    
+
    
+
+
    
+The number of audio channels supported by this core instance. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::NumMstStreams          
    
+
    
+
    
+
+
    
+The total number of MST streams supported by this core instance. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::PayloadDataWidth          
    
+
    
+
    
+
+
    
+The payload data width used by this core instance. 
 
    
 
    
 
@@ -153,7 +240,7 @@ The maximum link rate supported by this core's instance.
 
    
 
 
    
-Quad pixel support by this core's instance. 
+Quad pixel support by this core instance. 
 
    
 
    
 
@@ -168,7 +255,22 @@ Quad pixel support by this core's instance.
 
    
 
 
    
-The clock frequency of the core's S_AXI_ACLK port. 
+The clock frequency of the core instance's S_AXI_ACLK port. 
+
    
+
    
+
+
    
+
    
+      
+        
+          
+        
+      
    u8 XDptx_Config::SecondaryChEn          
    
+
    
+
    
+
+
    
+This core instance supports audio packets being sent by the secondary channel. 
 
    
 
    
 
@@ -183,7 +285,7 @@ The clock frequency of the core's S_AXI_ACLK port.
 
    
 
 
    
-YCrCb format support by this core's instance. 
+YCrCb format support by this core instance. 
 
    
 
    
 
@@ -198,7 +300,7 @@ YCrCb format support by this core's instance.
 
    
 
 
    
-YOnly format support by this core's instance. 
+YOnly format support by this core instance. 
 
    
 
    
 
    The documentation for this struct was generated from the following file:
    The MSA registers for stream 2 are at an offset from the corresponding registers of stream 0.

    @@ -8981,7 +9013,7 @@ Average stream symbol timeslots per MTP config.

    - +
    #define XDPTX_STREAM3_MSA_START   0x0550 #define XDPTX_STREAM3_MSA_START   0x05A0
    @@ -9004,40 +9036,23 @@ Start of the MSA registers for stream 3.

    Value:

    (XDPTX_STREAM3_MSA_START - \
-                XDPTX_STREAM1_MSA_START)
-
    The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. + XDPTX_STREAM0_MSA_START) +The MSA registers for stream 3 are at an offset from the corresponding registers of stream 0.

    - +

    - +
    #define XDPTX_STREAM4_MSA_START   0x05A0 #define XDPTX_STREAM_ID0   0

    -Start of the MSA registers for stream 4. -

    -

    - -

    -
    - - - - -
    #define XDPTX_STREAM4_MSA_START_OFFSET
    -
    -
    -

    -Value:

    (XDPTX_STREAM4_MSA_START - \
-                XDPTX_STREAM1_MSA_START)
-
    The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1.

    @@ -9083,21 +9098,6 @@ Start of the MSA registers for stream 4.

    - -

    - -

    -
    - - - - -
    #define XDPTX_STREAM_ID4   4
    -
    -
    - -

    -

    diff --git a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html index 4870629e..4bfae35a 100644 --- a/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html +++ b/XilinxProcessorIPLib/drivers/dptx/doc/html/api/xdptx__spm_8c.html @@ -32,7 +32,6 @@ This file contains the stream policy maker functions for the

    -#include "math.h"
    #include "    xdptx.h"
    #include "xdptx_hw.h"
    #include "xstatus.h"