From 8fbb1b0a90d8d9bb708aee03eb6d3cef433fb01d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Date: Fri, 25 Jul 2014 16:12:19 +0530 Subject: [PATCH] sw_apps:zynq_fsbl: Removed the PEEP code Removed the unwanted PEEP code from FSBL Signed-off-by: Krishna Chaitanya Acked-by: Nirmala Pelluri --- lib/sw_apps/zynq_fsbl/src/ddr_init.c | 282 --------------------------- lib/sw_apps/zynq_fsbl/src/main.c | 10 - 2 files changed, 292 deletions(-) delete mode 100644 lib/sw_apps/zynq_fsbl/src/ddr_init.c diff --git a/lib/sw_apps/zynq_fsbl/src/ddr_init.c b/lib/sw_apps/zynq_fsbl/src/ddr_init.c deleted file mode 100644 index 9b19260d..00000000 --- a/lib/sw_apps/zynq_fsbl/src/ddr_init.c +++ /dev/null @@ -1,282 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file ddr_init.c -* -* Initialize the DDR controller. When PCW is functioning, this would be gone. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who	Date			 Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm	06/19/09 First release
-* 2.00a jz	05/11/11 Changed register to #defines, updated to peep11
-* 3.00a mb	30/05/12 included fsbl.h
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_io.h" -#include "fsbl.h" - -/************************** Constant Definitions *****************************/ -#define DDR_CONFIG_BASE (XPS_DDR_CTRL_BASEADDR + 0x000) - -#define DDR_MSTR_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x000) - -#define DDR_TWORANKPHY_REG (XPS_DDR_CTRL_BASEADDR + 0x004) - -#define DDR_HPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x008) -#define DDR_LPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x00C) -#define DDR_W_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x010) -#define DDR_DRAM_PARAMS_1_REG (XPS_DDR_CTRL_BASEADDR + 0x014) -#define DDR_DRAM_PARAMS_2_REG (XPS_DDR_CTRL_BASEADDR + 0x018) -#define DDR_DRAM_PARAMS_3_REG (XPS_DDR_CTRL_BASEADDR + 0x01C) -#define DDR_DRAM_PARAMS_4_REG (XPS_DDR_CTRL_BASEADDR + 0x020) -#define DDR_DRAM_PARAMS_5_REG (XPS_DDR_CTRL_BASEADDR + 0x024) -#define DDR_DRAM_INIT_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x028) - -#define DDR_DRAM_MODE_1_REG (XPS_DDR_CTRL_BASEADDR + 0x02C) -#define DDR_DRAM_MODE_2_REG (XPS_DDR_CTRL_BASEADDR + 0x030) -#define DDR_DRAM_BURST8_REG (XPS_DDR_CTRL_BASEADDR + 0x034) - -#define DDR_DEBUG_REG (XPS_DDR_CTRL_BASEADDR + 0x038) - -#define DDR_ADDR_MAP_1_REG (XPS_DDR_CTRL_BASEADDR + 0x03C) -#define DDR_ADDR_MAP_2_REG (XPS_DDR_CTRL_BASEADDR + 0x040) -#define DDR_ADDR_MAP_3_REG (XPS_DDR_CTRL_BASEADDR + 0x044) - -#define DDR_ODT_RD_WR_REG (XPS_DDR_CTRL_BASEADDR + 0x048) -#define DDR_PHY_RDC_FIFO_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x04C) -#define DDR_REG_PHY_RDC_FIFO_CTRL (XPS_DDR_CTRL_BASEADDR + 0x050) -#define DDR_STATUS_REG (XPS_DDR_CTRL_BASEADDR + 0x054) - -#define DDR_DLL_CALIB_REG (XPS_DDR_CTRL_BASEADDR + 0x058) -#define DDR_ODT_REG (XPS_DDR_CTRL_BASEADDR + 0x05C) -#define DDR_MISC_1_REG (XPS_DDR_CTRL_BASEADDR + 0x060) -#define DDR_MISC_2_REG (XPS_DDR_CTRL_BASEADDR + 0x064) - -#define DDR_WR_DLL_FORCE (XPS_DDR_CTRL_BASEADDR + 0x068) -#define DDR_RD_DLL_FORCE0_REG (XPS_DDR_CTRL_BASEADDR + 0x06C) -#define DDR_RD_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x070) - -#define DDR_WR_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x074) -#define DDR_RD_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x078) - -#define DDR_MSTR_DLL_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x07C) -#define DDR_RD_SLAVE_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x080) -#define DDR_RD_SLAVE_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x084) - -#define DDR_OF_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x088) -#define DDR_OF_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x08C) -#define DDR_OF_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x090) -#define DDR_OF_STATUS3_REG (XPS_DDR_CTRL_BASEADDR + 0x094) - -#define DDR_MSTR_DLL_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x098) - -#define DDR_Wr_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x09C) -#define DDR_REFRESH_TIMER01_REG (XPS_DDR_CTRL_BASEADDR + 0x0A0) -#define DDR_T_ZQ_REG (XPS_DDR_CTRL_BASEADDR + 0x0A4) -#define DDR_T_ZQ_SHORT_INTERVAL_REG (XPS_DDR_CTRL_BASEADDR + 0x0A8) - -#define DDR_STATUS_DATA_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0AC) -#define DDR_STATUS_DATA_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B0) -#define DDR_STATUS_DQS_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0B4) -#define DDR_STATUS_DQS_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B8) - -#define DDR_WR_DATA_SLV0_REG (XPS_DDR_CTRL_BASEADDR + 0x17c) -#define DDR_WR_DATA_SLV1_REG (XPS_DDR_CTRL_BASEADDR + 0x180) -#define DDR_WR_DATA_SLV2_REG (XPS_DDR_CTRL_BASEADDR + 0x184) -#define DDR_WR_DATA_SLV3_REG (XPS_DDR_CTRL_BASEADDR + 0x188) - -#define DDR_ID_REG (XPS_DDR_CTRL_BASEADDR + 0x200) -#define DDR_DDR_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x204) - -#define DDR_PRIO_WR_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x208) -#define DDR_PRIO_WR_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x20C) -#define DDR_PRIO_WR_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x210) -#define DDR_PRIO_WR_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x214) -#define DDR_PRIO_RD_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x218) -#define DDR_PRIO_RD_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x21C) -#define DDR_PRIO_RD_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x220) -#define DDR_PRIO_RD_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x224) - -#define DDR_PERF_MON_1_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x228) -#define DDR_PERF_MON_1_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x22C) -#define DDR_PERF_MON_1_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x230) -#define DDR_PERF_MON_1_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x234) -#define DDR_PERF_MON_2_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x238) -#define DDR_PERF_MON_2_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x23C) -#define DDR_PERF_MON_2_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x240) -#define DDR_PERF_MON_2_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x244) -#define DDR_PERF_MON_3_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x248) -#define DDR_PERF_MON_3_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x24C) -#define DDR_PERF_MON_3_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x250) -#define DDR_PERF_MON_3_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x254) -#define DDR_TRUSTED_MEM_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x258) - -#define DDR_EXCLACC_CFG_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x25C) -#define DDR_EXCLACC_CFG_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x260) -#define DDR_EXCLACC_CFG_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x264) -#define DDR_EXCLACC_CFG_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x268) - -/* Trust zone configuration register */ -#define SLCR_LOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x4) -#define SLCR_UNLOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x8) -#define TZ_DDR_RAM_REG (XPS_SYS_CTRL_BASEADDR + 0x430) - - -/* Mask defines */ -#define DDR_OUT_RESET_MASK 0x1 - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define DDRIn32 Xil_In32 -#define DDROut32 Xil_Out32 -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void init_ddr(void); - -#define DDRIn32 Xil_In32 -#define DDROut32 Xil_Out32 - -static int verify = 0; - -static void NewDDROut32(u32 Address, u32 Value) -{ - u32 Data; - - if (verify) { - Data = DDRIn32(Address); - if (Data != Value) fsbl_printf(DEBUG_INFO,"Verify failed, Address = %08X, \ - Data = %08X, Expected = %08X\n\r", Address, Data, Value); - } else - DDROut32(Address, Value); -} - -#undef DDROut32 -#define DDROut32 NewDDROut32 - -void init_ddr(void) -{ - u32 RegValue; - - RegValue = DDRIn32(DDR_MSTR_CTRL_REG); - - /* If DDR is being taking out of reset, then it has been configured - */ - if (RegValue & DDR_OUT_RESET_MASK) - verify = 1; - - /* Configure DDR */ - DDROut32(DDR_MSTR_CTRL_REG, 0x00000200); - - /* direct rip of the DDR init tcl for the PEEP startup */ - DDROut32(DDR_TWORANKPHY_REG, 0x000C1061); /* # 0 */ - - DDROut32(DDR_LPR_PARAMS_REG, 0x03001001); //;#3 - DDROut32(DDR_W_PARAMS_REG, 0x00014001); //;#4 - - DDROut32(DDR_DRAM_PARAMS_1_REG, 0x0004e020); //; #5 - -#ifdef PEEP_CODE - DDROut32(DDR_DRAM_PARAMS_2_REG, 0x36264ccf); //; #6 -#else - DDROut32(DDR_DRAM_PARAMS_2_REG, 0x349B48CD); //; #6 -#endif - DDROut32(DDR_DRAM_PARAMS_3_REG, 0x820158a4); //; #7 - - DDROut32(DDR_DRAM_PARAMS_4_REG, 0x250882c4); //; #8 - - DDROut32(DDR_DRAM_INIT_PARAMS_REG, 0x00809004); //; #10 - - DDROut32(DDR_DRAM_MODE_1_REG, 0x0); //; #11 - - DDROut32(DDR_DRAM_MODE_2_REG, 0x00040952); //; #12 - - DDROut32(DDR_DRAM_BURST8_REG, 0x00020022); //; #13 - -#ifdef PEEP_CODE - DDROut32(DDR_ADDR_MAP_1_REG, 0xF88); //; #15 -#endif - -#ifdef PALLADIUM - DDROut32(DDR_ADDR_MAP_1_REG, 0x777); //; #15 -#endif - - DDROut32(DDR_ADDR_MAP_2_REG, 0xFF000000); //; #16 - - DDROut32(DDR_ADDR_MAP_3_REG, 0x0FF66666); //; #17 - - DDROut32(DDR_REG_PHY_RDC_FIFO_CTRL, 0x256); //; #20 - - DDROut32(DDR_ODT_REG, 0x2223); //; #23 - - DDROut32(DDR_MISC_2_REG, 0x00020FE0); //; #25 - - DDROut32(DDR_T_ZQ_REG, 0x10200800); //; #41 - - DDROut32(DDR_STATUS_DQS_SL_DLL_23_REG, 0x200065); //; #46 - - DDROut32(DDR_WR_DATA_SLV0_REG, 0x50); //; #95 - - DDROut32(DDR_WR_DATA_SLV1_REG, 0x50); //; #96 - - DDROut32(DDR_WR_DATA_SLV2_REG, 0x50); //; #97 - - DDROut32(DDR_WR_DATA_SLV3_REG, 0x50); //; #98 - - DDROut32(DDR_ID_REG, 0x0); //; #128 - - /* Enable ddr controller by taking the controller out of reset */ - DDROut32(DDR_MSTR_CTRL_REG, - DDRIn32(DDR_MSTR_CTRL_REG) | DDR_OUT_RESET_MASK); - -#ifdef PALLADIUM - - /* Workaround for early palladium, to be removed for 4.61 */ - DDROut32(SLCR_UNLOCK_REG, 0xDF0D); - - DDROut32(TZ_DDR_RAM_REG, 0xffffffff); - - DDROut32(SLCR_LOCK_REG, 0x767B); - -#endif /* PALLADIUM*/ -} diff --git a/lib/sw_apps/zynq_fsbl/src/main.c b/lib/sw_apps/zynq_fsbl/src/main.c index 94eaef9b..567033d8 100644 --- a/lib/sw_apps/zynq_fsbl/src/main.c +++ b/lib/sw_apps/zynq_fsbl/src/main.c @@ -159,9 +159,6 @@ extern char* getPS7MessageInfo(unsigned key); #ifdef PS7_POST_CONFIG extern int ps7_post_config(); #endif -#ifdef PEEP_CODE -extern void init_ddr(void); -#endif static void Update_MultiBootRegister(void); /* Exception handlers */ @@ -230,12 +227,6 @@ int main(void) u32 HandoffAddress = 0; u32 Status = XST_SUCCESS; -#ifdef PEEP_CODE - /* - * PEEP DDR initialization - */ - init_ddr(); -#else /* * PCW initialization for MIO,PLL,CLK and DDR */ @@ -250,7 +241,6 @@ int main(void) */ FsblHookFallback(); } -#endif /* * Unlock SLCR for SLCR register write