diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c index 94cd5d90..c20d38f9 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c @@ -269,24 +269,24 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) u8 Edid[XDPTX_EDID_SIZE]; /* Set the bits per color. If not set, the default is 6. */ - XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1, 8); + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0, 8); /* Set synchronous clock mode. */ - XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID1, 1); + XDptx_CfgMsaEnSynchClkMode(InstancePtr, XDPTX_STREAM_ID0, 1); + XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4); /* Choose a method for selecting the video mode. There are 3 ways to do this: * 1) Use the preferred timing from the monitor's EDID: * u8 Edid[XDPTX_EDID_SIZE]; * XDptx_GetEdid(InstancePtr, Edid); - * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID1, Edid); + * XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, XDPTX_STREAM_ID0, Edid); * * 2) Use a standard video timing mode (see mode_table.h): - * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID1, + * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0, XDPTX_VM_640x480_60_P); * * 3) Use a custom configuration for the main stream attributes (MSA): @@ -302,16 +302,16 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) * MsaConfigCustom.Dmt.VFrontPorch = 1; * MsaConfigCustom.Dmt.VSyncPulseWidth = 3; * MsaConfigCustom.Dmt.VBackPorch = 38; - * XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID1, + * XDptx_CfgMsaUseCustom(InstancePtr, XDPTX_STREAM_ID0, * &MsaConfigCustom, 1); */ Status = XDptx_GetEdid(InstancePtr, Edid); if (Status == XST_SUCCESS) { XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr, - XDPTX_STREAM_ID1, Edid); + XDPTX_STREAM_ID0, Edid); } else { - XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID1, + XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_STREAM_ID0, XDPTX_VM_640x480_60_P); } @@ -327,7 +327,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); /* Set the DisplayPort TX video mode. */ - XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID1); + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0); /* Configure video stream source or generator here. These function need * to be implemented in order for video to be displayed and is hardware diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c index 65621340..a4f40548 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_mst_example.c @@ -79,10 +79,10 @@ /* Define the mapping between sinks and streams. The sink numbers are in the * order that they are discovered by the XDptx_FindAccessibleDpDevices driver * function. */ -#define STREAM1_USE_SINKNUM 0 -#define STREAM2_USE_SINKNUM 1 -#define STREAM3_USE_SINKNUM 2 -#define STREAM4_USE_SINKNUM 3 +#define STREAM0_USE_SINKNUM 0 +#define STREAM1_USE_SINKNUM 1 +#define STREAM2_USE_SINKNUM 2 +#define STREAM3_USE_SINKNUM 3 #endif /* The video resolution from the display mode timings (DMT) table to use for @@ -92,6 +92,9 @@ /* The color depth (bits per color component) to use for each stream. */ #define USE_BPC 8 +/* Some MST configurations require delays when sending sideband messages. */ +#define USE_DELAYS_FOR_MST + /**************************** Function Prototypes *****************************/ u32 Dptx_MstExample(XDptx *InstancePtr, u16 DeviceId); @@ -221,14 +224,15 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) return XST_FAILURE; } - /* If required, add delays in MST mode. */ +#ifdef USE_DELAYS_FOR_MST InstancePtr->AuxDelayUs = 30000; InstancePtr->SbMsgDelayUs = 100000; +#endif + XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID0); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID1); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID2); XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID3); - XDptx_ClearMsaValues(InstancePtr, XDPTX_STREAM_ID4); #ifdef ALLOCATE_FROM_SINKLIST xil_printf("Find topology >>>\n"); @@ -247,11 +251,11 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) /* Enable multi-stream transport (MST) mode for this example. */ XDptx_MstCfgModeEnable(InstancePtr); for (StreamIndex = 0; StreamIndex < NumStreams; StreamIndex++) { - XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID1 + + XDptx_MstCfgStreamEnable(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex); } for (StreamIndex = NumStreams; StreamIndex < 4; StreamIndex++) { - XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID1 + + XDptx_MstCfgStreamDisable(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex); } @@ -259,24 +263,28 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) u8 Lct; u8 Rad[15]; - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) { Lct = 2; Rad[0] = 8; + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID0, Lct, Rad); + } + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { + Lct = 3; Rad[0] = 1; Rad[1] = 8; XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID1, Lct, Rad); } if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID2)) { - Lct = 3; Rad[0] = 1; Rad[1] = 8; + Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8; XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID2, Lct, Rad); } if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID3)) { - Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 8; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad); - } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) { Lct = 4; Rad[0] = 1; Rad[1] = 1; Rad[2] = 9; - XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID4, Lct, Rad); + XDptx_SetStreamSinkRad(InstancePtr, XDPTX_STREAM_ID3, Lct, Rad); } #else + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0)) { + XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID0, + STREAM0_USE_SINKNUM); + } if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1)) { XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID1, STREAM1_USE_SINKNUM); @@ -289,25 +297,21 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID3, STREAM3_USE_SINKNUM); } - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID4)) { - XDptx_SetStreamSelectFromSinkList(InstancePtr, XDPTX_STREAM_ID4, - STREAM4_USE_SINKNUM); - } #endif /* Disable MST for now. */ XDptx_MstDisable(InstancePtr); for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1 + + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex)) { - XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID1 + + XDptx_CfgMsaSetBpc(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex, Bpc); XDptx_CfgMsaEnSynchClkMode(InstancePtr, - XDPTX_STREAM_ID1 + StreamIndex, 1); + XDPTX_STREAM_ID0 + StreamIndex, 1); XDptx_CfgMsaUseStandardVideoMode(InstancePtr, - XDPTX_STREAM_ID1 + StreamIndex, VideoMode); + XDPTX_STREAM_ID0 + StreamIndex, VideoMode); } } @@ -321,9 +325,9 @@ u32 Dptx_MstExampleRun(XDptx *InstancePtr) /* Set the video modes for each stream. */ for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { - if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID1 + + if (XDptx_MstStreamIsEnabled(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex)) { - XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID1 + + XDptx_SetVideoMode(InstancePtr, XDPTX_STREAM_ID0 + StreamIndex); } } diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h index ed725331..12e224d1 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h @@ -144,11 +144,11 @@ in microseconds. */ /* @} */ -/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1. +/** @name DPTX core registers: Main stream attributes for SST / MST STREAM0. * @{ */ -#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers - for stream 1. */ +#define XDPTX_STREAM0_MSA_START 0x0180 /**< Start of the MSA registers + for stream 0. */ #define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in the horizontal framing period. */ @@ -297,33 +297,33 @@ extension packet. */ /* @} */ -/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. +/** @name DPTX core registers: Main stream attributes for MST STREAM1, 2, and 3. * @{ */ -#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers +#define XDPTX_STREAM1_MSA_START 0x0500 /**< Start of the MSA registers + for stream 1. */ +#define XDPTX_STREAM1_MSA_START_OFFSET (XDPTX_STREAM1_MSA_START - \ + XDPTX_STREAM0_MSA_START) /**< The MSA registers for + stream 1 are at an + offset from the + corresponding registers + of stream 0. */ +#define XDPTX_STREAM2_MSA_START 0x0550 /**< Start of the MSA registers for stream 2. */ #define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for + XDPTX_STREAM0_MSA_START) /**< The MSA registers for stream 2 are at an offset from the corresponding registers - of stream 1. */ -#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers + of stream 0. */ +#define XDPTX_STREAM3_MSA_START 0x05A0 /**< Start of the MSA registers for stream 3. */ #define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for + XDPTX_STREAM0_MSA_START) /**< The MSA registers for stream 3 are at an offset from the corresponding registers - of stream 1. */ -#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers - for stream 4. */ -#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \ - XDPTX_STREAM1_MSA_START) /**< The MSA registers for - stream 4 are at an - offset from the - corresponding registers - of stream 1. */ + of stream 0. */ /* @} */ #define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload @@ -365,13 +365,13 @@ 0x3 /**< Pseudo random bit sequence 7 transmitted. */ /* 0x01C: SOFTWARE_RESET */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \ +#define XDPTX_SOFT_RESET_VIDEO_STREAM0_MASK \ 0x00000001 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \ +#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \ 0x00000002 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \ +#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \ 0x00000004 /**< Reset video logic. */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \ +#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \ 0x00000008 /**< Reset video logic. */ #define XDPTX_SOFT_RESET_AUX_MASK \ 0x00000080 /**< Reset AUX logic. */ @@ -1165,10 +1165,10 @@ /** @name Stream identification. * @{ */ +#define XDPTX_STREAM_ID0 0 #define XDPTX_STREAM_ID1 1 #define XDPTX_STREAM_ID2 2 #define XDPTX_STREAM_ID3 3 -#define XDPTX_STREAM_ID4 4 /* @} */ /** @name Sideband message codes when the driver is in MST mode. diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c index c4325573..d97da820 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c @@ -254,6 +254,10 @@ u32 XDptx_MstCapable(XDptx *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + if (InstancePtr->Config.MstSupport == 0) { + return XST_NO_FEATURE; + } + /* Check that the RX device has a DisplayPort Configuration Data (DPCD) * version greater than or equal to 1.2 to be able to support MST * functionality. */ @@ -402,11 +406,11 @@ u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - return InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable; + return InstancePtr->MstStreamConfig[Stream].MstStreamEnable; } /******************************************************************************/ @@ -426,11 +430,11 @@ void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 1; + InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 1; } /******************************************************************************/ @@ -450,11 +454,11 @@ void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 0; + InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 0; } /******************************************************************************/ @@ -485,11 +489,11 @@ void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; + MstStream = &InstancePtr->MstStreamConfig[Stream]; Topology = &InstancePtr->Topology; MstStream->LinkCountTotal = Topology->SinkList[SinkNum]->LinkCountTotal; @@ -526,13 +530,13 @@ void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Xil_AssertVoid(LinkCountTotal > 0); Xil_AssertVoid(RelativeAddress != NULL); - MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; + MstStream = &InstancePtr->MstStreamConfig[Stream]; MstStream->LinkCountTotal = LinkCountTotal; for (Index = 0; Index < MstStream->LinkCountTotal - 1; Index++) { @@ -688,7 +692,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; MsaConfig = &InstancePtr->MsaConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { + if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) { Status = XDptx_AllocatePayloadVcIdTable(InstancePtr, MstStream->LinkCountTotal, MstStream->RelativeAddress, StreamIndex + 1, @@ -709,7 +713,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { + if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) { Status = XDptx_SendSbMsgAllocatePayload(InstancePtr, MstStream->LinkCountTotal, MstStream->RelativeAddress, StreamIndex + 1, diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c index 4789e154..00b1ef38 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c @@ -188,13 +188,13 @@ u32 XDptx_SelfTest(XDptx *InstancePtr) StreamOffset = 0; } else if (StreamIndex == 1) { - StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET; + StreamOffset = XDPTX_STREAM1_MSA_START_OFFSET; } else if (StreamIndex == 2) { - StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET; + StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET; } else if (StreamIndex == 3) { - StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET; + StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET; } for (Index = 0; Index < 20; Index++) { diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c index 0884c12e..dbfa2b09 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c @@ -111,11 +111,11 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; LinkConfig = &InstancePtr->LinkConfig; /* Verify the rest of the values used. */ @@ -280,11 +280,11 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; /* Configure the MSA values from the display monitor DMT table. */ MsaConfig->Dmt.HResolution = XDptx_DmtModes[VideoMode].HResolution; @@ -331,12 +331,12 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Xil_AssertVoid(Edid != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; Ptm = &Edid[XDPTX_EDID_PTM]; /* Configure the MSA values with the PTM information as @@ -440,12 +440,12 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Xil_AssertVoid(MsaConfigCustom != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; /* Copy the MSA values from the user configuration structure. */ MsaConfig->Dmt.HResolution = MsaConfigCustom->Dmt.HResolution; @@ -500,14 +500,14 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) || (BitsPerColor == 10) || (BitsPerColor == 12) || (BitsPerColor == 16)); - InstancePtr->MsaConfig[Stream - 1].BitsPerColor = BitsPerColor; + InstancePtr->MsaConfig[Stream].BitsPerColor = BitsPerColor; /* Calculate the rest of the MSA values. */ XDptx_CfgMsaRecalculate(InstancePtr, Stream); @@ -534,12 +534,12 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Xil_AssertVoid((Enable == 0) || (Enable == 1)); - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; MsaConfig->SynchronousClockMode = Enable; @@ -572,9 +572,9 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); XDptx_ClearMsaValues(InstancePtr, Stream); XDptx_SetMsaValues(InstancePtr, Stream); @@ -596,58 +596,58 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) { XDptx_Config *Config; - u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, - XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; + u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET, + XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Config = &InstancePtr->Config; XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream - 1) * 4, 0); + XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream) * 4, 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + - StreamOffset[Stream - 1], 0); + StreamOffset[Stream], 0); } /******************************************************************************/ @@ -668,70 +668,70 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) { XDptx_Config *Config; XDptx_MainStreamAttributes *MsaConfig; - u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, - XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; + u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET, + XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || - (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || - (Stream == XDPTX_STREAM_ID4)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || + (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || + (Stream == XDPTX_STREAM_ID3)); Config = &InstancePtr->Config; - MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; + MsaConfig = &InstancePtr->MsaConfig[Stream]; /* Set the main stream attributes to the associated DisplayPort TX core * registers. */ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + - StreamOffset[Stream - 1], MsaConfig->HClkTotal); + StreamOffset[Stream], MsaConfig->HClkTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + - StreamOffset[Stream - 1], MsaConfig->VClkTotal); + StreamOffset[Stream], MsaConfig->VClkTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + - StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPolarity | + StreamOffset[Stream], MsaConfig->Dmt.HSyncPolarity | (MsaConfig->Dmt.VSyncPolarity << XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + - StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPulseWidth); + StreamOffset[Stream], MsaConfig->Dmt.HSyncPulseWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + - StreamOffset[Stream - 1], MsaConfig->Dmt.VSyncPulseWidth); + StreamOffset[Stream], MsaConfig->Dmt.VSyncPulseWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + - StreamOffset[Stream - 1], MsaConfig->Dmt.HResolution); + StreamOffset[Stream], MsaConfig->Dmt.HResolution); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + - StreamOffset[Stream - 1], MsaConfig->Dmt.VResolution); + StreamOffset[Stream], MsaConfig->Dmt.VResolution); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + - StreamOffset[Stream - 1], MsaConfig->HStart); + StreamOffset[Stream], MsaConfig->HStart); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + - StreamOffset[Stream - 1], MsaConfig->VStart); + StreamOffset[Stream], MsaConfig->VStart); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + - StreamOffset[Stream - 1], MsaConfig->Misc0); + StreamOffset[Stream], MsaConfig->Misc0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + - StreamOffset[Stream - 1], MsaConfig->Misc1); + StreamOffset[Stream], MsaConfig->Misc1); XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + - StreamOffset[Stream - 1], MsaConfig->Dmt.PixelClkKhz); + StreamOffset[Stream], MsaConfig->Dmt.PixelClkKhz); XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + - StreamOffset[Stream - 1], MsaConfig->NVid); + StreamOffset[Stream], MsaConfig->NVid); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + - StreamOffset[Stream - 1], MsaConfig->UserPixelWidth); + StreamOffset[Stream], MsaConfig->UserPixelWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + - StreamOffset[Stream - 1], MsaConfig->DataPerLane); + StreamOffset[Stream], MsaConfig->DataPerLane); /* Set the transfer unit values to the associated DisplayPort TX core * registers. */ if (InstancePtr->MstEnable == 1) { XDptx_WriteReg(Config->BaseAddr, - XDPTX_STREAM0 + (Stream - 1) * 4, + XDPTX_STREAM0 + (Stream) * 4, ((MsaConfig->AvgBytesPerTU / 1000) << 16) | (MsaConfig->AvgBytesPerTU % 1000)); } XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + - StreamOffset[Stream - 1], MsaConfig->TransferUnitSize); + StreamOffset[Stream], MsaConfig->TransferUnitSize); XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + - StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU / 1000); + StreamOffset[Stream], MsaConfig->AvgBytesPerTU / 1000); XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + - StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU % 1000); + StreamOffset[Stream], MsaConfig->AvgBytesPerTU % 1000); XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + - StreamOffset[Stream - 1], MsaConfig->InitWait); + StreamOffset[Stream], MsaConfig->InitWait); } /******************************************************************************/ @@ -755,7 +755,7 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) { XDptx_MainStreamAttributes *MsaConfig = - &InstancePtr->MsaConfig[Stream - 1]; + &InstancePtr->MsaConfig[Stream]; XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; double PeakPixelBw; u32 LinkBw; @@ -770,18 +770,18 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27); /* Calculate the payload bandiwdth number (PBN). */ - InstancePtr->MstStreamConfig[Stream - 1].MstPbn = + InstancePtr->MstStreamConfig[Stream].MstPbn = 1.006 * PeakPixelBw * ((double)64 / 54); /* Ceil - round up if required, avoiding overhead of math.h. */ if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) > - ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn)) { - InstancePtr->MstStreamConfig[Stream - 1].MstPbn++; + ((double)InstancePtr->MstStreamConfig[Stream].MstPbn)) { + InstancePtr->MstStreamConfig[Stream].MstPbn++; } /* Calculate the average stream symbol time slots per MTP. */ Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw); MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 * - ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn / + ((double)InstancePtr->MstStreamConfig[Stream].MstPbn / LinkBw)); /* The target value to be found needs to follow the condition: @@ -826,7 +826,7 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) } /* Determine the PBN for the stream. */ - InstancePtr->MstStreamConfig[Stream - 1].MstPbn = + InstancePtr->MstStreamConfig[Stream].MstPbn = MsaConfig->TransferUnitSize * (LinkConfig->LaneCount * LinkConfig->LinkRate / 2); }