diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
index f624aa2f..e8acc360 100644
--- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
+++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_handoff.c
@@ -171,8 +171,9 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 			 * Release reset
 			 */
 			RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
+			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK |
+					CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
+					CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK);
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
 			/**
@@ -199,8 +200,9 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 			 * Release reset
 			 */
 			RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
+			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK |
+					CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
+					CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK);
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
 			/**
@@ -227,8 +229,10 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 			 * Release reset
 			 */
 			RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
+			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK |
+					CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
+					CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK);
+
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
 			/**
@@ -255,8 +259,10 @@ static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
 			 * Release reset
 			 */
 			RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK);
-			RegValue &= ~(CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK);
+			RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK |
+					CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
+					CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK);
+
 			XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
 
 			/**
diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
index 7e964c75..06ee54a6 100644
--- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
+++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
@@ -175,6 +175,11 @@ extern "C" {
 #define CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK    0X00000004U
 #define CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK    0X00000008U
 
+#define CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK    0X00002000U
+#define CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK    0X00001000U
+#define CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK    0X00000800U
+#define CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK    0X00000400U
+
 /* crl_apb */
 
 /**