diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd b/XilinxProcessorIPLib/drivers/dptx/data/dptx.mdd similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd rename to XilinxProcessorIPLib/drivers/dptx/data/dptx.mdd diff --git a/XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl b/XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl similarity index 100% rename from XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl rename to XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/index.html b/XilinxProcessorIPLib/drivers/dptx/examples/index.html new file mode 100755 index 00000000..b2e4baaa --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/index.html @@ -0,0 +1,20 @@ + + + + + +Driver example applications + + + +

Example applications for the dptx driver.

+
+ +

Copyright © 1995-2014 Xilinx, Inc. All rights reserved.

+ + diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/readme.txt b/XilinxProcessorIPLib/drivers/dptx/examples/readme.txt new file mode 100644 index 00000000..be07100a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dptx/examples/readme.txt @@ -0,0 +1,41 @@ +There are 4 examples included in this directory: +1) xdptx_intr_example.c : This interrupt example shows how to set up the + interrupt system and specify the interrupt handlers for when a DisplayPort + interrupt event occurs. An interrupt controller with a connection to the + DisplayPort interrupt signal needs to exist in the hardware system. + +2) xdptx_poll_example.c : This interrupt example shows how to poll the + DisplayPort TX instance's registers for DisplayPort interrupt events. + +3) xdptx_timer_example.c : This timer example shows how to override the default + sleep/delay functionality for MicroBlaze. A timer needs to exist in the + hardware system and will be used for sleep/delay functionality inside of a + callback function. The default behavior in MicroBlaze for sleep/delay is to + call MB_Sleep from microblaze_sleep.h, which has only millisecond accuracy. + For ARM/Zynq SoC systems, the supplied callback function will be ignored - + the usleep function will be called since the SoC has a timer built-in. + +4) xdptx_selftest_example.c : This self test example will perform a sanity check + on the state of the DisplayPort TX instance. It may be called prior to usage + of the core or after a reset to ensure that (a subset of) the registers hold + the default values. + +Each of these examples are meant to be used in conjunction with +xdptx_example_common.[ch] which holds common functionality for all examples. +After importing the examples, these files will need to be manually copied into +the example src/ directory. +This code shows how to train the main link and set up the + +Additionally, in order to be able to use the interrupt, polling, and timer +examples, the user will need to implement and link the following functions: +1) Dptx_InitPlatform : This function needs to do all hardware system + initialization. This function is invoked when calling +2) Dptx_ConfigureStreamSrc : This function needs to configure the source of the + stream (pattern generators, video input, etc.) such that a video stream, with + timings and video attributes that correspond to the main stream attributes + (MSA) configuration, is received by the DisplayPort Tx. The examples call + this function from the Dptx_Run->Dptx_StartVideoStream functions in + xdptx_example_common.c. + +Note: All example functions start with Dptx_*, while all driver functions start +with XDptx_*. diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c index ac6ec0d6..33e273cd 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c @@ -38,7 +38,11 @@ * the DisplayPort TX core by training the main link at the maximum common * capabilities between the TX and RX and checking the lane status. * - * @note The DisplayPort TX core does not work alone. Some platform + * @note The DisplayPort TX core does not work alone - video/audio + * sources need to be set up in the system correctly, as well as + * setting up the output path (for example, configuring the + * hardware system with the DisplayPort TX core output to an FMC + * card with DisplayPort output capabilities. Some platform * initialization will need to happen prior to calling XDptx driver * functions. See XAPP1178 as a reference. * @@ -59,26 +63,60 @@ /**************************** Function Prototypes *****************************/ -static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate); +static u32 Dptx_StartLink(XDptx *InstancePtr); static void Dptx_StartVideoStream(XDptx *InstancePtr); /**************************** Function Definitions ****************************/ -u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) +/******************************************************************************/ +/** + * This function will configure and establish a link with the receiver device, + * afterwards, a video stream will start to be sent over the main link. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param LaneCount is the number of lanes to use over the main link. + * @param LinkRate is the link rate to use over the main link. + * + * @return - XST_SUCCESS if main link was successfully established. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 Dptx_Run(XDptx *InstancePtr) { u32 Status; - Status = Dptx_StartLink(InstancePtr, LaneCount, LinkRate); + /* Configure and establish a link. */ + Status = Dptx_StartLink(InstancePtr); if (Status == XST_SUCCESS) { + /* Start the video stream. */ Dptx_StartVideoStream(InstancePtr); } else { - xil_printf("<-- Failed to train.\n"); + xil_printf("<-- Failed to establish/train the link.\n"); return XST_FAILURE; } return XST_SUCCESS; } +/******************************************************************************/ +/** + * This function will setup and initialize the DisplayPort TX core. The core's + * configuration parameters will be retrieved based on the configuration + * to the DisplayPort TX core instance with the specified device ID. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param DeviceId is the unique device ID of the DisplayPort TX core + * instance. + * + * @return - XST_SUCCESS if the device configuration was found and obtained + * and if the main link was successfully established. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) { XDptx_Config *ConfigPtr; @@ -89,6 +127,8 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) if (!ConfigPtr) { return XST_FAILURE; } + /* Copy the device configuration into the InstancePtr's Config + * structure. */ XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr); /* Initialize the DisplayPort TX core. */ @@ -100,28 +140,54 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId) return XST_SUCCESS; } -static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) +/******************************************************************************/ +/** + * This function will configure and establish a link with the receiver device. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return - XST_SUCCESS the if main link was successfully established. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 Dptx_StartLink(XDptx *InstancePtr) { u32 VsLevelTx; u32 PeLevelTx; u32 Status; + u8 LaneCount; + u8 LinkRate; - /* Obtain the capabilities of the sink by reading the monitor's DPCD. */ - Status = XDptx_GetSinkCapabilities(InstancePtr); + /* Obtain the capabilities of the RX device by reading the monitor's + * DPCD. */ + Status = XDptx_GetRxCapabilities(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#if defined(USE_MAX_LINK) - Status = XDptx_CheckLinkStatus(InstancePtr, - InstancePtr->LinkConfig.MaxLaneCount); +#if (TRAIN_USE_MAX_LINK == 1) + LaneCount = InstancePtr->LinkConfig.MaxLaneCount; + LinkRate = InstancePtr->LinkConfig.MaxLinkRate; #else - Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount); + LaneCount = TRAIN_USE_LANE_COUNT; + LinkRate = TRAIN_USE_LINK_RATE; #endif + + /* Check if the link is already trained */ + Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount); if (Status == XST_SUCCESS) { - xil_printf("-> Does not need training.\n"); - if (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, - XDPTX_LINK_BW_SET) == LinkRate) { + xil_printf("-> Link is already trained on %d lanes.\n", + LaneCount); + if (XDptx_ReadReg(InstancePtr->Config.BaseAddr, + XDPTX_LINK_BW_SET) == LinkRate) { + xil_printf("-> Link needs to be re-trained %d Mbps.\n", + (270 * LinkRate)); + } + else { + xil_printf("-> Link is already trained on %d Mbps.\n", + (270 * LinkRate)); return XST_SUCCESS; } } @@ -129,13 +195,18 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) xil_printf("-> Needs training.\n"); } else { + /* Either a connection does not exist or the supplied lane count + * is invalid. */ xil_printf("-> Error checking link status.\n"); return XST_FAILURE; } -#if defined(USE_MAX_LINK) - /* Configure the main link based on the common capabilities of the - * transmitter core and the sink monitor. */ + XDptx_SetEnhancedFrameMode(InstancePtr, 1); + XDptx_SetDownspread(InstancePtr, 0); + +#if (TRAIN_USE_MAX_LINK == 1) + /* Configure the main link based on the maximum common capabilities of + * the DisplayPort TX core and the receiver device. */ Status = XDptx_CfgMainLinkMax(InstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; @@ -143,10 +214,9 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) #else XDptx_SetLinkRate(InstancePtr, LinkRate); XDptx_SetLaneCount(InstancePtr, LaneCount); - XDptx_SetEnhancedFrameMode(InstancePtr, 1); - XDptx_SetDownspread(InstancePtr, 0); #endif + /* Train the link. */ xil_printf("******************************************\n"); Status = XDptx_EstablishLink(InstancePtr); if (Status != XST_SUCCESS) { @@ -154,11 +224,11 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) xil_printf("******************************************\n"); return XST_FAILURE; } - VsLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, - XDPTX_PHY_VOLTAGE_DIFF_LANE_0); - PeLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, - XDPTX_PHY_POSTCURSOR_LANE_0); + VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr, + XDPTX_PHY_VOLTAGE_DIFF_LANE_0); + PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr, + XDPTX_PHY_POSTCURSOR_LANE_0); xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n", InstancePtr->LinkConfig.LinkRate, InstancePtr->LinkConfig.LaneCount); @@ -170,6 +240,27 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate) return XST_SUCCESS; } +/******************************************************************************/ +/** + * This function will start sending a video stream over the main link. The + * settings to be used are as follows: + * - 8 bits per color. + * - Video timing and screen resolution used: + * - The connected monitor's preferred timing is used to determine the + * video resolution (and associated timings) for the stream. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Dptx_ConfigureStreamSrc is intentionally left for the user to + * implement since configuration of the stream source is + * application-specific. + * @note The Extended Display Identification Data (EDID) is read in order + * to obtain the video resolution and timings. If this read fails, + * a resolution of 640x480 is used at a refresh rate of 60Hz. + * +*******************************************************************************/ static void Dptx_StartVideoStream(XDptx *InstancePtr) { u32 Status; @@ -186,7 +277,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) * 2) Use a standard video timing mode (see mode_table.h): * XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P); * - * 3) Use a custom configuration for the main stream attributes: + * 3) Use a custom configuration for the main stream attributes (MSA): * XDptx_MainStreamAttributes MsaConfigCustom; * MsaConfigCustom.MVid = 108000; * MsaConfigCustom.HSyncPolarity = 0; @@ -204,8 +295,6 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) Status = XDptx_GetEdid(InstancePtr); if (Status == XST_SUCCESS) { XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr); - XDptx_CfgMsaUseStandardVideoMode(InstancePtr, - XDPTX_VM_640x480_60_P); } else { XDptx_CfgMsaUseStandardVideoMode(InstancePtr, @@ -215,21 +304,20 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr) /* Disable MST for this example. */ AuxData[0] = 0; XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData); - XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_TX_MST_CONFIG, - 0x0); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0); /* Disable main stream to force sending of IDLE patterns. */ XDptx_DisableMainLink(InstancePtr); /* Reset the transmitter. */ - XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK); - XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, 0x0); + XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0); /* Configure video stream source or generator here. This function needs * to be implemented in order for video to be displayed and is hardware * system specific. It is up to the user to implement this function. */ - Dptx_ConfigureVidgen(InstancePtr); + Dptx_ConfigureStreamSrc(InstancePtr); /*********************************/ XDptx_EnableMainLink(InstancePtr); diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h index dbea1824..3c4af098 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h @@ -38,7 +38,11 @@ * the DisplayPort TX core by training the main link at the maximum common * capabilities between the TX and RX and checking the lane status. * - * @note The DisplayPort TX core does not work alone. Some platform + * @note The DisplayPort TX core does not work alone - video/audio + * sources need to be set up in the system correctly, as well as + * setting up the output path (for example, configuring the + * hardware system with the DisplayPort TX core output to an FMC + * card with DisplayPort output capabilities. Some platform * initialization will need to happen prior to calling XDptx driver * functions. See XAPP1178 as a reference. * @@ -62,19 +66,61 @@ /**************************** Constant Definitions ****************************/ +/* The unique device ID of the DisplayPort TX core instance to be used with the + * examples.*/ +#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID + +/* If set to 1, the link training process will continue training despite failing + * by attempting training at a reduced link rate. It will also continue + * attempting to train the link at a reduced lane count if needed. With this + * option enabled, link training will return failure only when all link rate and + * lane count combinations have been exhausted - that is, training fails using + * 1-lane and a 1.62Gbps link rate. + * If set to 0, link training will return failure if the training failed using + * the current lane count and link rate settings. + * TRAIN_ADAPTIVE is used by the examples as input to the + * XDptx_EnableTrainAdaptive driver function. */ #define TRAIN_ADAPTIVE 1 + +/* A value of 1 is used to indicate that the DisplayPort output path has a + * redriver on the board that adjusts the voltage swing and pre-emphasis levels + * that are outputted from the FPGA. If this is the case, the voltage swing and + * pre-emphasis values supplied to the DisplayPort TX core will be evenly + * distributed among the available levels as specified in the IP documentation. + * Otherwise, a value of 0 is used to indicate that no redriver is present. In + * order to meet the necessary voltage swing and pre-emphasis levels required by + * a DisplayPort RX device, the level values specified to the DisplayPort TX + * core will require some compensation. + * TRAIN_HAS_REDRIVER is used by the examples as input to the + * XDptx_SetHasRedriverInPath driver function. + * Note: There are 16 possible voltage swing levels and 32 possible pre-emphasis + * levels in the DisplayPort TX core that will be mapped to 4 possible + * voltage swing and 4 possible pre-emphasis levels in the RX device. */ #define TRAIN_HAS_REDRIVER 1 -#define USE_MAX_LINK 1 -#define USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS -#define USE_LANE_COUNT 4 + +/* The link rate setting to begin link training with. Valid values are: + * XDPTX_LINK_BW_SET_540GBPS, XDPTX_LINK_BW_SET_270GBPS, and + * XDPTX_LINK_BW_SET_162GBPS. */ +#define TRAIN_USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS +/* The lane count setting to begin link training with. Valid values are: + * XDPTX_LANE_COUNT_SET_4, XDPTX_LANE_COUNT_SET_2, and + * XDPTX_LANE_COUNT_SET_1. */ +#define TRAIN_USE_LANE_COUNT XDPTX_LANE_COUNT_SET_4 +/* If set to 1, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will be ignored. + * Instead, the maximum common link capabilities between the DisplayPort TX core + * and the RX device will be used when establishing a link. + * If set to 0, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will determine the + * link rate and lane count settings that the link training process will begin + * with. */ +#define TRAIN_USE_MAX_LINK 1 /**************************** Function Prototypes *****************************/ extern u32 Dptx_PlatformInit(void); -extern u32 Dptx_ConfigureVidgen(XDptx *InstancePtr); +extern u32 Dptx_ConfigureStreamSrc(XDptx *InstancePtr); u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId); -u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate); +u32 Dptx_Run(XDptx *InstancePtr); /*************************** Variable Declarations ****************************/ diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c index 06089904..1bbd43b1 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c @@ -34,17 +34,19 @@ * * @file xdptx_intr_example.c * - * Contains a design example using the XDptx driver with interrupts. Upon hot- - * plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned - * on/off), the main link will be trained. + * Contains a design example using the XDptx driver with interrupts. Upon Hot- + * Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is + * turned on/off), the main link will be trained. * + * @note This example requires an interrupt controller connected to the + * processor and the DisplayPort TX core in the system. * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). - * See XAPP1178 for reference. - * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * input (Dptx_ConfigureStreamSrc - called in + * xdptx_example_common.c). See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are * declared extern in xdptx_example_common.h and are left up to the * user to implement. * @@ -65,44 +67,113 @@ #include "xil_printf.h" #include "xparameters.h" #include "xstatus.h" -#if defined(__MICROBLAZE__) +#ifdef XPAR_INTC_0_DEVICE_ID +/* For MicroBlaze systems. */ #include "xintc.h" -#elif defined(__arm__) -#include "xscugic.h" #else -#error "Unknown processor type." -#endif +/* For ARM/Zynq SoC systems. */ +#include "xscugic.h" +#endif /* XPAR_INTC_0_DEVICE_ID */ /**************************** Constant Definitions ****************************/ -#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID -#if defined(__MICROBLAZE__) +/* The following constants map to the XPAR parameters created in the + * xparameters.h file. */ +#ifdef XPAR_INTC_0_DEVICE_ID #define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID -#elif defined(__arm__) +#else #define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID -#endif +#endif /* XPAR_INTC_0_DEVICE_ID */ + +/****************************** Type Definitions ******************************/ + +/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system, + * different drivers and associated types will be used. */ +#ifdef XPAR_INTC_0_DEVICE_ID +#define INTC XIntc +#define INTC_HANDLER XIntc_InterruptHandler +#else +#define INTC XScuGic +#define INTC_HANDLER XScuGic_InterruptHandler +#endif /* XPAR_INTC_0_DEVICE_ID */ /**************************** Function Prototypes *****************************/ -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, - void *IntrHandler, u32 IntrId); -static void Dptx_InterruptHandler(XDptx *InstancePtr); +u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, + XDptx_HpdPulseHandler HpdPulseHandler); +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, + XDptx_HpdPulseHandler HpdPulseHandler); static void Dptx_HpdEventHandler(void *InstancePtr); static void Dptx_HpdPulseHandler(void *InstancePtr); /**************************** Variable Definitions ****************************/ -#if defined(__MICROBLAZE__) -static XIntc IntcInstance; -#elif defined(__arm__) -static XScuGic IntcInstance; -#endif +INTC IntcInstance; /* The interrupt controller instance. */ /**************************** Function Definitions ****************************/ +/******************************************************************************/ +/** + * This function is the main function of the XDptx interrupt example. If the + * DptxIntrExample function, which sets up the system succeeds, this function + * will wait for interrupts. Once a connection event or pulse is detected, link + * training will commence (if needed) and a video stream will start being sent + * over the main link. + * + * @param None. + * + * @return - XST_FAILURE if the interrupt example was unsuccessful - system + * setup failed. + * + * @note Unless setup failed, main will never return since + * DptxIntrExample is blocking (it is waiting on interrupts for + * Hot-Plug-Detect (HPD) events. + * +*******************************************************************************/ int main(void) +{ + /* Run the XDptx interrupt example. */ + Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID, + &IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID, + &Dptx_HpdEventHandler, &Dptx_HpdPulseHandler); + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * The main entry point for the interrupt example using the XDptx driver. This + * function will set up the system with interrupts and set up the Hot-Plug-Event + * (HPD) handlers. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param DeviceId is the unique device ID of the DisplayPort TX core + * instance. + * @param IntcPtr is a pointer to the interrupt instance. + * @param IntrId is the unique device ID of the interrupt controller. + * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to + * the interrupt controller. + * @param HpdEventHandler is a pointer to the handler called when an HPD + * event occurs. + * @param HpdPulseHandler is a pointer to the handler called when an HPD + * pulse occurs. + * + * @return - XST_FAILURE if the system setup failed. + * - XST_SUCCESS should never return since this function, if setup + * was successful, is blocking. + * + * @note If system setup was successful, this function is blocking in + * order to illustrate interrupt handling taking place for HPD + * events. + * +*******************************************************************************/ +u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, + XDptx_HpdPulseHandler HpdPulseHandler) { u32 Status; @@ -111,135 +182,168 @@ int main(void) Dptx_PlatformInit(); /******************/ - Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + Status = Dptx_SetupExample(InstancePtr, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#if defined(TRAIN_ADAPTIVE) - XDptx_EnableTrainAdaptive(&DptxInstance, 1); -#else - XDptx_EnableTrainAdaptive(&DptxInstance, 0); -#endif -#if defined(TRAIN_HAS_REDRIVER) - XDptx_SetHasRedriverInPath(&DptxInstance, 1); -#else - XDptx_SetHasRedriverInPath(&DptxInstance, 0); -#endif + XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); /* Setup interrupt handling in the system. */ - Status = Dptx_SetupInterruptHandler(&DptxInstance, - &Dptx_InterruptHandler, DP_INTERRUPT_ID); + Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId, + DpIntrId, HpdEventHandler, HpdPulseHandler); if (Status != XST_SUCCESS) { return XST_FAILURE; } - /* Do not return in order to allow interrupt handling to run. */ + /* Do not return in order to allow interrupt handling to run. HPD events + * (connect, disconnect, and pulse) will be detected and handled. */ while (1); + return XST_SUCCESS; } -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, - void *IntrHandler, u32 IntrId) +/******************************************************************************/ +/** + * This function sets up the interrupt system such that interrupts caused by + * Hot-Plug-Detect (HPD) events and pulses are handled. This function is + * application-specific for systems that have an interrupt controller connected + * to the processor. The user should modify this function to fit the + * application. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param IntcPtr is a pointer to the interrupt instance. + * @param IntrId is the unique device ID of the interrupt controller. + * @param DpIntrId is the interrupt ID of the DisplayPort TX connection to + * the interrupt controller. + * @param HpdEventHandler is a pointer to the handler called when an HPD + * event occurs. + * @param HpdPulseHandler is a pointer to the handler called when an HPD + * pulse occurs. + * + * @return - XST_SUCCESS if the interrupt system was successfully set up. + * - XST_FAILURE otherwise. + * + * @note An interrupt controller must be present in the system, connected + * to the processor and the DisplayPort TX core. + * +*******************************************************************************/ +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr, + u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler, + XDptx_HpdPulseHandler HpdPulseHandler) { u32 Status; -#if defined(__arm__) - XScuGic_Config *IntcConfig; -#endif /* Set the HPD interrupt handlers. */ - XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler, - InstancePtr); - XDptx_SetHpdPulseHandler(InstancePtr, &Dptx_HpdPulseHandler, - InstancePtr); + XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr); + XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr); /* Initialize interrupt controller driver. */ -#if defined(__MICROBLAZE__) - Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID); +#ifdef XPAR_INTC_0_DEVICE_ID + Status = XIntc_Initialize(IntcPtr, IntrId); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#elif defined(__arm__) - IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); - Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig, +#else + XScuGic_Config *IntcConfig; + + IntcConfig = XScuGic_LookupConfig(IntrId); + Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } - XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1); -#endif + XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1); +#endif /* XPAR_INTC_0_DEVICE_ID */ /* Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ -#if defined(__MICROBLAZE__) - Status = XIntc_Connect(&IntcInstance, IntrId, - (XInterruptHandler)IntrHandler, InstancePtr); -#elif defined(__arm__) - Status = XScuGic_Connect(&IntcInstance, IntrId, - (Xil_InterruptHandler)IntrHandler, InstancePtr); -#endif +#ifdef XPAR_INTC_0_DEVICE_ID + Status = XIntc_Connect(IntcPtr, DpIntrId, + (XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); +#else + Status = XScuGic_Connect(IntcPtr, DpIntrId, + (Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); +#endif /* XPAR_INTC_0_DEVICE_ID */ if (Status != XST_SUCCESS) { return XST_FAILURE; } /* Start the interrupt controller. */ -#if defined(__MICROBLAZE__) - Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE); +#ifdef XPAR_INTC_0_DEVICE_ID + Status = XIntc_Start(IntcPtr, XIN_REAL_MODE); if (Status != XST_SUCCESS) { return XST_FAILURE; } - XIntc_Enable(&IntcInstance, IntrId); -#elif defined(__arm__) - XScuGic_Enable(&IntcInstance, IntrId); -#endif + XIntc_Enable(IntcPtr, DpIntrId); +#else + XScuGic_Enable(IntcPtr, DpIntrId); +#endif /* XPAR_INTC_0_DEVICE_ID */ /* Initialize the exception table. */ Xil_ExceptionInit(); /* Register the interrupt controller handler with the exception table. */ -#if defined(__MICROBLAZE__) Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance); -#elif defined(__arm__) - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, - (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance); -#endif + (Xil_ExceptionHandler)INTC_HANDLER, IntcPtr); /* Enable exceptions. */ Xil_ExceptionEnable(); -#if defined(__MICROBLAZE__) - /* Enable interrupts in the MicroBlaze processor. */ - microblaze_enable_interrupts(); -#endif - return XST_SUCCESS; } -static void Dptx_InterruptHandler(XDptx *InstancePtr) -{ - XDptx_HpdInterruptHandler(InstancePtr); -} - +/******************************************************************************/ +/** + * This function is called when a Hot-Plug-Detect (HPD) event is received by the + * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the + * core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has + * occurred. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetHpdEventHandler driver function to set this + * function as the handler for HPD pulses. + * +*******************************************************************************/ static void Dptx_HpdEventHandler(void *InstancePtr) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; if (XDptx_IsConnected(XDptx_InstancePtr)) { xil_printf("+===> HPD connection event detected.\n"); - Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + + Dptx_Run(XDptx_InstancePtr); } else { xil_printf("+===> HPD disconnection event detected.\n\n"); } } +/******************************************************************************/ +/** + * This function is called when a Hot-Plug-Detect (HPD) pulse is received by the + * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit + * of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has + * occurred. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetHpdPulseHandler driver function to set this + * function as the handler for HPD pulses. + * +*******************************************************************************/ static void Dptx_HpdPulseHandler(void *InstancePtr) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; xil_printf("===> HPD pulse detected.\n"); - Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + Dptx_Run(XDptx_InstancePtr); } diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c index 769fb936..3db9d1a6 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c @@ -34,10 +34,13 @@ * * @file xdptx_intr_timer_example.c * - * Contains a design example using the XDptx driver with interrupts. Upon hot- - * plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned - * on/off), the main link will be trained. + * Contains a design example using the XDptx driver with interrupts and. Upon Hot- + * Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is + * turned on/off), the main link will be trained. * + * @note This example requires an interrupt controller connected to the + * processor and the DisplayPort TX core in the system. + * @note This example requires an AXI timer in the system. * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video @@ -66,30 +69,41 @@ #include "xparameters.h" #include "xstatus.h" #include "xtmrctr.h" -#if defined(__MICROBLAZE__) +#ifdef XPAR_INTC_0_DEVICE_ID +/* For MicroBlaze systems. */ #include "xintc.h" -#elif defined(__arm__) -#include "xscugic.h" #else -#error "Unknown processor type." -#endif +/* For ARM/Zynq SoC systems. */ +#include "xscugic.h" +#endif /* XPAR_INTC_0_DEVICE_ID */ /**************************** Constant Definitions ****************************/ -#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID -#if defined(__MICROBLAZE__) +/* The following constants map to the XPAR parameters created in the + * xparameters.h file. */ +#ifdef XPAR_INTC_0_DEVICE_ID #define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR #define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID -#elif defined(__arm__) +#else #define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID -#endif +#endif /* XPAR_INTC_0_DEVICE_ID */ + +/****************************** Type Definitions ******************************/ + +/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system, + * different drivers and associated types will be used. */ +#ifdef XPAR_INTC_0_DEVICE_ID +#define INTC XIntc +#define INTC_HANDLER XIntc_InterruptHandler +#else +#define INTC XScuGic +#define INTC_HANDLER XScuGic_InterruptHandler +#endif /* XPAR_INTC_0_DEVICE_ID */ /**************************** Function Prototypes *****************************/ -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, - void *IntrHandler, u32 IntrId); -static void Dptx_InterruptHandler(XDptx *InstancePtr); +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr); static void Dptx_HpdEventHandler(void *InstancePtr); static void Dptx_HpdPulseHandler(void *InstancePtr); @@ -97,12 +111,8 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); /**************************** Variable Definitions ****************************/ -#if defined(__MICROBLAZE__) -XIntc IntcInstance; -#elif defined(__arm__) -XScuGic IntcInstance; -#endif -XTmrCtr TimerCounterInst; +INTC IntcInstance; /* The interrupt controller instance. */ +XTmrCtr TimerCounterInst; /* The timer counter instance. */ /**************************** Function Definitions ****************************/ @@ -115,8 +125,12 @@ int main(void) Dptx_PlatformInit(); /******************/ - /* Set a custom timer handler for improved delay accuracy. - * Note: This only has an affect for MicroBlaze systems. */ + /* Set a custom timer handler for improved delay accuracy on MicroBlaze + * systems since the driver does not assume/have a dependency on the + * system having a timer in the FPGA. + * Note: This only has an affect for MicroBlaze systems since the Zynq + * SoC contains a timer, which is used when the driver calls the sleep + * function. */ XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs, &TimerCounterInst); @@ -125,20 +139,11 @@ int main(void) return XST_FAILURE; } -#if defined(TRAIN_ADAPTIVE) - XDptx_EnableTrainAdaptive(&DptxInstance, 1); -#else - XDptx_EnableTrainAdaptive(&DptxInstance, 0); -#endif -#if defined(TRAIN_HAS_REDRIVER) - XDptx_SetHasRedriverInPath(&DptxInstance, 1); -#else - XDptx_SetHasRedriverInPath(&DptxInstance, 0); -#endif + XDptx_EnableTrainAdaptive(&DptxInstance, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(&DptxInstance, TRAIN_HAS_REDRIVER); /* Setup interrupt handling in the system. */ - Status = Dptx_SetupInterruptHandler(&DptxInstance, - &Dptx_InterruptHandler, DP_INTERRUPT_ID); + Status = Dptx_SetupInterruptHandler(&DptxInstance); if (Status != XST_SUCCESS) { return XST_FAILURE; } @@ -148,13 +153,26 @@ int main(void) return XST_SUCCESS; } -static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, - void *IntrHandler, u32 IntrId) +/******************************************************************************/ +/** + * This function sets up the interrupt system such that interrupts caused by + * Hot-Plug-Detect (HPD) events and pulses are handled. This function is + * application-specific for systems that have an interrupt controller connected + * to the processor. The user should modify this function to fit the + * application. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return - XST_SUCCESS if the interrupt system was successfully set up. + * - XST_FAILURE otherwise. + * + * @note An interrupt controller must be present in the system, connected + * to the processor and the DisplayPort TX core. + * +*******************************************************************************/ +static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr) { u32 Status; -#if defined(__arm__) - XScuGic_Config *IntcConfig; -#endif /* Set the HPD interrupt handlers. */ XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler, @@ -163,96 +181,133 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, InstancePtr); /* Initialize interrupt controller driver. */ -#if defined(__MICROBLAZE__) +#ifdef XPAR_INTC_0_DEVICE_ID Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#elif defined(__arm__) +#else + XScuGic_Config *IntcConfig; + IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig, IntcConfig->CpuBaseAddress); if (Status != XST_SUCCESS) { return XST_FAILURE; } - XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1); -#endif + XScuGic_SetPriorityTriggerType(&IntcInstance, DP_INTERRUPT_ID, + 0xA0, 0x1); +#endif /* XPAR_INTC_0_DEVICE_ID */ /* Connect the device driver handler that will be called when an * interrupt for the device occurs, the handler defined above performs * the specific interrupt processing for the device. */ -#if defined(__MICROBLAZE__) - Status = XIntc_Connect(&IntcInstance, IntrId, - (XInterruptHandler)IntrHandler, InstancePtr); -#elif defined(__arm__) - Status = XScuGic_Connect(&IntcInstance, IntrId, - (Xil_InterruptHandler)IntrHandler, InstancePtr); -#endif +#ifdef XPAR_INTC_0_DEVICE_ID + Status = XIntc_Connect(&IntcInstance, DP_INTERRUPT_ID, + (XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); +#else + Status = XScuGic_Connect(&IntcInstance, DP_INTERRUPT_ID, + (Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr); +#endif /* XPAR_INTC_0_DEVICE_ID */ if (Status != XST_SUCCESS) { return XST_FAILURE; } /* Start the interrupt controller. */ -#if defined(__MICROBLAZE__) +#ifdef XPAR_INTC_0_DEVICE_ID Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE); if (Status != XST_SUCCESS) { return XST_FAILURE; } - XIntc_Enable(&IntcInstance, IntrId); -#elif defined(__arm__) - XScuGic_Enable(&IntcInstance, IntrId); -#endif + XIntc_Enable(&IntcInstance, DP_INTERRUPT_ID); +#else + XScuGic_Enable(&IntcInstance, DP_INTERRUPT_ID); +#endif /* XPAR_INTC_0_DEVICE_ID */ /* Initialize the exception table. */ Xil_ExceptionInit(); /* Register the interrupt controller handler with the exception table. */ -#if defined(__MICROBLAZE__) Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance); -#elif defined(__arm__) - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, - (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance); -#endif + (Xil_ExceptionHandler)INTC_HANDLER, &IntcInstance); /* Enable exceptions. */ Xil_ExceptionEnable(); -#if defined(__MICROBLAZE__) - /* Enable interrupts in the MicroBlaze processor. */ - microblaze_enable_interrupts(); -#endif - return XST_SUCCESS; } -static void Dptx_InterruptHandler(XDptx *InstancePtr) -{ - XDptx_HpdInterruptHandler(InstancePtr); -} - +/******************************************************************************/ +/** + * This function is called when a Hot-Plug-Detect (HPD) event is received by the + * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the + * core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has + * occurred. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetHpdEventHandler driver function to set this + * function as the handler for HPD pulses. + * +*******************************************************************************/ static void Dptx_HpdEventHandler(void *InstancePtr) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; if (XDptx_IsConnected(XDptx_InstancePtr)) { xil_printf("+===> HPD connection event detected.\n"); - Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + + Dptx_Run(XDptx_InstancePtr); } else { xil_printf("+===> HPD disconnection event detected.\n\n"); } } +/******************************************************************************/ +/** + * This function is called when a Hot-Plug-Detect (HPD) pulse is received by the + * DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit + * of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has + * occurred. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetHpdPulseHandler driver function to set this + * function as the handler for HPD pulses. + * +*******************************************************************************/ static void Dptx_HpdPulseHandler(void *InstancePtr) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; xil_printf("===> HPD pulse detected.\n"); - Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + Dptx_Run(XDptx_InstancePtr); } +/******************************************************************************/ +/** + * This function is used to override the driver's default sleep functionality. + * For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior + * is to use the MB_Sleep function from microblaze_sleep.h, which is implemented + * in software and only has millisecond accuracy. For this reason, using a + * hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is + * used - XDptx_WaitUs will ignore this custom timer handler. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetUserTimerHandler driver function to set this + * function as the handler for when the XDptx_WaitUs driver + * function is called. + * +*******************************************************************************/ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; @@ -265,7 +320,7 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0); } while (TimerVal < (MicroSeconds * - (XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000))); + (XDptx_InstancePtr->Config.SAxiClkHz / 1000000))); XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0); } diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c index a6b35eb2..2a6f2c56 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c @@ -35,16 +35,16 @@ * @file xdptx_poll_example.c * * Contains a design example using the XDptx driver with polling. Once the - * polling detects a hot-plug-detect event (DisplayPort cable is plugged/ + * polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/ * unplugged or the monitor is turned on/off), the main link will be trained. * * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). - * See XAPP1178 for reference. - * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * input (Dptx_ConfigureStreamSrc - called in + * xdptx_example_common.c). See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are * declared extern in xdptx_example_common.h and are left up to the * user to implement. * @@ -62,20 +62,60 @@ #include "xdptx.h" #include "xdptx_example_common.h" +#include "xil_printf.h" #include "xparameters.h" #include "xstatus.h" -/**************************** Constant Definitions ****************************/ - -#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID - /**************************** Function Prototypes *****************************/ +u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId); static void Dptx_HpdPoll(XDptx *InstancePtr); /**************************** Function Definitions ****************************/ +/******************************************************************************/ +/** + * This function is the main function of the XDptx polling example. + * + * @param None. + * + * @return - XST_FAILURE if the polling example was unsuccessful - system + * setup failed. + * + * @note Unless setup failed, main will never return since + * Dptx_PollExample is blocking (it is continuously polling for + * Hot-Plug-Detect (HPD) events. + * +*******************************************************************************/ int main(void) +{ + /* Run the XDptx polling example. */ + Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID); + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * The main entry point for the polling example using the XDptx driver. This + * function will set up the system. If this is successful, this example will + * begin polling the Hot-Plug-Detect (HPD) status registers for HPD events. Once + * a connection event or a pulse is detected, link training will commence (if + * needed) and a video stream will start being sent over the main link. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param DeviceId is the unique device ID of the DisplayPort TX core + * instance. + * + * @return - XST_FAILURE if the system setup failed. + * - XST_SUCCESS should never return since this function, if setup + * was successful, is blocking. + * + * @note If system setup was successful, this function is blocking in + * order to illustrate polling taking place for HPD events. + * +*******************************************************************************/ +u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId) { u32 Status; @@ -84,31 +124,36 @@ int main(void) Dptx_PlatformInit(); /******************/ - Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + Status = Dptx_SetupExample(InstancePtr, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#if defined(TRAIN_ADAPTIVE) - XDptx_EnableTrainAdaptive(&DptxInstance, 1); -#else - XDptx_EnableTrainAdaptive(&DptxInstance, 0); -#endif -#if defined(TRAIN_HAS_REDRIVER) - XDptx_SetHasRedriverInPath(&DptxInstance, 1); -#else - XDptx_SetHasRedriverInPath(&DptxInstance, 0); -#endif + XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); - /* A receiver must be connected at this point. */ + /* Continuously poll for HPD events. */ while (1) { - /* Continuously poll for HPD events. */ - Dptx_HpdPoll(&DptxInstance); + Dptx_HpdPoll(InstancePtr); } return XST_SUCCESS; } +/******************************************************************************/ +/** + * This function polls the XDPTX_INTERRUPT_SIG_STATE and XDPTX_INTERRUPT_STATUS + * registers for Hot-Plug-Detect (HPD) events and handles them accordingly. If a + * connection or pulse event is detected, link training will begin (if required) + * and a video stream will be initiated. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ static void Dptx_HpdPoll(XDptx *InstancePtr) { u32 InterruptSignalState; @@ -119,9 +164,9 @@ static void Dptx_HpdPoll(XDptx *InstancePtr) u32 HpdDuration; /* Read interrupt registers. */ - InterruptSignalState = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_SIG_STATE); - InterruptStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, + InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_INTERRUPT_STATUS); /* Check for HPD events. */ @@ -131,7 +176,8 @@ static void Dptx_HpdPoll(XDptx *InstancePtr) HpdPulseDetected = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK; if (HpdPulseDetected) { - HpdDuration = XDptx_ReadReg(InstancePtr, XDPTX_HPD_DURATION); + HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr, + XDPTX_HPD_DURATION); } /* HPD event handling. */ @@ -139,13 +185,13 @@ static void Dptx_HpdPoll(XDptx *InstancePtr) xil_printf("+===> HPD connection event detected.\n"); /* Initiate link training. */ - Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE); + Dptx_Run(InstancePtr); } else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) { xil_printf("===> HPD pulse detected.\n"); /* Re-train if needed. */ - Dptx_Run(InstancePtr, USE_LANE_COUNT, USE_LINK_RATE); + Dptx_Run(InstancePtr); } else if (!HpdState && HpdEvent) { xil_printf("+===> HPD disconnection event detected.\n\n"); diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c index b0b01fdb..6833c05b 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c @@ -56,13 +56,9 @@ #include "xparameters.h" #include "xstatus.h" -/**************************** Constant Definitions ****************************/ - -#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID - /**************************** Function Prototypes *****************************/ -static u32 Dptx_SelfTestExample(u16 DeviceId); +u32 Dptx_SelfTestExample(u16 DeviceId); /**************************** Function Definitions ****************************/ @@ -79,7 +75,7 @@ int main(void) return Status; } -static u32 Dptx_SelfTestExample(u16 DeviceId) +u32 Dptx_SelfTestExample(u16 DeviceId) { u32 Status; @@ -88,16 +84,8 @@ static u32 Dptx_SelfTestExample(u16 DeviceId) return XST_FAILURE; } -#if defined(TRAIN_ADAPTIVE) - XDptx_EnableTrainAdaptive(&DptxInstance, 1); -#else - XDptx_EnableTrainAdaptive(&DptxInstance, 0); -#endif -#if defined(TRAIN_HAS_REDRIVER) - XDptx_SetHasRedriverInPath(&DptxInstance, 1); -#else - XDptx_SetHasRedriverInPath(&DptxInstance, 0); -#endif + XDptx_EnableTrainAdaptive(&DptxInstance, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(&DptxInstance, TRAIN_HAS_REDRIVER); /* Run the self test. */ Status = XDptx_SelfTest(&DptxInstance); diff --git a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c index 12f0d8e8..bee81a05 100644 --- a/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c +++ b/XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c @@ -40,13 +40,14 @@ * the user may override the default MicroBlaze sleep with a function that will * use the hardware timer. * + * @note This example requires an AXI timer in the system. * @note For this example to display output, the user will need to * implement initialization of the system (Dptx_PlatformInit) and, * after training is complete, implement configuration of the video * stream source in order to provide the DisplayPort core with - * input (Dptx_ConfigureVidgen - called in xdptx_example_common.c). - * See XAPP1178 for reference. - * @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are + * input (Dptx_ConfigureStreamSrc - called in + * xdptx_example_common.c). See XAPP1178 for reference. + * @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are * declared extern in xdptx_example_common.h and are left up to the * user to implement. * @@ -64,25 +65,71 @@ #include "xdptx.h" #include "xdptx_example_common.h" +#include "xil_printf.h" #include "xparameters.h" #include "xstatus.h" #include "xtmrctr.h" -/**************************** Constant Definitions ****************************/ - -#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID - /**************************** Function Prototypes *****************************/ +u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, + XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc); static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds); /*************************** Variable Declarations ****************************/ -XTmrCtr TimerCounterInst; +XTmrCtr TimerCounterInst; /* The timer counter instance. */ /**************************** Function Definitions ****************************/ +/******************************************************************************/ +/** + * This function is the main function of the XDptx timer example. + * + * @param None. + * + * @return - XST_SUCCESS if the timer example finished successfully. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ int main(void) +{ + int Status; + + /* Run the XDptx timer example. */ + Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID, + &TimerCounterInst, &Dptx_CustomWaitUs); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * The main entry point for the timer example using the XDptx driver. This + * function will set up the system and the custom sleep handler. If this is + * successful, link training will commence and a video stream will start being + * sent over the main link. + * + * @param InstancePtr is a pointer to the XDptx instance. + * @param DeviceId is the unique device ID of the DisplayPort TX core + * instance. + * @param TimerCounterPtr is a pointer to the timer instance. + * @param UserSleepFunc is a pointer to the custom handler for sleep. + * + * @return - XST_SUCCESS if the system was set up correctly and link + * training was successful. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId, + XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc) { u32 Status; @@ -91,35 +138,50 @@ int main(void) Dptx_PlatformInit(); /*******************/ - /* Set a custom timer handler for improved delay accuracy. - * Note: This only has an affect for MicroBlaze systems. */ - XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs, - &TimerCounterInst); + /* Set a custom timer handler for improved delay accuracy on MicroBlaze + * systems since the driver does not assume/have a dependency on the + * system having a timer in the FPGA. + * Note: This only has an affect for MicroBlaze systems since the Zynq + * ARM SoC contains a timer, which is used when the driver calls the + * delay function. */ + XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr); - Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID); + Status = Dptx_SetupExample(InstancePtr, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } -#if defined(TRAIN_ADAPTIVE) - XDptx_EnableTrainAdaptive(&DptxInstance, 1); -#else - XDptx_EnableTrainAdaptive(&DptxInstance, 0); -#endif -#if defined(TRAIN_HAS_REDRIVER) - XDptx_SetHasRedriverInPath(&DptxInstance, 1); -#else - XDptx_SetHasRedriverInPath(&DptxInstance, 0); -#endif + XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE); + XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER); - /* A receiver must be connected at this point. */ - Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE); + /* A sink monitor must be connected at this point. See the polling or + * interrupt examples for how to wait for a connection event. */ + Status = Dptx_Run(InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } - /* Do not return in order to keep the program running. */ - while (1); return XST_SUCCESS; } +/******************************************************************************/ +/** + * This function is used to override the driver's default sleep functionality. + * For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior + * is to use the MB_Sleep function from microblaze_sleep.h, which is implemented + * in software and only has millisecond accuracy. For this reason, using a + * hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is + * used - XDptx_WaitUs will ignore this custom timer handler. + * + * @param InstancePtr is a pointer to the XDptx instance. + * + * @return None. + * + * @note Use the XDptx_SetUserTimerHandler driver function to set this + * function as the handler for when the XDptx_WaitUs driver + * function is called. + * +*******************************************************************************/ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) { XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr; @@ -132,7 +194,7 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds) TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0); } while (TimerVal < (MicroSeconds * - (XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000))); + (XDptx_InstancePtr->Config.SAxiClkHz / 1000000))); XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0); } diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c index 80324941..e8663b9d 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.c @@ -34,9 +34,11 @@ * * @file xdptx.c * - * Contains a minimal wset of functions for the XDptx driver that allow access - * to all the DisplayPort transmitter's functionality. See xdptx.h for a - * detailed description of the driver. + * Contains a minimal set of functions for the XDptx driver that allow access + * to all of the DisplayPort TX core's functionality. See xdptx.h for a detailed + * description of the driver. + * + * @note None. * *
  * MODIFICATION HISTORY:
@@ -61,9 +63,15 @@
 
 /**************************** Constant Definitions ****************************/
 
+/**
+ * The maximum voltage swing and pre-emphasis level is 3.
+ */
 #define XDPTX_MAXIMUM_VS_LEVEL 3
 #define XDPTX_MAXIMUM_PE_LEVEL 3
 
+/**
+ * Error out if an AUX transactions exceeds these defer or timeout values.
+ */
 #define XDPTX_AUX_MAX_DEFER_COUNT 50
 #define XDPTX_AUX_MAX_TIMEOUT_COUNT 50
 
@@ -131,56 +139,56 @@ static u32 XDptx_WaitPhyReady(XDptx *InstancePtr);
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if the DisplayPort TX core was successfully
+ * @return      - XST_SUCCESS if the DisplayPort TX core was successfully
  *                initialized.
- *              - XST_INVALID_PARAM if the supplied link rate does not
- *                correspond to either 1.62, 2.70, or 5.40 Gbps.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_InitializeTx(XDptx *InstancePtr)
 {
         u32 Status;
         u32 RegVal;
-        XDptx_Config *TxConfig = &InstancePtr->TxConfig;
+        XDptx_Config *Config = &InstancePtr->Config;
 
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
+        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
         /* Place the PHY (and GTTXRESET) into reset. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CONFIG,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
                                         XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK);
 
-        /* Disable the transmitter. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_ENABLE, 0);
+        /* Disable the DisplayPort TX core. */
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 0);
 
         /* Set the clock divider. */
-        RegVal = (XDptx_ReadReg(TxConfig->BaseAddr, XDPTX_AUX_CLK_DIVIDER) &
+        RegVal = (XDptx_ReadReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER) &
                                         ~XDPTX_AUX_CLK_DIVIDER_VAL_MASK) |
-                                        (TxConfig->SAxiClkHz / 1000000);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal);
+                                        (Config->SAxiClkHz / 1000000);
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_AUX_CLK_DIVIDER, RegVal);
 
-        /* Set the transmitter's clock speed. */
-        switch (TxConfig->MaxLinkRate) {
+        /* Set the DisplayPort TX core's clock speed. */
+        switch (Config->MaxLinkRate) {
         case XDPTX_LINK_BW_SET_540GBPS:
-                XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+                XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
                                                 XDPTX_PHY_CLOCK_SELECT_540GBPS);
                 break;
         case XDPTX_LINK_BW_SET_270GBPS:
-                XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+                XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
                                                 XDPTX_PHY_CLOCK_SELECT_270GBPS);
                 break;
         case XDPTX_LINK_BW_SET_162GBPS:
-                XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
+                XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CLOCK_SELECT,
                                                 XDPTX_PHY_CLOCK_SELECT_162GBPS);
                 break;
         default:
-                return XST_INVALID_PARAM;
+                break;
         }
 
         /* Bring the PHY (and GTTXRESET) out of reset. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_PHY_CONFIG,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_PHY_CONFIG,
                                         XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
 
         /* Wait for the PHY to be ready. */
@@ -189,11 +197,11 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
                 return XST_FAILURE;
         }
 
-        /* Enable the transmitter. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_ENABLE, 1);
+        /* Enable the DisplayPort TX core. */
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_ENABLE, 1);
 
-        /* Unmask hot-plug-detect (HPD) interrupts. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INTERRUPT_MASK,
+        /* Unmask Hot-Plug-Detect (HPD) interrupts. */
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_INTERRUPT_MASK,
                                 ~XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
                                 ~XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK &
                                 ~XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK);
@@ -204,7 +212,7 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
 /******************************************************************************/
 /**
  * This function retrieves the configuration for this DisplayPort TX instance
- * and fills in the InstancePtr->TxConfig structure.
+ * and fills in the InstancePtr->Config structure.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       ConfigPtr is a pointer to the configuration structure that will
@@ -213,6 +221,8 @@ u32 XDptx_InitializeTx(XDptx *InstancePtr)
  *              space. If the address translation is not used, then the physical
  *              address is passed.
  *
+ * @return      None.
+ *
  * @note        Unexpected errors may occur if the address mapping is changed
  *              after this function is invoked.
  *
@@ -227,40 +237,46 @@ void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
 
         InstancePtr->IsReady = 0;
 
-        InstancePtr->TxConfig.DeviceId = ConfigPtr->DeviceId;
-        InstancePtr->TxConfig.BaseAddr = EffectiveAddr;
-        InstancePtr->TxConfig.SAxiClkHz = ConfigPtr->SAxiClkHz;
+        InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+        InstancePtr->Config.BaseAddr = EffectiveAddr;
+        InstancePtr->Config.SAxiClkHz = ConfigPtr->SAxiClkHz;
 
-        InstancePtr->TxConfig.MaxLinkRate = ConfigPtr->MaxLinkRate;
-        InstancePtr->TxConfig.MaxLaneCount = ConfigPtr->MaxLaneCount;
+        InstancePtr->Config.MaxLinkRate = ConfigPtr->MaxLinkRate;
+        InstancePtr->Config.MaxLaneCount = ConfigPtr->MaxLaneCount;
 
         InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 }
 
 /******************************************************************************/
 /**
- * This function retrieves sink device capabilities from the receiver's DPCD.
+ * This function retrieves the RX device's capabilities from the RX device's
+ * DisplayPort Configuration Data (DPCD).
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return      
- *              - XST_SUCCESS if the DPCD was read successfully.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
+ * @return      - XST_SUCCESS if the DisplayPort Configuration Data was read
+ *                successfully.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
-u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr)
+u32 XDptx_GetRxCapabilities(XDptx *InstancePtr)
 {
         u32 Status;
         u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
         XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
-        XDptx_Config *TxConfig = &InstancePtr->TxConfig;
+        XDptx_Config *Config = &InstancePtr->Config;
         u8 RxMaxLinkRate;
         u8 RxMaxLaneCount;
 
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid(Dpcd != NULL);
+        Xil_AssertNonvoid(LinkConfig != NULL);
+        Xil_AssertNonvoid(Config != NULL);
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
@@ -275,10 +291,10 @@ u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr)
         RxMaxLinkRate = Dpcd[XDPTX_DPCD_MAX_LINK_RATE];
         RxMaxLaneCount = Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
                                         XDPTX_DPCD_MAX_LANE_COUNT_MASK;
-        LinkConfig->MaxLinkRate = (RxMaxLinkRate > TxConfig->MaxLinkRate) ?
-                        TxConfig->MaxLinkRate : RxMaxLinkRate;
-        LinkConfig->MaxLaneCount = (RxMaxLaneCount > TxConfig->MaxLaneCount) ?
-                                        TxConfig->MaxLaneCount : RxMaxLaneCount;
+        LinkConfig->MaxLinkRate = (RxMaxLinkRate > Config->MaxLinkRate) ?
+                        Config->MaxLinkRate : RxMaxLinkRate;
+        LinkConfig->MaxLaneCount = (RxMaxLaneCount > Config->MaxLaneCount) ?
+                                        Config->MaxLaneCount : RxMaxLaneCount;
 
         LinkConfig->SupportEnhancedFramingMode =
                                         Dpcd[XDPTX_DPCD_MAX_LANE_COUNT] &
@@ -292,15 +308,29 @@ u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr)
 
 /******************************************************************************/
 /**
- * This function retrieves the receiver's EDID.
+ * This function retrieves the RX device's Extended Display Identification Data
+ * (EDID).
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      - XST_SUCCESS if the I2C transactions to read the EDID were
+ *                successful.
+ *              - XST_ERROR_COUNT_MAX if the EDID read request timed out.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
+ *              - XST_FAILURE otherwise.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_GetEdid(XDptx *InstancePtr)
 {
         u32 Status;
 
+        /* Verify arguments. */
+        Xil_AssertNonvoid(InstancePtr != NULL);
+        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid(InstancePtr->RxConfig.Edid != NULL);
+
         Status = XDptx_IicRead(InstancePtr, XDPTX_EDID_ADDR, 0, XDPTX_EDID_SIZE,
                                                 InstancePtr->RxConfig.Edid);
         if (Status != XST_SUCCESS) {
@@ -313,17 +343,16 @@ u32 XDptx_GetEdid(XDptx *InstancePtr)
 /******************************************************************************/
 /**
  * This function determines the common capabilities between the DisplayPort TX
- * core and the receiver.
+ * core and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return      
- *              - XST_SUCCESS if main link settings were successfully set.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_INVALID_PARAM if the specified link configuration
- *                specifies a link rate or lane count that isn't valid.
+ * @return      - XST_SUCCESS if main link settings were successfully set.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr)
 {
@@ -333,59 +362,44 @@ u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        /* The link rate and lane count will be checked in XDptx_SetLinkRate and
+         * XDptx_SetLaneCount. */
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
         }
 
         /* Configure the main link to the maximum common link rate between the
-         * transmitter and the sink device. */
+         * DisplayPort TX core and the RX device. */
         Status = XDptx_SetLinkRate(InstancePtr, LinkConfig->MaxLinkRate);
         if (Status != XST_SUCCESS) {
                 return Status;
         }
 
         /* Configure the main link to the maximum common lane count between the
-         * transmitter and the sink device. */
+         * DisplayPort TX core and the RX device. */
         Status = XDptx_SetLaneCount(InstancePtr, LinkConfig->MaxLaneCount);
         if (Status != XST_SUCCESS) {
                 return Status;
         }
 
-        /* Configure enhanced frame mode for the main link if both the
-         * transmitter and sink device. */
-        Status = XDptx_SetEnhancedFrameMode(InstancePtr,
-                                        LinkConfig->SupportEnhancedFramingMode);
-        if (Status != XST_SUCCESS) {
-                return Status;
-        }
-
-        /* Configure downspreading for the main link if both the transmitter
-         * and sink device. */
-        Status = XDptx_SetDownspread(InstancePtr,
-                                        LinkConfig->SupportDownspreadControl);
-        if (Status != XST_SUCCESS) {
-                return Status;
-        }
-
         return XST_SUCCESS;
 }
 
 /******************************************************************************/
 /**
- * This function determines the common capabilities between the DisplayPort TX
- * core and the receiver.
+ * This function checks if the link needs training and runs the training
+ * sequence if training is required.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return      
- *              - XST_SUCCESS was either already trained, or has been
+ * @return      - XST_SUCCESS was either already trained, or has been
  *                trained successfully.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_INVALID_PARAM if the current link rate or lane count
- *                isn't valid.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_EstablishLink(XDptx *InstancePtr)
 {
@@ -394,17 +408,15 @@ u32 XDptx_EstablishLink(XDptx *InstancePtr)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        switch (InstancePtr->LinkConfig.LinkRate) {
-        case XDPTX_LINK_BW_SET_540GBPS:
-        case XDPTX_LINK_BW_SET_270GBPS:
-        case XDPTX_LINK_BW_SET_162GBPS:
-                /* Link rate is valid. */
-                break;
-        default:
-                return XST_INVALID_PARAM;
-        }
-        /* Lane count gets verified while checking the link status. */
+        Xil_AssertNonvoid((InstancePtr->LinkConfig.LinkRate ==
+                                                XDPTX_LINK_BW_SET_162GBPS) ||
+                        (InstancePtr->LinkConfig.LinkRate ==
+                                                XDPTX_LINK_BW_SET_270GBPS) ||
+                        (InstancePtr->LinkConfig.LinkRate ==
+                                                XDPTX_LINK_BW_SET_540GBPS));
+        /* The lane count will be checked in XDptx_CheckLinkStatus. */
+        Xil_AssertNonvoid(InstancePtr->RxConfig.LaneStatusAdjReqs != NULL);
+        Xil_AssertNonvoid(InstancePtr->RxConfig.DpcdRxCapsField != NULL);
 
         Status = XDptx_CheckLinkStatus(InstancePtr,
                                         InstancePtr->LinkConfig.LaneCount);
@@ -429,21 +441,21 @@ u32 XDptx_EstablishLink(XDptx *InstancePtr)
 
 /******************************************************************************/
 /**
- * This function checks if the reciever's DPCD indicates the reciever has
- * achieved and maintained clock recovery, channel equalization, symbol lock,
- * and interlane alignment for all lanes currently in use.
+ * This function checks if the reciever's DisplayPort Configuration Data (DPCD)
+ * indicates the reciever has achieved and maintained clock recovery, channel
+ * equalization, symbol lock, and interlane alignment for all lanes currently in
+ * use.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       LaneCount is the number of lanes to check.
  *
- * @return
- *              - XST_SUCCESS if the receiver has maintained clock recovery,
+ * @return      - XST_SUCCESS if the RX device has maintained clock recovery,
  *                channel equalization, symbol lock, and interlane alignment.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_INVALID_PARAM if the number of lanes to check does not
-                  match 1, 2, or 4 lanes.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount)
 {
@@ -454,10 +466,9 @@ u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        if ((LaneCount != 1) && (LaneCount != 2) && (LaneCount != 4)) {
-                return XST_INVALID_PARAM;
-        }
+        Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+                                        (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+                                        (LaneCount == XDPTX_LANE_COUNT_SET_4));
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
@@ -494,12 +505,16 @@ u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount)
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       Enable controls the downshift feature in the training process.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable)
 {
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
-        Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertVoid((Enable == 1) || (Enable == 0));
 
         InstancePtr->TrainAdaptive = Enable;
 }
@@ -515,12 +530,16 @@ void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable)
  * @param       Set establishes that a redriver exists in the DisplayPort output
  *              path.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set)
 {
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
-        Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertVoid((Set == 1) || (Set == 0));
 
         InstancePtr->HasRedriverInPath = Set;
 }
@@ -530,19 +549,19 @@ void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set)
  * This function issues a read request over the AUX channel.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
- * @param       Address is the starting address to read from the receiver.
- * @param       NumBytes is the number of bytes to read from the receiver.
+ * @param       Address is the starting address to read from the RX device.
+ * @param       NumBytes is the number of bytes to read from the RX device.
  * @param       Data is a pointer to the data buffer that will be filled with
  *              read data.
  *
- * @return
- *              - XST_SUCCESS if the AUX read request was successfully
+ * @return      - XST_SUCCESS if the AUX read request was successfully
  *                acknowledged.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_NO_DATA if no data was provided.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_ERROR_COUNT_MAX if the AUX request timed out.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
 {
@@ -560,10 +579,6 @@ u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
                 return XST_DEVICE_NOT_FOUND;
         }
 
-        if (Data == NULL) {
-                return XST_NO_DATA;
-        }
-
         /* Send AUX read transaction. */
         Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_READ, Address,
                                                         NumBytes, (u8 *)Data);
@@ -576,19 +591,19 @@ u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
  * This function issues a write request over the AUX channel.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
- * @param       Address is the starting address to write to the receiver.
- * @param       NumBytes is the number of bytes to write to the receiver.
+ * @param       Address is the starting address to write to the RX device.
+ * @param       NumBytes is the number of bytes to write to the RX device.
  * @param       Data is a pointer to the data buffer that contains the data
- *              to be written to the receiver.
+ *              to be written to the RX device.
  *
- * @return
- *              - XST_SUCCESS if AUX write request was successfully
+ * @return      - XST_SUCCESS if AUX write request was successfully
  *                acknowledged.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_NO_DATA if no data was provided.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_ERROR_COUNT_MAX if the AUX request timed out.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
 {
@@ -606,10 +621,6 @@ u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
                 return XST_DEVICE_NOT_FOUND;
         }
 
-        if (Data == NULL) {
-                return XST_NO_DATA;
-        }
-
         /* Send AUX write transaction. */
         Status = XDptx_AuxCommon(InstancePtr, XDPTX_AUX_CMD_WRITE, Address,
                                                         NumBytes, (u8 *)Data);
@@ -629,13 +640,14 @@ u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data)
  * @param       Data is a pointer to a buffer that will be filled with the I2C
  *              read data.
  *
- * @return
- *              - XST_SUCCESS if the I2C read has successfully completed with no
+ * @return      - XST_SUCCESS if the I2C read has successfully completed with no
  *                errors.
  *              - XST_ERROR_COUNT_MAX if the AUX request timed out.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
                                                         u8 NumBytes, void *Data)
@@ -687,13 +699,14 @@ u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
  * @param       Data is a pointer to a buffer which will be used as the data
  *              source for the write.
  *
- * @return
- *              - XST_SUCCESS if the I2C write has successfully completed with
+ * @return      - XST_SUCCESS if the I2C write has successfully completed with
  *                no errors.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_ERROR_COUNT_MAX if the AUX request timed out.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
                                                         u8 NumBytes, void *Data)
@@ -736,17 +749,19 @@ u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
 /******************************************************************************/
 /**
  * This function enables or disables 0.5% spreading of the clock for both the
- * DisplayPort and the sink device.
+ * DisplayPort and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
- * @param       Enable will enable or disable down-spread control.
+ * @param       Enable will downspread the main link signal if set to 1 and
+ *              disable downspreading if set to 0.
  *
- * @return
- *              - XST_SUCCESS if setting the downspread control enable was
+ * @return      - XST_SUCCESS if setting the downspread control enable was
  *                successful.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
 {
@@ -756,18 +771,19 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
         }
 
-        InstancePtr->LinkConfig.DownspreadControl = (Enable) ? 1 : 0;
+        InstancePtr->LinkConfig.DownspreadControl = Enable;
 
-        /* Write downspread enable to the transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_DOWNSPREAD_CTRL,
+        /* Write downspread enable to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_DOWNSPREAD_CTRL,
                                 InstancePtr->LinkConfig.DownspreadControl);
 
-        /* Preserve the current receiver settings. */
+        /* Preserve the current RX device settings. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -780,7 +796,7 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
                 RegVal &= ~XDPTX_DPCD_SPREAD_AMP_MASK;
         }
 
-        /* Write downspread enable to the sink device. */
+        /* Write downspread enable to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_DOWNSPREAD_CTRL, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -793,17 +809,19 @@ u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable)
 /******************************************************************************/
 /**
  * This function enables or disables the enhanced framing symbol sequence for
- * both the DisplayPort TX core and the sink device.
+ * both the DisplayPort TX core and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
- * @param       Enable will enable or disable enhanced frame mode.
+ * @param       Enable will enable enhanced frame mode if set to 1 and disable
+ *              it if set to 0.
  *
- * @return
- *              - XST_SUCCESS if setting the enhanced frame mode enable was
+ * @return      - XST_SUCCESS if setting the enhanced frame mode enable was
  *                successful.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
+ *              - XST_DEVICE_NOT_FOUND if no RX is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
 {
@@ -813,18 +831,19 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
         }
 
-        InstancePtr->LinkConfig.EnhancedFramingMode = (Enable) ? 1 : 0;
+        InstancePtr->LinkConfig.EnhancedFramingMode = Enable;
 
-        /* Write enhanced frame mode enable to the transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENHANCED_FRAME_EN,
+        /* Write enhanced frame mode enable to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENHANCED_FRAME_EN,
                                 InstancePtr->LinkConfig.EnhancedFramingMode);
 
-        /* Preserve the current receiver settings. */
+        /* Preserve the current RX device settings. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -837,7 +856,7 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
                 RegVal &= ~XDPTX_DPCD_ENHANCED_FRAME_EN_MASK;
         }
 
-        /* Write enhanced frame mode enable to the sink device. */
+        /* Write enhanced frame mode enable to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -850,18 +869,17 @@ u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable)
 /******************************************************************************/
 /**
  * This function sets the number of lanes to be used by the main link for both
- * the DisplayPort TX core and the sink device.
+ * the DisplayPort TX core and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       LaneCount is the number of lanes to be used over the main link.
  *
- * @return
- *              - XST_SUCCESS if setting the new lane count was successful.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_INVALID_PARAM if the supplied lane count is not either 1,
- *                2, or 4 lanes.
+ * @return      - XST_SUCCESS if setting the new lane count was successful.
+ *              - XST_DEVICE_NOT_FOUND if no RX is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
 {
@@ -871,10 +889,9 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        if ((LaneCount != 1) && (LaneCount != 2) && (LaneCount != 4)) {
-                return XST_INVALID_PARAM;
-        }
+        Xil_AssertNonvoid((LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+                                        (LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+                                        (LaneCount == XDPTX_LANE_COUNT_SET_4));
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
@@ -882,11 +899,11 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
 
         InstancePtr->LinkConfig.LaneCount = LaneCount;
 
-        /* Write the new lane count to the transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_LANE_COUNT_SET,
+        /* Write the new lane count to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LANE_COUNT_SET,
                                         InstancePtr->LinkConfig.LaneCount);
 
-        /* Preserve the current receiver settings. */
+        /* Preserve the current RX device settings. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -895,7 +912,7 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
         RegVal &= ~XDPTX_DPCD_LANE_COUNT_SET_MASK;
         RegVal |= InstancePtr->LinkConfig.LaneCount;
 
-        /* Write the new lane count to the sink device. */
+        /* Write the new lane count to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LANE_COUNT_SET, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -908,7 +925,7 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
 /******************************************************************************/
 /**
  * This function sets the data rate to be used by the main link for both the
- * DisplayPort TX core and the sink device.
+ * DisplayPort TX core and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       LinkRate is the link rate to be used over the main link based on
@@ -917,13 +934,12 @@ u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount)
  *              - XDPTX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
  *              - XDPTX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
  *
- * @return
- *              - XST_SUCCESS if setting the new link rate was successful.
- *              - XST_DEVICE_NOT_FOUND if no receiver is connected.
- *              - XST_INVALID_PARAM if the supplied link rate does not
- *                correspond to either 1.62, 2.70, or 5.40 Gbps.
+ * @return      - XST_SUCCESS if setting the new link rate was successful.
+ *              - XST_DEVICE_NOT_FOUND if no RX device is connected.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
 {
@@ -932,12 +948,15 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid((LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
+                                (LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
+                                (LinkRate == XDPTX_LINK_BW_SET_540GBPS));
 
         if (!XDptx_IsConnected(InstancePtr)) {
                 return XST_DEVICE_NOT_FOUND;
         }
 
-        /* Write a corresponding clock frequency to the transmitter. */
+        /* Write a corresponding clock frequency to the DisplayPort TX core. */
         switch (LinkRate) {
         case XDPTX_LINK_BW_SET_162GBPS:
                 Status = XDptx_SetClkSpeed(InstancePtr,
@@ -952,7 +971,7 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
                                                 XDPTX_PHY_CLOCK_SELECT_540GBPS);
                 break;
         default:
-                return XST_INVALID_PARAM;
+                break;
         }
         if (Status != XST_SUCCESS) {
                 return XST_FAILURE;
@@ -960,11 +979,11 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
 
         InstancePtr->LinkConfig.LinkRate = LinkRate;
 
-        /* Write new link rate to transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_LINK_BW_SET,
+        /* Write new link rate to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_LINK_BW_SET,
                                         InstancePtr->LinkConfig.LinkRate);
 
-        /* Write new link rate to sink device. */
+        /* Write new link rate to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_LINK_BW_SET, 1,
                                         &InstancePtr->LinkConfig.LinkRate);
         if (Status != XST_SUCCESS) {
@@ -977,15 +996,16 @@ u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate)
 /******************************************************************************/
 /**
  * This function enables or disables scrambling of symbols for both the
- * DisplayPort and the sink device.
+ * DisplayPort and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       Enable will enable or disable scrambling.
  *
- * @return
- *              - XST_SUCCESS if setting the scrambling enable was successful.
+ * @return      - XST_SUCCESS if setting the scrambling enable was successful.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable)
 {
@@ -995,14 +1015,15 @@ u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable)
         /* Verify arguments. */
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertNonvoid((Enable == 1) || (Enable == 0));
 
-        InstancePtr->LinkConfig.ScramblerEn = (Enable) ? 1 : 0;
+        InstancePtr->LinkConfig.ScramblerEn = Enable;
 
-        /* Write scrambler disable to the transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SCRAMBLING_DISABLE,
+        /* Write scrambler disable to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SCRAMBLING_DISABLE,
                                                                 Enable ? 0 : 1);
 
-        /* Preserve the current receiver settings. */
+        /* Preserve the current RX device settings. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
         if (Status != XST_SUCCESS) {
                 return XST_FAILURE;
@@ -1014,7 +1035,7 @@ u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable)
                 RegVal |= XDPTX_DPCD_TP_SET_SCRAMB_DIS_MASK;
         }
 
-        /* Write scrambler disable to the sink device. */
+        /* Write scrambler disable to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
         if (Status != XST_SUCCESS) {
                 return XST_FAILURE;
@@ -1029,6 +1050,10 @@ u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_EnableMainLink(XDptx *InstancePtr)
 {
@@ -1037,11 +1062,11 @@ void XDptx_EnableMainLink(XDptx *InstancePtr)
         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
         /* Reset the scrambler. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_FORCE_SCRAMBLER_RESET, 1);
 
         /* Enable the main stream. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_ENABLE_MAIN_STREAM, 1);
 }
 
@@ -1051,6 +1076,10 @@ void XDptx_EnableMainLink(XDptx *InstancePtr)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_DisableMainLink(XDptx *InstancePtr)
 {
@@ -1059,11 +1088,11 @@ void XDptx_DisableMainLink(XDptx *InstancePtr)
         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
         /* Reset the scrambler. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_FORCE_SCRAMBLER_RESET, 1);
 
         /* Disable the main stream. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_ENABLE_MAIN_STREAM, 0);
 }
 
@@ -1072,7 +1101,11 @@ void XDptx_DisableMainLink(XDptx *InstancePtr)
  * This function does a PHY reset.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
- & @param       Reset is the type of reset to assert.
+ * @param       Reset is the type of reset to assert.
+ *
+ * @return      None.
+ *
+ * @note        None.
  *
 *******************************************************************************/
 void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset)
@@ -1081,14 +1114,14 @@ void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset)
         Xil_AssertVoid(InstancePtr != NULL);
         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 0);
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0);
 
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_PHY_CONFIG, Reset);
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_PHY_CONFIG,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG, Reset);
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_PHY_CONFIG,
                                         XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
         XDptx_WaitPhyReady(InstancePtr);
 
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 1);
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 1);
 }
 
 /******************************************************************************/
@@ -1102,6 +1135,10 @@ void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset)
  *              will be passed to the custom sleep/delay function when it is
  *              invoked.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
                         XDptx_TimerHandler CallbackFunc, void *CallbackRef)
@@ -1129,6 +1166,10 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       MicroSeconds is the number of microseconds to delay/sleep for.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds)
 {
@@ -1159,7 +1200,7 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds)
  * machine, with each state returning the next state. First, the clock recovery
  * sequence will be run; if successful, the channel equalization sequence will
  * run. If either the clock recovery or channel equalization sequence failed,
- * the data rate or the number of lanes used will be reduced and training will
+ * the link rate or the number of lanes used will be reduced and training will
  * be re-attempted. If training fails at the minimal data rate, 1.62 Gbps with
  * a single lane, training will no longer re-attempt and fail.
  *
@@ -1169,16 +1210,14 @@ void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds)
  *              - XST_SUCCESS if the training process succeeded.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_RunTraining(XDptx *InstancePtr)
 {
         u32 Status;
         XDptx_TrainingState TrainingState = XDPTX_TS_CLOCK_RECOVERY;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         /* Disable scrambler. */
         Status = XDptx_SetScrambler(InstancePtr, 0);
         if (Status != XST_SUCCESS) {
@@ -1203,8 +1242,6 @@ static u32 XDptx_RunTraining(XDptx *InstancePtr)
                         TrainingState = XDptx_TrainingStateAdjustLaneCount(
                                                                 InstancePtr);
                         break;
-                case XDPTX_TS_FAILURE:
-                        return XST_FAILURE;
                 default:
                         break;
                 }
@@ -1212,6 +1249,9 @@ static u32 XDptx_RunTraining(XDptx *InstancePtr)
                 if (TrainingState == XDPTX_TS_SUCCESS) {
                         break;
                 }
+                else if (TrainingState == XDPTX_TS_FAILURE) {
+                        return XST_FAILURE;
+                }
 
                 if ((InstancePtr->TrainAdaptive == 0) &&
                         ((TrainingState == XDPTX_TS_ADJUST_LANE_COUNT) ||
@@ -1253,25 +1293,28 @@ static u32 XDptx_RunTraining(XDptx *InstancePtr)
  *         disabled.
  *      2) The clock recovery loop. If clock recovery is unsuccessful after
  *         MaxIterations loop iterations, return.
- *      2a) Wait for at least the period of time specified in the receiver's
- *          DPCD register, TRAINING_AUX_RD_INTERVAL.
+ *      2a) Wait for at least the period of time specified in the RX device's
+ *          DisplayPort Configuration Data (DPCD) register,
+ *          TRAINING_AUX_RD_INTERVAL.
  *      2b) Check if all lanes have achieved clock recovery lock. If so, return.
  *      2c) Check if the same voltage swing level has been used 5 consecutive
  *          times or if the maximum level has been reached. If so, return.
  *      2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
- *          requested by the receiver.
+ *          requested by the RX device.
  *      2e) Loop back to 2a.
  * For a more detailed description of the clock recovery sequence, see section
  * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
  * 
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence
+ * @return      - XDPTX_TS_CHANNEL_EQUALIZATION if the clock recovery sequence
  *                completed successfully.
- *              - XDPTX_TS_FAILURE if writing the drive settings to the receiver
- *                was unsuccesful.
- *              - XDPTX_TS_ADJUST_LINK_RATE if CR is unsuccessful.
+ *              - XDPTX_TS_FAILURE if writing the drive settings to the RX
+ *                device was unsuccesful.
+ *              - XDPTX_TS_ADJUST_LINK_RATE if the clock recovery sequence
+ *                did not complete successfully.
+ *
+ * @note        None.
  *
 *******************************************************************************/
 static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
@@ -1282,11 +1325,8 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
         u8 SameVsLevelCount = 0;
         XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        /* Obtain the required delay for CR as specified in the sink's DPCD. */
+        /* Obtain the required delay for clock recovery as specified by the
+         * RX device. */
         DelayUs = XDptx_GetTrainingDelay(InstancePtr, XDPTX_TS_CLOCK_RECOVERY);
 
         /* Start CRLock. */
@@ -1344,7 +1384,7 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
                         break;
                 }
 
-                /* Adjust the drive settings as requested by the sink device. */
+                /* Adjust the drive settings as requested by the RX device. */
                 Status = XDptx_AdjVswingPreemp(InstancePtr);
                 if (Status != XST_SUCCESS) {
                         /* The AUX write failed. */
@@ -1365,14 +1405,15 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
  *         scrambling disabled.
  *      2) The channel equalization loop. If channel equalization is
  *         unsuccessful after MaxIterations loop iterations, return.
- *      2a) Wait for at least the period of time specified in the receiver's
- *          DPCD register, TRAINING_AUX_RD_INTERVAL.
+ *      2a) Wait for at least the period of time specified in the RX device's
+ *          DisplayPort Configuration Data (DPCD) register,
+ *          TRAINING_AUX_RD_INTERVAL.
  *      2b) Check if all lanes have achieved channel equalization, symbol lock,
  *          and interlane alignment. If so, return.
  *      2c) Check if the same voltage swing level has been used 5 consecutive
  *          times or if the maximum level has been reached. If so, return.
  *      2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
- *          requested by the receiver.
+ *          requested by the RX device.
  *      2e) Loop back to 2a.
  * For a more detailed description of the channel equalization sequence, see
  * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
@@ -1382,12 +1423,14 @@ static XDptx_TrainingState XDptx_TrainingStateClockRecovery(XDptx *InstancePtr)
  *              clock recovery sequence before down-shifting to a reduced data
  *              rate or a reduced number of lanes.
  *
- * @return
- *              - XDPTX_TS_SUCCESS if training succeeded.
- *              - XDPTX_TS_FAILURE if writing the drive settings to the receiver
- *                was unsuccesful.
+ * @return      - XDPTX_TS_SUCCESS if training succeeded.
+ *              - XDPTX_TS_FAILURE if writing the drive settings to the RX
+ *                device was unsuccesful.
  *              - XDPTX_TS_ADJUST_LINK_RATE if, after MaxIterations loop
- *                iterations, clock recovery is unsuccessful.
+ *                iterations, the channel equalization sequence did not complete
+ *                successfully.
+ *
+ * @note        None.
  *
 *******************************************************************************/
 static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
@@ -1400,17 +1443,14 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
         u8 SameVsLevelCount = 0;
         XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        /* Obtain the required delay for CE as specified in the sink's DPCD. */
+        /* Obtain the required delay for channel equalization as specified by
+         * the RX device. */
         DelayUs = XDptx_GetTrainingDelay(InstancePtr,
                                                 XDPTX_TS_CHANNEL_EQUALIZATION);
 
         /* Start channel equalization. */
 
-        /* Write the current drive settings to the sink device. */
+        /* Write the current drive settings to the RX device. */
         Status = XDptx_SetVswingPreemp(InstancePtr);
         if (Status != XST_SUCCESS) {
                 return XDPTX_TS_FAILURE;
@@ -1475,7 +1515,7 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
                         break;
                 }
 
-                /* Adjust the drive settings as requested by the sink device. */
+                /* Adjust the drive settings as requested by the RX device. */
                 Status = XDptx_AdjVswingPreemp(InstancePtr);
                 if (Status != XST_SUCCESS) {
                         /* The AUX write failed. */
@@ -1505,39 +1545,40 @@ static XDptx_TrainingState XDptx_TrainingStateChannelEqualization(
  *                in use. Re-attempt training at a reduced lane count.
  *              - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr)
 {
         u32 Status;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         switch (InstancePtr->LinkConfig.LinkRate) {
         case XDPTX_LINK_BW_SET_540GBPS:
                 Status = XDptx_SetLinkRate(InstancePtr,
                                                 XDPTX_LINK_BW_SET_270GBPS);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
-
-                return XDPTX_TS_CLOCK_RECOVERY;
+                Status = XDPTX_TS_CLOCK_RECOVERY;
+                break;
         case XDPTX_LINK_BW_SET_270GBPS:
                 Status = XDptx_SetLinkRate(InstancePtr,
                                                 XDPTX_LINK_BW_SET_162GBPS);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
-
-                return XDPTX_TS_CLOCK_RECOVERY;
+                Status = XDPTX_TS_CLOCK_RECOVERY;
+                break;
         default:
                 /* Already at the lowest link rate. Try reducing the lane
                  * count next. */
+                Status = XDPTX_TS_ADJUST_LANE_COUNT;
                 break;
         }
 
-        return XDPTX_TS_ADJUST_LANE_COUNT;
+        return Status;
 }
 
 /******************************************************************************/
@@ -1558,6 +1599,8 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLinkRate(XDptx *InstancePtr)
  *              - XDPTX_TS_FAILURE if only one lane is already in use.
  *              - XDPTX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount(
                                                         XDptx *InstancePtr)
@@ -1565,68 +1608,68 @@ static XDptx_TrainingState XDptx_TrainingStateAdjustLaneCount(
         u32 Status;
         XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         switch (LinkConfig->LaneCount) {
-        case 4:
-                Status = XDptx_SetLaneCount(InstancePtr, 2);
+        case XDPTX_LANE_COUNT_SET_4:
+                Status = XDptx_SetLaneCount(InstancePtr,
+                                                        XDPTX_LANE_COUNT_SET_2);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
 
                 Status = XDptx_SetLinkRate(InstancePtr,
                                                 LinkConfig->MaxLinkRate);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
-
-                return XDPTX_TS_CLOCK_RECOVERY;
-        case 2:
-                Status = XDptx_SetLaneCount(InstancePtr, 1);
+                Status = XDPTX_TS_CLOCK_RECOVERY;
+                break;
+        case XDPTX_LANE_COUNT_SET_2:
+                Status = XDptx_SetLaneCount(InstancePtr,
+                                                        XDPTX_LANE_COUNT_SET_1);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
 
                 Status = XDptx_SetLinkRate(InstancePtr,
                                                 LinkConfig->MaxLinkRate);
                 if (Status != XST_SUCCESS) {
-                        return XDPTX_TS_FAILURE;
+                        Status = XDPTX_TS_FAILURE;
+                        break;
                 }
-
-                return XDPTX_TS_CLOCK_RECOVERY;
+                Status = XDPTX_TS_CLOCK_RECOVERY;
+                break;
         default:
                 /* Already at the lowest lane count. Training has failed at the
                  * lowest lane count and link rate. */
+                Status = XDPTX_TS_FAILURE;
                 break;
         }
 
-        return XDPTX_TS_FAILURE;
+        return Status;
 }
 
 /******************************************************************************/
 /**
- * This function will do a burst AUX read from the receiver over the AUX
+ * This function will do a burst AUX read from the RX device over the AUX
  * channel. The contents of the status registers will be stored for later use by
  * XDptx_CheckClockRecovery, XDptx_CheckChannelEqualization, and
  * XDptx_AdjVswingPreemp.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if the AUX read was successful.
+ * @return      - XST_SUCCESS if the AUX read was successful.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr)
 {
         u32 Status;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         /* Read and store 4 bytes of lane status and 2 bytes of adjustment
          * requests. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_STATUS_LANE_0_1,
@@ -1640,19 +1683,20 @@ static u32 XDptx_GetLaneStatusAdjReqs(XDptx *InstancePtr)
 
 /******************************************************************************/
 /**
- * This function checks if the receiver's DPCD indicates that the clock recovery
- * sequence during link training was successful - the receiver's link clock and
- * data recovery unit has realized and maintained the frequency lock for all
- * lanes currently in use.
+ * This function checks if the RX device's DisplayPort Configuration Data (DPCD)
+ * indicates that the clock recovery sequence during link training was
+ * successful - the RX device's link clock and data recovery unit has realized
+ * and maintained the frequency lock for all lanes currently in use.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       LaneCount is the number of lanes to check.
  *
- * @return
- *              - XST_SUCCESS if the receiver's clock recovery PLL has achieved
- *                frequency lock for all lanes in use.
+ * @return      - XST_SUCCESS if the RX device's clock recovery PLL has
+ *                achieved frequency lock for all lanes in use.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
 {
@@ -1661,14 +1705,9 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
 
         u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-        Xil_AssertNonvoid(LaneStatus != NULL);
-
         /* Check that all LANEx_CR_DONE bits are set. */
         switch (LaneCount) {
-        case 4:
+        case XDPTX_LANE_COUNT_SET_4:
                 if (!(LaneStatus[1] &
                                 XDPTX_DPCD_STATUS_LANE_3_CR_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1678,13 +1717,13 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 1. */
-        case 2:
+        case XDPTX_LANE_COUNT_SET_2:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_1_CR_DONE_MASK)) {
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 0. */
-        case 1:
+        case XDPTX_LANE_COUNT_SET_1:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1699,19 +1738,21 @@ static u32 XDptx_CheckClockRecovery(XDptx *InstancePtr, u8 LaneCount)
 
 /******************************************************************************/
 /**
- * This function checks if the receiver's DPCD indicates that the channel
- * equalization sequence during link training was successful - the receiver has
- * achieved channel equalization, symbol lock, and interlane alignment for all
- * lanes currently in use.
+ * This function checks if the RX device's DisplayPort Configuration Data (DPCD)
+ * indicates that the channel equalization sequence during link training was
+ * successful - the RX device has achieved channel equalization, symbol lock,
+ * and interlane alignment for all lanes currently in use.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       LaneCount is the number of lanes to check.
  *
- * @return
- *              - XST_SUCCESS if the receiver has achieved channel equalization
- *                symbol lock, and interlane alignment for all lanes in use.
+ * @return      - XST_SUCCESS if the RX device has achieved channel
+ *                equalization symbol lock, and interlane alignment for all
+ *                lanes in use.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
 {
@@ -1719,14 +1760,9 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
         u8 AuxData[6];
         u8 *LaneStatus = InstancePtr->RxConfig.LaneStatusAdjReqs;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-        Xil_AssertNonvoid(LaneStatus != NULL);
-
         /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
         switch (LaneCount) {
-        case 4:
+        case XDPTX_LANE_COUNT_SET_4:
                 if (!(LaneStatus[1] &
                                 XDPTX_DPCD_STATUS_LANE_3_CE_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1736,13 +1772,13 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 1. */
-        case 2:
+        case XDPTX_LANE_COUNT_SET_2:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_1_CE_DONE_MASK)) {
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 0. */
-        case 1:
+        case XDPTX_LANE_COUNT_SET_1:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_0_CE_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1754,7 +1790,7 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
 
         /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
         switch (LaneCount) {
-        case 4:
+        case XDPTX_LANE_COUNT_SET_4:
                 if (!(LaneStatus[1] &
                                 XDPTX_DPCD_STATUS_LANE_3_SL_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1764,13 +1800,13 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 1. */
-        case 2:
+        case XDPTX_LANE_COUNT_SET_2:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_1_SL_DONE_MASK)) {
                         return XST_FAILURE;
                 }
                 /* Drop through and check lane 0. */
-        case 1:
+        case XDPTX_LANE_COUNT_SET_1:
                 if (!(LaneStatus[0] &
                                 XDPTX_DPCD_STATUS_LANE_0_SL_DONE_MASK)) {
                         return XST_FAILURE;
@@ -1796,10 +1832,11 @@ static u32 XDptx_CheckChannelEqualization(XDptx *InstancePtr, u8 LaneCount)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if writing the settings was successful.
+ * @return      - XST_SUCCESS if writing the settings was successful.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
 {
@@ -1816,15 +1853,11 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
         u32 PeLevels[4] = {XDPTX_PE_LEVEL_0, XDPTX_PE_LEVEL_1,
                                         XDPTX_PE_LEVEL_2, XDPTX_PE_LEVEL_3};
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         if (InstancePtr->HasRedriverInPath == 0) {
                 PeLevel = PeLevels[PeLevelRx];
                 VsLevel = VsLevels[VsLevelRx];
 
-                /* Need to compensate due to lack of redriver. */
+                /* Need to compensate due to no redriver in the path. */
                 if (PeLevelRx != 0) {
                         VsLevel += XDPTX_VS_LEVEL_OFFSET;
                 }
@@ -1833,13 +1866,15 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
                 /* No need to compensate since redriver does that. Can evenly
                  * disperse the voltage swing and pre-emphasis levels. */
 
-                /* Map 16 possible voltage swing levels in TX to 4 in RX. */
+                /* Map 16 possible voltage swing levels in the DisplayPort TX
+                 * core to 4 possible in the RX device. */
                 VsLevel = VsLevelRx * 4 + 2;
-                /* Map 32 possible pre-emphasis levels in TX to 4 in RX. */
+                /* Map 32 possible pre-emphasis levels in the DisplayPort TX
+                 * core to 4 possible in the RX device. */
                 PeLevel = PeLevelRx * 8 + 4;
         }
 
-        /* Set up the data buffer for writing to the sink device. */
+        /* Set up the data buffer for writing to the RX device. */
         Data = (PeLevelRx << XDPTX_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
                                                                 VsLevelRx;
         /* The maximum voltage swing has been reached. */
@@ -1854,20 +1889,20 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
 
         for (Index = 0; Index < InstancePtr->LinkConfig.LaneCount; Index++) {
                 /* Disable pre-cursor levels. */
-                XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+                XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                         XDPTX_PHY_PRECURSOR_LANE_0 + 4 * Index, 0);
 
                 /* Write new voltage swing levels to the TX registers. */
-                XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+                XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                         XDPTX_PHY_VOLTAGE_DIFF_LANE_0 + 4 * Index, VsLevel);
 
                 /* Write new pre-emphasis levels to the TX registers. */
-                XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+                XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                         XDPTX_PHY_POSTCURSOR_LANE_0 + 4 * Index, PeLevel);
         }
 
         /* Write the voltage swing and pre-emphasis levels for each lane to the
-         * sink device. */
+         * RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TRAINING_LANE0_SET,
                                 InstancePtr->LinkConfig.LaneCount, AuxData);
         if (Status != XST_SUCCESS) {
@@ -1879,16 +1914,16 @@ static u32 XDptx_SetVswingPreemp(XDptx *InstancePtr)
 
 /******************************************************************************/
 /**
- * This function obtains adjustment requests for voltage swing and pre-emphasis
- * levels from the receiver and sets these new settings.
+ * This function sets new voltage swing and pre-emphasis levels using the
+ * adjustment requests obtained from the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if the adjustment request from the receiver and
- *                the new settings were written successfully.
+ * @return      - XST_SUCCESS if the new levels were written successfully.
  *              - XST_FAILURE otherwise (an AUX transaction failed).
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
 {
@@ -1898,11 +1933,6 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
         u8 PeLevelAdjReq[4];
         u8 *AdjReqs = &InstancePtr->RxConfig.LaneStatusAdjReqs[4];
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(AdjReqs != NULL);
-
         /* Analyze the adjustment requests for changes in voltage swing and
          * pre-emphasis levels. */
         VsLevelAdjReq[0] = AdjReqs[0] & XDPTX_DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
@@ -1950,7 +1980,8 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
                                         4 - InstancePtr->LinkConfig.VsLevel;
         }
 
-        /* Make the adjustments to both the transmitter and the sink device. */
+        /* Make the adjustments to both the DisplayPort TX core and the RX
+         * device. */
         Status = XDptx_SetVswingPreemp(InstancePtr);
         if (Status != XST_SUCCESS) {
                 return XST_FAILURE;
@@ -1962,7 +1993,7 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
 /******************************************************************************/
 /**
  * This function sets the training pattern to be used during link training for
- * both the DisplayPort TX core and the sink device.
+ * both the DisplayPort TX core and the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       Pattern selects the pattern to be used. One of the following:
@@ -1971,36 +2002,22 @@ static u32 XDptx_AdjVswingPreemp(XDptx *InstancePtr)
  *              - XDPTX_TRAINING_PATTERN_SET_TP2
  *              - XDPTX_TRAINING_PATTERN_SET_TP3
  *
- * @return
- *              - XST_SUCCESS if setting the pattern was successful.
- *              - XST_INVALID_PARAM if the supplied pattern select isn't valid.
+ * @return      - XST_SUCCESS if setting the pattern was successful.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern)
 {
         u32 Status;
         u8 RegVal;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        switch (Pattern) {
-        case XDPTX_TRAINING_PATTERN_SET_OFF:
-        case XDPTX_TRAINING_PATTERN_SET_TP1:
-        case XDPTX_TRAINING_PATTERN_SET_TP2:
-        case XDPTX_TRAINING_PATTERN_SET_TP3:
-                break;
-        default:
-                return XST_INVALID_PARAM;
-        }
-
-        /* Write to the transmitter. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        /* Write to the DisplayPort TX core. */
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                         XDPTX_TRAINING_PATTERN_SET, Pattern);
 
-        /* Preserve the current receiver settings. */
+        /* Preserve the current RX device settings. */
         Status = XDptx_AuxRead(InstancePtr, XDPTX_DPCD_TP_SET, 1, &RegVal);
                         RegVal &= ~XDPTX_DPCD_TP_SEL_MASK;
                         RegVal |= (Pattern & XDPTX_DPCD_TP_SEL_MASK);
@@ -2008,7 +2025,7 @@ static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern)
                 return XST_FAILURE;
         }
 
-        /* Write to the sink device. */
+        /* Write to the RX device. */
         Status = XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_TP_SET, 1,
                                                                 &RegVal);
         if (Status != XST_SUCCESS) {
@@ -2020,53 +2037,82 @@ static u32 XDptx_SetTrainingPattern(XDptx *InstancePtr, u32 Pattern)
 
 /******************************************************************************/
 /**
- * This function determines what the receiver's required training delay is for
+ * This function determines what the RX device's required training delay is for
  * link training.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       TrainingState is the current training state; either clock
  *              recovery or channel equalization.
  *
- * @return      The training delay specified in the receiver's DPCD register,
+ * @return      The training delay specified in the RX device's DisplayPort
+ *              Configuration Data (DPCD) register,
  *              XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_GetTrainingDelay(XDptx *InstancePtr,
                                         XDptx_TrainingState TrainingState)
 {
         u8 *Dpcd = InstancePtr->RxConfig.DpcdRxCapsField;
-
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(Dpcd != NULL);
+        u16 Delay;
 
         switch (Dpcd[XDPTX_DPCD_TRAIN_AUX_RD_INTERVAL]) {
         case XDPTX_DPCD_TRAIN_AUX_RD_INT_100_400US:
                 if (TrainingState == XDPTX_TS_CLOCK_RECOVERY) {
                         /* Delay for the clock recovery phase. */
-                        return 100;
+                        Delay = 100;
                 }
                 else {
                         /* Delay for the channel equalization phase. */
-                        return 400;
+                        Delay = 400;
                 }
+                break;
         case XDPTX_DPCD_TRAIN_AUX_RD_INT_4MS:
-                return 4000;
+                Delay = 4000;
+                break;
         case XDPTX_DPCD_TRAIN_AUX_RD_INT_8MS:
-                return 8000;
+                Delay = 8000;
+                break;
         case XDPTX_DPCD_TRAIN_AUX_RD_INT_12MS:
-                return 12000;
+                Delay = 12000;
+                break;
         case XDPTX_DPCD_TRAIN_AUX_RD_INT_16MS:
-                return 16000;
+                Delay = 16000;
+                break;
         default:
+                /* Default to 20 ms. */
+                Delay = 20000;
                 break;
         }
 
-        /* A DPCD register value corresponding with an unknown delay should
-         * default to 20 ms. */
-        return 20000;
+        return Delay;
 }
 
+/******************************************************************************/
+/**
+ * This function contains the common sequence of submitting an AUX command for
+ * AUX read, AUX write, I2C-over-AUX read, and I2C-over-AUX write transactions.
+ *
+ * @param       InstancePtr is a pointer to the XDptx instance.
+ * @param       CmdType is the type of AUX command (one of: XDPTX_AUX_CMD_READ,
+ *              XDPTX_AUX_CMD_WRITE, XDPTX_AUX_CMD_I2C_READ, or
+ *              XDPTX_AUX_CMD_I2C_WRITE.
+ * @param       Address is the starting address that the AUX transaction will
+ *              read/write from/to the RX device.
+ * @param       NumBytes is the number of bytes to read/write from/to the RX
+ *              device.
+ * @param       Data is a pointer to the data buffer that contains the data
+ *              to be read/written from/to the RX device.
+ *
+ * @return      - XST_SUCCESS if the AUX transaction request was acknowledged.
+ *              - XST_ERROR_COUNT_MAX if the AUX request timed out.
+ *              - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
+ *                reply code or if the AUX transaction failed).
+ *
+ * @note        None.
+ *
+*******************************************************************************/
 static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
                                                         u32 NumBytes, u8 *Data)
 {
@@ -2122,9 +2168,9 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
 
 /******************************************************************************/
 /**
- * This function submits the supplied AUX request to the sink device over the
- * AUX channel. If waiting for a reply times out, or if the DisplayPort TX core
- * indicates that the request was deferred, the request is sent again(up to a
+ * This function submits the supplied AUX request to the RX device over the AUX
+ * channel. If waiting for a reply times out, or if the DisplayPort TX core
+ * indicates that the request was deferred, the request is sent again (up to a
  * maximum specified by XDPTX_AUX_MAX_DEFER_COUNT|XDPTX_AUX_MAX_TIMEOUT_COUNT).
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
@@ -2133,13 +2179,14 @@ static u32 XDptx_AuxCommon(XDptx *InstancePtr, u32 CmdType, u32 Address,
  *              AUX command, as well as a write buffer used for write commands,
  *              and a read buffer for read commands.
  *
- * @return
- *              - XST_SUCCESS if the request was acknowledged.
+ * @return      - XST_SUCCESS if the request was acknowledged.
  *              - XST_ERROR_COUNT_MAX if resending the request exceeded the
  *                maximum for deferral and timeout.
- *              - XST_FAILURE otherwise (if the transmitter sees a NACK
+ *              - XST_FAILURE otherwise (if the DisplayPort TX core sees a NACK
  *                reply code or if the AUX transaction failed).
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request)
 {
@@ -2147,63 +2194,56 @@ static u32 XDptx_AuxRequest(XDptx *InstancePtr, XDptx_AuxTransaction *Request)
         u32 DeferCount = 0;
         u32 TimeoutCount = 0;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-        Xil_AssertNonvoid(Request != NULL);
-
         while ((DeferCount < XDPTX_AUX_MAX_DEFER_COUNT) &&
                                 (TimeoutCount < XDPTX_AUX_MAX_TIMEOUT_COUNT)) {
                 Status = XDptx_AuxWaitReady(InstancePtr);
                 if (Status != XST_SUCCESS) {
-                        /* The receiver isn't ready yet. */
+                        /* The RX device isn't ready yet. */
                         TimeoutCount++;
                         continue;
                 }
 
                 /* Send the request. */
                 Status = XDptx_AuxRequestSend(InstancePtr, Request);
-                switch (Status) {
-                case XST_SEND_ERROR:
+                if (Status == XST_SEND_ERROR) {
                         /* The request was deferred. */
                         DeferCount++;
-                        break;
-                case XST_ERROR_COUNT_MAX:
+                }
+                else if (Status == XST_ERROR_COUNT_MAX) {
                         /* Waiting for a reply timed out. */
                         TimeoutCount++;
-                        break;
-                case XST_FAILURE:
-                        /* The request was NACK'ed. */
-                        return XST_FAILURE;
-                default:
-                        /* The request was ACK'ed. */
-                        return XST_SUCCESS;
+                }
+                else {
+                        /* XST_FAILURE indicates that the request was NACK'ed,
+                         * XST_SUCCESS indicates that the request was ACK'ed. */
+                        return Status;
                 }
 
                 XDptx_WaitUs(InstancePtr, 100);
         }
 
-        /* The request was not successfully received by the sink device. */
+        /* The request was not successfully received by the RX device. */
         return XST_ERROR_COUNT_MAX;
 }
 
 /******************************************************************************/
 /**
- * This function submits the supplied AUX request to the sink device over the
- * AUX channel by writing the command, the destination sink address, (the write
- * buffer for write commands), and the data size to the DisplayPort TX core.
+ * This function submits the supplied AUX request to the RX device over the AUX
+ * channel by writing the command, the destination address, (the write buffer
+ * for write commands), and the data size to the DisplayPort TX core.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       Request is a pointer to an initialized XDptx_AuxTransaction
  *              structure containing the required information for issuing an AUX
  *              command. 
  *
- * @return
- *              - XST_SUCCESS if the request was acknowledged.
+ * @return      - XST_SUCCESS if the request was acknowledged.
  *              - XST_ERROR_COUNT_MAX if waiting for a reply timed out.
  *              - XST_SEND_ERROR if the request was deferred.
  *              - XST_FAILURE otherwise, if the request was NACK'ed.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
                                                 XDptx_AuxTransaction *Request)
@@ -2212,31 +2252,27 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
         u8 Index;
 
         /* Set the address for the request. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_AUX_ADDRESS,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_ADDRESS,
                                                         Request->Address);
 
-        switch (Request->CmdCode) {
-        case XDPTX_AUX_CMD_WRITE:
-        case XDPTX_AUX_CMD_I2C_WRITE:
-        case XDPTX_AUX_CMD_I2C_WRITE_MOT:
-                /* Feed write data into the transmitter FIFO. */
+        if ((Request->CmdCode == XDPTX_AUX_CMD_WRITE) ||
+                        (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE) ||
+                        (Request->CmdCode == XDPTX_AUX_CMD_I2C_WRITE_MOT)) {
+                /* Feed write data into the DisplayPort TX core's write FIFO. */
                 for (Index = 0; Index < Request->NumBytes; Index++) {
-                        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+                        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_AUX_WRITE_FIFO,
                                                 Request->Data[Index]);
                 }
-        default:
-                /* Not a write command. */
-                break;
         }
 
         /* Submit the command and the data size. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_AUX_CMD,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_AUX_CMD,
                                 ((Request->CmdCode << XDPTX_AUX_CMD_SHIFT) |
                                 ((Request->NumBytes - 1) &
                                 XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK)));
 
-        /* Check for a receiver reply to the submitted request. */
+        /* Check for a reply from the RX device to the submitted request. */
         Status = XDptx_AuxWaitReply(InstancePtr);
         if (Status != XST_SUCCESS) {
                 /* Waiting for a reply timed out. */
@@ -2244,35 +2280,30 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
         }
 
         /* Analyze the reply. */
-        Status = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+        Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                                         XDPTX_AUX_REPLY_CODE);
-        switch (Status) {
-        case XDPTX_AUX_REPLY_CODE_DEFER:
-        case XDPTX_AUX_REPLY_CODE_I2C_DEFER:
+        if ((Status == XDPTX_AUX_REPLY_CODE_DEFER) ||
+                                (Status == XDPTX_AUX_REPLY_CODE_I2C_DEFER)) {
                 /* The request was deferred. */
                 return XST_SEND_ERROR;
-        case XDPTX_AUX_REPLY_CODE_NACK:
-        case XDPTX_AUX_REPLY_CODE_I2C_NACK:
+        }
+        else if ((Status == XDPTX_AUX_REPLY_CODE_NACK) ||
+                                (Status == XDPTX_AUX_REPLY_CODE_I2C_NACK)) {
                 /* The request was not acknowledged. */
                 return XST_FAILURE;
-        default:
-                /* The request was acknowledged. */
-                break;
         }
 
-        switch (Request->CmdCode) {
-        case XDPTX_AUX_CMD_READ:
-        case XDPTX_AUX_CMD_I2C_READ:
-        case XDPTX_AUX_CMD_I2C_READ_MOT:
+        /* The request was acknowledged. */
+
+        if ((Request->CmdCode == XDPTX_AUX_CMD_READ) ||
+                        (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ) ||
+                        (Request->CmdCode == XDPTX_AUX_CMD_I2C_READ_MOT)) {
                 /* Obtain the read data from the reply FIFO. */
                 for (Index = 0; Index < Request->NumBytes; Index++) {
                         Request->Data[Index] = XDptx_ReadReg(
-                                                InstancePtr->TxConfig.BaseAddr,
+                                                InstancePtr->Config.BaseAddr,
                                                 XDPTX_AUX_REPLY_DATA);
                 }
-        default:
-                /* Not a read command. */
-                break;
         }
 
         return XST_SUCCESS;
@@ -2281,26 +2312,23 @@ static u32 XDptx_AuxRequestSend(XDptx *InstancePtr,
 /******************************************************************************/
 /**
  * This function waits for a reply indicating that the most recent AUX request
- * has been received by the sink device.
+ * has been received by the RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if a reply from the sink device was received.
+ * @return      - XST_SUCCESS if a reply was sent from the RX device.
  *              - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_AuxWaitReply(XDptx *InstancePtr)
 {
         u32 Timeout = 100;
         u32 Status;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         while (0 < Timeout) {
-                Status = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+                Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_INTERRUPT_STATUS);
 
                 /* Check for a timeout. */
@@ -2326,19 +2354,20 @@ static u32 XDptx_AuxWaitReply(XDptx *InstancePtr)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if the the receiver is no longer busy.
+ * @return      - XST_SUCCESS if the the RX device is no longer busy.
  *              - XST_ERROR_COUNT_MAX otherwise, if a timeout has occurred.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_AuxWaitReady(XDptx *InstancePtr)
 {
         u32 Status;
         u32 Timeout = 100;
 
-        /* Wait until the transmitter is ready. */
+        /* Wait until the DisplayPort TX core is ready. */
         do {
-                Status = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+                Status = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                         XDPTX_INTERRUPT_SIG_STATE);
 
                 /* Protect against an infinite loop. */
@@ -2364,40 +2393,29 @@ static u32 XDptx_AuxWaitReady(XDptx *InstancePtr)
  *              - XDPTX_PHY_CLOCK_SELECT_270GBPS = 0x03
  *              - XDPTX_PHY_CLOCK_SELECT_540GBPS = 0x05
  *
- * @return
- *              - XST_SUCCESS if the reset for each lane is done after the clock
+ * @return      - XST_SUCCESS if the reset for each lane is done after the clock
  *                frequency has been set.
- *              - XST_INVALID_PARAM if the clock frequency doesn't correspond to
- *                an associated 1.62, 2.70, or 5.40 Gbps link rate.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed)
 {
         u32 Status;
         u32 RegVal;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-        if (Speed != XDPTX_PHY_CLOCK_SELECT_162GBPS &&
-                                Speed != XDPTX_PHY_CLOCK_SELECT_270GBPS &&
-                                Speed != XDPTX_PHY_CLOCK_SELECT_540GBPS) {
-                return XST_INVALID_PARAM;
-        }
-
-        /* Disable the transmitter first. */
-        RegVal = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE);
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 0);
+        /* Disable the DisplayPort TX core first. */
+        RegVal = XDptx_ReadReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE);
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 0);
 
         /* Change speed of the feedback clock. */
-        XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr,
+        XDptx_WriteReg(InstancePtr->Config.BaseAddr,
                                                 XDPTX_PHY_CLOCK_SELECT, Speed);
 
-        /* Re-enable the transmitter if it was previously. */
+        /* Re-enable the DisplayPort TX core if it was previously enabled. */
         if (RegVal != 0) {
-                XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_ENABLE, 1);
+                XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_ENABLE, 1);
         }
 
         /* Wait until the PHY is ready. */
@@ -2415,23 +2433,20 @@ static u32 XDptx_SetClkSpeed(XDptx *InstancePtr, u32 Speed)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_ERROR_COUNT_MAX if the PHY failed to be ready.
+ * @return      - XST_ERROR_COUNT_MAX if the PHY failed to be ready.
  *              - XST_SUCCESS otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 static u32 XDptx_WaitPhyReady(XDptx *InstancePtr)
 {
         u32 Timeout = 100;
         u32 PhyStatus;
 
-        /* Verify arguments. */
-        Xil_AssertNonvoid(InstancePtr != NULL);
-        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
         /* Wait until the PHY is ready. */
         do {
-                PhyStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+                PhyStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                         XDPTX_PHY_STATUS) &
                                         XDPTX_PHY_STATUS_ALL_LANES_READY_MASK;
 
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
index f16465da..c1ec29ce 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
@@ -34,10 +34,121 @@
  *
  * @file xdptx.h
  *
- * The Xilinx DisplayPort transmitter (TX) driver.
+ * The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
+ * Xilinx DisplayPort soft IP core in source (TX) mode.
+ *
+ * The Xilinx DisplayPort soft IP supports the following features:
+ *      - 1, 2, or 4 lanes.
+ *      - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
+ *      - 1, 2, or 4 pixel-wide video interfaces.
+ *      - RGB and YCbCr color space.
+ *      - Up to 16 bits per component.
+ *      - Up to 4Kx2K monitor resolution.
+ *      - Auto lane rate and width negotiation.
+ *      - I2C over a 1Mb/s AUX channel.
+ *      - Secondary channel audio support (2 channels).
+ *      - 4 independent video multi-streams.
+ *
+ * The Xilinx DisplayPort soft IP does not support the following features:
+ *      - The automated test feature.
+ *      - Audio (3-8 channel).
+ *      - FAUX.
+ *      - Bridging function.
+ *      - MST audio.
+ *      - eDP optional features.
+ *      - iDP.
+ *      - GTC.
+ *
+ * DisplayPort overview
+ *
+ * A DisplayPort link consists of:
+ *      - A unidirectional main link which is used to transport isochronous data
+ *        streams such as video and audio. The main link may use 1, 2, or 4
+ *        lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
+ *        needs to be trained prior to sending streams.
+ *      - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
+ *        link training, link management, and device control.
+ *      - A hot-plug-detect (HPD) signal line is used to determine whether a
+ *        DisplayPort connection exists between the DisplayPort TX connector and
+ *        an RX device. It is serves as an interrupt request by the RX device.
+ *
+ * Driver description
+ *
+ * The device driver enables higher-level software (e.g., an application) to
+ * configure and control a DisplayPort TX soft IP, communicate and control an
+ * RX device/sink monitor over the AUX channel, and to initialize and transmit
+ * data streams over the main link.
+ *
+ * This driver implements link layer functionality: a Link Policy Maker (LPM)
+ * and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
+ * - The LPM manages the main link and is responsible for keeping the link
+ *   synchronized. It will establish a link with a downstream RX device by
+ *   undergoing a link training sequence which consists of:
+ *      - Clock recovery: The clock needs to be recovered and PLLs need to be
+ *        locked for all lanes.
+ *      - Channel equalization: All lanes need to achieve channel equalization
+ *        and and symbol lock, as well as for interlane alignment to take place.
+ * - The SPM manages transportation of an isochronous stream. That is, it will
+ *   initialize and maintain a video stream, establish a virtual channel to a
+ *   sink monitor, and transmit the stream.
+ *
+ * Using AUX transactions to read/write from/to the sink's DisplayPort
+ * Configuration Data (DPCD) address space, the LPM obtains the link
+ * capabilities, obtains link configuration and link and sink status, and
+ * configures and controls the link and sink. The main link is trained this way.
+ *
+ * I2C-over-AUX transactions are used to obtain the sink's Extended Display
+ * Identification Data (EDID) which give information on the display capabilities
+ * of the monitor. The SPM may use this information to determine what available
+ * screen resolutions and video timing are possible.
+ *
+ * Device configuration
+ *
+ * The device can be configured in various ways during the FPGA implementation
+ * process.  Configuration parameters are stored in the xdptx_g.c file which is
+ * generated when compiling the board support package (BSP). A table is defined
+ * where each entry contains configuration information for the DisplayPort
+ * instances present in the system. This information includes parameters that
+ * are defined in the driver's data/dptx.tcl file such as the base address of
+ * the memory-mapped device and the maximum number of lanes, maximum link rate,
+ * and video interface that the DisplayPort instance supports, among others.
+ *
+ * Interrupt processing
+ *
+ * DisplayPort interrupts occur on the HPD signal line when the DisplayPort
+ * cable is connected/disconnected or when the RX device sends a pulse. The user
+ * hardware design must contain an interrupt controller which the DisplayPort
+ * TX instance's interrupt signal is connected to. The user application must
+ * enable interrupts in the system and set up the interrupt controller such that
+ * the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
+ * When the XDptx_HpdInterruptHandler function is invoked, the handler will
+ * identify what type of DisplayPort interrupt has occurred, and will call
+ * either the HPD event handler function or the HPD pulse handler function,
+ * depending on whether a an HPD event on an HPD pulse event occurred.
+ *
+ * The DisplayPort Tx's XDPTX_INTERRUPT_STATUS register indicates the type of
+ * interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
+ * information to decide which handler to call. An HPD event is identified if
+ * bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
+ * identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
+ *
+ * The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
+ * function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
+ * function.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on argument
+ * values. Asserts can be turned off on a system-wide basis by defining, at
+ * compile time, the NDEBUG identifier.  By default, asserts are turned on and
+ * it is recommended that application developers leave asserts on during
+ * development.
  *
  * The driver currently supports single-stream transport (SST) functionality.
  *
+ * @note        For a 5.4Gbps link rate, a high performance 7 series FPGA is
+ *              required with a speed grade of -2 or -3.
+ *
  * 
  * MODIFICATION HISTORY:
  *
@@ -61,12 +172,11 @@
 
 /******************************************************************************/
 /**
- * This macro checks if there is a connected sink.
+ * This macro checks if there is a connected RX device.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - TRUE if there is a connection.
+ * @return      - TRUE if there is a connection.
  *              - FALSE if there is no connection.
  *
  * @note        C-style signature:
@@ -74,7 +184,7 @@
  *
 *******************************************************************************/
 #define XDptx_IsConnected(InstancePtr) \
-        (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, \
+        (XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
         XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
 
 /****************************** Type Definitions ******************************/
@@ -227,23 +337,27 @@ typedef struct {
 } XDptx_Config;
 
 /**
- * This typedef contains configuration information about the sink.
+ * This typedef contains configuration information about the RX device.
  */
 typedef struct {
         u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
                                         /**< The raw capabilities field
-                                                of the sink's DPCD. */
-        u8 Edid[XDPTX_EDID_SIZE];       /**< The sink's raw EDID. */
-        u8 LaneStatusAdjReqs[6];        /**< This is a raw read of the receiver
-                                                DPCD's status registers. The
-                                                first 4 bytes correspond to the
-                                                lane status from the receiver's
-                                                DPCD associated with clock
-                                                recovery, channel equalization,
-                                                symbol lock, and interlane
-                                                alignment. The 2 remaining bytes
-                                                represent the adjustments
-                                                requested by the DPCD. */
+                                                of the RX device's DisplayPort
+                                                Configuration Data (DPCD). */
+        u8 Edid[XDPTX_EDID_SIZE];       /**< The RX device's raw Extended
+                                                Display Identification Data
+                                                (EDID). */
+        u8 LaneStatusAdjReqs[6];        /**< This is a raw read of the
+                                                RX device's status registers.
+                                                The first 4 bytes correspond to
+                                                the lane status associated with
+                                                clock recovery, channel
+                                                equalization, symbol lock, and
+                                                interlane alignment. The
+                                                remaining 2 bytes represent the
+                                                pre-emphasis and voltage swing
+                                                level adjustments requested by
+                                                the RX device. */
 } XDptx_SinkConfig;
 
 /**
@@ -260,14 +374,14 @@ typedef struct {
                                                 use over the main link. */
         u8 DownspreadControl;           /**< Downspread control is currently in
                                                 use over the main link. */
-        u8 MaxLaneCount;                /**< The maximum lane count of the
-                                                source-sink main link. */
-        u8 MaxLinkRate;                 /**< The maximum link rate of the
-                                                source-sink main link. */
+        u8 MaxLaneCount;                /**< The maximum lane count of the main
+                                                link. */
+        u8 MaxLinkRate;                 /**< The maximum link rate of the main
+                                                link. */
         u8 SupportEnhancedFramingMode;  /**< Enhanced frame mode is supported by
-                                                the receiver. */
+                                                the RX device. */
         u8 SupportDownspreadControl;    /**< Downspread control is supported by
-                                                the receiver. */
+                                                the RX device. */
         u8 VsLevel;                     /**< The current voltage swing level for
                                                 each lane. */
         u8 PeLevel;                     /**< The current pre-emphasis/cursor
@@ -334,7 +448,7 @@ typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
 
 /******************************************************************************/ 
 /**
- * Callback type which represents the handler for a hot-plug-detect event
+ * Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
  * interrupt.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
@@ -344,7 +458,7 @@ typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
 
 /******************************************************************************/
 /**
- * Callback type which represents the handler for a hot-plug-detect pulse
+ * Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
  * interrupt.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
@@ -366,10 +480,11 @@ typedef struct {
         u8 HasRedriverInPath;                   /**< Redriver in path requires
                                                         different voltage swing
                                                         and pre-emphasis. */
-        XDptx_Config TxConfig;                  /**< Configuration structure for
-                                                        the core. */
+        XDptx_Config Config;                    /**< Configuration structure for
+                                                        the DisplayPort TX
+                                                        core. */
         XDptx_SinkConfig RxConfig;              /**< Configuration structure for
-                                                        the sink. */
+                                                        the RX device. */
         XDptx_LinkConfig LinkConfig;            /**< Configuration structure for
                                                         the main link. */
         XDptx_MainStreamAttributes MsaConfig;   /**< Configuration structure for
@@ -380,14 +495,14 @@ typedef struct {
         void *UserTimerPtr;                     /**< Pointer to a timer instance
                                                         used by the custom user
                                                         delay/sleep function. */
-        XDptx_HpdEventHandler HpdEventHandler;  /**< Callback function for hot-
-                                                        plug-detect event
+        XDptx_HpdEventHandler HpdEventHandler;  /**< Callback function for Hot-
+                                                        Plug-Detect (HPD) event
                                                         interrupts. */
         void *HpdEventCallbackRef;              /**< A pointer to the user data
                                                         passed to the HPD event
                                                         callback function.*/
-        XDptx_HpdPulseHandler HpdPulseHandler;  /**< Callback function for hot-
-                                                        plug-detect pulse
+        XDptx_HpdPulseHandler HpdPulseHandler;  /**< Callback function for Hot-
+                                                        Plug-Detect (HPD) pulse
                                                         interrupts. */
         void *HpdPulseCallbackRef;              /**< A pointer to the user data
                                                         passed to the HPD pulse
@@ -400,7 +515,7 @@ typedef struct {
 u32 XDptx_InitializeTx(XDptx *InstancePtr);
 void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
                                                         u32 EffectiveAddr);
-u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr);
+u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
 u32 XDptx_GetEdid(XDptx *InstancePtr);
 
 /* xdptx.c: Link policy maker functions. */
@@ -435,12 +550,12 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
 
 /* xdptx_spm.c: Stream policy maker functions. */
 void XDptx_CfgMsaRecalculate(XDptx *InstancePtr);
-u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
+void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
                                                 XDptx_VideoMode VideoMode);
 void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr);
 void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
                 XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
-u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
+void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
 void XDptx_SetVideoMode(XDptx *InstancePtr);
 
 /* xdptx_intr.c: Interrupt handling functions. */
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
index 3842f38a..02520eb7 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
@@ -60,7 +60,7 @@
 
 /******************************************************************************/
 /**
- * Address mapping for the DPTX core.
+ * Address mapping for the DisplayPort TX core.
  *
 *******************************************************************************/
 /** @name DPTX core registers: Link configuration field.
@@ -86,9 +86,9 @@
   * @{
   */
 #define XDPTX_ENABLE                    0x0080  /**< Enable the basic operations
-                                                        of the transmitter or
-                                                        output stuffing symbols
-                                                        if disabled. */
+                                                        of the DisplayPort TX
+                                                        core or output stuffing
+                                                        symbols if disabled. */
 #define XDPTX_ENABLE_MAIN_STREAM        0x0084  /**< Enable transmission of main
                                                         link video info. */
 #define XDPTX_ENABLE_SEC_STREAM         0x0088  /**< Enable the transmission of
@@ -143,6 +143,8 @@
 /** @name DPTX core registers: Main stream attributes for SST / MST STREAM1.
   * @{
   */
+#define XDPTX_STREAM1_MSA_START         0x0180  /**< Start of the MSA registers
+                                                        for stream 1. */
 #define XDPTX_MAIN_STREAM_HTOTAL        0x0180  /**< Total number of clocks in
                                                         the horizontal framing
                                                         period. */
@@ -279,223 +281,45 @@
                                                         CEA 861-C info frame. */
 #define XDPTX_TX_AUDIO_MAUD             0x0328  /**< M value of audio stream
                                                         as computed by the
-                                                        transmitter when audio
-                                                        clock and link clock are
-                                                        synchronous. */
+                                                        DisplayPort TX core when
+                                                        audio and link clocks
+                                                        are synchronous. */
 #define XDPTX_TX_AUDIO_NAUD             0x032C  /**< N value of audio stream
                                                         as computed by the
-                                                        transmitter when audio
-                                                        clock and link clock are
-                                                        synchronous. */
+                                                        DisplayPort TX core when
+                                                        audio and link clocks
+                                                        are synchronous. */
 #define XDPTX_TX_AUDIO_EXT_DATA         0x0330  /**< Word formatted as per
                                                         extension packet. */
 /* @} */
 
-/** @name DPTX core registers: Main stream attributes for MST STREAM2.
+/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.
   * @{
   */
-#define XDPTX_MAIN_STREAM2_HTOTAL       0x0500  /**< Total number of clocks in
-                                                        the horizontal framing
-                                                        period. */
-#define XDPTX_MAIN_STREAM2_VTOTAL       0x0504  /**< Total number of lines in
-                                                        the video frame. */
-#define XDPTX_MAIN_STREAM2_POLARITY     0x0508  /**< Polarity for the video sync
-                                                        signals. */
-#define XDPTX_MAIN_STREAM2_HSWIDTH      0x050C  /**< Width of the horizontal
-                                                        sync pulse. */
-#define XDPTX_MAIN_STREAM2_VSWIDTH      0x0510  /**< Width of the vertical sync
-                                                        pulse. */
-#define XDPTX_MAIN_STREAM2_HRES         0x0514  /**< Number of active pixels per
-                                                        line (the horizontal
-                                                        resolution). */
-#define XDPTX_MAIN_STREAM2_VRES         0x0518  /**< Number of active lines (the
-                                                        vertical resolution). */
-#define XDPTX_MAIN_STREAM2_HSTART       0x051C  /**< Number of clocks between
-                                                        the leading edge of the
-                                                        horizontal sync and the
-                                                        start of active data. */
-#define XDPTX_MAIN_STREAM2_VSTART       0x0520  /**< Number of lines between the
-                                                        leading edge of the
-                                                        vertical sync and the
-                                                        first line of active
-                                                        data. */
-#define XDPTX_MAIN_STREAM2_MISC0        0x0524  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_MAIN_STREAM2_MISC1        0x0528  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_M_VID_STREAM2             0x052C  /**< M value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_TU_SIZE_STREAM2           0x0530  /**< Size of a transfer unit in
-                                                        the framing logic. */
-#define XDPTX_N_VID_STREAM2             0x0534  /**< N value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_USER_PIXEL_WIDTH_STREAM2  0x0538  /**< Selects the width of the
-                                                        user data input port. */
-#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2 \
-                                        0x053C  /**< Used to translate the
-                                                        number of pixels per
-                                                        line to the native
-                                                        internal 16-bit
-                                                        datapath. */
-#define XDPTX_MAIN_STREAM2_INTERLACED   0x0540  /**< Video is interlaced. */
-#define XDPTX_MIN_BYTES_PER_TU_STREAM2  0x0544  /**< The minimum number of bytes
-                                                        per transfer unit. */
-#define XDPTX_FRAC_BYTES_PER_TU_STREAM2 0x0548  /**< The fractional component
-                                                        when calculated the
-                                                        XDPTX_MIN_BYTES_PER_TU
-                                                        register value. */
-#define XDPTX_INIT_WAIT_STREAM2         0x054C  /**< Number of initial wait
-                                                        cycles at the start of a
-                                                        new line by the framing
-                                                        logic, allowing enough
-                                                        data to be buffered in
-                                                        the input FIFO. */
-/* @} */
-
-/** @name DPTX core registers: Main stream attributes for MST STREAM3.
-  * @{
-  */
-#define XDPTX_MAIN_STREAM3_HTOTAL       0x0550  /**< Total number of clocks in
-                                                        the horizontal framing
-                                                        period. */
-#define XDPTX_MAIN_STREAM3_VTOTAL       0x0554  /**< Total number of lines in
-                                                        the video frame. */
-#define XDPTX_MAIN_STREAM3_POLARITY     0x0558  /**< Polarity for the video sync
-                                                        signals. */
-#define XDPTX_MAIN_STREAM3_HSWIDTH      0x055C  /**< Width of the horizontal
-                                                        sync pulse. */
-#define XDPTX_MAIN_STREAM3_VSWIDTH      0x0560  /**< Width of the vertical sync
-                                                        pulse. */
-#define XDPTX_MAIN_STREAM3_HRES         0x0564  /**< Number of active pixels per
-                                                        line (the horizontal
-                                                        resolution). */
-#define XDPTX_MAIN_STREAM3_VRES         0x0568  /**< Number of active lines (the
-                                                        vertical resolution). */
-#define XDPTX_MAIN_STREAM3_HSTART       0x056C  /**< Number of clocks between
-                                                        the leading edge of the
-                                                        horizontal sync and the
-                                                        start of active data. */
-#define XDPTX_MAIN_STREAM3_VSTART       0x0570  /**< Number of lines between the
-                                                        leading edge of the
-                                                        vertical sync and the
-                                                        first line of active
-                                                        data. */
-#define XDPTX_MAIN_STREAM3_MISC0        0x0574  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_MAIN_STREAM3_MISC1        0x0578  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_M_VID_STREAM3             0x057C  /**< M value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_TU_SIZE_STREAM3           0x0580  /**< Size of a transfer unit in
-                                                        the framing logic. */
-#define XDPTX_N_VID_STREAM3             0x0584  /**< N value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_USER_PIXEL_WIDTH_STREAM3  0x0588  /**< Selects the width of the
-                                                        user data input port. */
-#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3 \
-                                        0x058C  /**< Used to translate the
-                                                        number of pixels per
-                                                        line to the native
-                                                        internal 16-bit
-                                                        datapath. */
-#define XDPTX_MAIN_STREAM3_INTERLACED   0x0590  /**< Video is interlaced. */
-#define XDPTX_MIN_BYTES_PER_TU_STREAM3  0x0594  /**< The minimum number of bytes
-                                                        per transfer unit. */
-#define XDPTX_FRAC_BYTES_PER_TU_STREAM3 0x0598  /**< The fractional component
-                                                        when calculated the
-                                                        XDPTX_MIN_BYTES_PER_TU
-                                                        register value. */
-#define XDPTX_INIT_WAIT_STREAM3         0x059C  /**< Number of initial wait
-                                                        cycles at the start of a
-                                                        new line by the framing
-                                                        logic, allowing enough
-                                                        data to be buffered in
-                                                        the input FIFO. */
-/* @} */
-
-/** @name DPTX core registers: Main stream attributes for MST STREAM4.
-  * @{
-  */
-#define XDPTX_MAIN_STREAM4_HTOTAL       0x05A0  /**< Total number of clocks in
-                                                        the horizontal framing
-                                                        period. */
-#define XDPTX_MAIN_STREAM4_VTOTAL       0x05A4  /**< Total number of lines in
-                                                        the video frame. */
-#define XDPTX_MAIN_STREAM4_POLARITY     0x05A8  /**< Polarity for the video sync
-                                                        signals. */
-#define XDPTX_MAIN_STREAM4_HSWIDTH      0x05AC  /**< Width of the horizontal
-                                                        sync pulse. */
-#define XDPTX_MAIN_STREAM4_VSWIDTH      0x05B0  /**< Width of the vertical sync
-                                                        pulse. */
-#define XDPTX_MAIN_STREAM4_HRES         0x05B4  /**< Number of active pixels per
-                                                        line (the horizontal
-                                                        resolution). */
-#define XDPTX_MAIN_STREAM4_VRES         0x05B8  /**< Number of active lines (the
-                                                        vertical resolution). */
-#define XDPTX_MAIN_STREAM4_HSTART       0x05BC  /**< Number of clocks between
-                                                        the leading edge of the
-                                                        horizontal sync and the
-                                                        start of active data. */
-#define XDPTX_MAIN_STREAM4_VSTART       0x05C0  /**< Number of lines between the
-                                                        leading edge of the
-                                                        vertical sync and the
-                                                        first line of active
-                                                        data. */
-#define XDPTX_MAIN_STREAM4_MISC0        0x05C4  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_MAIN_STREAM4_MISC1        0x05C8  /**< Miscellaneous stream
-                                                        attributes. */
-#define XDPTX_M_VID_STREAM4             0x05CC  /**< M value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_TU_SIZE_STREAM4           0x05D0  /**< Size of a transfer unit in
-                                                        the framing logic. */
-#define XDPTX_N_VID_STREAM4             0x05D4  /**< N value for the video
-                                                        stream as computed by
-                                                        the source core in
-                                                        asynchronous clock mode.
-                                                        Must be written in
-                                                        synchronous mode. */
-#define XDPTX_USER_PIXEL_WIDTH_STREAM4  0x05D8  /**< Selects the width of the
-                                                        user data input port. */
-#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4 \
-                                        0x05DC  /**< Used to translate the
-                                                        number of pixels per
-                                                        line to the native
-                                                        internal 16-bit
-                                                        datapath. */
-#define XDPTX_MAIN_STREAM4_INTERLACED   0x05E0  /**< Video is interlaced. */
-#define XDPTX_MIN_BYTES_PER_TU_STREAM4  0x05E4  /**< The minimum number of bytes
-                                                        per transfer unit. */
-#define XDPTX_FRAC_BYTES_PER_TU_STREAM4 0x05E8  /**< The fractional component
-                                                        when calculated the
-                                                        XDPTX_MIN_BYTES_PER_TU
-                                                        register value. */
-#define XDPTX_INIT_WAIT_STREAM4         0x05EC  /**< Number of initial wait
-                                                        cycles at the start of a
-                                                        new line by the framing
-                                                        logic, allowing enough
-                                                        data to be buffered in
-                                                        the input FIFO. */
+#define XDPTX_STREAM2_MSA_START         0x0500  /**< Start of the MSA registers
+                                                        for stream 2. */
+#define XDPTX_STREAM2_MSA_START_OFFSET  (XDPTX_STREAM2_MSA_START - \
+                XDPTX_STREAM1_MSA_START)        /**< The MSA registers for
+                                                        stream 2 are at an
+                                                        offset from the
+                                                        corresponding registers
+                                                        of stream 1. */
+#define XDPTX_STREAM3_MSA_START         0x0550  /**< Start of the MSA registers
+                                                        for stream 3. */
+#define XDPTX_STREAM3_MSA_START_OFFSET  (XDPTX_STREAM3_MSA_START - \
+                XDPTX_STREAM1_MSA_START)        /**< The MSA registers for
+                                                        stream 2 are at an
+                                                        offset from the
+                                                        corresponding registers
+                                                        of stream 1. */
+#define XDPTX_STREAM4_MSA_START         0x05A0  /**< Start of the MSA registers
+                                                        for stream 4. */
+#define XDPTX_STREAM4_MSA_START_OFFSET  (XDPTX_STREAM4_MSA_START - \
+                XDPTX_STREAM1_MSA_START)        /**< The MSA registers for
+                                                        stream 2 are at an
+                                                        offset from the
+                                                        corresponding registers
+                                                        of stream 1. */
 /* @} */
 
 #define XDPTX_VC_PAYLOAD_BUFFER_ADDR    0x0800  /**< Virtual channel payload
@@ -510,6 +334,10 @@
 #define XDPTX_LINK_BW_SET_162GBPS       0x06    /**< 1.62 Gbps link rate. */
 #define XDPTX_LINK_BW_SET_270GBPS       0x0A    /**< 2.70 Gbps link rate. */
 #define XDPTX_LINK_BW_SET_540GBPS       0x14    /**< 5.40 Gbps link rate. */
+/* 0x001: LANE_COUNT_SET */
+#define XDPTX_LANE_COUNT_SET_1          0x01    /**< Lane count of 1. */
+#define XDPTX_LANE_COUNT_SET_2          0x02    /**< Lane count of 2. */
+#define XDPTX_LANE_COUNT_SET_4          0x04    /**< Lane count of 4. */
 /* 0x00C: TRAINING_PATTERN_SET */
 #define XDPTX_TRAINING_PATTERN_SET_OFF  0x0     /**< Training off. */
 #define XDPTX_TRAINING_PATTERN_SET_TP1  0x1     /**< Training pattern 1 used for
@@ -722,7 +550,7 @@
                                 4               /**< Shift bits for the internal
                                                         AUX reply state machine
                                                         status. */
-/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[0-4]_POLARITY */
+/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[1-4]_POLARITY */
 #define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \
                                 0x00000001      /**< Polarity of the horizontal
                                                         sync pulse. */
@@ -733,7 +561,7 @@
                                 1               /**< Shift bits for polarity of
                                                         the vertical sync
                                                         pulse. */
-/* 0x1A4, 0x524, 0x578, 0x5C8: MAIN_STREAM[0-4]_MISC0 */
+/* 0x1A4, 0x524, 0x574, 0x5C4: MAIN_STREAM[1-4]_MISC0 */
 #define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \
                                 0x00000001      /**< Synchronous clock. */
 #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \
@@ -741,6 +569,15 @@
 #define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \
                                 1               /**< Shift bits for component
                                                         format. */
+#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB \
+                                0x0             /**< Stream's component format
+                                                        is RGB. */
+#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 \
+                                0x1             /**< Stream's component format
+                                                        is YcbCr 4:2:2. */
+#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 \
+                                0x2             /**< Stream's component format
+                                                        is YcbCr 4:4:4. */
 #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \
                                 0x00000008      /**< Dynamic range. */
 #define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \
@@ -756,7 +593,17 @@
                                                         component (BDC). */
 #define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT \
                                 5               /**< Shift bits for BDC.*/
-/* 0x1A8, 0x528, 0x5C8: MAIN_STREAM[0-4]_MISC1 */
+#define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC \
+                                0x0             /**< 6 bits per component.*/
+#define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC \
+                                0x1             /**< 8 bits per component.*/
+#define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC \
+                                0x2             /**< 10 bits per component.*/
+#define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC \
+                                0x3             /**< 12 bits per component.*/
+#define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC \
+                                0x4             /**< 16 bits per component.*/
+/* 0x1A8, 0x528, 0x578, 0x5C8: MAIN_STREAM[1-4]_MISC1 */
 #define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \
                                 0x00000001      /**< Interlaced vertical total
                                                         even. */
@@ -877,11 +724,12 @@
 
 /******************************************************************************/
 /**
- * Address mapping for the DPCD of the downstream device.
+ * Address mapping for the DisplayPort Configuration Data (DPCD) of the
+ * downstream device.
  *
 *******************************************************************************/
-/** @name DPCD: Receiver capability field.
-  *
+/** @name DisplayPort Configuration Data: Receiver capability field.
+  * @{
   */
 #define XDPTX_DPCD_REV                                  0x00000
 #define XDPTX_DPCD_MAX_LINK_RATE                        0x00001
@@ -930,8 +778,8 @@
 #define XDPTX_DPCD_DOWNSP_3_DET_CAP                     0x0008C
 /* @} */
 
-/** @name DPCD: Link configuration field.
-  *
+/** @name DisplayPort Configuration Data: Link configuration field.
+  * @{
   */
 #define XDPTX_DPCD_LINK_BW_SET                          0x00100
 #define XDPTX_DPCD_LANE_COUNT_SET                       0x00101
@@ -973,8 +821,8 @@
 #define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT     0x001C2
 /* @} */
 
-/** @name DPCD: Link/sink status field.
-  *
+/** @name DisplayPort Configuration Data: Link/sink status field.
+  * @{
   */
 #define XDPTX_DPCD_SINK_COUNT                           0x00200
 #define XDPTX_DPCD_DEVICE_SERVICE_IRQ                   0x00201
@@ -996,7 +844,7 @@
 #define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3            0x00216
 /* @} */
 
-/** @name DPCD: Automated testing sub-field.
+/** @name DisplayPort Configuration Data: Automated testing sub-field.
   * @{
   */
 #define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS               0x00280
@@ -1007,13 +855,13 @@
                         (XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
 /* @} */
 
-/** @name DPCD: Sink control field.
+/** @name DisplayPort Configuration Data: Sink control field.
   * @{
   */
 #define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE             0x00600
 /* @} */
 
-/** @name DPCD: Sideband MSG buffers.
+/** @name DisplayPort Configuration Data: Sideband message buffers.
   * @{
   */
 #define XDPTX_DPCD_DOWN_REQ                             0x01000
@@ -1022,7 +870,7 @@
 #define XDPTX_DPCD_UP_REQ                               0x01600
 /* @} */
 
-/** @name DPCD: Event status indicator field.
+/** @name DisplayPort Configuration Data: Event status indicator field.
   * @{
   */
 #define XDPTX_DPCD_SINK_COUNT_ESI                       0x02002
@@ -1035,7 +883,7 @@
 #define XDPTX_DPCD_SINK_STATUS_ESI                      0x0200F
 /* @} */
 
-/** @name DPCD: Field addresses and sizes.
+/** @name DisplayPort Configuration Data: Field addresses and sizes.
   * @{
   */
 #define XDPTX_DPCD_RECEIVER_CAP_FIELD_START             XDPTX_DPCD_REV
@@ -1048,8 +896,9 @@
 
 /******************************************************************************/
 
-/** @name DPCD: Receiver capability field masks, shifts, and register values.
-  *
+/** @name DisplayPort Configuration Data: Receiver capability field masks,
+  *       shifts, and register values.
+  * @{
   */
 /* 0x00000: DPCD_REV */
 #define XDPTX_DPCD_REV_MNR_MASK                                 0x0F
@@ -1061,6 +910,9 @@
 #define XDPTX_DPCD_MAX_LINK_RATE_540GBPS                        0x14
 /* 0x00002: MAX_LANE_COUNT */
 #define XDPTX_DPCD_MAX_LANE_COUNT_MASK                          0x1F
+#define XDPTX_DPCD_MAX_LANE_COUNT_1                             0x01
+#define XDPTX_DPCD_MAX_LANE_COUNT_2                             0x02
+#define XDPTX_DPCD_MAX_LANE_COUNT_4                             0x04
 #define XDPTX_DPCD_TPS3_SUPPORT_MASK                            0x40
 #define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK                  0x80
 /* 0x00003: MAX_DOWNSPREAD */
@@ -1132,8 +984,9 @@
 #define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK                   0x04
 /* @} */
 
-/** @name DPCD: Link configuration field masks, shifts, and register values.
-  *
+/** @name DisplayPort Configuration Data: Link configuration field masks,
+  *       shifts, and register values.
+  * @{
   */
 /* 0x00100: XDPTX_DPCD_LINK_BW_SET */
 #define XDPTX_DPCD_LINK_BW_SET_162GBPS                          0x06
@@ -1141,6 +994,9 @@
 #define XDPTX_DPCD_LINK_BW_SET_540GBPS                          0x14
 /* 0x00101: LANE_COUNT_SET */
 #define XDPTX_DPCD_LANE_COUNT_SET_MASK                          0x1F
+#define XDPTX_DPCD_LANE_COUNT_SET_1                             0x01
+#define XDPTX_DPCD_LANE_COUNT_SET_2                             0x02
+#define XDPTX_DPCD_LANE_COUNT_SET_4                             0x04
 #define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK                       0x80
 /* 0x00102: TP_SET */
 #define XDPTX_DPCD_TP_SEL_MASK                                  0x03
@@ -1184,8 +1040,9 @@
 #define XDPTX_DPCD_UP_IS_SRC_MASK                               0x03
 /* @} */
 
-/** @name DPCD: Link/sink status field masks, shifts, and register values.
-  *
+/** @name DisplayPort Configuration Data: Link/sink status field masks, shifts,
+  *       and register values.
+  * @{
   */
 /* 0x00202: STATUS_LANE_0_1 */
 #define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK                   0x01
@@ -1234,10 +1091,11 @@
 
 /******************************************************************************/
 /**
- * Address mapping for the EDID of the downstream device.
+ * Address mapping for the Extended Display Identification Data (EDID) of the
+ * downstream device.
  *
 *******************************************************************************/
-/** @name EDID: Field addresses and sizes.
+/** @name Extended Display Identification Data: Field addresses and sizes.
   * @{
   */
 #define XDPTX_EDID_ADDR                                 0x50
@@ -1246,7 +1104,8 @@
 #define XDPTX_EDID_PTM                                  XDPTX_EDID_DTD_DD(0)
 /* @} */
 
-/** @name EDID: Register offsets for the DTD (detailed timing descriptor).
+/** @name Extended Display Identification Data: Register offsets for the
+  *       Detailed Timing Descriptor (DTD).
   * @{
   */
 #define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB                0x00
@@ -1268,7 +1127,8 @@
 #define XDPTX_EDID_DTD_VBORDER                          0x10
 #define XDPTX_EDID_DTD_SIGNAL                           0x11
 
-/** @name EDID: Masks, shifts, and register values.
+/** @name Extended Display Identification Data: Masks, shifts, and register
+  *       values.
   * @{
   */
 #define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK       0x0F
@@ -1326,6 +1186,8 @@
  * @param       RegOffset is the register offset to write to.
  * @param       Data is the 32-bit data to write to the specified register.
  *
+ * @return      None.
+ *
  * @note        C-style signature:
  *              void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
  *
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
index 431ea0f4..8fb61552 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
@@ -36,6 +36,8 @@
  *
  * This file contains functions related to XDptx interrupt handling.
  *
+ * @note        None.
+ *
  * 
  * MODIFICATION HISTORY:
  *
@@ -62,6 +64,10 @@
  * @param       CallbackRef is the user data item that will be passed to the
  *              callback function when it is invoked.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
                         XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
@@ -85,6 +91,10 @@ void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
  * @param       CallbackRef is the user data item that will be passed to the
  *              callback function when it is invoked.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
                         XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
@@ -107,6 +117,10 @@ void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
  * 
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
 {
@@ -120,9 +134,9 @@ void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
 
         /* Determine what kind of interrupt occurred.
          * Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
-        IntrStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+        IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                                         XDPTX_INTERRUPT_STATUS);
-        IntrStatus &= ~XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+        IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                                         XDPTX_INTERRUPT_MASK);
 
         HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
@@ -136,7 +150,7 @@ void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
         if (HpdPulseDetected) {
 		/* The source device must debounce the incoming HPD signal by
 		 * sampling the value at an interval greater than 250 ms. */
-                HpdDuration = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
+                HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
                                                         XDPTX_HPD_DURATION);
                 if (HpdDuration >= 250) {
                         InstancePtr->HpdPulseHandler(
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
index 78151b3f..baf5174f 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
@@ -36,6 +36,8 @@
  *
  * This file contains a diagnostic self-test function for the XDptx driver.
  *
+ * @note        None.
+ *
  * 
  * MODIFICATION HISTORY:
  *
@@ -57,16 +59,17 @@
 /**
  * This function runs a self-test on the XDptx driver/device. The test attempts
  * to intialize the DisplayPort TX core, train the main link at the highest
- * common capabilities between the core and the sink, and checks the status
+ * common capabilities between the core and the RX device, and checks the status
  * of the link after training.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
- * @return
- *              - XST_SUCCESS if the self-test passed. The main link has been
+ * @return      - XST_SUCCESS if the self-test passed. The main link has been
  *                trained and established successfully.
  *              - XST_FAILURE otherwise.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 u32 XDptx_SelfTest(XDptx *InstancePtr)
 {
@@ -77,8 +80,9 @@ u32 XDptx_SelfTest(XDptx *InstancePtr)
         Xil_AssertNonvoid(InstancePtr != NULL);
         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-        /* Obtain the capabilities of the sink by reading the DPCD. */
-        Status = XDptx_GetSinkCapabilities(InstancePtr);
+        /* Obtain the capabilities of the RX device by reading the DisplayPort
+         * Configuration Data (DPCD). */
+        Status = XDptx_GetRxCapabilities(InstancePtr);
         if (Status != XST_SUCCESS) {
                 return XST_FAILURE;
         }
@@ -90,7 +94,7 @@ u32 XDptx_SelfTest(XDptx *InstancePtr)
         }
 
         /* Attempt to establish a link at the maximum common capabilities
-         * between the DisplayPort TX core and the sink. */
+         * between the DisplayPort TX core and the RX device. */
         XDptx_EstablishLink(InstancePtr);
 
         /* Return whether or not the link has been successfully trained. */
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
index 90e690b3..08183a93 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
@@ -36,6 +36,8 @@
  *
  * This file contains static initialization methods for the XDptx driver.
  *
+ * @note        None.
+ *
  * 
  * MODIFICATION HISTORY:
  *
@@ -72,6 +74,8 @@ extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
  * @return      A pointer to the configuration table entry corresponding to the
  *              given device ID, or NULL if no match is found.
  *
+ * @note        None.
+ *
 *******************************************************************************/
 XDptx_Config *XDptx_LookupConfig(u16 DeviceId)
 {
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
index f47c3731..a974a6fc 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
@@ -38,6 +38,8 @@
  * These functions set up the DisplayPort TX core's main stream attributes that
  * determine how a video stream will be displayed.
  *
+ * @note        None.
+ *
  * 
  * MODIFICATION HISTORY:
  *
@@ -64,7 +66,7 @@ static void XDptx_SetMsaValues(XDptx *InstancePtr,
 
 /******************************************************************************/
 /**
- * This function calculates the following main stream attributes:
+ * This function calculates the following Main Stream Attributes (MSA):
  *      - Transfer unit size
  *      - User pixel width
  *      - NVid
@@ -93,6 +95,8 @@ static void XDptx_SetMsaValues(XDptx *InstancePtr,
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      None.
+ *
  * @note        The MsaConfig structure is modified with the new, calculated
  *              values. The main stream attributes that were used to derive the
  *              calculated values are untouched in the MsaConfig structure.
@@ -107,16 +111,35 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
 
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
+                        (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
+                        (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
+        Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
+                        (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
+                        (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
+        Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
+                                        (LinkConfig->SynchronousClockMode == 1));
+        Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
+                                        (LinkConfig->DynamicRange == 1));
+        Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
+                                        (LinkConfig->YCbCrColorimetry == 1));
+        Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
+                                        (MsaConfig->BitsPerColor == 8) ||
+                                        (MsaConfig->BitsPerColor == 10) ||
+                                        (MsaConfig->BitsPerColor == 12) ||
+                                        (MsaConfig->BitsPerColor == 16));
 
-        /* For SST. */
+        /* Fixed transfer unit size. */
         MsaConfig->TransferUnitSize = 64;
 
         /* Set the user pixel width to handle clocks that exceed the
          * capabilities of the DisplayPort TX core. */
-        if ((MsaConfig->MVid > 150000) && (LinkConfig->LaneCount == 4)) {
+        if ((MsaConfig->MVid > 300000) &&
+                        (LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
                 MsaConfig->UserPixelWidth = 4;
         }
-        else if ((MsaConfig->MVid > 80000) && (LinkConfig->LaneCount == 2)) {
+        else if ((MsaConfig->MVid > 75000) &&
+                        (LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
                 MsaConfig->UserPixelWidth = 2;
         }
         else {
@@ -124,11 +147,7 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
         }
 
         /* Compute the rest of the MSA values. */
-        MsaConfig->NVid = (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS) ?
-                                540000 :
-                        (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ?
-                                270000 :
-                        162000;
+        MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
         MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
         MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
         MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
@@ -137,32 +156,51 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
         MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
                                 MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
                                 MsaConfig->VResolution);
-        MsaConfig->Misc0 = (MsaConfig->BitsPerColor == 6) ? 0x00 :
-                                (MsaConfig->BitsPerColor == 8) ? 0x01 :
-                                (MsaConfig->BitsPerColor == 10) ? 0x02 :
-                                (MsaConfig->BitsPerColor == 12) ? 0x03 :
-                                (MsaConfig->BitsPerColor == 16) ? 0x04 :
-                                0x00;
-        MsaConfig->Misc0 = MsaConfig->Misc0 <<
-                                        XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT;
-        MsaConfig->Misc0 = MsaConfig->Misc0 | (LinkConfig->ComponentFormat <<
-                        XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
-                        (LinkConfig->DynamicRange <<
-                        XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
+
+        /* Miscellaneous attributes. */
+        if (MsaConfig->BitsPerColor == 6) {
+                MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
+        }
+        else if (MsaConfig->BitsPerColor == 8) {
+                MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
+        }
+        else if (MsaConfig->BitsPerColor == 10) {
+                MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
+        }
+        else if (MsaConfig->BitsPerColor == 12) {
+                MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
+        }
+        else if (MsaConfig->BitsPerColor == 16) {
+                MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
+        }
+        MsaConfig->Misc0 = (MsaConfig->Misc0 <<
+                        XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
                         (LinkConfig->YCbCrColorimetry <<
                         XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
-                        (LinkConfig->SynchronousClockMode &
-                        XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK);
+                        (LinkConfig->DynamicRange <<
+                        XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
+                        (LinkConfig->ComponentFormat <<
+                        XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
+                        (LinkConfig->SynchronousClockMode);
         MsaConfig->Misc1 = 0;
+
         MsaConfig->DataPerLane = (MsaConfig->HResolution *
                 MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
 
-        /* If RGB | YCbCr444, * 3 ; If YCbCr422, * 2 ; If YOnly, * 1. */
-        BitsPerPixel = (LinkConfig->ComponentFormat == 1) ?
-                        MsaConfig->BitsPerColor * 2 :
-                        MsaConfig->BitsPerColor * 3;
-        VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
+        /* Determine the number of bits per pixel for the specified color
+         * component format. */
+        if (LinkConfig->ComponentFormat ==
+                        XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
+                /* YCbCr422 color component format. */
+                BitsPerPixel = MsaConfig->BitsPerColor * 2;
+        }
+        else {
+                /* RGB or YCbCr 4:4:4 color component format. */
+                BitsPerPixel = MsaConfig->BitsPerColor * 3;
+        }
 
+        /* Calculate the transfer unit size. */
+        VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
         MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
                         (LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
 
@@ -184,39 +222,32 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
 
 /******************************************************************************/
 /**
- * This function sets the main stream attribute values in the configuration
- * structure to match one of the standard display mode timings from the
- * XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists
- * the available video modes.
+ * This function sets the Main Stream Attribute (MSA) values in the
+ * configuration structure to match one of the standard display mode timings
+ * from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The
+ * XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  * @param       VideoMode is one of the enumerated standard video modes that is
- *              used to determine the main stream attributes to be used.
+ *              used to determine the MSA values to be used.
  *
- * @return
- *              - XST_INVALID_PARAM if the supplied video mode isn't in the DMT
- *                table.
- *              - XST_SUCCESS otherwise.
+ * @return      None.
  *
  * @note        The InstancePtr->MsaConfig structure is modified to reflect the
- *              main stream attribute values associated to the specified video
- *              mode.
+ *              MSA values associated to the specified video mode.
  *
 *******************************************************************************/
-u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
+void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
                                                 XDptx_VideoMode VideoMode)
 {
         XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
 
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(MsaConfig != NULL);
+        Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
 
-        if (VideoMode > XDPTX_VM_LAST) {
-                return XST_INVALID_PARAM;
-        }
-
-        /* Configure the main stream attribute values from the display monitor
-         * timing (DMT) table. */
+        /* Configure the MSA values from the display monitor DMT table. */
         MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
         MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
         MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
@@ -231,19 +262,19 @@ u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
 
         /* Calculate the rest of the MSA values. */
         XDptx_CfgMsaRecalculate(InstancePtr);
-
-        return XST_SUCCESS;
 }
 
 /******************************************************************************/
 /**
  * This function sets the main stream attribute values in the configuration
- * structure to match the preferred timing of the sink monitor. This preferred
- * timing information is stored in the sink's extended display identification
- * data (EDID).
+ * structure to match the preferred timing of the sink monitor. This Preferred
+ * Timing Mode (PTM) information is stored in the sink's Extended Display
+ * Identification Data (EDID).
  *
  * @param       InstancePtr is a pointer to the XDptx instance
  *
+ * @return      None.
+ *
  * @note        The InstancePtr->MsaConfig structure is modified to reflect the
  *              main stream attribute values associated to the preferred timing
  *              of the sink monitor.
@@ -256,9 +287,11 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
 
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(MsaConfig != NULL);
+        Xil_AssertVoid(Ptm != NULL);
 
-        /* Configure the MSA values with the preferred timing mode (PTM) as
-         * specified by the preferred detailed timing descriptor of the
+        /* Configure the MSA values with the PTM information as
+         * specified by the preferred Detailed Timing Descriptor (DTD) of the
          * monitor's EDID.
          * Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
          * versions may not contain this information. */
@@ -351,6 +384,8 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
  * @param       Recalculate is a boolean enable that determines whether or not
  *              the main stream attributes should be recalculated.
  *
+ * @return      None.
+ *
  * @note        The InstancePtr-> MsaConfig structure is modified with the new
  *              values.
  *
@@ -362,6 +397,7 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
 
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(MsaConfig != NULL);
         Xil_AssertVoid(MsaConfigCustom != NULL);
 
         /* Copy the MSA values from the user configuration structure. */
@@ -406,38 +442,25 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
  * @param       InstancePtr is a pointer to the XDptx instance
  * @param       BitsPerColor is the new number of bits per color to use.
  *
+ * @return      None.
+ *
  * @note        The InstancePtr->MsaConfig structure is modified to reflect the
  *              new main stream attributes associated with a new bits per color
  *              value.
  *
- * @return
- *              - XST_INVALID_PARAM if the supplied bits per color value is not
- *                either 6, 8, 10, 12, or 16.
- *              - XST_SUCCESS otherwise.
- *
 *******************************************************************************/
-u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
+void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
 {
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
-
-        switch (BitsPerColor) {
-        case 6:
-        case 8:
-        case 10:
-        case 12:
-        case 16:
-                break;
-        default:
-                return XST_INVALID_PARAM;
-        }
+        Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
+                                (BitsPerColor == 10) || (BitsPerColor == 12) ||
+                                (BitsPerColor == 16));
 
         InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
 
         /* Calculate the rest of the MSA values. */
         XDptx_CfgMsaRecalculate(InstancePtr);
-
-        return XST_SUCCESS;
 }
 
 /******************************************************************************/
@@ -448,11 +471,17 @@ u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
  *
  * @param       InstancePtr is a pointer to the XDptx instance
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 void XDptx_SetVideoMode(XDptx *InstancePtr)
 {
         /* Verify arguments. */
         Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
 
         XDptx_ClearMsaValues(InstancePtr);
         XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
@@ -465,33 +494,34 @@ void XDptx_SetVideoMode(XDptx *InstancePtr)
  *
  * @param       InstancePtr is a pointer to the XDptx instance.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 static void XDptx_ClearMsaValues(XDptx *InstancePtr)
 {
-        /* Verify arguments. */
-        Xil_AssertVoid(InstancePtr != NULL);
+        XDptx_Config *Config = &InstancePtr->Config;
 
-        XDptx_Config *TxConfig = &InstancePtr->TxConfig;
-
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, 0);
-	XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, 0);
+	XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT, 0);
 }
 
 /******************************************************************************/
@@ -504,58 +534,58 @@ static void XDptx_ClearMsaValues(XDptx *InstancePtr)
  * @param       MsaConfig is a pointer to the main stream attributes
  *              configuration structure.
  *
+ * @return      None.
+ *
+ * @note        None.
+ *
 *******************************************************************************/
 static void XDptx_SetMsaValues(XDptx *InstancePtr,
                                         XDptx_MainStreamAttributes *MsaConfig)
 {
-        /* Verify arguments. */
-        Xil_AssertVoid(InstancePtr != NULL);
-        Xil_AssertVoid(MsaConfig != NULL);
-
-        XDptx_Config *TxConfig = &InstancePtr->TxConfig;
+        XDptx_Config *Config = &InstancePtr->Config;
 
         /* Set the main stream attributes to the associated DisplayPort TX core
          * registers. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
                 MsaConfig->HClkTotal);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
                 MsaConfig->VClkTotal);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
                 MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
                 XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
                 MsaConfig->HSyncPulseWidth);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
                 MsaConfig->VSyncPulseWidth);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
                 MsaConfig->HResolution);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
                 MsaConfig->VResolution);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
                 MsaConfig->HStart);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
                 MsaConfig->VStart);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
                 MsaConfig->Misc0);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
                 MsaConfig->Misc1);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
                 MsaConfig->MVid);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
                 MsaConfig->NVid);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
                 MsaConfig->UserPixelWidth);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
                 MsaConfig->DataPerLane);
 
         /* Set the transfer unit values to the associated DisplayPort TX core
          * registers. */
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
                 MsaConfig->TransferUnitSize);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
                 MsaConfig->AvgBytesPerTU / 1000);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
                 MsaConfig->AvgBytesPerTU % 1000);
-        XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT,
+        XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
                 MsaConfig->InitWait);
 }
diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
index 41af9e19..270ca6aa 100644
--- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
+++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
@@ -36,6 +36,8 @@
  *
  * Contains display monitor timing (DMT) modes for various standard resolutions.
  *
+ * @note        None.
+ *
  * 
  * MODIFICATION HISTORY:
  *