| xdptx.c | |
| xdptx.h | |
| xdptx_edid.c | |
| xdptx_hw.h | |
| xdptx_intr.c | |
| xdptx_mst.c | |
| xdptx_selftest.c | |
| xdptx_sinit.c | |
| xdptx_spm.c | |
| xdp.c | |
| xdp.h | |
| xdp_edid.c | |
| xdp_hw.h | |
| xdp_intr.c | |
| xdp_mst.c | |
| xdp_selftest.c | |
| xdp_sinit.c | |
| xdp_spm.c |
+Here is a list of all file members with links to the files they belong to: +
+
+
+
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. +The Xilinx DisplayPort transmitter (DP) driver. This driver supports the Xilinx DisplayPort soft IP core in both transmit/source (TX) and receive/sink (RX) modes of operation.
+The Xilinx DisplayPort soft IP supports the following features:
+The Xilinx DisplayPort soft IP does not support the following features:
+DisplayPort overview
+A DisplayPort link consists of:
+Device configuration
+The device can be configured in various ways during the FPGA implementation process. Configuration parameters are stored in the xdp_g.c file which is generated when compiling the board support package (BSP). A table is defined where each entry contains configuration information for the DisplayPort instances present in the system. This information includes parameters that are defined in the driver's data/dp.tcl file such as the base address of the memory-mapped device and the maximum number of lanes, maximum link rate, and video interface that the DisplayPort instance supports, among others.
+The DisplayPort core may be configured in both transmitter (TX) or receiver (RX) modes of operation. Depending on which mode of operation the hardware is configured for, the set of registers associated with the core will be different.
+Driver description
+The DisplayPort (DP) driver consists of functions, structures, and definitions: 1) Specific to the DisplayPort TX mode of operation.
+Driver description: TX mode of operation
+The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort TX soft IP, communicate and control an RX device/sink monitor over the AUX channel, and to initialize and transmit data streams over the main link. This driver follows the DisplayPort 1.2a specification.
+This driver implements link layer functionality: a Link Policy Maker (LPM) and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
+Using AUX transactions to read/write from/to the sink's DisplayPort Configuration Data (DPCD) address space, the LPM obtains the link capabilities, obtains link configuration and link and sink status, and configures and controls the link and sink. The main link is trained this way.
+I2C-over-AUX transactions are used to obtain the sink's Extended Display Identification Data (EDID) which give information on the display capabilities of the monitor. The SPM may use this information to determine what available screen resolutions and video timing are possible.
+Driver description: RX mode of operation
+The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort RX soft IP.
+This driver gives applications the ability to configure the RX using various settings, handle and issue interrupts, and modify a subset of its DisplayPort Configuration Data (DPCD) fields.
+Link training is done automatically by the hardware.
+Interrupt processing: TX mode of operation
+For the driver to process interrupts, the application must set up the system's interrupt controller and connect the XDp_InterruptHandler function to service interrupts. When an interrupt occurs, XDp_InterruptHandler will check which mode of operation the DisplayPort core is running in, and will call the appropriate interrupt handler for that core (XDp_TxInterruptHandler or XDp_RxInterruptHandler - local to xdp_intr.c).
+Interrupt processing: TX mode of operation
+DisplayPort interrupts occur on the HPD signal line when the DisplayPort cable is connected/disconnected or when the RX device sends a pulse. The user hardware design must contain an interrupt controller which the DisplayPort TX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDp_TxHpdInterruptHandler handler will service DisplayPort interrupts. When the XDp_TxHpdInterruptHandler function is invoked, the handler will identify what type of DisplayPort interrupt has occurred, and will call either the HPD event handler function or the HPD pulse handler function, depending on whether a an HPD event on an HPD pulse event occurred.
+The DisplayPort TX's XDP_TX_INTERRUPT_STATUS register indicates the type of interrupt that has occured, and the XDp_TxInterruptHandler will use this information to decide which handler to call. An HPD event is identified if bit XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is identified from the XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
+The HPD event handler may be set up by using the XDp_TxSetHpdEventHandler function and, for the HPD pulse handler, the XDp_TxSetHpdPulseHandler function.
+Interrupt processing: RX mode of operation
+The DisplayPort RX driver may generate a pulse on the hot-plug-detect (HPD) signal line using the XDp_RxGenerateHpdInterrupt function. This allows the RX to send an interrupt to the upstream TX device, useful for signaling the TX that it needs to do some checks for changes in downstream devices or a loss of link training.
+For RX interrupt handling of HPD events or events that happen internal to the RX, the user hardware design must contain an interrupt controller which the DisplayPort RX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDp_RxInterruptHandler handler will service interrupts. When the XDp_RxInterruptHandler function is invoked, the handler will identify what type of interrupt has occurred, and will call the appropriate interrupt handler.
+The DisplayPort RX's XDP_RX_INTERRUPT_CAUSE register indicates the type of interrupt that has occured, and the XDp_RxInterruptHandler will use this information to decide which handler to call.
+The handlers are set up using the XDp_RxSetIntr* functions.
+Specific interrupts may be enabled or disabled using the XDp_RxInterruptEnable and XDp_RxInterruptDisable functions.
+Multi-stream transport (MST) mode: TX mode of operation
+The current version of this driver doesn't support MST functionality when the core is configured do run in the RX mode of operation.
+The driver handles MST mode functionality in TX mode of operation, including sideband messaging, topology discovery, virtual channel payload ID table management, and directing streams to different sinks.
+MST testing has been done at all possible link rate/lane count/topology/ resolution/color depth combinations with each setting using following values:
+Audio
+The driver does not handle audio. For an example as to how to configure and transmit audio, examples/xdptx_audio_example.c illustrates the required sequence in the TX mode of operation. The user will need to configure the audio source connected to the Displayport TX instance and set up the audio info frame as per user requirements.
+Asserts
+Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.
+Limitations: TX mode of operation
+
+
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. +Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html new file mode 100644 index 00000000..8b710a54 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/struct_x_dp-members.html @@ -0,0 +1,31 @@ + + + +
| Config | XDp | |
| IsReady | XDp | |
| RxInstance | XDp | |
| TxInstance | XDp | |
| UserTimerPtr | XDp | |
| UserTimerWaitUs | XDp |
#include <xdp.h>
++
Public Attributes | |
| XDp_Config | Config |
| u32 | IsReady |
| XDp_TimerHandler | UserTimerWaitUs |
| void * | UserTimerPtr |
| union { | |
| XDp_Tx TxInstance | |
| XDp_Rx RxInstance | |
| }; | |
| union { ... } | +
+ +
| XDp_Config XDp::Config | +
+Configuration structure for the DisplayPort TX core. +
| u32 XDp::IsReady | +
+Device is initialized and ready. +
| XDp_Rx XDp::RxInstance | +
+ +
| XDp_Tx XDp::TxInstance | +
+ +
| void* XDp::UserTimerPtr | +
+Pointer to a timer instance used by the custom user delay/sleep function. +
| XDp_TimerHandler XDp::UserTimerWaitUs | +
+Custom user function for delay/sleep. +
+
| Address | XDp_AuxTransaction | |
| CmdCode | XDp_AuxTransaction | |
| Data | XDp_AuxTransaction | |
| NumBytes | XDp_AuxTransaction |
+
Public Attributes | |
| u16 | CmdCode |
| u8 | NumBytes |
| u32 | Address |
| u8 * | Data |
| u32 XDp_AuxTransaction::Address | +
+The AUX or I2C start address that the AUX transaction will perform work on. +
| u16 XDp_AuxTransaction::CmdCode | +
+The AUX command code that specifies what type of AUX transaction is taking place. +
| u8* XDp_AuxTransaction::Data | +
+The data buffer that will store the data read from AUX read transactions or the data to write for AUX write transactions. +
| u8 XDp_AuxTransaction::NumBytes | +
+The number of bytes that the AUX transaction will perform work on. +
+
#include <xdp.h>
++
Public Attributes | |
| u16 | DeviceId |
| u32 | BaseAddr |
| u32 | SAxiClkHz |
| u8 | MaxLaneCount |
| u8 | MaxLinkRate |
| u8 | MaxBitsPerColor |
| u8 | QuadPixelEn |
| u8 | DualPixelEn |
| u8 | YCrCbEn |
| u8 | YOnlyEn |
| u8 | PayloadDataWidth |
| u8 | SecondaryChEn |
| u8 | NumAudioChs |
| u8 | MstSupport |
| u8 | NumMstStreams |
| u8 | DpProtocol |
| u8 | IsRx |
| u32 XDp_Config::BaseAddr | +
+The base address of the core instance. +
| u16 XDp_Config::DeviceId | +
+Device instance ID. +
| u8 XDp_Config::DpProtocol | +
+The DisplayPort protocol version that this core instance is configured for. 0 = v1.1a, 1 = v1.2. +
| u8 XDp_Config::DualPixelEn | +
+Dual pixel support by this core instance. +
| u8 XDp_Config::IsRx | +
+The type of DisplayPort core. 0 = TX, 1 = RX. +
| u8 XDp_Config::MaxBitsPerColor | +
+The maximum bits/color supported by this core instance +
| u8 XDp_Config::MaxLaneCount | +
+The maximum lane count supported by this core instance. +
| u8 XDp_Config::MaxLinkRate | +
+The maximum link rate supported by this core instance. +
| u8 XDp_Config::MstSupport | +
+Multi-stream transport (MST) mode is enabled by this core instance. +
| u8 XDp_Config::NumAudioChs | +
+The number of audio channels supported by this core instance. +
| u8 XDp_Config::NumMstStreams | +
+The total number of MST streams supported by this core instance. +
| u8 XDp_Config::PayloadDataWidth | +
+The payload data width used by this core instance. +
| u8 XDp_Config::QuadPixelEn | +
+Quad pixel support by this core instance. +
| u32 XDp_Config::SAxiClkHz | +
+The clock frequency of the core instance's S_AXI_ACLK port. +
| u8 XDp_Config::SecondaryChEn | +
+This core instance supports audio packets being sent by the secondary channel. +
| u8 XDp_Config::YCrCbEn | +
+YCrCb format support by this core instance. +
| u8 XDp_Config::YOnlyEn | +
+YOnly format support by this core instance. +
+
#include <xdp.h>
++
Public Attributes | |
| XDp_RxLinkConfig | LinkConfig |
| XDp_IntrHandler | IntrVmChangeHandler |
| void * | IntrVmChangeCallbackRef |
| XDp_IntrHandler | IntrPowerStateHandler |
| void * | IntrPowerStateCallbackRef |
| XDp_IntrHandler | IntrNoVideoHandler |
| void * | IntrNoVideoCallbackRef |
| XDp_IntrHandler | IntrVBlankHandler |
| void * | IntrVBlankCallbackRef |
| XDp_IntrHandler | IntrTrainingLostHandler |
| void * | IntrTrainingLostCallbackRef |
| XDp_IntrHandler | IntrVideoHandler |
| void * | IntrVideoCallbackRef |
| XDp_IntrHandler | IntrTrainingDoneHandler |
| void * | IntrTrainingDoneCallbackRef |
| XDp_IntrHandler | IntrBwChangeHandler |
| void * | IntrBwChangeCallbackRef |
| XDp_IntrHandler | IntrTp1Handler |
| void * | IntrTp1CallbackRef |
| XDp_IntrHandler | IntrTp2Handler |
| void * | IntrTp2CallbackRef |
| XDp_IntrHandler | IntrTp3Handler |
| void * | IntrTp3CallbackRef |
| void* XDp_Rx::IntrBwChangeCallbackRef | +
+A pointer to the user data passed to the bandwidth change callback function. +
| XDp_IntrHandler XDp_Rx::IntrBwChangeHandler | +
+Callback function for bandwidth change interrupts. +
| void* XDp_Rx::IntrNoVideoCallbackRef | +
+A pointer to the user data passed to the no video callback function. +
| XDp_IntrHandler XDp_Rx::IntrNoVideoHandler | +
+Callback function for no video interrupts. +
| void* XDp_Rx::IntrPowerStateCallbackRef | +
+A pointer to the user data passed to the power state change callback function. +
| XDp_IntrHandler XDp_Rx::IntrPowerStateHandler | +
+Callback function for power state change interrupts. +
| void* XDp_Rx::IntrTp1CallbackRef | +
+A pointer to the user data passed to the training pattern 1 callback function. +
| XDp_IntrHandler XDp_Rx::IntrTp1Handler | +
+Callback function for training pattern 1 interrupts. +
| void* XDp_Rx::IntrTp2CallbackRef | +
+A pointer to the user data passed to the training pattern 2 callback function. +
| XDp_IntrHandler XDp_Rx::IntrTp2Handler | +
+Callback function for training pattern 2 interrupts. +
| void* XDp_Rx::IntrTp3CallbackRef | +
+A pointer to the user data passed to the training pattern 3 callback function. +
| XDp_IntrHandler XDp_Rx::IntrTp3Handler | +
+Callback function for training pattern 3 interrupts. +
| void* XDp_Rx::IntrTrainingDoneCallbackRef | +
+A pointer to the user data passed to the training done callback function. +
| XDp_IntrHandler XDp_Rx::IntrTrainingDoneHandler | +
+Callback function for training done interrupts. +
| void* XDp_Rx::IntrTrainingLostCallbackRef | +
+A pointer to the user data passed to the training lost callback function. +
| XDp_IntrHandler XDp_Rx::IntrTrainingLostHandler | +
+Callback function for training lost interrupts. +
| void* XDp_Rx::IntrVBlankCallbackRef | +
+A pointer to the user data passed to the vertical blanking callback function. +
| XDp_IntrHandler XDp_Rx::IntrVBlankHandler | +
+Callback function for vertical blanking interrupts. +
| void* XDp_Rx::IntrVideoCallbackRef | +
+A pointer to the user data passed to the valid video callback function. +
| XDp_IntrHandler XDp_Rx::IntrVideoHandler | +
+Callback function for valid video interrupts. +
| void* XDp_Rx::IntrVmChangeCallbackRef | +
+A pointer to the user data passed to the video mode change callback function. +
| XDp_IntrHandler XDp_Rx::IntrVmChangeHandler | +
+Callback function for video mode change interrupts. +
| XDp_RxLinkConfig XDp_Rx::LinkConfig | +
+Configuration structure for the main link. +
+
| LaneCount | XDp_RxLinkConfig | |
| LinkRate | XDp_RxLinkConfig |
#include <xdp.h>
++
Public Attributes | |
| u8 | LaneCount |
| u8 | LinkRate |
| u8 XDp_RxLinkConfig::LaneCount | +
+The current lane count of the main link. +
| u8 XDp_RxLinkConfig::LinkRate | +
+The current link rate of the main link. +
+
| Body | XDp_SidebandMsg | |
| Header | XDp_SidebandMsg |
+
Public Attributes | |
| XDp_SidebandMsgHeader | Header |
| XDp_SidebandMsgBody | Body |
| XDp_SidebandMsgBody XDp_SidebandMsg::Body | +
+The body segment of the sideband message. +
| XDp_SidebandMsgHeader XDp_SidebandMsg::Header | +
+The header segment of the sideband message. +
+
| Crc | XDp_SidebandMsgBody | |
| MsgData | XDp_SidebandMsgBody | |
| MsgDataLength | XDp_SidebandMsgBody |
+
Public Attributes | |
| u8 | MsgData [62] |
| u8 | MsgDataLength |
| u8 | Crc |
| u8 XDp_SidebandMsgBody::Crc | +
+The cyclic-redundancy check (CRC) value of the body data. +
| u8 XDp_SidebandMsgBody::MsgData[62] | +
+The raw body data of the sideband message. +
| u8 XDp_SidebandMsgBody::MsgDataLength | +
+The number of data bytes stored as part of the sideband message body. +
+
+
Public Attributes | |
| u8 | LinkCountTotal |
| u8 | LinkCountRemaining |
| u8 | RelativeAddress [15] |
| u8 | BroadcastMsg |
| u8 | PathMsg |
| u8 | MsgBodyLength |
| u8 | StartOfMsgTransaction |
| u8 | EndOfMsgTransaction |
| u8 | MsgSequenceNum |
| u8 | Crc |
| u8 | MsgHeaderLength |
| u8 XDp_SidebandMsgHeader::BroadcastMsg | +
+Specifies that this message is a broadcast message, to be handled by all downstream devices. +
| u8 XDp_SidebandMsgHeader::Crc | +
+The cyclic-redundancy check (CRC) value of the header data. +
| u8 XDp_SidebandMsgHeader::EndOfMsgTransaction | +
+This message is the last sideband message in the transaction. +
| u8 XDp_SidebandMsgHeader::LinkCountRemaining | +
+The remaining link count until the sideband message reaches the target device. +
| u8 XDp_SidebandMsgHeader::LinkCountTotal | +
+The total number of DisplayPort links connecting the device device that this sideband message is targeted from the DisplayPort TX. +
| u8 XDp_SidebandMsgHeader::MsgBodyLength | +
+The total number of data bytes that are stored in the sideband message body. +
| u8 XDp_SidebandMsgHeader::MsgHeaderLength | +
+The number of data bytes stored as part of the sideband message header. +
| u8 XDp_SidebandMsgHeader::MsgSequenceNum | +
+Identifies invidiual message transactions to a given DisplayPort device. +
| u8 XDp_SidebandMsgHeader::PathMsg | +
+Specifies that this message is a path message, to be handled by all the devices between the origin and the target device. +
| u8 XDp_SidebandMsgHeader::RelativeAddress[15] | +
+The relative address from the DisplayPort TX to the target device. +
| u8 XDp_SidebandMsgHeader::StartOfMsgTransaction | +
+This message is the first sideband message in the transaction. +
+
| Data | XDp_SidebandReply | |
| Length | XDp_SidebandReply |
+
Public Attributes | |
| u8 | Length |
| u8 | Data [256] |
| u8 XDp_SidebandReply::Data[256] | +
+The raw reply data. +
| u8 XDp_SidebandReply::Length | +
+The number of bytes of reply data. +
+
#include <xdp.h>
++
Public Attributes | |
| u32 | MstEnable |
| u8 | TrainAdaptive |
| XDp_TxSinkConfig | RxConfig |
| XDp_TxLinkConfig | LinkConfig |
| XDp_TxBoardChar | BoardChar |
| XDp_TxMainStreamAttributes | MsaConfig [4] |
| XDp_TxMstStream | MstStreamConfig [4] |
| XDp_TxTopology | Topology |
| u32 | AuxDelayUs |
| u32 | SbMsgDelayUs |
| XDp_IntrHandler | HpdEventHandler |
| void * | HpdEventCallbackRef |
| XDp_IntrHandler | HpdPulseHandler |
| void * | HpdPulseCallbackRef |
| u32 XDp_Tx::AuxDelayUs | +
+Amount of latency in micro- seconds to use between AUX transactions. +
| XDp_TxBoardChar XDp_Tx::BoardChar | +
+Some board characteristics information that affects link training. +
| void* XDp_Tx::HpdEventCallbackRef | +
+A pointer to the user data passed to the HPD event callback function. +
| XDp_IntrHandler XDp_Tx::HpdEventHandler | +
+Callback function for Hot- Plug-Detect (HPD) event interrupts. +
| void* XDp_Tx::HpdPulseCallbackRef | +
+A pointer to the user data passed to the HPD pulse callback function. +
| XDp_IntrHandler XDp_Tx::HpdPulseHandler | +
+Callback function for Hot- Plug-Detect (HPD) pulse interrupts. +
| XDp_TxLinkConfig XDp_Tx::LinkConfig | +
+Configuration structure for the main link. +
| XDp_TxMainStreamAttributes XDp_Tx::MsaConfig[4] | +
+Configuration structure for the main stream attributes (MSA). Each stream has its own set of attributes. When MST mode is disabled, only MsaConfig[0] is used. +
| u32 XDp_Tx::MstEnable | +
+Multi-stream transport (MST) mode. Enables functionality, allowing multiple streams to be sent over the main link. +
| XDp_TxMstStream XDp_Tx::MstStreamConfig[4] | +
+Configuration structure for a multi-stream transport (MST) stream. +
| XDp_TxSinkConfig XDp_Tx::RxConfig | +
+Configuration structure for the RX device. +
| u32 XDp_Tx::SbMsgDelayUs | +
+Amount of latency in micro- seconds to use between sideband messages for multi-stream transport (MST) mode. +
| XDp_TxTopology XDp_Tx::Topology | +
+The topology of connected downstream DisplayPort devices when the driver is running in MST mode. +
| u8 XDp_Tx::TrainAdaptive | +
+Downshift lane count and link rate if necessary during training. +
+
| HasRedriverInPath | XDp_TxBoardChar | |
| TxPeLevels | XDp_TxBoardChar | |
| TxVsLevels | XDp_TxBoardChar | |
| TxVsOffset | XDp_TxBoardChar |
#include <xdp.h>
++
Public Attributes | |
| u8 | HasRedriverInPath |
| u8 | TxVsLevels [4] |
| u8 | TxPeLevels [4] |
| u8 | TxVsOffset |
| u8 XDp_TxBoardChar::HasRedriverInPath | +
+Redriver in path requires different voltage swing and pre-emphasis. +
| u8 XDp_TxBoardChar::TxPeLevels[4] | +
+The pre-emphasis/cursor level to be used by the DisplayPort TX. +
| u8 XDp_TxBoardChar::TxVsLevels[4] | +
+The voltage swing levels to be used by the DisplayPort TX. +
| u8 XDp_TxBoardChar::TxVsOffset | +
+Voltage swing compensation offset used when pre-emphasis is used. +
+
#include <xdp.h>
++
Public Attributes | |
| u8 | LaneCount |
| u8 | LinkRate |
| u8 | ScramblerEn |
| u8 | EnhancedFramingMode |
| u8 | DownspreadControl |
| u8 | MaxLaneCount |
| u8 | MaxLinkRate |
| u8 | SupportEnhancedFramingMode |
| u8 | SupportDownspreadControl |
| u8 | VsLevel |
| u8 | PeLevel |
| u8 | Pattern |
| u8 XDp_TxLinkConfig::DownspreadControl | +
+Downspread control is currently in use over the main link. +
| u8 XDp_TxLinkConfig::EnhancedFramingMode | +
+Enhanced frame mode is currently in use over the main link. +
| u8 XDp_TxLinkConfig::LaneCount | +
+The current lane count of the main link. +
| u8 XDp_TxLinkConfig::LinkRate | +
+The current link rate of the main link. +
| u8 XDp_TxLinkConfig::MaxLaneCount | +
+The maximum lane count of the main link. +
| u8 XDp_TxLinkConfig::MaxLinkRate | +
+The maximum link rate of the main link. +
| u8 XDp_TxLinkConfig::Pattern | +
+The current pattern currently in use over the main link. +
| u8 XDp_TxLinkConfig::PeLevel | +
+The current pre-emphasis/cursor level for each lane. +
| u8 XDp_TxLinkConfig::ScramblerEn | +
+Symbol scrambling is currently in use over the main link. +
| u8 XDp_TxLinkConfig::SupportDownspreadControl | +
+Downspread control is supported by the RX device. +
| u8 XDp_TxLinkConfig::SupportEnhancedFramingMode | +
+Enhanced frame mode is supported by the RX device. +
| u8 XDp_TxLinkConfig::VsLevel | +
+The current voltage swing level for each lane. +
+
#include <xdp.h>
++
Public Attributes | |
| XVidC_VideoTimingMode | Vtm |
| u32 | PixelClockHz |
| u32 | HStart |
| u32 | VStart |
| u32 | Misc0 |
| u32 | Misc1 |
| u32 | NVid |
| u32 | UserPixelWidth |
| u32 | DataPerLane |
| u32 | AvgBytesPerTU |
| u32 | TransferUnitSize |
| u32 | InitWait |
| u32 | BitsPerColor |
| u8 | ComponentFormat |
| u8 | DynamicRange |
| u8 | YCbCrColorimetry |
| u8 | SynchronousClockMode |
| u8 | OverrideUserPixelWidth |
| u32 XDp_TxMainStreamAttributes::AvgBytesPerTU | +
+Average number of bytes per transfer unit, scaled up by a factor of 1000. +
| u32 XDp_TxMainStreamAttributes::BitsPerColor | +
+Number of bits per color component. +
| u8 XDp_TxMainStreamAttributes::ComponentFormat | +
+The component format currently in use by the video stream. +
| u32 XDp_TxMainStreamAttributes::DataPerLane | +
+Used to translate the number of pixels per line to the native internal 16-bit datapath. +
| u8 XDp_TxMainStreamAttributes::DynamicRange | +
+The dynamic range currently in use by the video stream. +
| u32 XDp_TxMainStreamAttributes::HStart | +
+Horizontal blank start (in pixels). +
| u32 XDp_TxMainStreamAttributes::InitWait | +
+Number of initial wait cycles at the start of a new line by the framing logic. +
| u32 XDp_TxMainStreamAttributes::Misc0 | +
+Miscellaneous stream attributes 0 as specified by the DisplayPort 1.2 specification. +
| u32 XDp_TxMainStreamAttributes::Misc1 | +
+Miscellaneous stream attributes 1 as specified by the DisplayPort 1.2 specification. +
| u32 XDp_TxMainStreamAttributes::NVid | +
+N value for the video stream. +
| u8 XDp_TxMainStreamAttributes::OverrideUserPixelWidth | +
+If set to 1, the value stored for UserPixelWidth will be used as the pixel width. +
| u32 XDp_TxMainStreamAttributes::PixelClockHz | +
+The pixel clock of the stream (in Hz). +
| u8 XDp_TxMainStreamAttributes::SynchronousClockMode | +
+Synchronous clock mode is currently in use by the video stream. +
| u32 XDp_TxMainStreamAttributes::TransferUnitSize | +
+Size of the transfer unit in the framing logic. In MST mode, this is also the number of time slots that are alloted in the payload ID table. +
| u32 XDp_TxMainStreamAttributes::UserPixelWidth | +
+The width of the user data input port. +
| u32 XDp_TxMainStreamAttributes::VStart | +
+Vertical blank start (in lines). +
| XVidC_VideoTimingMode XDp_TxMainStreamAttributes::Vtm | +
+The video timing. +
| u8 XDp_TxMainStreamAttributes::YCbCrColorimetry | +
+The YCbCr colorimetry currently in use by the video stream. +
+
| LinkCountTotal | XDp_TxMstStream | |
| MstPbn | XDp_TxMstStream | |
| MstStreamEnable | XDp_TxMstStream | |
| RelativeAddress | XDp_TxMstStream |
#include <xdp.h>
++
Public Attributes | |
| u8 | LinkCountTotal |
| u8 | RelativeAddress [15] |
| u16 | MstPbn |
| u8 | MstStreamEnable |
| u8 XDp_TxMstStream::LinkCountTotal | +
+ +
| u16 XDp_TxMstStream::MstPbn | +
+The relative address from the DisplayPort TX to the sink device that this MST stream is targeting. Payload bandwidth number used to allocate bandwidth for the MST stream. +
| u8 XDp_TxMstStream::MstStreamEnable | +
+In MST mode, enables the corresponding stream for this MSA configuration. +
| u8 XDp_TxMstStream::RelativeAddress[15] | +
+The total number of DisplayPort links from the DisplayPort TX to the sink device that this MST stream is targeting. +
+
#include <xdp.h>
++
Public Attributes | |
| u8 | ReplyType |
| u8 | RequestId |
| u32 | Guid [4] |
| u8 | NumPorts |
| XDp_TxSbMsgLinkAddressReplyPortDetail | PortDetails [16] |
| u32 XDp_TxSbMsgLinkAddressReplyDeviceInfo::Guid[4] | +
+The global unique identifier (GUID) of the branch device. +
| u8 XDp_TxSbMsgLinkAddressReplyDeviceInfo::NumPorts | +
+The number of ports associated with this branch device. +
| XDp_TxSbMsgLinkAddressReplyPortDetail XDp_TxSbMsgLinkAddressReplyDeviceInfo::PortDetails[16] | +
+An array describing all ports attached to this branch device. +
| u8 XDp_TxSbMsgLinkAddressReplyDeviceInfo::ReplyType | +
+The reply type of the sideband message. A value of 1 indicates that the request wasn't successful and the return data will give the reason for a negative-acknowledge (NACK). +
| u8 XDp_TxSbMsgLinkAddressReplyDeviceInfo::RequestId | +
+The request identifier of the reply. This should correspond to the request identifier for the LINK_ADDRESS sideband message request. +
+
#include <xdp.h>
++
Public Attributes | |
| u8 | InputPort |
| u8 | PeerDeviceType |
| u8 | PortNum |
| u8 | MsgCapStatus |
| u8 | DpDevPlugStatus |
| u8 | LegacyDevPlugStatus |
| u8 | DpcdRev |
| u32 | Guid [4] |
| u8 | NumSdpStreams |
| u8 | NumSdpStreamSinks |
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::DpcdRev | +
+The DisplayPort Configuration Data (DPCD) revision of the device connected to this port. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::DpDevPlugStatus | +
+There is a device connected to this port. +
| u32 XDp_TxSbMsgLinkAddressReplyPortDetail::Guid[4] | +
+The global unique identifier (GUID) of the device connected to this port. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::InputPort | +
+Specifies that this port is an input port. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::LegacyDevPlugStatus | +
+This port is connected to a legacy device. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::MsgCapStatus | +
+This port or the device at this port can send and receive MST messages. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::NumSdpStreams | +
+The total number of Secondary-Data Packet (SDP) streams that this port can handle. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::NumSdpStreamSinks | +
+The number of SDP streams associated with this port. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::PeerDeviceType | +
+Specifies the device type connected to this port. +
| u8 XDp_TxSbMsgLinkAddressReplyPortDetail::PortNum | +
+The port number of this port. +
+
| DpcdRxCapsField | XDp_TxSinkConfig | |
| LaneStatusAdjReqs | XDp_TxSinkConfig |
#include <xdp.h>
++
Public Attributes | |
| u8 | DpcdRxCapsField [16] |
| u8 | LaneStatusAdjReqs [6] |
| u8 XDp_TxSinkConfig::DpcdRxCapsField[16] | +
+The first 16 bytes of the raw capabilities field of the RX device's DisplayPort Configuration Data (DPCD). +
| u8 XDp_TxSinkConfig::LaneStatusAdjReqs[6] | +
+This is a raw read of the RX device's status registers. The first 4 bytes correspond to the lane status associated with clock recovery, channel equalization, symbol lock, and interlane alignment. The remaining 2 bytes represent the pre-emphasis and voltage swing level adjustments requested by the RX device. +
+
| NodeTable | XDp_TxTopology | |
| NodeTotal | XDp_TxTopology | |
| SinkList | XDp_TxTopology | |
| SinkTotal | XDp_TxTopology |
#include <xdp.h>
++
Public Attributes | |
| u8 | NodeTotal |
| XDp_TxTopologyNode | NodeTable [63] |
| u8 | SinkTotal |
| XDp_TxTopologyNode * | SinkList [63] |
| XDp_TxTopologyNode XDp_TxTopology::NodeTable[63] | +
+A table listing all the nodes in the MST topology. +
| u8 XDp_TxTopology::NodeTotal | +
+The total number of nodes that were found in the MST topology. +
| XDp_TxTopologyNode* XDp_TxTopology::SinkList[63] | +
+A pointer list of sinks in the MST topology. The entries will point to the sinks in the NodeTable. +
| u8 XDp_TxTopology::SinkTotal | +
+The total number of sinks in the MST topology. +
+
| DeviceType | XDp_TxTopologyNode | |
| DpcdRev | XDp_TxTopologyNode | |
| Guid | XDp_TxTopologyNode | |
| LinkCountTotal | XDp_TxTopologyNode | |
| MsgCapStatus | XDp_TxTopologyNode | |
| RelativeAddress | XDp_TxTopologyNode |
#include <xdp.h>
++
Public Attributes | |
| u32 | Guid [4] |
| u8 | RelativeAddress [15] |
| u8 | DeviceType |
| u8 | LinkCountTotal |
| u8 | DpcdRev |
| u8 | MsgCapStatus |
| u8 XDp_TxTopologyNode::DeviceType | +
+The type of DisplayPort device. Either a branch or sink. +
| u8 XDp_TxTopologyNode::DpcdRev | +
+The revision of the device's DisplayPort Configuration Data (DPCD). For this device to support MST features, this value must represent a protocl version greater or equal to 1.2. +
| u32 XDp_TxTopologyNode::Guid[4] | +
+The global unique identifier (GUID) of the device. +
| u8 XDp_TxTopologyNode::LinkCountTotal | +
+The total number of DisplayPort links connecting this device to the DisplayPort TX. +
| u8 XDp_TxTopologyNode::MsgCapStatus | +
+This device is capable of sending and receiving sideband messages. +
| u8 XDp_TxTopologyNode::RelativeAddress[15] | +
+The relative address from the DisplayPort TX to this device. +
+
#include <xdprx.h>
++
Public Attributes | |
| XDp_Config | Config |
| u32 | IsReady |
| XDprx_LinkConfig | LinkConfig |
| XDp_TimerHandler | UserTimerWaitUs |
| void * | UserTimerPtr |
| XDprx_IntrHandler | IntrVmChangeHandler |
| void * | IntrVmChangeCallbackRef |
| XDprx_IntrHandler | IntrPowerStateHandler |
| void * | IntrPowerStateCallbackRef |
| XDprx_IntrHandler | IntrNoVideoHandler |
| void * | IntrNoVideoCallbackRef |
| XDprx_IntrHandler | IntrVBlankHandler |
| void * | IntrVBlankCallbackRef |
| XDprx_IntrHandler | IntrTrainingLostHandler |
| void * | IntrTrainingLostCallbackRef |
| XDprx_IntrHandler | IntrVideoHandler |
| void * | IntrVideoCallbackRef |
| XDprx_IntrHandler | IntrTrainingDoneHandler |
| void * | IntrTrainingDoneCallbackRef |
| XDprx_IntrHandler | IntrBwChangeHandler |
| void * | IntrBwChangeCallbackRef |
| XDprx_IntrHandler | IntrTp1Handler |
| void * | IntrTp1CallbackRef |
| XDprx_IntrHandler | IntrTp2Handler |
| void * | IntrTp2CallbackRef |
| XDprx_IntrHandler | IntrTp3Handler |
| void * | IntrTp3CallbackRef |
| XDp_Config XDprx::Config | +
+Configuration structure for the DisplayPort RX core. It is important to keep this member first in the XDprx order. +
| void* XDprx::IntrBwChangeCallbackRef | +
+A pointer to the user data passed to the bandwidth change callback function. +
| XDprx_IntrHandler XDprx::IntrBwChangeHandler | +
+Callback function for bandwidth change interrupts. +
| void* XDprx::IntrNoVideoCallbackRef | +
+A pointer to the user data passed to the no video callback function. +
| XDprx_IntrHandler XDprx::IntrNoVideoHandler | +
+Callback function for no video interrupts. +
| void* XDprx::IntrPowerStateCallbackRef | +
+A pointer to the user data passed to the power state change callback function. +
| XDprx_IntrHandler XDprx::IntrPowerStateHandler | +
+Callback function for power state change interrupts. +
| void* XDprx::IntrTp1CallbackRef | +
+A pointer to the user data passed to the training pattern 1 callback function. +
| XDprx_IntrHandler XDprx::IntrTp1Handler | +
+Callback function for training pattern 1 interrupts. +
| void* XDprx::IntrTp2CallbackRef | +
+A pointer to the user data passed to the training pattern 2 callback function. +
| XDprx_IntrHandler XDprx::IntrTp2Handler | +
+Callback function for training pattern 2 interrupts. +
| void* XDprx::IntrTp3CallbackRef | +
+A pointer to the user data passed to the training pattern 3 callback function. +
| XDprx_IntrHandler XDprx::IntrTp3Handler | +
+Callback function for training pattern 3 interrupts. +
| void* XDprx::IntrTrainingDoneCallbackRef | +
+A pointer to the user data passed to the training done callback function. +
| XDprx_IntrHandler XDprx::IntrTrainingDoneHandler | +
+Callback function for training done interrupts. +
| void* XDprx::IntrTrainingLostCallbackRef | +
+A pointer to the user data passed to the training lost callback function. +
| XDprx_IntrHandler XDprx::IntrTrainingLostHandler | +
+Callback function for training lost interrupts. +
| void* XDprx::IntrVBlankCallbackRef | +
+A pointer to the user data passed to the vertical blanking callback function. +
| XDprx_IntrHandler XDprx::IntrVBlankHandler | +
+Callback function for vertical blanking interrupts. +
| void* XDprx::IntrVideoCallbackRef | +
+A pointer to the user data passed to the valid video callback function. +
| XDprx_IntrHandler XDprx::IntrVideoHandler | +
+Callback function for valid video interrupts. +
| void* XDprx::IntrVmChangeCallbackRef | +
+A pointer to the user data passed to the video mode change callback function. +
| XDprx_IntrHandler XDprx::IntrVmChangeHandler | +
+Callback function for video mode change interrupts. +
| u32 XDprx::IsReady | +
+Device is initialized and ready. +
| XDprx_LinkConfig XDprx::LinkConfig | +
+Configuration structure for the main link. +
| void* XDprx::UserTimerPtr | +
+Pointer to a timer instance used by the custom user delay/sleep function. +
| XDp_TimerHandler XDprx::UserTimerWaitUs | +
+Custom user function for delay/sleep. +
+
| LaneCount | XDprx_LinkConfig | |
| LinkRate | XDprx_LinkConfig |
#include <xdprx.h>
++
Public Attributes | |
| u8 | LaneCount |
| u8 | LinkRate |
| u8 XDprx_LinkConfig::LaneCount | +
+The current lane count of the main link. +
| u8 XDprx_LinkConfig::LinkRate | +
+The current link rate of the main link. +
+
Public Attributes | ||
| XDp_Config | Config | |
| u32 | MstEnable | |
| u32 | IsReady | |
| u8 | TrainAdaptive | |
| XDptx_Config | Config | |
| XDptx_SinkConfig | RxConfig | |
| XDptx_LinkConfig | LinkConfig | |
| u32 | SbMsgDelayUs | |
| XDptx_TimerHandler | UserTimerWaitUs | |
| XDp_TimerHandler | UserTimerWaitUs | |
| void * | UserTimerPtr | |
| ComponentFormat | XDptx_MainStreamAttributes | |
| DataPerLane | XDptx_MainStreamAttributes | |
| DynamicRange | XDptx_MainStreamAttributes | |
| HClkTotal | XDptx_MainStreamAttributes | |
| HStart | XDptx_MainStreamAttributes | |
| InitWait | XDptx_MainStreamAttributes | |
| Misc0 | XDptx_MainStreamAttributes | |
| Misc1 | XDptx_MainStreamAttributes | |
| NVid | XDptx_MainStreamAttributes | |
| OverrideUserPixelWidth | XDptx_MainStreamAttributes | |
| PixelClockHz | XDptx_MainStreamAttributes | |
| SynchronousClockMode | XDptx_MainStreamAttributes | |
| TransferUnitSize | XDptx_MainStreamAttributes | |
| UserPixelWidth | XDptx_MainStreamAttributes | |
| VClkTotal | XDptx_MainStreamAttributes | |
| VStart | XDptx_MainStreamAttributes | |
| Vtm | XDptx_MainStreamAttributes | |
| Vtm | XDptx_MainStreamAttributes | |
| YCbCrColorimetry | XDptx_MainStreamAttributes | |
Public Attributes | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| XVid_VideoTimingMode | Vtm | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| XVidC_VideoTimingMode | Vtm | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | HClkTotal | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | VClkTotal | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | PixelClockHz | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | HStart | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 XDptx_MainStreamAttributes::HClkTotal | -
-Horizontal total time (in pixels). -
| u32 XDptx_MainStreamAttributes::PixelClockHz | +
+The pixel clock of the stream (in Hz). +
| u32 XDptx_MainStreamAttributes::VClkTotal | -
-Vertical total time (in pixels). -
| XVid_VideoTimingMode XDptx_MainStreamAttributes::Vtm | +XVidC_VideoTimingMode XDptx_MainStreamAttributes::Vtm |
+
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+#include "xenv.h"
+
Classes | |
| struct | XDp_AuxTransaction |
Defines | |
| #define | XDP_TX_MAXIMUM_VS_LEVEL 3 |
| #define | XDP_TX_MAXIMUM_PE_LEVEL 3 |
| #define | XDP_AUX_MAX_DEFER_COUNT 50 |
| #define | XDP_AUX_MAX_TIMEOUT_COUNT 50 |
| #define | XDP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 |
Enumerations | |
| enum | XDp_TxTrainingState { + XDP_TX_TS_CLOCK_RECOVERY, +XDP_TX_TS_CHANNEL_EQUALIZATION, +XDP_TX_TS_ADJUST_LINK_RATE, +XDP_TX_TS_ADJUST_LANE_COUNT, + + XDP_TX_TS_FAILURE, +XDP_TX_TS_SUCCESS + + } |
Functions | |
| void | XDp_CfgInitialize (XDp *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) |
| u32 | XDp_Initialize (XDp *InstancePtr) |
| u32 | XDp_TxGetRxCapabilities (XDp *InstancePtr) |
| u32 | XDp_TxCfgMainLinkMax (XDp *InstancePtr) |
| u32 | XDp_TxEstablishLink (XDp *InstancePtr) |
| u32 | XDp_TxCheckLinkStatus (XDp *InstancePtr, u8 LaneCount) |
| void | XDp_TxEnableTrainAdaptive (XDp *InstancePtr, u8 Enable) |
| void | XDp_TxSetHasRedriverInPath (XDp *InstancePtr, u8 Set) |
| void | XDp_TxCfgTxVsOffset (XDp *InstancePtr, u8 Offset) |
| void | XDp_TxCfgTxVsLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
| void | XDp_TxCfgTxPeLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
| u32 | XDp_TxIsConnected (XDp *InstancePtr) |
| u32 | XDp_TxAuxRead (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) |
| u32 | XDp_TxAuxWrite (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) |
| u32 | XDp_TxIicRead (XDp *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) |
| u32 | XDp_TxIicWrite (XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) |
| u32 | XDp_TxSetDownspread (XDp *InstancePtr, u8 Enable) |
| u32 | XDp_TxSetEnhancedFrameMode (XDp *InstancePtr, u8 Enable) |
| u32 | XDp_TxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
| u32 | XDp_TxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
| u32 | XDp_TxSetScrambler (XDp *InstancePtr, u8 Enable) |
| void | XDp_TxEnableMainLink (XDp *InstancePtr) |
| void | XDp_TxDisableMainLink (XDp *InstancePtr) |
| void | XDp_TxResetPhy (XDp *InstancePtr, u32 Reset) |
| u32 | XDp_RxCheckLinkStatus (XDp *InstancePtr) |
| void | XDp_RxDtgEn (XDp *InstancePtr) |
| void | XDp_RxDtgDis (XDp *InstancePtr) |
| void | XDp_RxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
| void | XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
| void | XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
| void | XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds) |
| #define XDP_AUX_MAX_DEFER_COUNT 50 | +
+ +
| #define XDP_AUX_MAX_TIMEOUT_COUNT 50 | +
+ +
| #define XDP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 | +
+ +
| #define XDP_TX_MAXIMUM_PE_LEVEL 3 | +
+ +
| #define XDP_TX_MAXIMUM_VS_LEVEL 3 | +
+ +
+
| enum XDp_TxTrainingState | +
+This typedef enumerates the list of training states used in the state machine during the link training process.
+ ++
| void XDp_CfgInitialize | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_Config * | +ConfigPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. | |
| EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
| u32 XDp_Initialize | +( | +XDp * | +InstancePtr | +) | ++ |
+This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_RxCheckLinkStatus | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if the reciever's internal registers indicate that link training has complete. That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxDtgDis | +( | +XDp * | +InstancePtr | +) | ++ |
+This function disables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxDtgEn | +( | +XDp * | +InstancePtr | +) | ++ |
+This function enables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxSetLaneCount | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| void XDp_RxSetLinkRate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| void XDp_SetUserTimerHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_TimerHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a custom delay/sleep function to be used by the XDp driver.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. |
| u32 XDp_TxAuxRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | void * | +ReadData | + |
| + | ) | ++ |
+This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DpcdAddress | is the starting address to read from the RX device. | |
| BytesToRead | is the number of bytes to read from the RX device. | |
| ReadData | is a pointer to the data buffer that will be filled with read data. |
| u32 XDp_TxAuxWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | void * | +WriteData | + |
| + | ) | ++ |
+This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DpcdAddress | is the starting address to write to the RX device. | |
| BytesToWrite | is the number of bytes to write to the RX device. | |
| WriteData | is a pointer to the data buffer that contains the data to be written to the RX device. |
| u32 XDp_TxCfgMainLinkMax | +( | +XDp * | +InstancePtr | +) | ++ |
+This function determines the common capabilities between the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxCfgTxPeLevel | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Level, | +|
| + | + | u8 | +TxLevel | + |
| + | ) | ++ |
+This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Level | is the pre-emphasis training level to set the DisplayPort TX level for. | |
| TxLevel | is the DisplayPort TX pre-emphasis level value to be used during link training. |
| void XDp_TxCfgTxVsLevel | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Level, | +|
| + | + | u8 | +TxLevel | + |
| + | ) | ++ |
+This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Level | is the voltage swing training level to set the DisplayPort TX level for. | |
| TxLevel | is the DisplayPort TX voltage swing level value to be used during link training. |
| void XDp_TxCfgTxVsOffset | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Offset | + |
| + | ) | ++ |
+This function sets the voltage swing offset to use during training when no redriver exists. The offset will be added to the DisplayPort TX's voltage swing level value when pre-emphasis is used (when the pre-emphasis level not equal to 0).
+
| InstancePtr | is a pointer to the XDp instance. | |
| Offset | is the value to set for the voltage swing offset. |
| u32 XDp_TxCheckLinkStatus | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function checks if the reciever's DisplayPort Configuration Data (DPCD) indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to check. |
| void XDp_TxDisableMainLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function disables the main link.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxEnableMainLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function enables the main link.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxEnableTrainAdaptive | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables downshifting during the training process.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | controls the downshift feature in the training process. |
| u32 XDp_TxEstablishLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if the link needs training and runs the training sequence if training is required.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxGetRxCapabilities | +( | +XDp * | +InstancePtr | +) | ++ |
+This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u16 | +Offset, | +|
| + | + | u16 | +BytesToRead, | +|
| + | + | void * | +ReadData | + |
| + | ) | ++ |
+This function performs an I2C read over the AUX channel. The read message will be divided into multiple transactions if the requested data spans multiple segments. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
+
| InstancePtr | is a pointer to the XDp instance. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
| u32 XDp_TxIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | void * | +WriteData | + |
| + | ) | ++ |
+This function performs an I2C write over the AUX channel.
+
| InstancePtr | is a pointer to the XDp instance. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| u32 XDp_TxIsConnected | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if there is a connected RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxResetPhy | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Reset | + |
| + | ) | ++ |
+This function does a PHY reset.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Reset | is the type of reset to assert. |
| u32 XDp_TxSetDownspread | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will downspread the main link signal if set to 1 and disable downspreading if set to 0. |
| u32 XDp_TxSetEnhancedFrameMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will enable enhanced frame mode if set to 1 and disable it if set to 0. |
| void XDp_TxSetHasRedriverInPath | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Set | + |
| + | ) | ++ |
+This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. XDp_TxSetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Set | establishes that a redriver exists in the DisplayPort output path. |
| u32 XDp_TxSetLaneCount | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| u32 XDp_TxSetLinkRate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| u32 XDp_TxSetScrambler | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will enable or disable scrambling. |
| void XDp_WaitUs | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +MicroSeconds | + |
| + | ) | ++ |
+This function is the delay/sleep function for the XDp driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
+
| InstancePtr | is a pointer to the XDp instance. | |
| MicroSeconds | is the number of microseconds to delay/sleep for. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8h.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8h.html new file mode 100644 index 00000000..ad5460be --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp_8h.html @@ -0,0 +1,5276 @@ + +
+ +
+#include "xil_assert.h"
+#include "xil_types.h"
+#include "xdp_hw.h"
+#include "xstatus.h"
+#include "xvidc.h"
+
Classes | |
| struct | XDp_Config |
| struct | XDp_TxSinkConfig |
| struct | XDp_TxLinkConfig |
| struct | XDp_TxMainStreamAttributes |
| struct | XDp_TxMstStream |
| struct | XDp_TxBoardChar |
| struct | XDp_TxTopologyNode |
| struct | XDp_TxTopology |
| struct | XDp_TxSbMsgLinkAddressReplyPortDetail |
| struct | XDp_TxSbMsgLinkAddressReplyDeviceInfo |
| struct | XDp_RxLinkConfig |
| struct | XDp_Tx |
| struct | XDp_Rx |
| struct | XDp |
Defines | |
| #define | XDP_TX 0 |
| #define | XDP_RX 1 |
| #define | XDp_CfgGetCoreType(ConfigPtr) ((ConfigPtr)->IsRx ? XDP_RX : XDP_TX) |
| #define | XDptx_ReadReg XDp_ReadReg |
| #define | XDprx_ReadReg XDp_ReadReg |
| #define | XDptx_WriteReg XDp_WriteReg |
| #define | XDprx_WriteReg XDp_WriteReg |
| #define | XDptx_Config XDp_Config |
| #define | XDprx_Config XDp_Config |
| #define | XDptx_TimerHandler XDp_TimerHandler |
| #define | XDprx_TimerHandler XDp_TimerHandler |
| #define | XDptx_HpdEventHandler XDp_IntrHandler |
| #define | XDptx_HpdPulseHandler XDp_IntrHandler |
| #define | XDprx_IntrHandler XDp_IntrHandler |
| #define | XDptx_LookupConfig XDp_LookupConfig |
| #define | XDprx_LookupConfig XDp_LookupConfig |
| #define | XDptx_CfgInitialize XDp_CfgInitialize |
| #define | XDprx_CfgInitialize XDp_CfgInitialize |
| #define | XDptx_InitializeTx XDp_Initialize |
| #define | XDprx_InitializeRx XDp_Initialize |
| #define | XDptx_WaitUs XDp_WaitUs |
| #define | XDprx_WaitUs XDp_WaitUs |
| #define | XDptx_SetUserTimerHandler XDp_SetUserTimerHandler |
| #define | XDprx_SetUserTimerHandler XDp_SetUserTimerHandler |
| #define | XDptx_SelfTest XDp_SelfTest |
| #define | XDprx_SelfTest XDp_SelfTest |
| #define | XDptx_HpdInterruptHandler XDp_InterruptHandler |
| #define | XDprx_InterruptHandler XDp_InterruptHandler |
| #define | XDptx_ XDp_Tx |
| #define | XDprx_ XDp_Rx |
| #define | XDptx XDp |
| #define | XDprx XDp |
| #define | XDPTX_DPCD_ XDP_DPCD_ |
| #define | XDPTX_ XDP_TX_ |
| #define | XDPRX_ XDP_RX_ |
| #define | XDPTX XDP_TX |
| #define | XDPRX XDP_RX |
Typedefs | |
| typedef void(*) | XDp_TimerHandler (void *InstancePtr, u32 MicroSeconds) |
| typedef void(*) | XDp_IntrHandler (void *InstancePtr) |
Functions | |
| XDp_Config * | XDp_LookupConfig (u16 DeviceId) |
| void | XDp_CfgInitialize (XDp *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) |
| u32 | XDp_Initialize (XDp *InstancePtr) |
| u32 | XDp_TxGetRxCapabilities (XDp *InstancePtr) |
| u32 | XDp_TxCfgMainLinkMax (XDp *InstancePtr) |
| u32 | XDp_TxEstablishLink (XDp *InstancePtr) |
| u32 | XDp_TxCheckLinkStatus (XDp *InstancePtr, u8 LaneCount) |
| void | XDp_TxEnableTrainAdaptive (XDp *InstancePtr, u8 Enable) |
| void | XDp_TxSetHasRedriverInPath (XDp *InstancePtr, u8 Set) |
| void | XDp_TxCfgTxVsOffset (XDp *InstancePtr, u8 Offset) |
| void | XDp_TxCfgTxVsLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
| void | XDp_TxCfgTxPeLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
| u32 | XDp_TxAuxRead (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) |
| u32 | XDp_TxAuxWrite (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) |
| u32 | XDp_TxIicRead (XDp *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) |
| u32 | XDp_TxIicWrite (XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) |
| u32 | XDp_TxSetDownspread (XDp *InstancePtr, u8 Enable) |
| u32 | XDp_TxSetEnhancedFrameMode (XDp *InstancePtr, u8 Enable) |
| u32 | XDp_TxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
| u32 | XDp_TxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
| u32 | XDp_TxSetScrambler (XDp *InstancePtr, u8 Enable) |
| void | XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
| void | XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds) |
| u32 | XDp_TxIsConnected (XDp *InstancePtr) |
| void | XDp_TxEnableMainLink (XDp *InstancePtr) |
| void | XDp_TxDisableMainLink (XDp *InstancePtr) |
| void | XDp_TxResetPhy (XDp *InstancePtr, u32 Reset) |
| u32 | XDp_RxCheckLinkStatus (XDp *InstancePtr) |
| void | XDp_RxDtgEn (XDp *InstancePtr) |
| void | XDp_RxDtgDis (XDp *InstancePtr) |
| void | XDp_RxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
| void | XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
| u32 | XDp_TxGetEdid (XDp *InstancePtr, u8 *Edid) |
| u32 | XDp_TxGetRemoteEdid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid) |
| u32 | XDp_TxGetEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum) |
| u32 | XDp_TxGetRemoteEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxGetRemoteEdidDispIdExt (XDp *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxGetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) |
| u32 | XDp_TxGetRemoteTiledDisplayDb (XDp *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr) |
| void | XDp_InterruptHandler (XDp *InstancePtr) |
| void | XDp_TxSetHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_TxSetHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxGenerateHpdInterrupt (XDp *InstancePtr, u16 DurationUs) |
| void | XDp_RxInterruptEnable (XDp *InstancePtr, u32 Mask) |
| void | XDp_RxInterruptDisable (XDp *InstancePtr, u32 Mask) |
| void | XDp_RxSetIntrVmChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrVBlankHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTrainingLostHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp1Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp2Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp3Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_TxMstCfgModeEnable (XDp *InstancePtr) |
| void | XDp_TxMstCfgModeDisable (XDp *InstancePtr) |
| u32 | XDp_TxMstCapable (XDp *InstancePtr) |
| u32 | XDp_TxMstEnable (XDp *InstancePtr) |
| u32 | XDp_TxMstDisable (XDp *InstancePtr) |
| void | XDp_TxMstCfgStreamEnable (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxMstCfgStreamDisable (XDp *InstancePtr, u8 Stream) |
| u8 | XDp_TxMstStreamIsEnabled (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxSetStreamSelectFromSinkList (XDp *InstancePtr, u8 Stream, u8 SinkNum) |
| void | XDp_TxSetStreamSinkRad (XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxDiscoverTopology (XDp *InstancePtr) |
| u32 | XDp_TxFindAccessibleDpDevices (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress) |
| void | XDp_TxTopologySwapSinks (XDp *InstancePtr, u8 Index0, u8 Index1) |
| void | XDp_TxTopologySortSinksByTiling (XDp *InstancePtr) |
| u32 | XDp_TxRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxAllocatePayloadStreams (XDp *InstancePtr) |
| u32 | XDp_TxAllocatePayloadVcIdTable (XDp *InstancePtr, u8 VcId, u8 Ts) |
| u32 | XDp_TxClearPayloadVcIdTable (XDp *InstancePtr) |
| u32 | XDp_TxSendSbMsgRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxSendSbMsgRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxSendSbMsgRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxSendSbMsgRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxSendSbMsgLinkAddress (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo) |
| u32 | XDp_TxSendSbMsgEnumPathResources (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn) |
| u32 | XDp_TxSendSbMsgAllocatePayload (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn) |
| u32 | XDp_TxSendSbMsgClearPayloadIdTable (XDp *InstancePtr) |
| void | XDp_TxWriteGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4]) |
| void | XDp_TxGetGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid) |
| u32 | XDp_SelfTest (XDp *InstancePtr) |
| void | XDp_TxCfgMsaRecalculate (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxCfgMsaUseStandardVideoMode (XDp *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode) |
| void | XDp_TxCfgMsaUseEdidPreferredTiming (XDp *InstancePtr, u8 Stream, u8 *Edid) |
| void | XDp_TxCfgMsaUseCustom (XDp *InstancePtr, u8 Stream, XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate) |
| void | XDp_TxCfgMsaSetBpc (XDp *InstancePtr, u8 Stream, u8 BitsPerColor) |
| void | XDp_TxCfgMsaEnSynchClkMode (XDp *InstancePtr, u8 Stream, u8 Enable) |
| void | XDp_TxSetVideoMode (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxClearMsaValues (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxSetMsaValues (XDp *InstancePtr, u8 Stream) |
| void | XDp_RxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth) |
| #define XDp_CfgGetCoreType | +( | +ConfigPtr | ++ | ) | +((ConfigPtr)->IsRx ? XDP_RX : XDP_TX) | +
+This is function determines whether the DisplayPort core that the configuration structure represents is a transmitter (TX) or a receiver (RX).
+
| ConfigPtr | is a pointer to the DisplayPort core's configuration structure. |
| #define XDP_RX 1 | +
+ +
| #define XDP_TX 0 | +
+ +
| #define XDPRX XDP_RX | +
+ +
| #define XDprx XDp | +
+ +
| #define XDPRX_ XDP_RX_ | +
+ +
| #define XDprx_ XDp_Rx | +
+ +
| #define XDprx_CfgInitialize XDp_CfgInitialize | +
+ +
| #define XDprx_Config XDp_Config | +
+ +
| #define XDprx_InitializeRx XDp_Initialize | +
+ +
| #define XDprx_InterruptHandler XDp_InterruptHandler | +
+ +
| #define XDprx_IntrHandler XDp_IntrHandler | +
+ +
| #define XDprx_LookupConfig XDp_LookupConfig | +
+ +
| #define XDprx_ReadReg XDp_ReadReg | +
+ +
| #define XDprx_SelfTest XDp_SelfTest | +
+ +
| #define XDprx_SetUserTimerHandler XDp_SetUserTimerHandler | +
+ +
| #define XDprx_TimerHandler XDp_TimerHandler | +
+ +
| #define XDprx_WaitUs XDp_WaitUs | +
+ +
| #define XDprx_WriteReg XDp_WriteReg | +
+ +
| #define XDPTX XDP_TX | +
+ +
| #define XDptx XDp | +
+ +
| #define XDPTX_ XDP_TX_ | +
+ +
| #define XDptx_ XDp_Tx | +
+ +
| #define XDptx_CfgInitialize XDp_CfgInitialize | +
+ +
| #define XDptx_Config XDp_Config | +
+ +
| #define XDPTX_DPCD_ XDP_DPCD_ | +
+ +
| #define XDptx_HpdEventHandler XDp_IntrHandler | +
+ +
| #define XDptx_HpdInterruptHandler XDp_InterruptHandler | +
+ +
| #define XDptx_HpdPulseHandler XDp_IntrHandler | +
+ +
| #define XDptx_InitializeTx XDp_Initialize | +
+ +
| #define XDptx_LookupConfig XDp_LookupConfig | +
+ +
| #define XDptx_ReadReg XDp_ReadReg | +
+ +
| #define XDptx_SelfTest XDp_SelfTest | +
+ +
| #define XDptx_SetUserTimerHandler XDp_SetUserTimerHandler | +
+ +
| #define XDptx_TimerHandler XDp_TimerHandler | +
+ +
| #define XDptx_WaitUs XDp_WaitUs | +
+ +
| #define XDptx_WriteReg XDp_WriteReg | +
+ +
+
| typedef void(*) XDp_IntrHandler(void *InstancePtr) | +
+Callback type which represents the handler for interrupts.
+
| InstancePtr | is a pointer to the XDp instance. |
| typedef void(*) XDp_TimerHandler(void *InstancePtr, u32 MicroSeconds) | +
+Callback type which represents a custom timer wait handler. This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.
+
| InstancePtr | is a pointer to the XDp instance. | |
| MicroSeconds | is the number of microseconds to be passed to the timer function. |
+
| void XDp_CfgInitialize | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_Config * | +ConfigPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. | |
| EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
| u32 XDp_Initialize | +( | +XDp * | +InstancePtr | +) | ++ |
+This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_InterruptHandler | +( | +XDp * | +InstancePtr | +) | ++ |
+This function is the interrupt handler for the XDp driver. When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.
+
| InstancePtr | is a pointer to the XDp instance. |
| XDp_Config* XDp_LookupConfig | +( | +u16 | +DeviceId | +) | ++ |
+This function looks for the device configuration based on the unique device ID. The table XDp_ConfigTable[] contains the configuration information for each device in the system.
+
| DeviceId | is the unique device ID of the device being looked up. |
| u32 XDp_RxCheckLinkStatus | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if the reciever's internal registers indicate that link training has complete. That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxDtgDis | +( | +XDp * | +InstancePtr | +) | ++ |
+This function disables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxDtgEn | +( | +XDp * | +InstancePtr | +) | ++ |
+This function enables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxGenerateHpdInterrupt | +( | +XDp * | +InstancePtr, | +|
| + | + | u16 | +DurationUs | + |
| + | ) | ++ |
+This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DurationUs | is the duration of the HPD pulse, in microseconds. |
| void XDp_RxInterruptDisable | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function disables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Mask | specifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts. |
| void XDp_RxInterruptEnable | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function enables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Mask | specifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts. |
| void XDp_RxSetIntrBwChangeHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a bandwidth change interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrNoVideoHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a no video interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrPowerStateHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when the power state interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp1Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 1 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp2Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 2 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp3Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 3 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTrainingDoneHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training done interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTrainingLostHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training lost interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVBlankHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a vertical blanking interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVideoHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a valid video interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVmChangeHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a video mode change interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetLaneCount | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| void XDp_RxSetLinkRate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| void XDp_RxSetUserPixelWidth | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +UserPixelWidth | + |
| + | ) | ++ |
+This function configures the number of pixels output through the user data interface.
+
| InstancePtr | is a pointer to the XDp instance. | |
| UserPixelWidth | is the user pixel width to be configured. |
| u32 XDp_SelfTest | +( | +XDp * | +InstancePtr | +) | ++ |
+This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. The sanity test checks whether or not all tested registers hold their default reset values.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_SetUserTimerHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_TimerHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a custom delay/sleep function to be used by the XDp driver.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. |
| u32 XDp_TxAllocatePayloadStreams | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will allocate bandwidth for all enabled stream.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxAllocatePayloadVcIdTable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +VcId, | +|
| + | + | u8 | +Ts | + |
| + | ) | ++ |
+This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress.
+
| InstancePtr | is a pointer to the XDp instance. | |
| VcId | is the unique virtual channel ID to allocate into the payload ID tables. | |
| Ts | is the number of timeslots to allocate in the payload ID tables. |
+
| u32 XDp_TxAuxRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | void * | +ReadData | + |
| + | ) | ++ |
+This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DpcdAddress | is the starting address to read from the RX device. | |
| BytesToRead | is the number of bytes to read from the RX device. | |
| ReadData | is a pointer to the data buffer that will be filled with read data. |
| u32 XDp_TxAuxWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | void * | +WriteData | + |
| + | ) | ++ |
+This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DpcdAddress | is the starting address to write to the RX device. | |
| BytesToWrite | is the number of bytes to write to the RX device. | |
| WriteData | is a pointer to the data buffer that contains the data to be written to the RX device. |
| u32 XDp_TxCfgMainLinkMax | +( | +XDp * | +InstancePtr | +) | ++ |
+This function determines the common capabilities between the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxCfgMsaEnSynchClkMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables synchronous clock mode for a video stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to enable or disable synchronous clock mode. | |
| Enable | if set to 1, will enable synchronous clock mode. Otherwise, if set to 0, synchronous clock mode will be disabled. |
| void XDp_TxCfgMsaRecalculate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function calculates the following Main Stream Attributes (MSA):
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to calculate the MSA values. |
| void XDp_TxCfgMsaSetBpc | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +BitsPerColor | + |
| + | ) | ++ |
+This function sets the bits per color value of the video stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the color depth. | |
| BitsPerColor | is the new number of bits per color to use. |
| void XDp_TxCfgMsaUseCustom | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | XDp_TxMainStreamAttributes * | +MsaConfigCustom, | +|
| + | + | u8 | +Recalculate | + |
| + | ) | ++ |
+This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| MsaConfigCustom | is the structure that will be used to copy the main stream attributes from (into InstancePtr->TxInstance.MsaConfig). | |
| Recalculate | is a boolean enable that determines whether or not the main stream attributes should be recalculated. |
| void XDp_TxCfgMsaUseEdidPreferredTiming | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| Edid | is a pointer to the Edid to use for the specified stream. |
| void XDp_TxCfgMsaUseStandardVideoMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | XVidC_VideoMode | +VideoMode | + |
| + | ) | ++ |
+This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table. The XDp_TxVideoMode enumeration in xvidc.h lists the available video modes.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| VideoMode | is one of the enumerated standard video modes that is used to determine the MSA values to be used. |
| void XDp_TxCfgTxPeLevel | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Level, | +|
| + | + | u8 | +TxLevel | + |
| + | ) | ++ |
+This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Level | is the pre-emphasis training level to set the DisplayPort TX level for. | |
| TxLevel | is the DisplayPort TX pre-emphasis level value to be used during link training. |
| void XDp_TxCfgTxVsLevel | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Level, | +|
| + | + | u8 | +TxLevel | + |
| + | ) | ++ |
+This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Level | is the voltage swing training level to set the DisplayPort TX level for. | |
| TxLevel | is the DisplayPort TX voltage swing level value to be used during link training. |
| void XDp_TxCfgTxVsOffset | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Offset | + |
| + | ) | ++ |
+This function sets the voltage swing offset to use during training when no redriver exists. The offset will be added to the DisplayPort TX's voltage swing level value when pre-emphasis is used (when the pre-emphasis level not equal to 0).
+
| InstancePtr | is a pointer to the XDp instance. | |
| Offset | is the value to set for the voltage swing offset. |
| u32 XDp_TxCheckLinkStatus | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function checks if the reciever's DisplayPort Configuration Data (DPCD) indicates the reciever has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to check. |
| void XDp_TxClearMsaValues | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function clears the main stream attributes registers of the DisplayPort TX core.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to clear the MSA values. |
| u32 XDp_TxClearPayloadVcIdTable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| void XDp_TxDisableMainLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function disables the main link.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxDiscoverTopology | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxEnableMainLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function enables the main link.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxEnableTrainAdaptive | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables downshifting during the training process.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | controls the downshift feature in the training process. |
| u32 XDp_TxEstablishLink | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if the link needs training and runs the training sequence if training is required.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxFindAccessibleDpDevices | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the current downstream device in the recursion. | |
| RelativeAddress | is the relative address from the DisplayPort source to the current target DisplayPort device in the recursion. |
| u32 XDp_TxGetDispIdDataBlock | +( | +u8 * | +DisplayIdRaw, | +|
| + | + | u8 | +SectionTag, | +|
| + | + | u8 ** | +DataBlockPtr | + |
| + | ) | ++ |
+Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure.
+
| DisplayIdRaw | is a pointer to the DisplayID data. | |
| SectionTag | is the tag to search for that represents the desired section data block. | |
| DataBlockPtr | will be set by this function to point to the appropriate section data block that is part of the DisplayIdRaw. |
| u32 XDp_TxGetEdid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Edid | is a pointer to the Edid buffer to save to. |
| u32 XDp_TxGetEdidBlock | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +BlockNum | + |
| + | ) | ++ |
+Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number. A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the block data to. | |
| BlockNum | is the EDID block number to retrieve. |
| void XDp_TxGetGuid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 * | +Guid | + |
| + | ) | ++ |
+This function will obtain the global unique identifier (GUID) for the target DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target device. | |
| Guid | is a pointer to the GUID that will store the existing GUID of the target device. |
| u32 XDp_TxGetRemoteEdid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| Edid | is a pointer to the Edid buffer to save to. |
| u32 XDp_TxGetRemoteEdidBlock | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +BlockNum, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number. A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the block data to. | |
| BlockNum | is the EDID block number to retrieve. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| u32 XDp_TxGetRemoteEdidDispIdExt | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the DisplayID to. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| u32 XDp_TxGetRemoteTiledDisplayDb | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +EdidExt, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 ** | +DataBlockPtr | + |
| + | ) | ++ |
+Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure. The DisplayID structure is part of the Extended Display Identification Data (EDID) in the form of an extension block.
+
| InstancePtr | is a pointer to the XDp instance. | |
| EdidExt | is a pointer to the data area that will be filled by the retrieved DisplayID extension block. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. | |
| DataBlockPtr | will be set by this function to point to the TDT data block that is part of the EdidExt extension block. |
| u32 XDp_TxGetRxCapabilities | +( | +XDp * | +InstancePtr | +) | ++ |
+This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u16 | +Offset, | +|
| + | + | u16 | +BytesToRead, | +|
| + | + | void * | +ReadData | + |
| + | ) | ++ |
+This function performs an I2C read over the AUX channel. The read message will be divided into multiple transactions if the requested data spans multiple segments. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
+
| InstancePtr | is a pointer to the XDp instance. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
| u32 XDp_TxIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | void * | +WriteData | + |
| + | ) | ++ |
+This function performs an I2C write over the AUX channel.
+
| InstancePtr | is a pointer to the XDp instance. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| u32 XDp_TxIsConnected | +( | +XDp * | +InstancePtr | +) | ++ |
+This function checks if there is a connected RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxMstCapable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode. A DisplayPort Configuration Data (DPCD) version of 1.2 or higher is required and the MST capability bit in the DPCD must be set for this function to return XST_SUCCESS.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| void XDp_TxMstCfgModeDisable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will disable multi-stream transport (MST) mode for the driver.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxMstCfgModeEnable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will enable multi-stream transport (MST) mode for the driver.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxMstCfgStreamDisable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be disabled. |
| void XDp_TxMstCfgStreamEnable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be enabled. |
| u32 XDp_TxMstDisable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxMstEnable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u8 XDp_TxMstStreamIsEnabled | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will check whether
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID to check for enable/disable status. |
| u32 XDp_TxRemoteDpcdRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the starting address to read from the RX device. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to the data buffer that will be filled with read data. |
| u32 XDp_TxRemoteDpcdWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the starting address to write to the RX device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| u32 XDp_TxRemoteIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u16 | +Offset, | +|
| + | + | u16 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function performs a remote I2C read by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
| u32 XDp_TxRemoteIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function performs a remote I2C write by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| void XDp_TxResetPhy | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Reset | + |
| + | ) | ++ |
+This function does a PHY reset.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Reset | is the type of reset to assert. |
| u32 XDp_TxSendSbMsgAllocatePayload | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +VcId, | +|
| + | + | u16 | +Pbn | + |
| + | ) | ++ |
+This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| VcId | is the unique virtual channel ID to allocate into the payload ID tables. | |
| Pbn | is the payload bandwidth number that determines how much bandwidth will be allocated for the virtual channel. |
+
| u32 XDp_TxSendSbMsgClearPayloadIdTable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxSendSbMsgEnumPathResources | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u16 * | +AvailPbn, | +|
| + | + | u16 * | +FullPbn | + |
| + | ) | ++ |
+This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| AvailPbn | is a pointer to the available PBN of the path whose value will be filled in by this function. | |
| FullPbn | is a pointer to the total PBN of the path whose value will be filled in by this function. |
+
+AvailPbn will be modified with the available PBN from the reply.
+FullPbn will be modified with the total PBN of the path from the reply.
| u32 XDp_TxSendSbMsgLinkAddress | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | XDp_TxSbMsgLinkAddressReplyDeviceInfo * | +DeviceInfo | + |
| + | ) | ++ |
+This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device. It is used to determine the resources available for that device and some device information for each of the ports connected to the branch device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort branch device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort branch device. | |
| DeviceInfo | is a pointer to the device information structure whose contents will be filled in with the information obtained by the LINK_ADDRESS sideband message. |
+
| u32 XDp_TxSendSbMsgRemoteDpcdRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the DPCD address of the target device that data will be read from. | |
| BytesToRead | is the number of bytes to read from the specified DPCD address. | |
| ReadData | is a pointer to a buffer that will be filled with the DPCD read data. |
+
| u32 XDp_TxSendSbMsgRemoteDpcdWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the DPCD address of the target device that data will be written to. | |
| BytesToWrite | is the number of bytes to write to the specified DPCD address. | |
| WriteData | is a pointer to a buffer that stores the data to write to the DPCD location. |
+
| u32 XDp_TxSendSbMsgRemoteIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicDeviceId, | +|
| + | + | u8 | +Offset, | +|
| + | + | u8 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicDeviceId | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read from the I2C address. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
+
| u32 XDp_TxSendSbMsgRemoteIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicDeviceId, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+ +
| u32 XDp_TxSetDownspread | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will downspread the main link signal if set to 1 and disable downspreading if set to 0. |
| u32 XDp_TxSetEnhancedFrameMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will enable enhanced frame mode if set to 1 and disable it if set to 0. |
| void XDp_TxSetHasRedriverInPath | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Set | + |
| + | ) | ++ |
+This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. XDp_TxSetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Set | establishes that a redriver exists in the DisplayPort output path. |
| void XDp_TxSetHpdEventHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a hot-plug-detect event interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_TxSetHpdPulseHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| u32 XDp_TxSetLaneCount | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| u32 XDp_TxSetLinkRate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| void XDp_TxSetMsaValues | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the MSA values for. |
| u32 XDp_TxSetScrambler | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Enable | will enable or disable scrambling. |
| void XDp_TxSetStreamSelectFromSinkList | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +SinkNum | + |
| + | ) | ++ |
+This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be mapped to a DisplayPort device. | |
| SinkNum | is the sink ID in the sink list that will be mapped to the stream. |
+The topology will need to be determined prior to calling this function using the XDp_TxFindAccessibleDpDevices.
| void XDp_TxSetStreamSinkRad | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+This function will map a stream to a downstream DisplayPort TX device determined by the relative address.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number that will be mapped to a DisplayPort device. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| void XDp_TxSetVideoMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the MSA values for. |
| void XDp_TxTopologySortSinksByTiling | +( | +XDp * | +InstancePtr | +) | ++ |
+Order the sink list with all sinks of the same tiled display being sorted by 'tile order'. Refer to the XDp_TxGetDispIdTdtTileOrder macro on how to determine the 'tile order'. Sinks of a tiled display will have an index in the sink list that is lower than all indices of other sinks within that same tiled display that have a greater 'tile order'. When operations are done on the sink list, this ordering will ensure that sinks within the same tiled display will be acted upon in a consistent manner - with an incrementing sink list index, sinks with a lower 'tile order' will be acted upon first relative to the other sinks in the same tiled display. Multiple tiled displays may exist in the sink list.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxTopologySwapSinks | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Index0, | +|
| + | + | u8 | +Index1 | + |
| + | ) | ++ |
+Swap the ordering of the sinks in the topology's sink list. All sink information is preserved in the node table - the swapping takes place only on the pointers to the sinks in the node table. The reason this swapping is done is so that functions that use the sink list will act on the sinks in a different order.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Index0 | is the sink list's index of one of the sink pointers to be swapped. | |
| Index1 | is the sink list's index of the other sink pointer to be swapped. |
| void XDp_TxWriteGuid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +Guid[4] | + |
| + | ) | ++ |
+This function will write a global unique identifier (GUID) to the target DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target device. | |
| Guid | is a the GUID to write to the target device. |
| void XDp_WaitUs | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +MicroSeconds | + |
| + | ) | ++ |
+This function is the delay/sleep function for the XDp driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
+
| InstancePtr | is a pointer to the XDp instance. | |
| MicroSeconds | is the number of microseconds to delay/sleep for. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__edid_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__edid_8c.html new file mode 100644 index 00000000..37a4e2ca --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__edid_8c.html @@ -0,0 +1,418 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+
Functions | |
| u32 | XDp_TxGetEdid (XDp *InstancePtr, u8 *Edid) |
| u32 | XDp_TxGetRemoteEdid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid) |
| u32 | XDp_TxGetEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum) |
| u32 | XDp_TxGetRemoteEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxGetRemoteEdidDispIdExt (XDp *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxGetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) |
| u32 | XDp_TxGetRemoteTiledDisplayDb (XDp *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr) |
| u32 XDp_TxGetDispIdDataBlock | +( | +u8 * | +DisplayIdRaw, | +|
| + | + | u8 | +SectionTag, | +|
| + | + | u8 ** | +DataBlockPtr | + |
| + | ) | ++ |
+Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure.
+
| DisplayIdRaw | is a pointer to the DisplayID data. | |
| SectionTag | is the tag to search for that represents the desired section data block. | |
| DataBlockPtr | will be set by this function to point to the appropriate section data block that is part of the DisplayIdRaw. |
| u32 XDp_TxGetEdid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Edid | is a pointer to the Edid buffer to save to. |
| u32 XDp_TxGetEdidBlock | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +BlockNum | + |
| + | ) | ++ |
+Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number. A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the block data to. | |
| BlockNum | is the EDID block number to retrieve. |
| u32 XDp_TxGetRemoteEdid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| Edid | is a pointer to the Edid buffer to save to. |
| u32 XDp_TxGetRemoteEdidBlock | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +BlockNum, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number. A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the block data to. | |
| BlockNum | is the EDID block number to retrieve. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| u32 XDp_TxGetRemoteEdidDispIdExt | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +Data, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Data | is a pointer to the data buffer to save the DisplayID to. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| u32 XDp_TxGetRemoteTiledDisplayDb | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 * | +EdidExt, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 ** | +DataBlockPtr | + |
| + | ) | ++ |
+Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure. The DisplayID structure is part of the Extended Display Identification Data (EDID) in the form of an extension block.
+
| InstancePtr | is a pointer to the XDp instance. | |
| EdidExt | is a pointer to the data area that will be filled by the retrieved DisplayID extension block. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. | |
| DataBlockPtr | will be set by this function to point to the TDT data block that is part of the EdidExt extension block. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html new file mode 100644 index 00000000..6162fa8b --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__hw_8h.html @@ -0,0 +1,15694 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xil_io.h"
+
| #define XDP_DPCD_ADAPTER_CAP 0x0000F | +
+ +
| #define XDP_DPCD_ADAPTER_CTRL 0x001A0 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_0_1 0x00206 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 | +
+ +
| #define XDP_DPCD_ADJ_REQ_LANE_2_3 0x00207 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2 0x0020C | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 | +
+ +
| #define XDP_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 | +
+ +
| #define XDP_DPCD_AUD_DEC_LAT_15_8 0x00025 | +
+ +
| #define XDP_DPCD_AUD_DEC_LAT_7_0 0x00024 | +
+ +
| #define XDP_DPCD_AUD_DEL_INS_15_8 0x0002C | +
+ +
| #define XDP_DPCD_AUD_DEL_INS_23_16 0x0002D | +
+ +
| #define XDP_DPCD_AUD_DEL_INS_7_0 0x0002B | +
+ +
| #define XDP_DPCD_AUD_PP_LAT_15_8 0x00027 | +
+ +
| #define XDP_DPCD_AUD_PP_LAT_7_0 0x00026 | +
+ +
| #define XDP_DPCD_AUDIO_DELAY_15_8 0x00113 | +
+ +
| #define XDP_DPCD_AUDIO_DELAY_23_6 0x00114 | +
+ +
| #define XDP_DPCD_AUDIO_DELAY_7_0 0x00112 | +
+ +
| #define XDP_DPCD_AV_GRANULARITY 0x00023 | +
+ +
| #define XDP_DPCD_BACK_CH_STATUS 0x00122 | +
+ +
| #define XDP_DPCD_BRANCH_DEVICE_CTRL 0x001A1 | +
+ +
| #define XDP_DPCD_DEVICE_SERVICE_IRQ 0x00201 | +
+ +
| #define XDP_DPCD_DOWN_REP 0x01400 | +
+ +
| #define XDP_DPCD_DOWN_REQ 0x01000 | +
+ +
| #define XDP_DPCD_DOWNSP_0_CAP 0x00080 | +
+ +
| #define XDP_DPCD_DOWNSP_0_DET_CAP 0x00080 | +
+ +
| #define XDP_DPCD_DOWNSP_1_CAP 0x00081 | +
+ +
| #define XDP_DPCD_DOWNSP_1_DET_CAP 0x00084 | +
+ +
| #define XDP_DPCD_DOWNSP_2_CAP 0x00082 | +
+ +
| #define XDP_DPCD_DOWNSP_2_DET_CAP 0x00088 | +
+ +
| #define XDP_DPCD_DOWNSP_3_CAP 0x00083 | +
+ +
| #define XDP_DPCD_DOWNSP_3_DET_CAP 0x0008C | +
+ +
| #define XDP_DPCD_DOWNSP_COUNT_MASK 0x0F | +
+ +
| #define XDP_DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 | +
+ +
| #define XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 | +
+ +
| #define XDP_DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 | +
+ +
| #define XDP_DPCD_DOWNSP_PRESENT 0x00005 | +
+ +
| #define XDP_DPCD_DOWNSP_PRESENT_MASK 0x01 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_DP 0x0 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_MASK 0x06 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_OTHERS 0x3 | +
+ +
| #define XDP_DPCD_DOWNSP_TYPE_SHIFT 1 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 | +
+ +
| #define XDP_DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 | +
+ +
| #define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 | +
+ +
| #define XDP_DPCD_DOWNSPREAD_CTRL 0x00107 | +
+ +
| #define XDP_DPCD_EDP_CFG_CAP 0x0000D | +
+ +
| #define XDP_DPCD_EDP_CFG_SET 0x0010A | +
+ +
| #define XDP_DPCD_ENHANCED_FRAME_EN_MASK 0x80 | +
+ +
| #define XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 | +
+ +
| #define XDP_DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 | +
+ +
| #define XDP_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 | +
+ +
| #define XDP_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 | +
+ +
| #define XDP_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 | +
+ +
| #define XDP_DPCD_FAUX_CAP 0x00020 | +
+ +
| #define XDP_DPCD_FAUX_CAP_MASK 0x01 | +
+ +
| #define XDP_DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 | +
+ +
| #define XDP_DPCD_FAUX_FORWARD_CH_STATUS 0x00280 | +
+ +
| #define XDP_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D | +
+ +
| #define XDP_DPCD_FAUX_MODE_CTRL 0x00120 | +
+ +
| #define XDP_DPCD_GUID 0x00030 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_100KBIPS 0x08 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_10KBIPS 0x04 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_1KBIPS 0x01 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_1MBIPS 0x20 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_400KBIPS 0x10 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_5KBIPS 0x02 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_CAP 0x0000C | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_NONE 0x00 | +
+ +
| #define XDP_DPCD_I2C_SPEED_CTL_SET 0x00109 | +
+ +
| #define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 | +
+ +
| #define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK 0x40 | +
+ +
| #define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01 | +
+ +
| #define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK 0x80 | +
+ +
| #define XDP_DPCD_LANE_COUNT_SET 0x00101 | +
+ +
| #define XDP_DPCD_LANE_COUNT_SET_1 0x01 | +
+ +
| #define XDP_DPCD_LANE_COUNT_SET_2 0x02 | +
+ +
| #define XDP_DPCD_LANE_COUNT_SET_4 0x04 | +
+ +
| #define XDP_DPCD_LANE_COUNT_SET_MASK 0x1F | +
+ +
| #define XDP_DPCD_LINK_BW_SET 0x00100 | +
+ +
| #define XDP_DPCD_LINK_BW_SET_162GBPS 0x06 | +
+ +
| #define XDP_DPCD_LINK_BW_SET_270GBPS 0x0A | +
+ +
| #define XDP_DPCD_LINK_BW_SET_540GBPS 0x14 | +
+ +
| #define XDP_DPCD_LINK_CFG_FIELD_SIZE 0x100 | +
+ +
| #define XDP_DPCD_LINK_CFG_FIELD_START XDP_DPCD_LINK_BW_SET | +
+ +
| #define XDP_DPCD_LINK_QUAL_LANE0_SET 0x0010B | +
+ +
| #define XDP_DPCD_LINK_QUAL_LANE1_SET 0x0010C | +
+ +
| #define XDP_DPCD_LINK_QUAL_LANE2_SET 0x0010D | +
+ +
| #define XDP_DPCD_LINK_QUAL_LANE3_SET 0x0010E | +
+ +
| #define XDP_DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 | +
+ +
| #define XDP_DPCD_LINK_SINK_STATUS_FIELD_START XDP_DPCD_SINK_COUNT | +
+ +
| #define XDP_DPCD_MAX_DOWNSPREAD 0x00003 | +
+ +
| #define XDP_DPCD_MAX_DOWNSPREAD_MASK 0x01 | +
+ +
| #define XDP_DPCD_MAX_LANE_COUNT 0x00002 | +
+ +
| #define XDP_DPCD_MAX_LANE_COUNT_1 0x01 | +
+ +
| #define XDP_DPCD_MAX_LANE_COUNT_2 0x02 | +
+ +
| #define XDP_DPCD_MAX_LANE_COUNT_4 0x04 | +
+ +
| #define XDP_DPCD_MAX_LANE_COUNT_MASK 0x1F | +
+ +
| #define XDP_DPCD_MAX_LINK_RATE 0x00001 | +
+ +
| #define XDP_DPCD_MAX_LINK_RATE_162GBPS 0x06 | +
+ +
| #define XDP_DPCD_MAX_LINK_RATE_270GBPS 0x0A | +
+ +
| #define XDP_DPCD_MAX_LINK_RATE_540GBPS 0x14 | +
+ +
| #define XDP_DPCD_ML_CH_CODING_CAP 0x00006 | +
+ +
| #define XDP_DPCD_ML_CH_CODING_MASK 0x01 | +
+ +
| #define XDP_DPCD_ML_CH_CODING_SET 0x00108 | +
+ +
| #define XDP_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 | +
+ +
| #define XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 | +
+ +
| #define XDP_DPCD_MST_CAP_MASK 0x01 | +
+ +
| #define XDP_DPCD_MST_EN_MASK 0x01 | +
+ +
| #define XDP_DPCD_MSTM_CAP 0x00021 | +
+ +
| #define XDP_DPCD_MSTM_CTRL 0x00111 | +
+ +
| #define XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 | +
+ +
| #define XDP_DPCD_NORP_PWR_V_CAP 0x00004 | +
+ +
| #define XDP_DPCD_NUM_AUDIO_EPS 0x00022 | +
+ +
| #define XDP_DPCD_OUI_SUPPORT_MASK 0x80 | +
+ +
| #define XDP_DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 | +
+ +
| #define XDP_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 | +
+ +
| #define XDP_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 | +
+ +
| #define XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 | +
+ +
| #define XDP_DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 | +
+ +
| #define XDP_DPCD_RECEIVER_CAP_FIELD_START XDP_DPCD_REV | +
+ +
| #define XDP_DPCD_REP_LAT 0x0002A | +
+ +
| #define XDP_DPCD_REV 0x00000 | +
+ +
| #define XDP_DPCD_REV_MJR_MASK 0xF0 | +
+ +
| #define XDP_DPCD_REV_MJR_SHIFT 4 | +
+ +
| #define XDP_DPCD_REV_MNR_MASK 0x0F | +
+ +
| #define XDP_DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 | +
+ +
| #define XDP_DPCD_RX_GTC_MSTR_REQ 0x00058 | +
+ +
| #define XDP_DPCD_RX_GTC_VALUE_15_8 0x00055 | +
+ +
| #define XDP_DPCD_RX_GTC_VALUE_23_16 0x00056 | +
+ +
| #define XDP_DPCD_RX_GTC_VALUE_31_24 0x00057 | +
+ +
| #define XDP_DPCD_RX_GTC_VALUE_7_0 0x00054 | +
+ +
| #define XDP_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 | +
+ +
| #define XDP_DPCD_RX_PORT0_CAP_0 0x00008 | +
+ +
| #define XDP_DPCD_RX_PORT0_CAP_1 0x00009 | +
+ +
| #define XDP_DPCD_RX_PORT1_CAP_0 0x0000A | +
+ +
| #define XDP_DPCD_RX_PORT1_CAP_1 0x0000B | +
+ +
| #define XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 | +
+ +
| #define XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 | +
+ +
| #define XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 | +
+ +
| #define XDP_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E | +
+ +
| #define XDP_DPCD_SINK_COUNT 0x00200 | +
+ +
| #define XDP_DPCD_SINK_COUNT_ESI 0x02002 | +
+ +
| #define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 | +
+ +
| #define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 | +
+ +
| #define XDP_DPCD_SINK_LANE0_1_STATUS 0x0200C | +
+ +
| #define XDP_DPCD_SINK_LANE2_3_STATUS 0x0200D | +
+ +
| #define XDP_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 | +
+ +
| #define XDP_DPCD_SINK_STATUS 0x00205 | +
+ +
| #define XDP_DPCD_SINK_STATUS_ESI 0x0200F | +
+ +
| #define XDP_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 | +
+ +
| #define XDP_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 | +
+ +
| #define XDP_DPCD_SPREAD_AMP_MASK 0x10 | +
+ +
| #define XDP_DPCD_STATUS_LANE_0_1 0x00202 | +
+ +
| #define XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 | +
+ +
| #define XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 | +
+ +
| #define XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 | +
+ +
| #define XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 | +
+ +
| #define XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 | +
+ +
| #define XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 | +
+ +
| #define XDP_DPCD_STATUS_LANE_2_3 0x00203 | +
+ +
| #define XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 | +
+ +
| #define XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 | +
+ +
| #define XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 | +
+ +
| #define XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 | +
+ +
| #define XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 | +
+ +
| #define XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 | +
+ +
| #define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 | +
+ +
| #define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 | +
+ +
| #define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 | +
+ +
| #define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 | +
+ +
| #define XDP_DPCD_TP_SEL_MASK 0x03 | +
+ +
| #define XDP_DPCD_TP_SEL_OFF 0x0 | +
+ +
| #define XDP_DPCD_TP_SEL_TP1 0x1 | +
+ +
| #define XDP_DPCD_TP_SEL_TP2 0x2 | +
+ +
| #define XDP_DPCD_TP_SEL_TP3 0x3 | +
+ +
| #define XDP_DPCD_TP_SET 0x00102 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_D102_TEST 0x1 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_MASK 0x06 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_OFF 0x0 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_PRBS7 0x3 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_SER_MES 0x2 | +
+ +
| #define XDP_DPCD_TP_SET_LQP_SHIFT 2 | +
+ +
| #define XDP_DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 | +
+ +
| #define XDP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 | +
+ +
| #define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 | +
+ +
| #define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 | +
+ +
| #define XDP_DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 | +
+ +
| #define XDP_DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 | +
+ +
| #define XDP_DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 | +
+ +
| #define XDP_DPCD_TPS3_SUPPORT_MASK 0x40 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INT_12MS 0x03 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INT_16MS 0x04 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INT_4MS 0x01 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INT_8MS 0x02 | +
+ +
| #define XDP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E | +
+ +
| #define XDP_DPCD_TRAINING_LANE0_1_SET2 0x0010F | +
+ +
| #define XDP_DPCD_TRAINING_LANE0_SET 0x00103 | +
+ +
| #define XDP_DPCD_TRAINING_LANE1_SET 0x00104 | +
+ +
| #define XDP_DPCD_TRAINING_LANE2_3_SET2 0x00110 | +
+ +
| #define XDP_DPCD_TRAINING_LANE2_SET 0x00105 | +
+ +
| #define XDP_DPCD_TRAINING_LANE3_SET 0x00106 | +
+ +
| #define XDP_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 | +
+ +
| #define XDP_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 | +
+ +
| #define XDP_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 | +
+ +
| #define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 | +
+ +
| #define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 | +
+ +
| #define XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 | +
+ +
| #define XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 | +
+ +
| #define XDP_DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 | +
+ +
| #define XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 | +
+ +
| #define XDP_DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 | +
+ +
| #define XDP_DPCD_TRAINING_SCORE_LANE_0 0x00208 | +
+ +
| #define XDP_DPCD_TRAINING_SCORE_LANE_1 0x00209 | +
+ +
| #define XDP_DPCD_TRAINING_SCORE_LANE_2 0x0020A | +
+ +
| #define XDP_DPCD_TRAINING_SCORE_LANE_3 0x0020B | +
+ +
| #define XDP_DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 | +
+ +
| #define XDP_DPCD_TX_GTC_VALUE_15_8 0x00155 | +
+ +
| #define XDP_DPCD_TX_GTC_VALUE_23_16 0x00156 | +
+ +
| #define XDP_DPCD_TX_GTC_VALUE_31_24 0x00157 | +
+ +
| #define XDP_DPCD_TX_GTC_VALUE_7_0 0x00154 | +
+ +
| #define XDP_DPCD_UP_IS_SRC_MASK 0x03 | +
+ +
| #define XDP_DPCD_UP_REP 0x01200 | +
+ +
| #define XDP_DPCD_UP_REQ 0x01600 | +
+ +
| #define XDP_DPCD_UP_REQ_EN_MASK 0x02 | +
+ +
| #define XDP_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 | +
+ +
| #define XDP_DPCD_VC_PAYLOAD_ID_SLOT | +( | +SlotNum | ++ | ) | +(XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum) | +
+ +
| #define XDP_DPCD_VID_INTER_LAT 0x00028 | +
+ +
| #define XDP_DPCD_VID_PROG_LAT 0x00029 | +
+ +
| #define XDP_EDID_ADDR 0x50 | +
+ +
| #define XDP_EDID_BLOCK_SIZE 128 | +
+ +
| #define XDP_EDID_DTD_DD | +( | +Num | ++ | ) | +(0x36 + (18 * Num)) | +
+ +
| #define XDP_EDID_DTD_HBLANK_LSB 0x03 | +
+ +
| #define XDP_EDID_DTD_HBORDER 0x0F | +
+ +
| #define XDP_EDID_DTD_HFPORCH_LSB 0x08 | +
+ +
| #define XDP_EDID_DTD_HIMGSIZE_MM_LSB 0x0C | +
+ +
| #define XDP_EDID_DTD_HRES_HBLANK_U4 0x04 | +
+ +
| #define XDP_EDID_DTD_HRES_LSB 0x02 | +
+ +
| #define XDP_EDID_DTD_HSPW_LSB 0x09 | +
+ +
| #define XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00 | +
+ +
| #define XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB 0x01 | +
+ +
| #define XDP_EDID_DTD_SIGNAL 0x11 | +
+ +
| #define XDP_EDID_DTD_SIGNAL_HPOLARITY_MASK 0x02 | +
+ +
| #define XDP_EDID_DTD_SIGNAL_HPOLARITY_SHIFT 1 | +
+ +
| #define XDP_EDID_DTD_SIGNAL_VPOLARITY_MASK 0x04 | +
+ +
| #define XDP_EDID_DTD_SIGNAL_VPOLARITY_SHIFT 2 | +
+ +
| #define XDP_EDID_DTD_VBLANK_LSB 0x06 | +
+ +
| #define XDP_EDID_DTD_VBORDER 0x10 | +
+ +
| #define XDP_EDID_DTD_VFPORCH_VSPW_L4 0x0A | +
+ +
| #define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 | +
+ +
| #define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 | +
+ +
| #define XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK 0x0F | +
+ +
| #define XDP_EDID_DTD_VIMGSIZE_MM_LSB 0x0D | +
+ +
| #define XDP_EDID_DTD_VRES_LSB 0x05 | +
+ +
| #define XDP_EDID_DTD_VRES_VBLANK_U4 0x07 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2 0x0B | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK 0x30 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT 4 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 | +
+ +
| #define XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK 0x03 | +
+ +
| #define XDP_EDID_DTD_XIMGSIZE_MM_U4 0x0E | +
+ +
| #define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 | +
+ +
| #define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 | +
+ +
| #define XDP_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F | +
+ +
| #define XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F | +
+ +
| #define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK 0xF0 | +
+ +
| #define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT 4 | +
+ +
| #define XDP_EDID_EXT_BLOCK_COUNT 0x7E | +
+ +
| #define XDP_EDID_EXT_BLOCK_TAG 0x00 | +
+ +
| #define XDP_EDID_EXT_BLOCK_TAG_DISPID 0x70 | +
+ +
| #define XDP_EDID_PTM XDP_EDID_DTD_DD(0) | +
+ +
| #define XDp_In32 Xil_In32 | +
+ +
| #define XDp_Out32 Xil_Out32 | +
+ +
| #define XDp_ReadReg | +( | +BaseAddress, | |||
| + | + | RegOffset | ++ | ) | +XDp_In32((BaseAddress) + (RegOffset)) | +
+This is a low-level function that reads from the specified register.
+
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to be read from. |
| #define XDP_RX_AUDIO_CONTROL 0x300 | +
+Enables audio stream packets in main link. +
| #define XDP_RX_AUDIO_EXT_DATA | +( | +NUM | ++ | ) | +(0x330 + 4 * (NUM - 1)) | +
+Word formatted as per extension packet. +
| #define XDP_RX_AUDIO_INFO_DATA | +( | +NUM | ++ | ) | +(0x304 + 4 * (NUM - 1)) | +
+Word formatted as per CEA 861-C info frame. +
| #define XDP_RX_AUDIO_MAUD 0x324 | +
+M value of audio stream as decoded from audio time stamp packet. +
| #define XDP_RX_AUDIO_NAUD 0x328 | +
+N value of audio stream as decoded from audio time stamp packet. +
| #define XDP_RX_AUDIO_STATUS 0x32C | +
+Status of audio stream. +
| #define XDP_RX_AUDIO_UNSUPPORTED 0x098 | +
+DPCD register bit to inform the DisplayPort TX that audio data is not supported. +
| #define XDP_RX_AUX_CLK_DIVIDER 0x004 | +
+Clock divider value for generating the internal 1MHz clock. +
| #define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 | +
+AUX (noise) signal width filter. +
| #define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 | +
+Shift bits for AUX signal width filter. +
| #define XDP_RX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF | +
+Clock divider value. +
| #define XDP_RX_AUX_REQ_IN_PROGRESS 0x020 | +
+Indicates the receipt of an AUX channel request. +
| #define XDP_RX_CDR_CONTROL_CONFIG 0x21C | +
+Control the configuration for clock and data recovery. +
| #define XDP_RX_CORE_ID 0x0FC | +
+DisplayPort protocol version and revision. +
| #define XDP_RX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 | +
+DisplayPort protocol major version. +
| #define XDP_RX_CORE_ID_DP_MJR_VER_SHIFT 24 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDP_RX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 | +
+DisplayPort protocol minor version. +
| #define XDP_RX_CORE_ID_DP_MNR_VER_SHIFT 16 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDP_RX_CORE_ID_DP_REV_MASK 0x000000F0 | +
+DisplayPort protocol revision. +
| #define XDP_RX_CORE_ID_DP_REV_SHIFT 8 | +
+Shift bits for DisplayPort protocol revision. +
| #define XDP_RX_CORE_ID_TYPE_MASK 0x0000000F | +
+Core type. +
| #define XDP_RX_CORE_ID_TYPE_RX 0x1 | +
+Core is a receiver. +
| #define XDP_RX_CORE_ID_TYPE_TX 0x0 | +
+Core is a transmitter. +
| #define XDP_RX_DEVICE_SERVICE_IRQ 0x090 | +
+Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state. +
| #define XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK 0x10 | +
+Indicates a new DOWN_REPLY buffer message is ready. +
| #define XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK 0x01 | +
+Indicates that a new command is present in the REMOTE_CMD register. +
| #define XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK 0x02 | +
+Reflects the SINK_SPECIFIC_IRQ state. +
| #define XDP_RX_DOWN_REP 0xB00 | +
+Down reply buffer address space. +
| #define XDP_RX_DOWN_REQ 0xA00 | +
+Down request buffer address space. +
| #define XDP_RX_DPCD_DOWNSPREAD_CONTROL 0x430 | +
+The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled. +
| #define XDP_RX_DPCD_ENHANCED_FRAME_EN 0x408 | +
+Current setting for enhanced framing symbol mode as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_LANE01_STATUS 0x43C | +
+Link training status for lanes 0 and 1 as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_LANE23_STATUS 0x440 | +
+Link training status for lanes 2 and 3 as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_LANE_COUNT_SET 0x404 | +
+Current lane count setting as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_LINK_BW_SET 0x400 | +
+Current link bandwidth setting as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 | +
+Current value of the link quality pattern field as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 | +
+8B/10B encoding setting as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 | +
+Value of the output clock enable field as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_SCRAMBLING_DISABLE 0x418 | +
+Value of the scrambling disable field as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_SET_POWER_STATE 0x438 | +
+Power state requested by the TX as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_SOURCE_OUI_VALUE 0x444 | +
+ +
| #define XDP_RX_DPCD_SYM_ERR_CNT01 0x448 | +
+ +
| #define XDP_RX_DPCD_SYM_ERR_CNT23 0x44C | +
+ +
| #define XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C | +
+Current value of the symbol error count select field as exposed in the RX DPCD. +
| #define XDP_RX_DPCD_TRAINING_LANE_0_SET 0x420 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 0. +
| #define XDP_RX_DPCD_TRAINING_LANE_1_SET 0x424 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 1. +
| #define XDP_RX_DPCD_TRAINING_LANE_2_SET 0x428 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 2. +
| #define XDP_RX_DPCD_TRAINING_LANE_3_SET 0x42C | +
+The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3. +
| #define XDP_RX_DPCD_TRAINING_PATTERN_SET 0x40C | +
+Current training pattern setting as exposed in the RX DPCD. +
| #define XDP_RX_DTG_ENABLE 0x00C | +
+Enables the display timing generator (DTG). +
| #define XDP_RX_FAST_I2C_DIVIDER 0x060 | +
+Fast I2C mode clock divider value. +
| #define XDP_RX_GT_DRP_CH_STATUS 0x2A8 | +
+Provides access to GT DRP channel status. +
| #define XDP_RX_GT_DRP_COMMAND 0x2A0 | +
+Provides access to the GT DRP ports. +
| #define XDP_RX_GT_DRP_READ_DATA 0x2A4 | +
+Provides access to GT DRP read data. +
| #define XDP_RX_GUID0 0x0E0 | +
+Lower 4 bytes of the DPCD's GUID field. +
| #define XDP_RX_GUID1 0x0E4 | +
+Bytes 4 to 7 of the DPCD's GUID field. +
| #define XDP_RX_GUID2 0x0E8 | +
+Bytes 8 to 11 of the DPCD's GUID field. +
| #define XDP_RX_GUID3 0x0EC | +
+Upper 4 bytes of the DPCD's GUID field. +
| #define XDP_RX_HPD_INTERRUPT 0x02C | +
+Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal. +
| #define XDP_RX_HPD_INTERRUPT_ASSERT_MASK 0x00000001 | +
+Instructs the RX core to assert an interrupt to the TX using the HPD signal. +
| #define XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK 0xFFFF0000 | +
+The length of the HPD pulse to generate (in microseconds). +
| #define XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 | +
+Shift bits for the HPD pulse length. +
| #define XDP_RX_HSYNC_WIDTH 0x050 | +
+Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG). +
| #define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK 0xFF00 | +
+Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch). +
| #define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 | +
+Shift bits for the front porch. +
| #define XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK 0x00FF | +
+Specifies the number of clock cycles the horizontal sync pulse is asserted. +
| #define XDP_RX_INTERRUPT_CAUSE 0x040 | +
+Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel. +
| #define XDP_RX_INTERRUPT_CAUSE_1 0x048 | +
+Indicates the cause of a pending host interrupts for streams 2, 3, 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) | +
+Interrupt caused by an audio extension packet being received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) | +
+Interrupt caused by an audio info packet being received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) | +
+Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) | +
+Interrupt caused by the start of the blanking interval for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) | +
+Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK | +( | +Stream | ++ | ) | +XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) | +
+Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK | +
+Interrupt caused by a change in bandwidth. +
| #define XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK | +
+Interrupt caused by a downstream reply being ready. +
| #define XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK | +
+Interrupt caused by a downstream request being ready. +
| #define XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK | +
+Interrupt caused by an audio extension packet being received. +
| #define XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK | +
+Interrupt caused by an audio info packet being received. +
| #define XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK | +
+Interrupt caused by the no-video condition being detected after active video received. +
| #define XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK | +
+Interrupt caused by a power state change. +
| #define XDP_RX_INTERRUPT_CAUSE_TP1_MASK XDP_RX_INTERRUPT_MASK_TP1_MASK | +
+Interrupt caused by the start of training pattern 1. +
| #define XDP_RX_INTERRUPT_CAUSE_TP2_MASK XDP_RX_INTERRUPT_MASK_TP2_MASK | +
+Interrupt caused by the start of training pattern 2. +
| #define XDP_RX_INTERRUPT_CAUSE_TP3_MASK XDP_RX_INTERRUPT_MASK_TP3_MASK | +
+Interrupt caused by the start of training pattern 3. +
| #define XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK | +
+Interrupt caused by link training completion. +
| #define XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK | +
+Interrupt caused by training loss on active lanes. +
| #define XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK XDP_RX_INTERRUPT_MASK_VBLANK_MASK | +
+Interrupt caused by the start of the blanking interval. +
| #define XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK | +
+Interrupt caused by a virtual channel payload being allocated. +
| #define XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK | +
+Interrupt caused by a virtual channel payload being allocated. +
| #define XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK XDP_RX_INTERRUPT_MASK_VIDEO_MASK | +
+Interrupt caused by a valid video frame being detected on the main link. Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character. +
| #define XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK | +
+Interrupt caused by a resolution change, as detected from the MSA fields. +
| #define XDP_RX_INTERRUPT_MASK 0x014 | +
+Masks the specified interrupt sources for stream 1. +
| #define XDP_RX_INTERRUPT_MASK_1 0x044 | +
+Masks the specified interrupt sources for streams 2, 3, 4. +
| #define XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00001 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00002 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00008 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00010 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00020 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00004 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4. +
| #define XDP_RX_INTERRUPT_MASK_ALL_MASK 0x7FFFF | +
+Mask all interrupts. +
| #define XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK 0x08000 | +
+Mask the interrupt assertion for a change in bandwidth. +
| #define XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK 0x01000 | +
+Mask the interrupt assertion for a downstream reply being ready. +
| #define XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK 0x02000 | +
+Mask the interrupt assertion for a downstream request being ready. +
| #define XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK 0x00200 | +
+Mask the interrupt assertion for an audio extension packet being received. +
| #define XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK 0x00100 | +
+Mask the interrupt assertion for an audio info packet being received. +
| #define XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK 0x00004 | +
+Mask the interrupt assertion for the no-video condition being detected after active video received. +
| #define XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK 0x00002 | +
+Mask the interrupt assertion for a power state change. +
| #define XDP_RX_INTERRUPT_MASK_TP1_MASK 0x10000 | +
+Mask the interrupt assertion for start of training pattern 1. +
| #define XDP_RX_INTERRUPT_MASK_TP2_MASK 0x20000 | +
+Mask the interrupt assertion for start of training pattern 2. +
| #define XDP_RX_INTERRUPT_MASK_TP3_MASK 0x40000 | +
+Mask the interrupt assertion for start of training pattern 3. +
| #define XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK 0x04000 | +
+Mask the interrupt assertion for link training completion. +
| #define XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK 0x00010 | +
+Mask the interrupt assertion for training loss on active lanes. +
| #define XDP_RX_INTERRUPT_MASK_VBLANK_MASK 0x00008 | +
+Mask the interrupt assertion for the start of the blanking interval. +
| #define XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK 0x00400 | +
+Mask the interrupt assertion for a virtual channel payload being allocated. +
| #define XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK 0x00800 | +
+Mask the interrupt assertion for a virtual channel payload being allocated. +
| #define XDP_RX_INTERRUPT_MASK_VIDEO_MASK 0x00040 | +
+Mask the interrupt assertion for a valid video frame being detected on the main link. Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character. +
| #define XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK 0x00001 | +
+Mask the interrupt assertion for a resolution change, as detected from the MSA fields. +
| #define XDP_RX_LINK_ENABLE 0x000 | +
+Enable the receiver core. +
| #define XDP_RX_LOCAL_EDID_AUDIO 0x088 | +
+Indicates the presence of EDID information for the audio stream. +
| #define XDP_RX_LOCAL_EDID_VIDEO 0x084 | +
+Indicates the presence of EDID information for the video stream. +
| #define XDP_RX_MIN_VOLTAGE_SWING 0x214 | +
+Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training. +
| #define XDP_RX_MISC_CTRL 0x018 | +
+Miscellaneous control of RX behavior. +
| #define XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK 0x4 | +
+When set, I2C DEFERs will be sent as AUX DEFERs to the source device. +
| #define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK 0x2 | +
+When set, the long I2C write data transfwers are responded to using DEFER instead of partial ACKs. +
| #define XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK 0x1 | +
+When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally. +
| #define XDP_RX_MSA_HRES 0x500 | +
+Number of active pixels per line (the horizontal resolution). +
| #define XDP_RX_MSA_HSPOL 0x504 | +
+The horizontal sync polarity. +
| #define XDP_RX_MSA_HSTART 0x50C | +
+Number of clocks between the leading edge of the horizontal sync and the start of active data. +
| #define XDP_RX_MSA_HSWIDTH 0x508 | +
+Width of the horizontal sync pulse. +
| #define XDP_RX_MSA_HTOTAL 0x510 | +
+Total number of clocks in the horizontal framing period. +
| #define XDP_RX_MSA_MISC0 0x528 | +
+Miscellaneous stream attributes. +
| #define XDP_RX_MSA_MISC1 0x52C | +
+Miscellaneous stream attributes. +
| #define XDP_RX_MSA_MVID 0x530 | +
+Used to recover the video clock from the link clock. +
| #define XDP_RX_MSA_NVID 0x534 | +
+Used to recover the video clock from the link clock. +
| #define XDP_RX_MSA_VBID 0x538 | +
+The most recently received VB-ID value. +
| #define XDP_RX_MSA_VHEIGHT 0x514 | +
+Number of active lines (the vertical resolution). +
| #define XDP_RX_MSA_VSPOL 0x518 | +
+The vertical sync polarity. +
| #define XDP_RX_MSA_VSTART 0x520 | +
+Number of lines between the leading edge of the vertical sync and the first line of active data. +
| #define XDP_RX_MSA_VSWIDTH 0x51C | +
+Width of the vertical sync pulse. +
| #define XDP_RX_MSA_VTOTAL 0x524 | +
+Total number of lines in the video frame. +
| #define XDP_RX_MST_CAP 0x0D0 | +
+Used to enable or disable MST capability. +
| #define XDP_RX_OVER_CTRL_DPCD 0x0B8 | +
+Used to enable AXI/APB write access to the DPCD capability structure. +
| #define XDP_RX_OVER_DOWNSPREAD_CTRL 0x0BC | +
+Used to override downspread control in the DPCD. +
| #define XDP_RX_OVER_GUID 0x0F0 | +
+Used to override the GUID field in the DPCD with what is stored in XDP_RX_GUID[0-3]. +
| #define XDP_RX_OVER_LANE_COUNT_SET 0x0A0 | +
+Used to override the lane count setting in the DPCD. +
| #define XDP_RX_OVER_LANE_COUNT_SET_1 0x1 | +
+Lane count of 1. +
| #define XDP_RX_OVER_LANE_COUNT_SET_2 0x2 | +
+Lane count of 2. +
| #define XDP_RX_OVER_LANE_COUNT_SET_4 0x4 | +
+Lane count of 4. +
| #define XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK 0x80 | +
+Capability override for enhanced framing. +
| #define XDP_RX_OVER_LANE_COUNT_SET_MASK 0x1F | +
+The lane count override value. +
| #define XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK 0x20 | +
+Capability override for training pattern 3. +
| #define XDP_RX_OVER_LINK_BW_SET 0x09C | +
+Used to override the main link bandwidth setting in the DPCD. +
| #define XDP_RX_OVER_LINK_BW_SET_162GBPS 0x06 | +
+1.62 Gbps link rate. +
| #define XDP_RX_OVER_LINK_BW_SET_270GBPS 0x0A | +
+2.70 Gbps link rate. +
| #define XDP_RX_OVER_LINK_BW_SET_540GBPS 0x14 | +
+5.40 Gbps link rate. +
| #define XDP_RX_OVER_LINK_QUAL_LANE0_SET 0x0C0 | +
+Used to override the LINK_QUAL_LANE0_SET register in the DPCD. +
| #define XDP_RX_OVER_LINK_QUAL_LANE1_SET 0x0C4 | +
+Used to override the LINK_QUAL_LANE1_SET register in the DPCD. +
| #define XDP_RX_OVER_LINK_QUAL_LANE2_SET 0x0C8 | +
+Used to override the LINK_QUAL_LANE2_SET register in the DPCD. +
| #define XDP_RX_OVER_LINK_QUAL_LANE3_SET 0x0CC | +
+Used to override the LINK_QUAL_LANE3_SET register in the DPCD. +
| #define XDP_RX_OVER_TP_SET 0x0A4 | +
+Used to override the link training pattern in the DPCD. +
| #define XDP_RX_OVER_TP_SET_LQP_SET_MASK 0x000C | +
+Link quality pattern set override. +
| #define XDP_RX_OVER_TP_SET_LQP_SET_SHIFT 2 | +
+Shift bits for link quality pattern set override. +
| #define XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK 0x0010 | +
+Recovered clock output enable override. +
| #define XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK 0x0020 | +
+Scrambling disable override. +
| #define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK 0x00C0 | +
+Symbol error count override. +
| #define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT 6 | +
+Shift bits for symbol error count override. +
| #define XDP_RX_OVER_TP_SET_TP_SELECT_MASK 0x0003 | +
+Training pattern select override. +
| #define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK 0xFF00 | +
+Training AUX read interval override. +
| #define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT 8 | +
+Shift bits for training AUX read interval override. +
| #define XDP_RX_OVER_TRAINING_LANE0_SET 0x0A8 | +
+Used to override the TRAINING_LANE0_SET register in the DPCD. +
| #define XDP_RX_OVER_TRAINING_LANE1_SET 0x0AC | +
+Used to override the TRAINING_LANE1_SET register in the DPCD. +
| #define XDP_RX_OVER_TRAINING_LANE2_SET 0x0B0 | +
+Used to override the TRAINING_LANE2_SET register in the DPCD. +
| #define XDP_RX_OVER_TRAINING_LANE3_SET 0x0B4 | +
+Used to override the TRAINING_LANE3_SET register in the DPCD. +
| #define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 | +
+Maximum pre-emphasis override. +
| #define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 | +
+Maximum voltage swing override. +
| #define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK 0x18 | +
+Pre-emphasis set override. +
| #define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT 3 | +
+Shift bits for pre-emphasis set override. +
| #define XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK 0x03 | +
+Voltage swing set override. +
| #define XDP_RX_PHY_CONFIG 0x200 | +
+Transceiver PHY reset and configuration. +
| #define XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK 0x04000000 | +
+Enable the individual lane polarity. +
| #define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK 0x00000003 | +
+Rest GT and PHY. +
| #define XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK 0x00000001 | +
+Hold the GTPLL in reset. +
| #define XDP_RX_PHY_CONFIG_GTRX_RESET_MASK 0x00000002 | +
+Hold GTRXRESET in reset. +
| #define XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x00000000 | +
+Release reset. +
| #define XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK 0x01000000 | +
+Issue reset at every link rate change. +
| #define XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK 0x02000000 | +
+Issue reset at start of training pattern 1. +
| #define XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK 0x00800000 | +
+Issue reset at every training iteration. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK 0x00000400 | +
+Hold RX_PHY_BUF reset. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK 0x00400000 | +
+Set RX_PHY_CDRHOLD. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK 0x00000800 | +
+Hold RX_PHY_DFE_LPM reset. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK 0x00010000 | +
+Set RX_PHY_EYESCANRESET. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK 0x00020000 | +
+Set RX_PHY_ EYESCANTRIGGER. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK 0x0000E000 | +
+Set RX_PHY_LOOPBACK. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK 0x00000200 | +
+Hold RX_PHY_PCS reset. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK 0x00000100 | +
+Hold RX_PHY_PMA reset. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK 0x08000000 | +
+Configure RX_PHY_POLARITY for lane 0. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK 0x10000000 | +
+Configure RX_PHY_POLARITY for lane 1. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK 0x20000000 | +
+Configure RX_PHY_POLARITY for lane 2. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK 0x40000000 | +
+Configure RX_PHY_POLARITY for lane 3. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK 0x00001000 | +
+Set RX_PHY_POLARITY. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK 0x00040000 | +
+Set RX_PHY_PRBSCNTRESET. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK 0x00080000 | +
+Set RX_PHY_RXLPMHFHOLD. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK 0x00200000 | +
+Set RX_PHY_ RXLPMHFOVERDEN. +
| #define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK 0x00100000 | +
+Set RX_PHY_RXLPMLFHOLD. +
| #define XDP_RX_PHY_POWER_DOWN 0x210 | +
+Control PHY power down. +
| #define XDP_RX_PHY_POWER_DOWN_LANE_0_MASK 0x1 | +
+Power down the PHY for lane 0. +
| #define XDP_RX_PHY_POWER_DOWN_LANE_1_MASK 0x2 | +
+Power down the PHY for lane 1. +
| #define XDP_RX_PHY_POWER_DOWN_LANE_2_MASK 0x4 | +
+Power down the PHY for lane 2. +
| #define XDP_RX_PHY_POWER_DOWN_LANE_3_MASK 0x8 | +
+Power down the PHY for lane 3. +
| #define XDP_RX_PHY_STATUS 0x208 | +
+Current PHY status. +
| #define XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F | +
+All lanes are ready. +
| #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK 0x00010000 | +
+Lane aligment status for lane 0. +
| #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK 0x00020000 | +
+Lane aligment status for lane 1. +
| #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK 0x00040000 | +
+Lane aligment status for lane 2. +
| #define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK 0x00080000 | +
+Lane aligment status for lane 3. +
| #define XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK 0x00000013 | +
+Lanes 0 and 1 are ready. +
| #define XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 | +
+FPGA fabric clock PLL locked. +
| #define XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 | +
+PLL locked for lanes 0 and 1. +
| #define XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 | +
+PLL locked for lanes 2 and 3. +
| #define XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK 0x00000100 | +
+PRBS error on lane 0. +
| #define XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK 0x00000200 | +
+PRBS error on lane 1. +
| #define XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK 0x00000400 | +
+PRBS error on lane 2. +
| #define XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK 0x00000800 | +
+PRBS error on lane 3. +
| #define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 | +
+Reset done for lanes 0 and 1. +
| #define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C | +
+Reset done for lanes 2 and 3. +
| #define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 | +
+Shift bits for reset done for lanes 2 and 3. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT 26 | +
+Shift bits for RX buffer status lane 1. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK 0x03000000 | +
+RX buffer status lane 0. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT 24 | +
+Shift bits for RX buffer status lane 0. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK 0x0C000000 | +
+RX buffer status lane 1. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK 0x30000000 | +
+RX buffer status lane 2. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT 28 | +
+Shift bits for RX buffer status lane 2. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK 0xC0000000 | +
+RX buffer status lane 3. +
| #define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT 30 | +
+Shift bits for RX buffer status lane 3. +
| #define XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK 0x00000080 | +
+Receiver clock locked. +
| #define XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK 0x00001000 | +
+RX voltage low on lane 0. +
| #define XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK 0x00002000 | +
+RX voltage low on lane 1. +
| #define XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK 0x00004000 | +
+RX voltage low on lane 2. +
| #define XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK 0x00008000 | +
+RX voltage low on lane 3. +
| #define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK 0x00100000 | +
+Symbol lock status for lane 0. +
| #define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK 0x00200000 | +
+Symbol lock status for lane 1. +
| #define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK 0x00400000 | +
+Symbol lock status for lane 2. +
| #define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK 0x00800000 | +
+Symbol lock status for lane 3. +
| #define XDP_RX_REMOTE_CMD 0x08C | +
+Used for passing remote information to the DisplayPort TX. +
| #define XDP_RX_REQ_ADDRESS 0x038 | +
+Contains the address field of the most recent AUX request. +
| #define XDP_RX_REQ_CLK_WIDTH 0x030 | +
+Holds the half period of the recovered AUX clock. +
| #define XDP_RX_REQ_CMD 0x034 | +
+Provides the most recent AUX command received. +
| #define XDP_RX_REQ_COUNT 0x028 | +
+Provides a running total of the number of AUX requests received. +
| #define XDP_RX_REQ_ERROR_COUNT 0x024 | +
+Provides a running total of errors detected on inbound AUX channel requests. +
| #define XDP_RX_REQ_LENGTH 0x03C | +
+Contains length of the most recent AUX request. +
| #define XDP_RX_SINK_COUNT 0x0D4 | +
+The sink device count. +
| #define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 | +
+User access to the sink specific field as exposed in the RX DPCD (0xFF bytes). +
| #define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD_REG | +( | +RegNum | ++ | ) | +(XDP_RX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) | +
+ +
| #define XDP_RX_SOFT_RESET 0x01C | +
+Software reset. +
| #define XDP_RX_SOFT_RESET_AUX_MASK 0x80 | +
+Reset the AUX logic. +
| #define XDP_RX_SOFT_RESET_VIDEO_MASK 0x01 | +
+Reset the video logic. +
| #define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 | +
+User access to the source specific field as exposed in the RX DPCD (0xFF bytes). +
| #define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD_REG | +( | +RegNum | ++ | ) | +(XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) | +
+ +
| #define XDP_RX_STREAM1_MSA_START 0x500 | +
+Start of the MSA registers for stream 1. +
| #define XDP_RX_STREAM2_MSA_START 0x540 | +
+Start of the MSA registers for stream 2. +
| #define XDP_RX_STREAM2_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. +| #define XDP_RX_STREAM3_MSA_START 0x580 | +
+Start of the MSA registers for stream 3. +
| #define XDP_RX_STREAM3_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. +| #define XDP_RX_STREAM4_MSA_START 0x5C0 | +
+Start of the MSA registers for stream 4. +
| #define XDP_RX_STREAM4_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. +| #define XDP_RX_USER_FIFO_OVERFLOW 0x110 | +
+Indicates an overflow in user FIFO. +
| #define XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream) | +
+Indicates that the internal FIFO has detected on overflow condition for the specified stream. +
| #define XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream << 8) | +
+Indicates that the video timing FIFO has overflown for the specified stream. +
| #define XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream << 4) | +
+Indicates that the video unpack FIFO has overflown for the specified stream. +
| #define XDP_RX_USER_PIXEL_WIDTH 0x010 | +
+Selects the width of the user data input port. +
| #define XDP_RX_USER_PIXEL_WIDTH_1 0x1 | +
+Single pixel wide interface. +
| #define XDP_RX_USER_PIXEL_WIDTH_2 0x2 | +
+Dual pixel output mode. +
| #define XDP_RX_USER_PIXEL_WIDTH_4 0x4 | +
+Quad pixel output mode. +
| #define XDP_RX_USER_VSYNC_STATE 0x114 | +
+Provides a mechanism for the host processor to monitor the state of the video data path. +
| #define XDP_RX_USER_VSYNC_STATE_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream) | +
+The state of the vertical sync pulse for the specified stream. +
| #define XDP_RX_VC_PAYLOAD_TABLE 0x800 | +
+Virtual channel payload table (0xFF bytes). +
| #define XDP_RX_VC_PAYLOAD_TABLE_ID_SLOT | +( | +SlotNum | ++ | ) | +(XDP_RX_VC_PAYLOAD_TABLE + SlotNum) | +
+ +
| #define XDP_RX_VERSION 0x0F8 | +
+Version and revision of the DisplayPort core. +
| #define XDP_RX_VERSION_CORE_PATCH_MASK 0x00000030 | +
+Core patch details. +
| #define XDP_RX_VERSION_CORE_PATCH_SHIFT 8 | +
+Shift bits for core patch details. +
| #define XDP_RX_VERSION_CORE_VER_MJR_MASK 0x0000F000 | +
+Core major version. +
| #define XDP_RX_VERSION_CORE_VER_MJR_SHIFT 24 | +
+Shift bits for core major version. +
| #define XDP_RX_VERSION_CORE_VER_MNR_MASK 0x00000F00 | +
+Core minor version. +
| #define XDP_RX_VERSION_CORE_VER_MNR_SHIFT 16 | +
+Shift bits for core minor version. +
| #define XDP_RX_VERSION_CORE_VER_REV_MASK 0x000000C0 | +
+Core version revision. +
| #define XDP_RX_VERSION_CORE_VER_REV_SHIFT 12 | +
+Shift bits for core version revision. +
| #define XDP_RX_VERSION_INTER_REV_MASK 0x0000000F | +
+Internal revision. +
| #define XDP_RX_VIDEO_UNSUPPORTED 0x094 | +
+DPCD register bit to inform the DisplayPort TX that video data is not supported. +
| #define XDP_SEGPTR_ADDR 0x30 | +
+ +
| #define XDP_TX_AUDIO_CHANNELS 0x0304 | +
+Used to input active channel count. +
| #define XDP_TX_AUDIO_CONTROL 0x0300 | +
+Enables audio stream packets in main link and buffer control. +
| #define XDP_TX_AUDIO_EXT_DATA | +( | +NUM | ++ | ) | +(0x0330 + 4 * (NUM - 1)) | +
+Word formatted as per extension packet. +
| #define XDP_TX_AUDIO_INFO_DATA | +( | +NUM | ++ | ) | +(0x0308 + 4 * (NUM - 1)) | +
+Word formatted as per CEA 861-C info frame. +
| #define XDP_TX_AUDIO_MAUD 0x0328 | +
+M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. +
| #define XDP_TX_AUDIO_NAUD 0x032C | +
+N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. +
| #define XDP_TX_AUX_ADDRESS 0x0108 | +
+Specifies the address of current AUX command. +
| #define XDP_TX_AUX_CLK_DIVIDER 0x010C | +
+Clock divider value for generating the internal 1MHz clock. +
| #define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 | +
+AUX (noise) signal width filter. +
| #define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 | +
+Shift bits for AUX signal width filter. +
| #define XDP_TX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF | +
+Clock divider value. +
| #define XDP_TX_AUX_CMD 0x0100 | +
+Initiates AUX commands. +
| #define XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 | +
+Address only transfer enable (STOP will be sent after command). +
| #define XDP_TX_AUX_CMD_I2C_READ 0x1 | +
+I2C-over-AUX read command. +
| #define XDP_TX_AUX_CMD_I2C_READ_MOT 0x5 | +
+I2C-over-AUX read MOT (middle-of-transaction) command. +
| #define XDP_TX_AUX_CMD_I2C_WRITE 0x0 | +
+I2C-over-AUX write command. +
| #define XDP_TX_AUX_CMD_I2C_WRITE_MOT 0x4 | +
+I2C-over-AUX write MOT (middle-of-transaction) command. +
| #define XDP_TX_AUX_CMD_I2C_WRITE_STATUS 0x2 | +
+I2C-over-AUX write status command. +
| #define XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT 0x6 | +
+I2C-over-AUX write status MOT (middle-of- transaction) command. +
| #define XDP_TX_AUX_CMD_MASK 0x00000F00 | +
+AUX command. +
| #define XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F | +
+Number of bytes to transfer with the current AUX command. +
| #define XDP_TX_AUX_CMD_READ 0x9 | +
+AUX read command. +
| #define XDP_TX_AUX_CMD_SHIFT 8 | +
+Shift bits for command. +
| #define XDP_TX_AUX_CMD_WRITE 0x8 | +
+AUX write command. +
| #define XDP_TX_AUX_REPLY_CODE 0x0138 | +
+Reply code received from the most recent AUX command. +
| #define XDP_TX_AUX_REPLY_CODE_ACK 0x0 | +
+AUX command ACKed. +
| #define XDP_TX_AUX_REPLY_CODE_DEFER 0x2 | +
+AUX command deferred. +
| #define XDP_TX_AUX_REPLY_CODE_I2C_ACK 0x0 | +
+I2C-over-AUX command not ACKed. +
| #define XDP_TX_AUX_REPLY_CODE_I2C_DEFER 0x8 | +
+I2C-over-AUX command deferred. +
| #define XDP_TX_AUX_REPLY_CODE_I2C_NACK 0x4 | +
+I2C-over-AUX command not ACKed. +
| #define XDP_TX_AUX_REPLY_CODE_NACK 0x1 | +
+AUX command not ACKed. +
| #define XDP_TX_AUX_REPLY_COUNT 0x013C | +
+Number of reply transactions receieved over AUX. +
| #define XDP_TX_AUX_REPLY_DATA 0x0134 | +
+Reply data received during the AUX reply. +
| #define XDP_TX_AUX_WRITE_FIFO 0x0104 | +
+Write data for the current AUX command. +
| #define XDP_TX_CORE_ID 0x00FC | +
+DisplayPort protocol version and revision. +
| #define XDP_TX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 | +
+DisplayPort protocol major version. +
| #define XDP_TX_CORE_ID_DP_MJR_VER_SHIFT 24 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDP_TX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 | +
+DisplayPort protocol minor version. +
| #define XDP_TX_CORE_ID_DP_MNR_VER_SHIFT 16 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDP_TX_CORE_ID_DP_REV_MASK 0x000000F0 | +
+DisplayPort protocol revision. +
| #define XDP_TX_CORE_ID_DP_REV_SHIFT 8 | +
+Shift bits for DisplayPort protocol revision. +
| #define XDP_TX_CORE_ID_TYPE_MASK 0x0000000F | +
+Core type. +
| #define XDP_TX_CORE_ID_TYPE_RX 0x1 | +
+Core is a receiver. +
| #define XDP_TX_CORE_ID_TYPE_TX 0x0 | +
+Core is a transmitter. +
| #define XDP_TX_DISPID_DB_SEC_REV 0x01 | +
+ +
| #define XDP_TX_DISPID_DB_SEC_SIZE 0x02 | +
+ +
| #define XDP_TX_DISPID_DB_SEC_TAG 0x00 | +
+ +
| #define XDP_TX_DISPID_EXT_COUNT 0x03 | +
+ +
| #define XDP_TX_DISPID_PAYLOAD_START 0x04 | +
+ +
| #define XDP_TX_DISPID_SIZE 0x01 | +
+ +
| #define XDP_TX_DISPID_TDT_HSIZE0 0x07 | +
+ +
| #define XDP_TX_DISPID_TDT_HSIZE1 0x08 | +
+ +
| #define XDP_TX_DISPID_TDT_PCODE0 0x13 | +
+ +
| #define XDP_TX_DISPID_TDT_PCODE1 0x14 | +
+ +
| #define XDP_TX_DISPID_TDT_SN0 0x15 | +
+ +
| #define XDP_TX_DISPID_TDT_SN1 0x16 | +
+ +
| #define XDP_TX_DISPID_TDT_SN2 0x17 | +
+ +
| #define XDP_TX_DISPID_TDT_SN3 0x18 | +
+ +
| #define XDP_TX_DISPID_TDT_TAG 0x12 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP0 0x04 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK (0xF << 4) | +
+ +
| #define XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT 4 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK 0xF | +
+ +
| #define XDP_TX_DISPID_TDT_TOP1 0x05 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK (0xF << 4) | +
+ +
| #define XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT 4 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK 0xF | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2 0x06 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK (0x3 << 2) | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT 2 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK (0x3 << 6) | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT 6 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK 0x3 | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK (0x3 << 4) | +
+ +
| #define XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT 4 | +
+ +
| #define XDP_TX_DISPID_TDT_VENID0 0x10 | +
+ +
| #define XDP_TX_DISPID_TDT_VENID1 0x11 | +
+ +
| #define XDP_TX_DISPID_TDT_VENID2 0x12 | +
+ +
| #define XDP_TX_DISPID_TDT_VSIZE0 0x09 | +
+ +
| #define XDP_TX_DISPID_TDT_VSIZE1 0x0A | +
+ +
| #define XDP_TX_DISPID_TYPE 0x02 | +
+ +
| #define XDP_TX_DISPID_VER_REV 0x00 | +
+ +
| #define XDP_TX_DOWNSPREAD_CTRL 0x0018 | +
+Enable a 0.5% spreading of the clock. +
| #define XDP_TX_ENABLE 0x0080 | +
+Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. +
| #define XDP_TX_ENABLE_MAIN_STREAM 0x0084 | +
+Enable transmission of main link video info. +
| #define XDP_TX_ENABLE_SEC_STREAM 0x0088 | +
+Enable the transmission of secondary link info. +
| #define XDP_TX_ENHANCED_FRAME_EN 0x0008 | +
+Enable enhanced framing symbol sequence. +
| #define XDP_TX_FORCE_SCRAMBLER_RESET 0x00C0 | +
+Force a scrambler reset. +
| #define XDP_TX_FRAC_BYTES_PER_TU 0x01C8 | +
+The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value. +
| #define XDP_TX_GT_DRP_CHANNEL_STATUS 0x02A8 | +
+Provides access to GT DRP channel status. +
| #define XDP_TX_GT_DRP_COMMAND 0x02A0 | +
+Provides acces to the GT DRP ports. +
| #define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F | +
+DRP address. +
| #define XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 | +
+DRP read/write command (Read=0, Write=1). +
| #define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 | +
+DRP write data. +
| #define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 | +
+Shift bits for DRP write data. +
| #define XDP_TX_GT_DRP_READ_DATA 0x02A4 | +
+Provides access to GT DRP read data. +
| #define XDP_TX_HPD_DURATION 0x0150 | +
+Duration of the HPD pulse in microseconds. +
| #define XDP_TX_INIT_WAIT 0x01CC | +
+Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. +
| #define XDP_TX_INTERRUPT_MASK 0x0144 | +
+Masks the specified interrupt sources. +
| #define XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK 0x00000020 | +
+Mask extended packet transmit interrupt. +
| #define XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK 0x00000002 | +
+Mask HPD event interrupt. +
| #define XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK 0x00000001 | +
+Mask HPD IRQ interrupt. +
| #define XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK 0x00000010 | +
+Mask HPD pulse detected interrupt. +
| #define XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK 0x00000004 | +
+Mask reply received interrupt. +
| #define XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK 0x00000008 | +
+Mask reply received interrupt. +
| #define XDP_TX_INTERRUPT_SIG_STATE 0x0130 | +
+The raw signal values for interupt events. +
| #define XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 | +
+Raw state of the HPD pin on the DP connector. +
| #define XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK 0x00000004 | +
+A reply is currently being received. +
| #define XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK 0x00000008 | +
+A reply timeout has occurred. +
| #define XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK 0x00000002 | +
+A request is currently being sent. +
| #define XDP_TX_INTERRUPT_STATUS 0x0140 | +
+Status for interrupt events. +
| #define XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK 0x00000020 | +
+Extended packet has been transmitted and the core is ready to accept a new packet. +
| #define XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK 0x00000002 | +
+Detected the presence of the HPD signal. +
| #define XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK 0x00000001 | +
+Detected an IRQ framed with the proper timing on the HPD signal. +
| #define XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK 0x00000010 | +
+A pulse on the HPD line was detected. +
| #define XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK 0x00000004 | +
+An AUX reply transaction has been detected. +
| #define XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK 0x00000008 | +
+A reply timeout has occurred. +
| #define XDP_TX_LANE_COUNT_SET 0x0004 | +
+Set lane count setting. +
| #define XDP_TX_LANE_COUNT_SET_1 0x01 | +
+Lane count of 1. +
| #define XDP_TX_LANE_COUNT_SET_2 0x02 | +
+Lane count of 2. +
| #define XDP_TX_LANE_COUNT_SET_4 0x04 | +
+Lane count of 4. +
| #define XDP_TX_LINK_BW_SET 0x0000 | +
+Set main link bandwidth setting. +
| #define XDP_TX_LINK_BW_SET_162GBPS 0x06 | +
+1.62 Gbps link rate. +
| #define XDP_TX_LINK_BW_SET_270GBPS 0x0A | +
+2.70 Gbps link rate. +
| #define XDP_TX_LINK_BW_SET_540GBPS 0x14 | +
+5.40 Gbps link rate. +
| #define XDP_TX_LINK_QUAL_PATTERN_SET 0x0010 | +
+Transmit the link quality pattern. +
| #define XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST 0x1 | +
+D10.2 unscrambled test pattern transmitted. +
| #define XDP_TX_LINK_QUAL_PATTERN_SET_OFF 0x0 | +
+Link quality test pattern not transmitted. +
| #define XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7 0x3 | +
+Pseudo random bit sequence 7 transmitted. +
| #define XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES 0x2 | +
+Symbol error rate measurement pattern transmitted. +
| #define XDP_TX_M_VID 0x01AC | +
+M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +
| #define XDP_TX_MAIN_STREAM_HRES 0x0194 | +
+Number of active pixels per line (the horizontal resolution). +
| #define XDP_TX_MAIN_STREAM_HSTART 0x019C | +
+Number of clocks between the leading edge of the horizontal sync and the start of active data. +
| #define XDP_TX_MAIN_STREAM_HSWIDTH 0x018C | +
+Width of the horizontal sync pulse. +
| #define XDP_TX_MAIN_STREAM_HTOTAL 0x0180 | +
+Total number of clocks in the horizontal framing period. +
| #define XDP_TX_MAIN_STREAM_INTERLACED 0x01C0 | +
+Video is interlaced. +
| #define XDP_TX_MAIN_STREAM_MISC0 0x01A4 | +
+Miscellaneous stream attributes. +
| #define XDP_TX_MAIN_STREAM_MISC1 0x01A8 | +
+Miscellaneous stream attributes. +
| #define XDP_TX_MAIN_STREAM_POLARITY 0x0188 | +
+Polarity for the video sync signals. +
| #define XDP_TX_MAIN_STREAM_VRES 0x0198 | +
+Number of active lines (the vertical resolution). +
| #define XDP_TX_MAIN_STREAM_VSTART 0x01A0 | +
+Number of lines between the leading edge of the vertical sync and the first line of active data. +
| #define XDP_TX_MAIN_STREAM_VSWIDTH 0x0190 | +
+Width of the vertical sync pulse. +
| #define XDP_TX_MAIN_STREAM_VTOTAL 0x0184 | +
+Total number of lines in the video frame. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC 0x2 | +
+10 bits per component. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC 0x3 | +
+12 bits per component. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC 0x4 | +
+16 bits per component. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC 0x0 | +
+6 bits per component. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC 0x1 | +
+8 bits per component. +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 | +
+Bit depth per color component (BDC). +
| #define XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT 5 | +
+Shift bits for BDC. +
| #define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 | +
+Component format. +
| #define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB 0x0 | +
+Stream's component format is RGB. +
| #define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 | +
+Shift bits for component format. +
| #define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 0x1 | +
+Stream's component format is YcbCr 4:2:2. +
| #define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 0x2 | +
+Stream's component format is YcbCr 4:4:4. +
| #define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 | +
+Dynamic range. +
| #define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 | +
+Shift bits for dynamic range. +
| #define XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK 0x00000001 | +
+Synchronous clock. +
| #define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 | +
+YCbCr colorimetry. +
| #define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 | +
+Shift bits for YCbCr colorimetry. +
| #define XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK 0x00000001 | +
+Interlaced vertical total even. +
| #define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK 0x00000006 | +
+Stereo video attribute. +
| #define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT 1 | +
+Shift bits for stereo video attribute. +
| #define XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK 0x00000001 | +
+Polarity of the horizontal sync pulse. +
| #define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK 0x00000002 | +
+Polarity of the vertical sync pulse. +
| #define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 | +
+Shift bits for polarity of the vertical sync pulse. +
| #define XDP_TX_MIN_BYTES_PER_TU 0x01C4 | +
+The minimum number of bytes per transfer unit. +
| #define XDP_TX_MST_CONFIG 0x00D0 | +
+Enable MST. +
| #define XDP_TX_MST_CONFIG_MST_EN_MASK 0x00000001 | +
+Enable MST. +
| #define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK 0x00000002 | +
+The VC payload has been updated in the sink. +
| #define XDP_TX_N_VID 0x01B4 | +
+N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode. +
| #define XDP_TX_PE_LEVEL_0 0x00 | +
+Pre-emphasis level 0. +
| #define XDP_TX_PE_LEVEL_1 0x0E | +
+Pre-emphasis level 1. +
| #define XDP_TX_PE_LEVEL_2 0x14 | +
+Pre-emphasis level 2. +
| #define XDP_TX_PE_LEVEL_3 0x1B | +
+Pre-emphasis level 3. +
| #define XDP_TX_PHY_CLOCK_SELECT 0x0234 | +
+Instructs the PHY PLL to generate the proper clock frequency for the required link rate. +
| #define XDP_TX_PHY_CLOCK_SELECT_162GBPS 0x1 | +
+1.62 Gbps link. +
| #define XDP_TX_PHY_CLOCK_SELECT_270GBPS 0x3 | +
+2.70 Gbps link. +
| #define XDP_TX_PHY_CLOCK_SELECT_540GBPS 0x5 | +
+5.40 Gbps link. +
| #define XDP_TX_PHY_CONFIG 0x0200 | +
+Transceiver PHY reset and configuration. +
| #define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 | +
+Rest GT and PHY. +
| #define XDP_TX_PHY_CONFIG_GTTX_RESET_MASK 0x0000002 | +
+Hold GTTXRESET in reset. +
| #define XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x0000000 | +
+Release reset. +
| #define XDP_TX_PHY_CONFIG_PHY_RESET_MASK 0x0000001 | +
+Hold the PHY in reset. +
| #define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 | +
+Set TX_PHY_LOOPBACK. +
| #define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0000200 | +
+Hold TX_PHY_PCS reset. +
| #define XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK 0x0000100 | +
+Hold TX_PHY_PMA reset. +
| #define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000400 | +
+Set TX_PHY_POLARITY. +
| #define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0001000 | +
+Set TX_PHY_PRBSFORCEERR. +
| #define XDP_TX_PHY_POSTCURSOR_LANE_0 0x024C | +
+Controls the post-cursor level. +
| #define XDP_TX_PHY_POSTCURSOR_LANE_1 0x0250 | +
+Controls the post-cursor level. +
| #define XDP_TX_PHY_POSTCURSOR_LANE_2 0x0254 | +
+Controls the post-cursor level. +
| #define XDP_TX_PHY_POSTCURSOR_LANE_3 0x0258 | +
+Controls the post-cursor level. +
| #define XDP_TX_PHY_POWER_DOWN 0x0238 | +
+Controls PHY power down. +
| #define XDP_TX_PHY_PRECURSOR_LANE_0 0x023C | +
+Controls the pre-cursor level. +
| #define XDP_TX_PHY_PRECURSOR_LANE_1 0x0240 | +
+Controls the pre-cursor level. +
| #define XDP_TX_PHY_PRECURSOR_LANE_2 0x0244 | +
+Controls the pre-cursor level. +
| #define XDP_TX_PHY_PRECURSOR_LANE_3 0x0248 | +
+Controls the pre-cursor level. +
| #define XDP_TX_PHY_STATUS 0x0280 | +
+Current PHY status. +
| #define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F | +
+All lanes are ready. +
| #define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK 0x00000013 | +
+Lanes 0 and 1 are ready. +
| #define XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 | +
+FPGA fabric clock PLL locked. +
| #define XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 | +
+PLL locked for lanes 0 and 1. +
| #define XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 | +
+PLL locked for lanes 2 and 3. +
| #define XDP_TX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 | +
+Reset done for lanes 0 and 1. +
| #define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C | +
+Reset done for lanes 2 and 3. +
| #define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 | +
+Shift bits for reset done for lanes 2 and 3. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK 0x00030000 | +
+TX buffer status lane 0. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT 16 | +
+Shift bits for TX buffer status lane 0. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK 0x00300000 | +
+TX buffer status lane 1. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT 20 | +
+Shift bits for TX buffer status lane 1. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK 0x03000000 | +
+TX buffer status lane 2. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT 24 | +
+Shift bits for TX buffer status lane 2. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK 0x30000000 | +
+TX buffer status lane 3. +
| #define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT 28 | +
+Shift bits for TX buffer status lane 3. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK 0x000C0000 | +
+TX error on lane 0. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT 18 | +
+Shift bits for TX error on lane 0. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK 0x00C00000 | +
+TX error on lane 1. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT 22 | +
+Shift bits for TX error on lane 1. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK 0x0C000000 | +
+TX error on lane 2. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT 26 | +
+Shift bits for TX error on lane 2. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK 0xC0000000 | +
+TX error on lane 3. +
| #define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT 30 | +
+Shift bits for TX error on lane 3. +
| #define XDP_TX_PHY_TRANSMIT_PRBS7 0x0230 | +
+Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. +
| #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 | +
+Controls the differential voltage swing. +
| #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 | +
+Controls the differential voltage swing. +
| #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 | +
+Controls the differential voltage swing. +
| #define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x022C | +
+Controls the differential voltage swing. +
| #define XDP_TX_REPLY_DATA_COUNT 0x0148 | +
+Total number of data bytes actually received during a transaction. +
| #define XDP_TX_REPLY_STATUS 0x014C | +
+Reply status of most recent AUX transaction. +
| #define XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 | +
+Detected an error in the AUX reply of the most recent transaction. +
| #define XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 | +
+AUX reply is currently being received. +
| #define XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 | +
+AUX transaction is complete and a valid reply transaction received. +
| #define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 | +
+Internal AUX reply state machine status bits. +
| #define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 | +
+Shift bits for the internal AUX reply state machine status. +
| #define XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 | +
+AUX request is currently being transmitted. +
| #define XDP_TX_SBMSG_ALLOCATE_PAYLOAD 0x11 | +
+ +
| #define XDP_TX_SBMSG_CLEAR_PAYLOAD_ID_TABLE 0x14 | +
+ +
| #define XDP_TX_SBMSG_ENUM_PATH_RESOURCES 0x10 | +
+ +
| #define XDP_TX_SBMSG_LINK_ADDRESS 0x01 | +
+ +
| #define XDP_TX_SBMSG_REMOTE_DPCD_READ 0x20 | +
+ +
| #define XDP_TX_SBMSG_REMOTE_DPCD_WRITE 0x21 | +
+ +
| #define XDP_TX_SBMSG_REMOTE_I2C_READ 0x22 | +
+ +
| #define XDP_TX_SBMSG_REMOTE_I2C_WRITE 0x23 | +
+ +
| #define XDP_TX_SCRAMBLING_DISABLE 0x0014 | +
+Disable scrambler and transmit all symbols. +
| #define XDP_TX_SOFT_RESET 0x001C | +
+Software reset. +
| #define XDP_TX_SOFT_RESET_AUX_MASK 0x00000080 | +
+Reset AUX logic. +
| #define XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK 0x00000001 | +
+Reset video logic. +
| #define XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK 0x00000002 | +
+Reset video logic. +
| #define XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK 0x00000004 | +
+Reset video logic. +
| #define XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK 0x00000008 | +
+Reset video logic. +
| #define XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK 0x0000000F | +
+Reset video logic for all streams. +
| #define XDP_TX_STREAM1 0x01D0 | +
+Average stream symbol timeslots per MTP config. +
| #define XDP_TX_STREAM1_MSA_START 0x0180 | +
+Start of the MSA registers for stream 1. +
| #define XDP_TX_STREAM2 0x01D4 | +
+Average stream symbol timeslots per MTP config. +
| #define XDP_TX_STREAM2_MSA_START 0x0500 | +
+Start of the MSA registers for stream 2. +
| #define XDP_TX_STREAM2_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. +| #define XDP_TX_STREAM3 0x01D8 | +
+Average stream symbol timeslots per MTP config. +
| #define XDP_TX_STREAM3_MSA_START 0x0550 | +
+Start of the MSA registers for stream 3. +
| #define XDP_TX_STREAM3_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. +| #define XDP_TX_STREAM4 0x01DC | +
+Average stream symbol timeslots per MTP config. +
| #define XDP_TX_STREAM4_MSA_START 0x05A0 | +
+Start of the MSA registers for stream 4. +
| #define XDP_TX_STREAM4_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. +| #define XDP_TX_STREAM_ID1 1 | +
+ +
| #define XDP_TX_STREAM_ID2 2 | +
+ +
| #define XDP_TX_STREAM_ID3 3 | +
+ +
| #define XDP_TX_STREAM_ID4 4 | +
+ +
| #define XDP_TX_TRAINING_PATTERN_SET 0x000C | +
+Set the link training pattern. +
| #define XDP_TX_TRAINING_PATTERN_SET_OFF 0x0 | +
+Training off. +
| #define XDP_TX_TRAINING_PATTERN_SET_TP1 0x1 | +
+Training pattern 1 used for clock recovery. +
| #define XDP_TX_TRAINING_PATTERN_SET_TP2 0x2 | +
+Training pattern 2 used for channel equalization. +
| #define XDP_TX_TRAINING_PATTERN_SET_TP3 0x3 | +
+Training pattern 3 used for channel equalization for cores with DP v1.2. +
| #define XDP_TX_TU_SIZE 0x01B0 | +
+Size of a transfer unit in the framing logic. +
| #define XDP_TX_USER_DATA_COUNT_PER_LANE 0x01BC | +
+Used to translate the number of pixels per line to the native internal 16-bit datapath. +
| #define XDP_TX_USER_FIFO_OVERFLOW 0x0110 | +
+Indicates an overflow in user FIFO. +
| #define XDP_TX_USER_PIXEL_WIDTH 0x01B8 | +
+Selects the width of the user data input port. +
| #define XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x0800 | +
+Virtual channel payload table (0xFF bytes). +
| #define XDP_TX_VERSION 0x00F8 | +
+Version and revision of the DisplayPort core. +
| #define XDP_TX_VERSION_CORE_PATCH_MASK 0x00000030 | +
+Core patch details. +
| #define XDP_TX_VERSION_CORE_PATCH_SHIFT 8 | +
+Shift bits for core patch details. +
| #define XDP_TX_VERSION_CORE_VER_MJR_MASK 0x0000F000 | +
+Core major version. +
| #define XDP_TX_VERSION_CORE_VER_MJR_SHIFT 24 | +
+Shift bits for core major version. +
| #define XDP_TX_VERSION_CORE_VER_MNR_MASK 0x00000F00 | +
+Core minor version. +
| #define XDP_TX_VERSION_CORE_VER_MNR_SHIFT 16 | +
+Shift bits for core minor version. +
| #define XDP_TX_VERSION_CORE_VER_REV_MASK 0x000000C0 | +
+Core version revision. +
| #define XDP_TX_VERSION_CORE_VER_REV_SHIFT 12 | +
+Shift bits for core version revision. +
| #define XDP_TX_VERSION_INTER_REV_MASK 0x0000000F | +
+Internal revision. +
| #define XDP_TX_VS_LEVEL_0 0x2 | +
+Voltage swing level 0. +
| #define XDP_TX_VS_LEVEL_1 0x5 | +
+Voltage swing level 1. +
| #define XDP_TX_VS_LEVEL_2 0x8 | +
+Voltage swing level 2. +
| #define XDP_TX_VS_LEVEL_3 0xF | +
+Voltage swing level 3. +
| #define XDP_TX_VS_LEVEL_OFFSET 0x4 | +
+Voltage swing compensation offset used when there's no redriver in display path. +
| #define XDp_TxGetDispIdTdtHLoc | +( | +Tdt | ++ | ) | ++ |
+Value:
((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT) << 4) | \ + ((Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK) >> \ + XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT)) +
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxGetDispIdTdtHTotal | +( | +Tdt | ++ | ) | ++ |
+Value:
(((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT) << 4) | \ + ((Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK) >> \ + XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT)) + 1) +
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxGetDispIdTdtNumTiles | +( | +Tdt | ++ | ) | +(XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt)) | +
+Given a Tiled Display Topology (TDT) data block, retrieve the total number of tiles in the tiled display. The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxGetDispIdTdtTileOrder | +( | +Tdt | ++ | ) | ++ |
+Value:
((XDp_TxGetDispIdTdtVLoc(Tdt) * XDp_TxGetDispIdTdtHTotal(Tdt)) + \ + XDp_TxGetDispIdTdtHLoc(Tdt)) +
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxGetDispIdTdtVLoc | +( | +Tdt | ++ | ) | ++ |
+Value:
(((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK) << \ + 4) | (Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK)) +
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxGetDispIdTdtVTotal | +( | +Tdt | ++ | ) | ++ |
+Value:
(((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK) \ + >> XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT) << 4) | \ + (Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK)) + 1) +
+
| Tdt | is a pointer to the TDT data block. |
| #define XDp_TxIsEdidExtBlockDispId | +( | +Ext | ++ | ) | +(Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID) | +
+Check if an Extended Display Identification Data (EDID) extension block is of type DisplayID.
+
| Ext | is a pointer to the EDID extension block under comparison. |
| #define XDp_WriteReg | +( | +BaseAddress, | |||
| + | + | RegOffset, | |||
| + | + | Data | ++ | ) | +XDp_Out32((BaseAddress) + (RegOffset), (Data)) | +
+This is a low-level function that writes to the specified register.
+
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to write to. | |
| Data | is the 32-bit data to write to the specified register. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html new file mode 100644 index 00000000..44ebc53e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__intr_8c.html @@ -0,0 +1,801 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+
Functions | |
| void | XDp_InterruptHandler (XDp *InstancePtr) |
| void | XDp_RxGenerateHpdInterrupt (XDp *InstancePtr, u16 DurationUs) |
| void | XDp_RxInterruptEnable (XDp *InstancePtr, u32 Mask) |
| void | XDp_RxInterruptDisable (XDp *InstancePtr, u32 Mask) |
| void | XDp_TxSetHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_TxSetHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrVmChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrVBlankHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTrainingLostHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp1Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp2Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDp_RxSetIntrTp3Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
| void XDp_InterruptHandler | +( | +XDp * | +InstancePtr | +) | ++ |
+This function is the interrupt handler for the XDp driver. When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_RxGenerateHpdInterrupt | +( | +XDp * | +InstancePtr, | +|
| + | + | u16 | +DurationUs | + |
| + | ) | ++ |
+This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.
+
| InstancePtr | is a pointer to the XDp instance. | |
| DurationUs | is the duration of the HPD pulse, in microseconds. |
| void XDp_RxInterruptDisable | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function disables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Mask | specifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts. |
| void XDp_RxInterruptEnable | +( | +XDp * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function enables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Mask | specifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts. |
| void XDp_RxSetIntrBwChangeHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a bandwidth change interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrNoVideoHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a no video interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrPowerStateHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when the power state interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp1Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 1 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp2Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 2 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTp3Handler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 3 interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTrainingDoneHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training done interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrTrainingLostHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training lost interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVBlankHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a vertical blanking interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVideoHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a valid video interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_RxSetIntrVmChangeHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a video mode change interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_TxSetHpdEventHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a hot-plug-detect event interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDp_TxSetHpdPulseHandler | +( | +XDp * | +InstancePtr, | +|
| + | + | XDp_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.
+
| InstancePtr | is a pointer to the XDp instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html new file mode 100644 index 00000000..8ed2d836 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__mst_8c.html @@ -0,0 +1,1722 @@ + +
+ ++ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "string.h"
+#include "xdp.h"
+
Classes | |
| struct | XDp_SidebandMsgHeader |
| struct | XDp_SidebandMsgBody |
| struct | XDp_SidebandMsg |
| struct | XDp_SidebandReply |
Defines | |
| #define | XDP_TX_MAX_SBMSG_REPLY_TIMEOUT_COUNT 5000 |
| #define | XDP_TX_VCP_TABLE_MAX_TIMEOUT_COUNT 30 |
Functions | |
| void | XDp_TxMstCfgModeEnable (XDp *InstancePtr) |
| void | XDp_TxMstCfgModeDisable (XDp *InstancePtr) |
| u32 | XDp_TxMstCapable (XDp *InstancePtr) |
| u32 | XDp_TxMstEnable (XDp *InstancePtr) |
| u32 | XDp_TxMstDisable (XDp *InstancePtr) |
| u8 | XDp_TxMstStreamIsEnabled (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxMstCfgStreamEnable (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxMstCfgStreamDisable (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxSetStreamSelectFromSinkList (XDp *InstancePtr, u8 Stream, u8 SinkNum) |
| void | XDp_TxSetStreamSinkRad (XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress) |
| u32 | XDp_TxDiscoverTopology (XDp *InstancePtr) |
| u32 | XDp_TxFindAccessibleDpDevices (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress) |
| void | XDp_TxTopologySwapSinks (XDp *InstancePtr, u8 Index0, u8 Index1) |
| void | XDp_TxTopologySortSinksByTiling (XDp *InstancePtr) |
| u32 | XDp_TxRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxAllocatePayloadStreams (XDp *InstancePtr) |
| u32 | XDp_TxAllocatePayloadVcIdTable (XDp *InstancePtr, u8 VcId, u8 Ts) |
| u32 | XDp_TxClearPayloadVcIdTable (XDp *InstancePtr) |
| u32 | XDp_TxSendSbMsgRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxSendSbMsgRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxSendSbMsgRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData) |
| u32 | XDp_TxSendSbMsgRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData) |
| u32 | XDp_TxSendSbMsgLinkAddress (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDp_TxSbMsgLinkAddressReplyDeviceInfo *DeviceInfo) |
| u32 | XDp_TxSendSbMsgEnumPathResources (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn) |
| u32 | XDp_TxSendSbMsgAllocatePayload (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn) |
| u32 | XDp_TxSendSbMsgClearPayloadIdTable (XDp *InstancePtr) |
| void | XDp_TxWriteGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 Guid[4]) |
| void | XDp_TxGetGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 *Guid) |
Variables | |
| u32 | GuidTable [16][4] |
| #define XDP_TX_MAX_SBMSG_REPLY_TIMEOUT_COUNT 5000 | +
+ +
| #define XDP_TX_VCP_TABLE_MAX_TIMEOUT_COUNT 30 | +
+ +
+
| u32 XDp_TxAllocatePayloadStreams | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will allocate bandwidth for all enabled stream.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxAllocatePayloadVcIdTable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +VcId, | +|
| + | + | u8 | +Ts | + |
| + | ) | ++ |
+This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress.
+
| InstancePtr | is a pointer to the XDp instance. | |
| VcId | is the unique virtual channel ID to allocate into the payload ID tables. | |
| Ts | is the number of timeslots to allocate in the payload ID tables. |
+
| u32 XDp_TxClearPayloadVcIdTable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxDiscoverTopology | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
+
| InstancePtr | is a pointer to the XDp instance. |
| u32 XDp_TxFindAccessibleDpDevices | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the current downstream device in the recursion. | |
| RelativeAddress | is the relative address from the DisplayPort source to the current target DisplayPort device in the recursion. |
| void XDp_TxGetGuid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 * | +Guid | + |
| + | ) | ++ |
+This function will obtain the global unique identifier (GUID) for the target DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target device. | |
| Guid | is a pointer to the GUID that will store the existing GUID of the target device. |
| u32 XDp_TxMstCapable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode. A DisplayPort Configuration Data (DPCD) version of 1.2 or higher is required and the MST capability bit in the DPCD must be set for this function to return XST_SUCCESS.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| void XDp_TxMstCfgModeDisable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will disable multi-stream transport (MST) mode for the driver.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxMstCfgModeEnable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will enable multi-stream transport (MST) mode for the driver.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxMstCfgStreamDisable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be disabled. |
| void XDp_TxMstCfgStreamEnable | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be enabled. |
| u32 XDp_TxMstDisable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxMstEnable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u8 XDp_TxMstStreamIsEnabled | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function will check whether
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID to check for enable/disable status. |
| u32 XDp_TxRemoteDpcdRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the starting address to read from the RX device. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to the data buffer that will be filled with read data. |
| u32 XDp_TxRemoteDpcdWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the starting address to write to the RX device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| u32 XDp_TxRemoteIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u16 | +Offset, | +|
| + | + | u16 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function performs a remote I2C read by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
| u32 XDp_TxRemoteIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicAddress, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function performs a remote I2C write by sending a sideband message. In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicAddress | is the address on the I2C bus of the target device. | |
| BytesToWrite | is the number of bytes to write. | |
| WriteData | is a pointer to a buffer which will be used as the data source for the write. |
| u32 XDp_TxSendSbMsgAllocatePayload | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +VcId, | +|
| + | + | u16 | +Pbn | + |
| + | ) | ++ |
+This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| VcId | is the unique virtual channel ID to allocate into the payload ID tables. | |
| Pbn | is the payload bandwidth number that determines how much bandwidth will be allocated for the virtual channel. |
+
| u32 XDp_TxSendSbMsgClearPayloadIdTable | +( | +XDp * | +InstancePtr | +) | ++ |
+This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 XDp_TxSendSbMsgEnumPathResources | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u16 * | +AvailPbn, | +|
| + | + | u16 * | +FullPbn | + |
| + | ) | ++ |
+This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| AvailPbn | is a pointer to the available PBN of the path whose value will be filled in by this function. | |
| FullPbn | is a pointer to the total PBN of the path whose value will be filled in by this function. |
+
+AvailPbn will be modified with the available PBN from the reply.
+FullPbn will be modified with the total PBN of the path from the reply.
| u32 XDp_TxSendSbMsgLinkAddress | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | XDp_TxSbMsgLinkAddressReplyDeviceInfo * | +DeviceInfo | + |
| + | ) | ++ |
+This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device. It is used to determine the resources available for that device and some device information for each of the ports connected to the branch device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort branch device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort branch device. | |
| DeviceInfo | is a pointer to the device information structure whose contents will be filled in with the information obtained by the LINK_ADDRESS sideband message. |
+
| u32 XDp_TxSendSbMsgRemoteDpcdRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the DPCD address of the target device that data will be read from. | |
| BytesToRead | is the number of bytes to read from the specified DPCD address. | |
| ReadData | is a pointer to a buffer that will be filled with the DPCD read data. |
+
| u32 XDp_TxSendSbMsgRemoteDpcdWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +DpcdAddress, | +|
| + | + | u32 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| DpcdAddress | is the DPCD address of the target device that data will be written to. | |
| BytesToWrite | is the number of bytes to write to the specified DPCD address. | |
| WriteData | is a pointer to a buffer that stores the data to write to the DPCD location. |
+
| u32 XDp_TxSendSbMsgRemoteIicRead | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicDeviceId, | +|
| + | + | u8 | +Offset, | +|
| + | + | u8 | +BytesToRead, | +|
| + | + | u8 * | +ReadData | + |
| + | ) | ++ |
+This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. | |
| IicDeviceId | is the address on the I2C bus of the target device. | |
| Offset | is the offset at the specified address of the targeted I2C device that the read will start from. | |
| BytesToRead | is the number of bytes to read from the I2C address. | |
| ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
+
| u32 XDp_TxSendSbMsgRemoteIicWrite | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u8 | +IicDeviceId, | +|
| + | + | u8 | +BytesToWrite, | +|
| + | + | u8 * | +WriteData | + |
| + | ) | ++ |
+ +
| void XDp_TxSetStreamSelectFromSinkList | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +SinkNum | + |
| + | ) | ++ |
+This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream ID that will be mapped to a DisplayPort device. | |
| SinkNum | is the sink ID in the sink list that will be mapped to the stream. |
+The topology will need to be determined prior to calling this function using the XDp_TxFindAccessibleDpDevices.
| void XDp_TxSetStreamSinkRad | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress | + |
| + | ) | ++ |
+This function will map a stream to a downstream DisplayPort TX device determined by the relative address.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number that will be mapped to a DisplayPort device. | |
| LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
| void XDp_TxTopologySortSinksByTiling | +( | +XDp * | +InstancePtr | +) | ++ |
+Order the sink list with all sinks of the same tiled display being sorted by 'tile order'. Refer to the XDp_TxGetDispIdTdtTileOrder macro on how to determine the 'tile order'. Sinks of a tiled display will have an index in the sink list that is lower than all indices of other sinks within that same tiled display that have a greater 'tile order'. When operations are done on the sink list, this ordering will ensure that sinks within the same tiled display will be acted upon in a consistent manner - with an incrementing sink list index, sinks with a lower 'tile order' will be acted upon first relative to the other sinks in the same tiled display. Multiple tiled displays may exist in the sink list.
+
| InstancePtr | is a pointer to the XDp instance. |
| void XDp_TxTopologySwapSinks | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Index0, | +|
| + | + | u8 | +Index1 | + |
| + | ) | ++ |
+Swap the ordering of the sinks in the topology's sink list. All sink information is preserved in the node table - the swapping takes place only on the pointers to the sinks in the node table. The reason this swapping is done is so that functions that use the sink list will act on the sinks in a different order.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Index0 | is the sink list's index of one of the sink pointers to be swapped. | |
| Index1 | is the sink list's index of the other sink pointer to be swapped. |
| void XDp_TxWriteGuid | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +LinkCountTotal, | +|
| + | + | u8 * | +RelativeAddress, | +|
| + | + | u32 | +Guid[4] | + |
| + | ) | ++ |
+This function will write a global unique identifier (GUID) to the target DisplayPort device.
+
| InstancePtr | is a pointer to the XDp instance. | |
| LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. | |
| RelativeAddress | is the relative address from the DisplayPort source to the target device. | |
| Guid | is a the GUID to write to the target device. |
+
| u32 GuidTable[16][4] | +
+Initial value:
{
+ {0x12341234, 0x43214321, 0x56785678, 0x87658765},
+ {0xDEADBEEF, 0xBEEFDEAD, 0x10011001, 0xDADADADA},
+ {0xDABADABA, 0x10011001, 0xBADABADA, 0x5AD5AD5A},
+ {0x12345678, 0x43214321, 0xABCDEF98, 0x87658765},
+ {0x12141214, 0x41214121, 0x56785678, 0x87658765},
+ {0xD1CDB11F, 0xB11FD1CD, 0xFEBCDA90, 0xDCDCDCDC},
+ {0xDCBCDCBC, 0xE000E000, 0xBCDCBCDC, 0x5CD5CD5C},
+ {0x11111111, 0x11111111, 0x11111111, 0x11111111},
+ {0x22222222, 0x22222222, 0x22222222, 0x22222222},
+ {0x33333333, 0x33333333, 0x33333333, 0x33333333},
+ {0xAAAAAAAA, 0xFFFFFFFF, 0xFEBCDA90, 0xDCDCDCDC},
+ {0xBBBBBBBB, 0xE000E000, 0xFFFFFFFF, 0x5CD5CD5C},
+ {0xCCCCCCCC, 0x11111111, 0x11111111, 0xFFFFFFFF},
+ {0xDDDDDDDD, 0x22222222, 0xFFFFFFFF, 0x22222222},
+ {0xEEEEEEEE, 0xFFFFFFFF, 0x33333333, 0x33333333},
+ {0x12145678, 0x41214121, 0xCBCD1F98, 0x87658765}
+}
++Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html new file mode 100644 index 00000000..32b444c8 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__selftest_8c.html @@ -0,0 +1,148 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+
Functions | |
| u32 | XDp_SelfTest (XDp *InstancePtr) |
Variables | |
| u32 | TxResetValues [53][2] |
| u32 | TxResetValuesMsa [20][2] |
| u32 | RxResetValues [46][2] |
| u32 XDp_SelfTest | +( | +XDp * | +InstancePtr | +) | ++ |
+This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. The sanity test checks whether or not all tested registers hold their default reset values.
+
| InstancePtr | is a pointer to the XDp instance. |
+
| u32 RxResetValues[46][2] | +
+This table contains the default values for the DisplayPort RX core's general usage registers. +
| u32 TxResetValues[53][2] | +
+This table contains the default values for the DisplayPort TX core's general usage registers. +
| u32 TxResetValuesMsa[20][2] | +
+Initial value:
+{
+ {XDP_TX_MAIN_STREAM_HTOTAL, 0},
+ {XDP_TX_MAIN_STREAM_VTOTAL, 0},
+ {XDP_TX_MAIN_STREAM_POLARITY, 0},
+ {XDP_TX_MAIN_STREAM_HSWIDTH, 0},
+ {XDP_TX_MAIN_STREAM_VSWIDTH, 0},
+ {XDP_TX_MAIN_STREAM_HRES, 0},
+ {XDP_TX_MAIN_STREAM_VRES, 0},
+ {XDP_TX_MAIN_STREAM_HSTART, 0},
+ {XDP_TX_MAIN_STREAM_VSTART, 0},
+ {XDP_TX_MAIN_STREAM_MISC0, 0},
+ {XDP_TX_MAIN_STREAM_MISC1, 0},
+ {XDP_TX_M_VID, 0},
+ {XDP_TX_TU_SIZE, 0},
+ {XDP_TX_N_VID, 0},
+ {XDP_TX_USER_PIXEL_WIDTH, 0},
+ {XDP_TX_USER_DATA_COUNT_PER_LANE, 0},
+ {XDP_TX_MAIN_STREAM_INTERLACED, 0},
+ {XDP_TX_MIN_BYTES_PER_TU, 0},
+ {XDP_TX_FRAC_BYTES_PER_TU, 0},
+ {XDP_TX_INIT_WAIT, 32}
+}
++Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html new file mode 100644 index 00000000..4df51c60 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__sinit_8c.html @@ -0,0 +1,90 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+#include "xparameters.h"
+
Functions | |
| XDp_Config * | XDp_LookupConfig (u16 DeviceId) |
Variables | |
| XDp_Config | XDp_ConfigTable [XPAR_XDP_NUM_INSTANCES] |
| XDp_Config* XDp_LookupConfig | +( | +u16 | +DeviceId | +) | ++ |
+This function looks for the device configuration based on the unique device ID. The table XDp_ConfigTable[] contains the configuration information for each device in the system.
+
| DeviceId | is the unique device ID of the device being looked up. |
+
| XDp_Config XDp_ConfigTable[XPAR_XDP_NUM_INSTANCES] | +
+A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. +
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html new file mode 100644 index 00000000..faaa5791 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdp__spm_8c.html @@ -0,0 +1,486 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdp.h"
+
Functions | |
| void | XDp_TxCfgMsaRecalculate (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxCfgMsaUseStandardVideoMode (XDp *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode) |
| void | XDp_TxCfgMsaUseEdidPreferredTiming (XDp *InstancePtr, u8 Stream, u8 *Edid) |
| void | XDp_TxCfgMsaUseCustom (XDp *InstancePtr, u8 Stream, XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate) |
| void | XDp_TxCfgMsaSetBpc (XDp *InstancePtr, u8 Stream, u8 BitsPerColor) |
| void | XDp_TxCfgMsaEnSynchClkMode (XDp *InstancePtr, u8 Stream, u8 Enable) |
| void | XDp_TxSetVideoMode (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxClearMsaValues (XDp *InstancePtr, u8 Stream) |
| void | XDp_TxSetMsaValues (XDp *InstancePtr, u8 Stream) |
| void | XDp_RxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth) |
| void XDp_RxSetUserPixelWidth | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +UserPixelWidth | + |
| + | ) | ++ |
+This function configures the number of pixels output through the user data interface.
+
| InstancePtr | is a pointer to the XDp instance. | |
| UserPixelWidth | is the user pixel width to be configured. |
| void XDp_TxCfgMsaEnSynchClkMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +Enable | + |
| + | ) | ++ |
+This function enables or disables synchronous clock mode for a video stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to enable or disable synchronous clock mode. | |
| Enable | if set to 1, will enable synchronous clock mode. Otherwise, if set to 0, synchronous clock mode will be disabled. |
| void XDp_TxCfgMsaRecalculate | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function calculates the following Main Stream Attributes (MSA):
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to calculate the MSA values. |
| void XDp_TxCfgMsaSetBpc | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 | +BitsPerColor | + |
| + | ) | ++ |
+This function sets the bits per color value of the video stream.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the color depth. | |
| BitsPerColor | is the new number of bits per color to use. |
| void XDp_TxCfgMsaUseCustom | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | XDp_TxMainStreamAttributes * | +MsaConfigCustom, | +|
| + | + | u8 | +Recalculate | + |
| + | ) | ++ |
+This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| MsaConfigCustom | is the structure that will be used to copy the main stream attributes from (into InstancePtr->TxInstance.MsaConfig). | |
| Recalculate | is a boolean enable that determines whether or not the main stream attributes should be recalculated. |
| void XDp_TxCfgMsaUseEdidPreferredTiming | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | u8 * | +Edid | + |
| + | ) | ++ |
+This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| Edid | is a pointer to the Edid to use for the specified stream. |
| void XDp_TxCfgMsaUseStandardVideoMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream, | +|
| + | + | XVidC_VideoMode | +VideoMode | + |
| + | ) | ++ |
+This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table. The XDp_TxVideoMode enumeration in xvidc.h lists the available video modes.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which the MSA values will be used for. | |
| VideoMode | is one of the enumerated standard video modes that is used to determine the MSA values to be used. |
| void XDp_TxClearMsaValues | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function clears the main stream attributes registers of the DisplayPort TX core.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to clear the MSA values. |
| void XDp_TxSetMsaValues | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the MSA values for. |
| void XDp_TxSetVideoMode | +( | +XDp * | +InstancePtr, | +|
| + | + | u8 | +Stream | + |
| + | ) | ++ |
+This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.
+
| InstancePtr | is a pointer to the XDp instance. | |
| Stream | is the stream number for which to set the MSA values for. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8c.html new file mode 100644 index 00000000..45713129 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8c.html @@ -0,0 +1,421 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/14 Initial release. ++
+#include "xdprx.h"
+#include "xstatus.h"
+
Functions | |
| void | XDprx_CfgInitialize (XDprx *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) |
| u32 | XDprx_InitializeRx (XDprx *InstancePtr) |
| u32 | XDprx_CheckLinkStatus (XDprx *InstancePtr) |
| void | XDprx_DtgEn (XDprx *InstancePtr) |
| void | XDprx_DtgDis (XDprx *InstancePtr) |
| void | XDprx_SetLinkRate (XDprx *InstancePtr, u8 LinkRate) |
| void | XDprx_SetLaneCount (XDprx *InstancePtr, u8 LaneCount) |
| void | XDprx_SetUserPixelWidth (XDprx *InstancePtr, u8 UserPixelWidth) |
| void | XDprx_SetUserTimerHandler (XDprx *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_WaitUs (XDprx *InstancePtr, u32 MicroSeconds) |
| void XDprx_CfgInitialize | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDp_Config * | +ConfigPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function retrieves the configuration for this DisplayPort RX instance and fills in the InstancePtr->Config structure.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. | |
| EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
| u32 XDprx_CheckLinkStatus | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function checks if the reciever's internal registers indicate that link training has complete. That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_DtgDis | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function disables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_DtgEn | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function enables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDprx instance. |
| u32 XDprx_InitializeRx | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function prepares the DisplayPort RX core for use.
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_SetLaneCount | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| void XDprx_SetLinkRate | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| void XDprx_SetUserPixelWidth | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +UserPixelWidth | + |
| + | ) | ++ |
+This function configures the number of pixels output through the user data interface.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| UserPixelWidth | is the user pixel width to be configured. |
| void XDprx_SetUserTimerHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDp_TimerHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a custom delay/sleep function to be used by the XDprx driver.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. |
| void XDprx_WaitUs | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +MicroSeconds | + |
| + | ) | ++ |
+This function is the delay/sleep function for the XDprx driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| MicroSeconds | is the number of microseconds to delay/sleep for. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8h.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8h.html new file mode 100644 index 00000000..89fc11ad --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx_8h.html @@ -0,0 +1,1165 @@ + +
+ ++Driver description
+The device driver enables higher-level software (e.g., an application) to configure and control a DisplayPort RX soft IP.
+This driver gives applications the ability to configure the RX using various settings, handle and issue interrupts, and modify a subset of its DisplayPort Configuration Data (DPCD) fields.
+Interrupt processing
+The DisplayPort RX driver may generate a pulse on the hot-plug-detect (HPD) signal line using the XDprx_GenerateHpdInterrupt function. This allows the RX to send an interrupt to the upstream TX device, useful for signaling the TX that it needs to do some checks for changes in downstream devices or a loss of link training.
+For RX interrupt handling of HPD events or events that happen internal to the RX, the user hardware design must contain an interrupt controller which the DisplayPort RX instance's interrupt signal is connected to. The user application must enable interrupts in the system and set up the interrupt controller such that the XDprx_InterruptHandler handler will service interrupts. When the XDprx_InterruptHandler function is invoked, the handler will identify what type of interrupt has occurred, and will call the appropriate interrupt handler.
+The DisplayPort RX's XDPRX_INTERRUPT_CAUSE register indicates the type of interrupt that has occured, and the XDprx_InterruptHandler will use this information to decide which handler to call.
+The handlers are set up using the XDprx_SetIntr* functions.
+Specific interrupts may be enabled or disabled using the XDprx_InterruptEnable and XDprx_InterruptDisable functions.
+Multi-stream transport (MST) mode
+The DisplayPort RX driver does not support MST functionality in 2015.1.
+Audio
+The driver does not handle audio.
+
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/14 Initial release. ++
+#include "xdp.h"
+#include "xdprx_hw.h"
+
Classes | |
| struct | XDprx_LinkConfig |
| struct | XDprx |
Typedefs | |
| typedef void(*) | XDprx_IntrHandler (void *InstancePtr) |
Functions | |
| void | XDprx_CfgInitialize (XDprx *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) |
| u32 | XDprx_InitializeRx (XDprx *InstancePtr) |
| u32 | XDprx_CheckLinkStatus (XDprx *InstancePtr) |
| void | XDprx_DtgEn (XDprx *InstancePtr) |
| void | XDprx_DtgDis (XDprx *InstancePtr) |
| void | XDprx_SetLinkRate (XDprx *InstancePtr, u8 LinkRate) |
| void | XDprx_SetLaneCount (XDprx *InstancePtr, u8 LaneCount) |
| void | XDprx_SetUserPixelWidth (XDprx *InstancePtr, u8 UserPixelWidth) |
| void | XDprx_SetUserTimerHandler (XDprx *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_WaitUs (XDprx *InstancePtr, u32 MicroSeconds) |
| void | XDprx_InterruptHandler (XDprx *InstancePtr) |
| void | XDprx_GenerateHpdInterrupt (XDprx *InstancePtr, u16 DurationUs) |
| void | XDprx_InterruptEnable (XDprx *InstancePtr, u32 Mask) |
| void | XDprx_InterruptDisable (XDprx *InstancePtr, u32 Mask) |
| void | XDprx_SetIntrVmChangeHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrPowerStateHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrNoVideoHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrVBlankHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTrainingLostHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrVideoHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTrainingDoneHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrBwChangeHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp1Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp2Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp3Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| u32 | XDprx_SelfTest (XDprx *InstancePtr) |
| typedef void(*) XDprx_IntrHandler(void *InstancePtr) | +
+Callback type which represents the handler for interrupts.
+
| InstancePtr | is a pointer to the XDprx instance. |
+
| void XDprx_CfgInitialize | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDp_Config * | +ConfigPtr, | +|
| + | + | u32 | +EffectiveAddr | + |
| + | ) | ++ |
+This function retrieves the configuration for this DisplayPort RX instance and fills in the InstancePtr->Config structure.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. | |
| EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
| u32 XDprx_CheckLinkStatus | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function checks if the reciever's internal registers indicate that link training has complete. That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_DtgDis | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function disables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_DtgEn | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function enables the display timing generator (DTG).
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_GenerateHpdInterrupt | +( | +XDprx * | +InstancePtr, | +|
| + | + | u16 | +DurationUs | + |
| + | ) | ++ |
+This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| DurationUs | is the duration of the HPD pulse, in microseconds. |
| u32 XDprx_InitializeRx | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function prepares the DisplayPort RX core for use.
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_InterruptDisable | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function disables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| Mask | specifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts. |
| void XDprx_InterruptEnable | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function enables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| Mask | specifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts. |
| void XDprx_InterruptHandler | +( | +XDprx * | +InstancePtr | +) | ++ |
| u32 XDprx_SelfTest | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function runs a self-test on the XDprx driver/device. The sanity test checks whether or not all tested registers hold their default reset values.
+
| InstancePtr | is a pointer to the XDprx instance. |
| void XDprx_SetIntrBwChangeHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a bandwidth change interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrNoVideoHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a no video interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrPowerStateHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when the power state interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp1Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 1 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp2Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 2 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp3Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 3 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTrainingDoneHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training done interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTrainingLostHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training lost interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVBlankHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a vertical blanking interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVideoHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a valid video interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVmChangeHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a video mode change interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetLaneCount | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +LaneCount | + |
| + | ) | ++ |
+This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| LaneCount | is the number of lanes to be used over the main link. |
| void XDprx_SetLinkRate | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +LinkRate | + |
| + | ) | ++ |
+This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
| void XDprx_SetUserPixelWidth | +( | +XDprx * | +InstancePtr, | +|
| + | + | u8 | +UserPixelWidth | + |
| + | ) | ++ |
+This function configures the number of pixels output through the user data interface.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| UserPixelWidth | is the user pixel width to be configured. |
| void XDprx_SetUserTimerHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDp_TimerHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a custom delay/sleep function to be used by the XDprx driver.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. |
| void XDprx_WaitUs | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +MicroSeconds | + |
| + | ) | ++ |
+This function is the delay/sleep function for the XDprx driver. For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| MicroSeconds | is the number of microseconds to delay/sleep for. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__hw_8h.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__hw_8h.html new file mode 100644 index 00000000..e2a131a9 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__hw_8h.html @@ -0,0 +1,5169 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/14 Initial release. ++
+#include "xil_io.h"
+
| #define XDPRX_AUDIO_UNSUPPORTED 0x098 | +
+DPCD register bit to inform the DisplayPort TX that audio data is not supported. +
| #define XDPRX_AUX_CLK_DIVIDER 0x004 | +
+Clock divider value for generating the internal 1MHz clock. +
| #define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 | +
+AUX (noise) signal width filter. +
| #define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 | +
+Shift bits for AUX signal width filter. +
| #define XDPRX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF | +
+Clock divider value. +
| #define XDPRX_AUX_REQ_IN_PROGRESS 0x020 | +
+Indicates the receipt of an AUX channel request. +
| #define XDPRX_CDR_CONTROL_CONFIG 0x21C | +
+Control the configuration for clock and data recovery. +
| #define XDPRX_CORE_ID 0x0FC | +
+DisplayPort protocol version and revision. +
| #define XDPRX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 | +
+DisplayPort protocol major version. +
| #define XDPRX_CORE_ID_DP_MJR_VER_SHIFT 24 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDPRX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 | +
+DisplayPort protocol minor version. +
| #define XDPRX_CORE_ID_DP_MNR_VER_SHIFT 16 | +
+Shift bits for DisplayPort protocol major version. +
| #define XDPRX_CORE_ID_DP_REV_MASK 0x000000F0 | +
+DisplayPort protocol revision. +
| #define XDPRX_CORE_ID_DP_REV_SHIFT 8 | +
+Shift bits for DisplayPort protocol revision. +
| #define XDPRX_CORE_ID_TYPE_MASK 0x0000000F | +
+Core type. +
| #define XDPRX_CORE_ID_TYPE_RX 0x1 | +
+Core is a receiver. +
| #define XDPRX_CORE_ID_TYPE_TX 0x0 | +
+Core is a transmitter. +
| #define XDPRX_DEVICE_SERVICE_IRQ 0x090 | +
+Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state. +
| #define XDPRX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK 0x10 | +
+Indicates a new DOWN_REPLY buffer message is ready. +
| #define XDPRX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK 0x01 | +
+Indicates that a new command is present in the REMOTE_CMD register. +
| #define XDPRX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK 0x02 | +
+Reflects the SINK_SPECIFIC_IRQ state. +
| #define XDPRX_DOWN_REP 0xB00 | +
+Down reply buffer address space. +
| #define XDPRX_DOWN_REQ 0xA00 | +
+Down request buffer address space. +
| #define XDPRX_DPCD_DOWNSPREAD_CONTROL 0x430 | +
+The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled. +
| #define XDPRX_DPCD_ENHANCED_FRAME_EN 0x408 | +
+Current setting for enhanced framing symbol mode as exposed in the RX DPCD. +
| #define XDPRX_DPCD_LANE01_STATUS 0x43C | +
+Link training status for lanes 0 and 1 as exposed in the RX DPCD. +
| #define XDPRX_DPCD_LANE23_STATUS 0x440 | +
+Link training status for lanes 2 and 3 as exposed in the RX DPCD. +
| #define XDPRX_DPCD_LANE_COUNT_SET 0x404 | +
+Current lane count setting as exposed in the RX DPCD. +
| #define XDPRX_DPCD_LINK_BW_SET 0x400 | +
+Current link bandwidth setting as exposed in the RX DPCD. +
| #define XDPRX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 | +
+Current value of the link quality pattern field as exposed in the RX DPCD. +
| #define XDPRX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 | +
+8B/10B encoding setting as exposed in the RX DPCD. +
| #define XDPRX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 | +
+Value of the output clock enable field as exposed in the RX DPCD. +
| #define XDPRX_DPCD_SCRAMBLING_DISABLE 0x418 | +
+Value of the scrambling disable field as exposed in the RX DPCD. +
| #define XDPRX_DPCD_SET_POWER_STATE 0x438 | +
+Power state requested by the TX as exposed in the RX DPCD. +
| #define XDPRX_DPCD_SOURCE_OUI_VALUE 0x444 | +
+ +
| #define XDPRX_DPCD_SYM_ERR_CNT01 0x448 | +
+ +
| #define XDPRX_DPCD_SYM_ERR_CNT23 0x44C | +
+ +
| #define XDPRX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C | +
+Current value of the symbol error count select field as exposed in the RX DPCD. +
| #define XDPRX_DPCD_TRAINING_LANE_0_SET 0x420 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 0. +
| #define XDPRX_DPCD_TRAINING_LANE_1_SET 0x424 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 1. +
| #define XDPRX_DPCD_TRAINING_LANE_2_SET 0x428 | +
+The RX DPCD value used by the TX during link training to configure the RX PHY lane 2. +
| #define XDPRX_DPCD_TRAINING_LANE_3_SET 0x42C | +
+The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3. +
| #define XDPRX_DPCD_TRAINING_PATTERN_SET 0x40C | +
+Current training pattern setting as exposed in the RX DPCD. +
| #define XDPRX_DTG_ENABLE 0x00C | +
+Enables the display timing generator (DTG). +
| #define XDPRX_FAST_I2C_DIVIDER 0x060 | +
+Fast I2C mode clock divider value. +
| #define XDPRX_GT_DRP_CH_STATUS 0x2A8 | +
+Provides access to GT DRP channel status. +
| #define XDPRX_GT_DRP_COMMAND 0x2A0 | +
+Provides access to the GT DRP ports. +
| #define XDPRX_GT_DRP_READ_DATA 0x2A4 | +
+Provides access to GT DRP read data. +
| #define XDPRX_GUID0 0x0E0 | +
+Lower 4 bytes of the DPCD's GUID field. +
| #define XDPRX_GUID1 0x0E4 | +
+Bytes 4 to 7 of the DPCD's GUID field. +
| #define XDPRX_GUID2 0x0E8 | +
+Bytes 8 to 11 of the DPCD's GUID field. +
| #define XDPRX_GUID3 0x0EC | +
+Upper 4 bytes of the DPCD's GUID field. +
| #define XDPRX_HPD_INTERRUPT 0x02C | +
+Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal. +
| #define XDPRX_HPD_INTERRUPT_ASSERT_MASK 0x00000001 | +
+Instructs the RX core to assert an interrupt to the TX using the HPD signal. +
| #define XDPRX_HPD_INTERRUPT_LENGTH_US_MASK 0xFFFF0000 | +
+The length of the HPD pulse to generate (in microseconds). +
| #define XDPRX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 | +
+Shift bits for the HPD pulse length. +
| #define XDPRX_HSYNC_WIDTH 0x050 | +
+Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG). +
| #define XDPRX_HSYNC_WIDTH_FRONT_PORCH_MASK 0xFF00 | +
+Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch). +
| #define XDPRX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 | +
+Shift bits for the front porch. +
| #define XDPRX_HSYNC_WIDTH_PULSE_WIDTH_MASK 0x00FF | +
+Specifies the number of clock cycles the horizontal sync pulse is asserted. +
| #define XDprx_In32 Xil_In32 | +
+ +
| #define XDPRX_INTERRUPT_CAUSE 0x040 | +
+Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel. +
| #define XDPRX_INTERRUPT_CAUSE_1 0x048 | +
+Indicates the cause of a pending host interrupts for streams 2, 3, 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) | +
+Interrupt caused by an audio extension packet being received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) | +
+Interrupt caused by an audio info packet being received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) | +
+Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) | +
+Interrupt caused by the start of the blanking interval for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) | +
+Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK | +( | +Stream | ++ | ) | +XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) | +
+Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_CAUSE_BW_CHANGE_MASK XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK | +
+Interrupt caused by a change in bandwidth. +
| #define XDPRX_INTERRUPT_CAUSE_DOWN_REPLY_MASK XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK | +
+Interrupt caused by a downstream reply being ready. +
| #define XDPRX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK | +
+Interrupt caused by a downstream request being ready. +
| #define XDPRX_INTERRUPT_CAUSE_EXT_PKT_MASK XDPRX_INTERRUPT_MASK_EXT_PKT_MASK | +
+Interrupt caused by an audio extension packet being received. +
| #define XDPRX_INTERRUPT_CAUSE_INFO_PKT_MASK XDPRX_INTERRUPT_MASK_INFO_PKT_MASK | +
+Interrupt caused by an audio info packet being received. +
| #define XDPRX_INTERRUPT_CAUSE_NO_VIDEO_MASK XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK | +
+Interrupt caused by the no-video condition being detected after active video received. +
| #define XDPRX_INTERRUPT_CAUSE_POWER_STATE_MASK XDPRX_INTERRUPT_MASK_POWER_STATE_MASK | +
+Interrupt caused by a power state change. +
| #define XDPRX_INTERRUPT_CAUSE_TP1_MASK XDPRX_INTERRUPT_MASK_TP1_MASK | +
+Interrupt caused by the start of training pattern 1. +
| #define XDPRX_INTERRUPT_CAUSE_TP2_MASK XDPRX_INTERRUPT_MASK_TP2_MASK | +
+Interrupt caused by the start of training pattern 2. +
| #define XDPRX_INTERRUPT_CAUSE_TP3_MASK XDPRX_INTERRUPT_MASK_TP3_MASK | +
+Interrupt caused by the start of training pattern 3. +
| #define XDPRX_INTERRUPT_CAUSE_TRAINING_DONE_MASK XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK | +
+Interrupt caused by link training completion. +
| #define XDPRX_INTERRUPT_CAUSE_TRAINING_LOST_MASK XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK | +
+Interrupt caused by training loss on active lanes. +
| #define XDPRX_INTERRUPT_CAUSE_VBLANK_MASK XDPRX_INTERRUPT_MASK_VBLANK_MASK | +
+Interrupt caused by the start of the blanking interval. +
| #define XDPRX_INTERRUPT_CAUSE_VCP_ALLOC_MASK XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK | +
+Interrupt caused by a virtual channel payload being allocated. +
| #define XDPRX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK | +
+Interrupt caused by a virtual channel payload being allocated. +
| #define XDPRX_INTERRUPT_CAUSE_VIDEO_MASK XDPRX_INTERRUPT_MASK_VIDEO_MASK | +
+Interrupt caused by a valid video frame being detected on the main link. Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character. +
| #define XDPRX_INTERRUPT_CAUSE_VM_CHANGE_MASK XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK | +
+Interrupt caused by a resolution change, as detected from the MSA fields. +
| #define XDPRX_INTERRUPT_MASK 0x014 | +
+Masks the specified interrupt sources for stream 1. +
| #define XDPRX_INTERRUPT_MASK_1 0x044 | +
+Masks the specified interrupt sources for streams 2, 3, 4. +
| #define XDPRX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00001 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00002 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00008 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00010 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00020 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK | +( | +Stream | ++ | ) | +(0x00004 << ((Stream - 2) * 6)) | +
+Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4. +
| #define XDPRX_INTERRUPT_MASK_ALL_MASK 0x7FFFF | +
+Mask all interrupts. +
| #define XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK 0x08000 | +
+Mask the interrupt assertion for a change in bandwidth. +
| #define XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK 0x01000 | +
+Mask the interrupt assertion for a downstream reply being ready. +
| #define XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK 0x02000 | +
+Mask the interrupt assertion for a downstream request being ready. +
| #define XDPRX_INTERRUPT_MASK_EXT_PKT_MASK 0x00200 | +
+Mask the interrupt assertion for an audio extension packet being received. +
| #define XDPRX_INTERRUPT_MASK_INFO_PKT_MASK 0x00100 | +
+Mask the interrupt assertion for an audio info packet being received. +
| #define XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK 0x00004 | +
+Mask the interrupt assertion for the no-video condition being detected after active video received. +
| #define XDPRX_INTERRUPT_MASK_POWER_STATE_MASK 0x00002 | +
+Mask the interrupt assertion for a power state change. +
| #define XDPRX_INTERRUPT_MASK_TP1_MASK 0x10000 | +
+Mask the interrupt assertion for start of training pattern 1. +
| #define XDPRX_INTERRUPT_MASK_TP2_MASK 0x20000 | +
+Mask the interrupt assertion for start of training pattern 2. +
| #define XDPRX_INTERRUPT_MASK_TP3_MASK 0x40000 | +
+Mask the interrupt assertion for start of training pattern 3. +
| #define XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK 0x04000 | +
+Mask the interrupt assertion for link training completion. +
| #define XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK 0x00010 | +
+Mask the interrupt assertion for training loss on active lanes. +
| #define XDPRX_INTERRUPT_MASK_VBLANK_MASK 0x00008 | +
+Mask the interrupt assertion for the start of the blanking interval. +
| #define XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK 0x00400 | +
+Mask the interrupt assertion for a virtual channel payload being allocated. +
| #define XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK 0x00800 | +
+Mask the interrupt assertion for a virtual channel payload being allocated. +
| #define XDPRX_INTERRUPT_MASK_VIDEO_MASK 0x00040 | +
+Mask the interrupt assertion for a valid video frame being detected on the main link. Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character. +
| #define XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK 0x00001 | +
+Mask the interrupt assertion for a resolution change, as detected from the MSA fields. +
| #define XDPRX_LINK_ENABLE 0x000 | +
+Enable the receiver core. +
| #define XDPRX_LOCAL_EDID_AUDIO 0x088 | +
+Indicates the presence of EDID information for the audio stream. +
| #define XDPRX_LOCAL_EDID_VIDEO 0x084 | +
+Indicates the presence of EDID information for the video stream. +
| #define XDPRX_MIN_VOLTAGE_SWING 0x214 | +
+Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training. +
| #define XDPRX_MISC_CTRL 0x018 | +
+Miscellaneous control of RX behavior. +
| #define XDPRX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK 0x4 | +
+When set, I2C DEFERs will be sent as AUX DEFERs to the source device. +
| #define XDPRX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK 0x2 | +
+When set, the long I2C write data transfwers are responded to using DEFER instead of partial ACKs. +
| #define XDPRX_MISC_CTRL_USE_FILT_MSA_MASK 0x1 | +
+When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally. +
| #define XDPRX_MSA_HRES 0x500 | +
+Number of active pixels per line (the horizontal resolution). +
| #define XDPRX_MSA_HSPOL 0x504 | +
+The horizontal sync polarity. +
| #define XDPRX_MSA_HSTART 0x50C | +
+Number of clocks between the leading edge of the horizontal sync and the start of active data. +
| #define XDPRX_MSA_HSWIDTH 0x508 | +
+Width of the horizontal sync pulse. +
| #define XDPRX_MSA_HTOTAL 0x510 | +
+Total number of clocks in the horizontal framing period. +
| #define XDPRX_MSA_MISC0 0x528 | +
+Miscellaneous stream attributes. +
| #define XDPRX_MSA_MISC1 0x52C | +
+Miscellaneous stream attributes. +
| #define XDPRX_MSA_MVID 0x530 | +
+Used to recover the video clock from the link clock. +
| #define XDPRX_MSA_NVID 0x534 | +
+Used to recover the video clock from the link clock. +
| #define XDPRX_MSA_VBID 0x538 | +
+The most recently received VB-ID value. +
| #define XDPRX_MSA_VHEIGHT 0x514 | +
+Number of active lines (the vertical resolution). +
| #define XDPRX_MSA_VSPOL 0x518 | +
+The vertical sync polarity. +
| #define XDPRX_MSA_VSTART 0x520 | +
+Number of lines between the leading edge of the vertical sync and the first line of active data. +
| #define XDPRX_MSA_VSWIDTH 0x51C | +
+Width of the vertical sync pulse. +
| #define XDPRX_MSA_VTOTAL 0x524 | +
+Total number of lines in the video frame. +
| #define XDPRX_MST_CAP 0x0D0 | +
+Used to enable or disable MST capability. +
| #define XDprx_Out32 Xil_Out32 | +
+ +
| #define XDPRX_OVER_CTRL_DPCD 0x0B8 | +
+Used to enable AXI/APB write access to the DPCD capability structure. +
| #define XDPRX_OVER_DOWNSPREAD_CTRL 0x0BC | +
+Used to override downspread control in the DPCD. +
| #define XDPRX_OVER_GUID 0x0F0 | +
+Used to override the GUID field in the DPCD with what is stored in XDPRX_GUID[0-3]. +
| #define XDPRX_OVER_LANE_COUNT_SET 0x0A0 | +
+Used to override the lane count setting in the DPCD. +
| #define XDPRX_OVER_LANE_COUNT_SET_1 0x1 | +
+Lane count of 1. +
| #define XDPRX_OVER_LANE_COUNT_SET_2 0x2 | +
+Lane count of 2. +
| #define XDPRX_OVER_LANE_COUNT_SET_4 0x4 | +
+Lane count of 4. +
| #define XDPRX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK 0x80 | +
+Capability override for enhanced framing. +
| #define XDPRX_OVER_LANE_COUNT_SET_MASK 0x1F | +
+The lane count override value. +
| #define XDPRX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK 0x20 | +
+Capability override for training pattern 3. +
| #define XDPRX_OVER_LINK_BW_SET 0x09C | +
+Used to override the main link bandwidth setting in the DPCD. +
| #define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 | +
+1.62 Gbps link rate. +
| #define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A | +
+2.70 Gbps link rate. +
| #define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 | +
+5.40 Gbps link rate. +
| #define XDPRX_OVER_LINK_QUAL_LANE0_SET 0x0C0 | +
+Used to override the LINK_QUAL_LANE0_SET register in the DPCD. +
| #define XDPRX_OVER_LINK_QUAL_LANE1_SET 0x0C4 | +
+Used to override the LINK_QUAL_LANE1_SET register in the DPCD. +
| #define XDPRX_OVER_LINK_QUAL_LANE2_SET 0x0C8 | +
+Used to override the LINK_QUAL_LANE2_SET register in the DPCD. +
| #define XDPRX_OVER_LINK_QUAL_LANE3_SET 0x0CC | +
+Used to override the LINK_QUAL_LANE3_SET register in the DPCD. +
| #define XDPRX_OVER_TP_SET 0x0A4 | +
+Used to override the link training pattern in the DPCD. +
| #define XDPRX_OVER_TP_SET_LQP_SET_MASK 0x000C | +
+Link quality pattern set override. +
| #define XDPRX_OVER_TP_SET_LQP_SET_SHIFT 2 | +
+Shift bits for link quality pattern set override. +
| #define XDPRX_OVER_TP_SET_REC_CLK_OUT_EN_MASK 0x0010 | +
+Recovered clock output enable override. +
| #define XDPRX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK 0x0020 | +
+Scrambling disable override. +
| #define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK 0x00C0 | +
+Symbol error count override. +
| #define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT 6 | +
+Shift bits for symbol error count override. +
| #define XDPRX_OVER_TP_SET_TP_SELECT_MASK 0x0003 | +
+Training pattern select override. +
| #define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK 0xFF00 | +
+Training AUX read interval override. +
| #define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT 8 | +
+Shift bits for training AUX read interval override. +
| #define XDPRX_OVER_TRAINING_LANE0_SET 0x0A8 | +
+Used to override the TRAINING_LANE0_SET register in the DPCD. +
| #define XDPRX_OVER_TRAINING_LANE1_SET 0x0AC | +
+Used to override the TRAINING_LANE1_SET register in the DPCD. +
| #define XDPRX_OVER_TRAINING_LANE2_SET 0x0B0 | +
+Used to override the TRAINING_LANE2_SET register in the DPCD. +
| #define XDPRX_OVER_TRAINING_LANE3_SET 0x0B4 | +
+Used to override the TRAINING_LANE3_SET register in the DPCD. +
| #define XDPRX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 | +
+Maximum pre-emphasis override. +
| #define XDPRX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 | +
+Maximum voltage swing override. +
| #define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_MASK 0x18 | +
+Pre-emphasis set override. +
| #define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT 3 | +
+Shift bits for pre-emphasis set override. +
| #define XDPRX_OVER_TRAINING_LANEX_SET_VS_SET_MASK 0x03 | +
+Voltage swing set override. +
| #define XDPRX_PHY_CONFIG 0x200 | +
+Transceiver PHY reset and configuration. +
| #define XDPRX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK 0x04000000 | +
+Enable the individual lane polarity. +
| #define XDPRX_PHY_CONFIG_GT_ALL_RESET_MASK 0x00000003 | +
+Rest GT and PHY. +
| #define XDPRX_PHY_CONFIG_GTPLL_RESET_MASK 0x00000001 | +
+Hold the GTPLL in reset. +
| #define XDPRX_PHY_CONFIG_GTRX_RESET_MASK 0x00000002 | +
+Hold GTRXRESET in reset. +
| #define XDPRX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x00000000 | +
+Release reset. +
| #define XDPRX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK 0x01000000 | +
+Issue reset at every link rate change. +
| #define XDPRX_PHY_CONFIG_RESET_AT_TP1_START_MASK 0x02000000 | +
+Issue reset at start of training pattern 1. +
| #define XDPRX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK 0x00800000 | +
+Issue reset at every training iteration. +
| #define XDPRX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK 0x00000400 | +
+Hold RX_PHY_BUF reset. +
| #define XDPRX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK 0x00400000 | +
+Set RX_PHY_CDRHOLD. +
| #define XDPRX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK 0x00000800 | +
+Hold RX_PHY_DFE_LPM reset. +
| #define XDPRX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK 0x00010000 | +
+Set RX_PHY_EYESCANRESET. +
| #define XDPRX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK 0x00020000 | +
+Set RX_PHY_ EYESCANTRIGGER. +
| #define XDPRX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK 0x0000E000 | +
+Set RX_PHY_LOOPBACK. +
| #define XDPRX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK 0x00000200 | +
+Hold RX_PHY_PCS reset. +
| #define XDPRX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK 0x00000100 | +
+Hold RX_PHY_PMA reset. +
| #define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK 0x08000000 | +
+Configure RX_PHY_POLARITY for lane 0. +
| #define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK 0x10000000 | +
+Configure RX_PHY_POLARITY for lane 1. +
| #define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK 0x20000000 | +
+Configure RX_PHY_POLARITY for lane 2. +
| #define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK 0x40000000 | +
+Configure RX_PHY_POLARITY for lane 3. +
| #define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_MASK 0x00001000 | +
+Set RX_PHY_POLARITY. +
| #define XDPRX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK 0x00040000 | +
+Set RX_PHY_PRBSCNTRESET. +
| #define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK 0x00080000 | +
+Set RX_PHY_RXLPMHFHOLD. +
| #define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK 0x00200000 | +
+Set RX_PHY_ RXLPMHFOVERDEN. +
| #define XDPRX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK 0x00100000 | +
+Set RX_PHY_RXLPMLFHOLD. +
| #define XDPRX_PHY_POWER_DOWN 0x210 | +
+Control PHY power down. +
| #define XDPRX_PHY_POWER_DOWN_LANE_0_MASK 0x1 | +
+Power down the PHY for lane 0. +
| #define XDPRX_PHY_POWER_DOWN_LANE_1_MASK 0x2 | +
+Power down the PHY for lane 1. +
| #define XDPRX_PHY_POWER_DOWN_LANE_2_MASK 0x4 | +
+Power down the PHY for lane 2. +
| #define XDPRX_PHY_POWER_DOWN_LANE_3_MASK 0x8 | +
+Power down the PHY for lane 3. +
| #define XDPRX_PHY_STATUS 0x208 | +
+Current PHY status. +
| #define XDPRX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F | +
+All lanes are ready. +
| #define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK 0x00010000 | +
+Lane aligment status for lane 0. +
| #define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK 0x00020000 | +
+Lane aligment status for lane 1. +
| #define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK 0x00040000 | +
+Lane aligment status for lane 2. +
| #define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK 0x00080000 | +
+Lane aligment status for lane 3. +
| #define XDPRX_PHY_STATUS_LANES_0_1_READY_MASK 0x00000013 | +
+Lanes 0 and 1 are ready. +
| #define XDPRX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 | +
+FPGA fabric clock PLL locked. +
| #define XDPRX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 | +
+PLL locked for lanes 0 and 1. +
| #define XDPRX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 | +
+PLL locked for lanes 2 and 3. +
| #define XDPRX_PHY_STATUS_PRBSERR_LANE_0_MASK 0x00000100 | +
+PRBS error on lane 0. +
| #define XDPRX_PHY_STATUS_PRBSERR_LANE_1_MASK 0x00000200 | +
+PRBS error on lane 1. +
| #define XDPRX_PHY_STATUS_PRBSERR_LANE_2_MASK 0x00000400 | +
+PRBS error on lane 2. +
| #define XDPRX_PHY_STATUS_PRBSERR_LANE_3_MASK 0x00000800 | +
+PRBS error on lane 3. +
| #define XDPRX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 | +
+Reset done for lanes 0 and 1. +
| #define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C | +
+Reset done for lanes 2 and 3. +
| #define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 | +
+Shift bits for reset done for lanes 2 and 3. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT 26 | +
+Shift bits for RX buffer status lane 1. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK 0x03000000 | +
+RX buffer status lane 0. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT 24 | +
+Shift bits for RX buffer status lane 0. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK 0x0C000000 | +
+RX buffer status lane 1. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK 0x30000000 | +
+RX buffer status lane 2. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT 28 | +
+Shift bits for RX buffer status lane 2. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK 0xC0000000 | +
+RX buffer status lane 3. +
| #define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT 30 | +
+Shift bits for RX buffer status lane 3. +
| #define XDPRX_PHY_STATUS_RX_CLK_LOCK_MASK 0x00000080 | +
+Receiver clock locked. +
| #define XDPRX_PHY_STATUS_RX_VLOW_LANE_0_MASK 0x00001000 | +
+RX voltage low on lane 0. +
| #define XDPRX_PHY_STATUS_RX_VLOW_LANE_1_MASK 0x00002000 | +
+RX voltage low on lane 1. +
| #define XDPRX_PHY_STATUS_RX_VLOW_LANE_2_MASK 0x00004000 | +
+RX voltage low on lane 2. +
| #define XDPRX_PHY_STATUS_RX_VLOW_LANE_3_MASK 0x00008000 | +
+RX voltage low on lane 3. +
| #define XDPRX_PHY_STATUS_SYM_LOCK_LANE_0_MASK 0x00100000 | +
+Symbol lock status for lane 0. +
| #define XDPRX_PHY_STATUS_SYM_LOCK_LANE_1_MASK 0x00200000 | +
+Symbol lock status for lane 1. +
| #define XDPRX_PHY_STATUS_SYM_LOCK_LANE_2_MASK 0x00400000 | +
+Symbol lock status for lane 2. +
| #define XDPRX_PHY_STATUS_SYM_LOCK_LANE_3_MASK 0x00800000 | +
+Symbol lock status for lane 3. +
| #define XDprx_ReadReg | +( | +BaseAddress, | |||
| + | + | RegOffset | ++ | ) | +XDprx_In32((BaseAddress) + (RegOffset)) | +
+This is a low-level function that reads from the specified register.
+
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to be read from. |
| #define XDPRX_REMOTE_CMD 0x08C | +
+Used for passing remote information to the DisplayPort TX. +
| #define XDPRX_REQ_ADDRESS 0x038 | +
+Contains the address field of the most recent AUX request. +
| #define XDPRX_REQ_CLK_WIDTH 0x030 | +
+Holds the half period of the recovered AUX clock. +
| #define XDPRX_REQ_CMD 0x034 | +
+Provides the most recent AUX command received. +
| #define XDPRX_REQ_COUNT 0x028 | +
+Provides a running total of the number of AUX requests received. +
| #define XDPRX_REQ_ERROR_COUNT 0x024 | +
+Provides a running total of errors detected on inbound AUX channel requests. +
| #define XDPRX_REQ_LENGTH 0x03C | +
+Contains length of the most recent AUX request. +
| #define XDPRX_RX_AUDIO_CONTROL 0x300 | +
+Enables audio stream packets in main link. +
| #define XDPRX_RX_AUDIO_EXT_DATA | +( | +NUM | ++ | ) | +(0x330 + 4 * (NUM - 1)) | +
+Word formatted as per extension packet. +
| #define XDPRX_RX_AUDIO_INFO_DATA | +( | +NUM | ++ | ) | +(0x304 + 4 * (NUM - 1)) | +
+Word formatted as per CEA 861-C info frame. +
| #define XDPRX_RX_AUDIO_MAUD 0x324 | +
+M value of audio stream as decoded from audio time stamp packet. +
| #define XDPRX_RX_AUDIO_NAUD 0x328 | +
+N value of audio stream as decoded from audio time stamp packet. +
| #define XDPRX_RX_AUDIO_STATUS 0x32C | +
+Status of audio stream. +
| #define XDPRX_SINK_COUNT 0x0D4 | +
+The sink device count. +
| #define XDPRX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 | +
+User access to the sink specific field as exposed in the RX DPCD (0xFF bytes). +
| #define XDPRX_SINK_DEVICE_SPECIFIC_FIELD_REG | +( | +RegNum | ++ | ) | +(XDPRX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) | +
+ +
| #define XDPRX_SOFT_RESET 0x01C | +
+Software reset. +
| #define XDPRX_SOFT_RESET_AUX_MASK 0x80 | +
+Reset the AUX logic. +
| #define XDPRX_SOFT_RESET_VIDEO_MASK 0x01 | +
+Reset the video logic. +
| #define XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 | +
+User access to the source specific field as exposed in the RX DPCD (0xFF bytes). +
| #define XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD_REG | +( | +RegNum | ++ | ) | +(XDPRX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) | +
+ +
| #define XDPRX_STREAM1_MSA_START 0x500 | +
+Start of the MSA registers for stream 1. +
| #define XDPRX_STREAM2_MSA_START 0x540 | +
+Start of the MSA registers for stream 2. +
| #define XDPRX_STREAM2_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. +| #define XDPRX_STREAM3_MSA_START 0x580 | +
+Start of the MSA registers for stream 3. +
| #define XDPRX_STREAM3_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. +| #define XDPRX_STREAM4_MSA_START 0x5C0 | +
+Start of the MSA registers for stream 4. +
| #define XDPRX_STREAM4_MSA_START_OFFSET | +
+Value:
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. +| #define XDPRX_USER_FIFO_OVERFLOW 0x110 | +
+Indicates an overflow in user FIFO. +
| #define XDPRX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream) | +
+Indicates that the internal FIFO has detected on overflow condition for the specified stream. +
| #define XDPRX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream << 8) | +
+Indicates that the video timing FIFO has overflown for the specified stream. +
| #define XDPRX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream << 4) | +
+Indicates that the video unpack FIFO has overflown for the specified stream. +
| #define XDPRX_USER_PIXEL_WIDTH 0x010 | +
+Selects the width of the user data input port. +
| #define XDPRX_USER_PIXEL_WIDTH_1 0x1 | +
+Single pixel wide interface. +
| #define XDPRX_USER_PIXEL_WIDTH_2 0x2 | +
+Dual pixel output mode. +
| #define XDPRX_USER_PIXEL_WIDTH_4 0x4 | +
+Quad pixel output mode. +
| #define XDPRX_USER_VSYNC_STATE 0x114 | +
+Provides a mechanism for the host processor to monitor the state of the video data path. +
| #define XDPRX_USER_VSYNC_STATE_STREAMX_MASK | +( | +Stream | ++ | ) | +(Stream) | +
+The state of the vertical sync pulse for the specified stream. +
| #define XDPRX_VC_PAYLOAD_TABLE 0x800 | +
+Virtual channel payload table (0xFF bytes). +
| #define XDPRX_VC_PAYLOAD_TABLE_ID_SLOT | +( | +SlotNum | ++ | ) | +(XDPRX_VC_PAYLOAD_TABLE + SlotNum) | +
+ +
| #define XDPRX_VERSION 0x0F8 | +
+Version and revision of the DisplayPort core. +
| #define XDPRX_VERSION_CORE_PATCH_MASK 0x00000030 | +
+Core patch details. +
| #define XDPRX_VERSION_CORE_PATCH_SHIFT 8 | +
+Shift bits for core patch details. +
| #define XDPRX_VERSION_CORE_VER_MJR_MASK 0x0000F000 | +
+Core major version. +
| #define XDPRX_VERSION_CORE_VER_MJR_SHIFT 24 | +
+Shift bits for core major version. +
| #define XDPRX_VERSION_CORE_VER_MNR_MASK 0x00000F00 | +
+Core minor version. +
| #define XDPRX_VERSION_CORE_VER_MNR_SHIFT 16 | +
+Shift bits for core minor version. +
| #define XDPRX_VERSION_CORE_VER_REV_MASK 0x000000C0 | +
+Core version revision. +
| #define XDPRX_VERSION_CORE_VER_REV_SHIFT 12 | +
+Shift bits for core version revision. +
| #define XDPRX_VERSION_INTER_REV_MASK 0x0000000F | +
+Internal revision. +
| #define XDPRX_VIDEO_UNSUPPORTED 0x094 | +
+DPCD register bit to inform the DisplayPort TX that video data is not supported. +
| #define XDprx_WriteReg | +( | +BaseAddress, | |||
| + | + | RegOffset, | |||
| + | + | Data | ++ | ) | +XDprx_Out32((BaseAddress) + (RegOffset), (Data)) | +
+This is a low-level function that writes to the specified register.
+
| BaseAddress | is the base address of the device. | |
| RegOffset | is the register offset to write to. | |
| Data | is the 32-bit data to write to the specified register. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__intr_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__intr_8c.html new file mode 100644 index 00000000..81637672 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__intr_8c.html @@ -0,0 +1,708 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/14 Initial release. ++
+#include "xdprx.h"
+
Functions | |
| void | XDprx_InterruptHandler (XDprx *InstancePtr) |
| void | XDprx_GenerateHpdInterrupt (XDprx *InstancePtr, u16 DurationUs) |
| void | XDprx_InterruptEnable (XDprx *InstancePtr, u32 Mask) |
| void | XDprx_InterruptDisable (XDprx *InstancePtr, u32 Mask) |
| void | XDprx_SetIntrVmChangeHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrPowerStateHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrNoVideoHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrVBlankHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTrainingLostHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrVideoHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTrainingDoneHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrBwChangeHandler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp1Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp2Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void | XDprx_SetIntrTp3Handler (XDprx *InstancePtr, XDprx_IntrHandler CallbackFunc, void *CallbackRef) |
| void XDprx_GenerateHpdInterrupt | +( | +XDprx * | +InstancePtr, | +|
| + | + | u16 | +DurationUs | + |
| + | ) | ++ |
+This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| DurationUs | is the duration of the HPD pulse, in microseconds. |
| void XDprx_InterruptDisable | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function disables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| Mask | specifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts. |
| void XDprx_InterruptEnable | +( | +XDprx * | +InstancePtr, | +|
| + | + | u32 | +Mask | + |
| + | ) | ++ |
+This function enables interrupts associated with the specified mask.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| Mask | specifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts. |
| void XDprx_InterruptHandler | +( | +XDprx * | +InstancePtr | +) | ++ |
| void XDprx_SetIntrBwChangeHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a bandwidth change interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrNoVideoHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a no video interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrPowerStateHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when the power state interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp1Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 1 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp2Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 2 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTp3Handler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training pattern 3 interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTrainingDoneHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training done interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrTrainingLostHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a training lost interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVBlankHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a vertical blanking interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVideoHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a valid video interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
| void XDprx_SetIntrVmChangeHandler | +( | +XDprx * | +InstancePtr, | +|
| + | + | XDprx_IntrHandler | +CallbackFunc, | +|
| + | + | void * | +CallbackRef | + |
| + | ) | ++ |
+This function installs a callback function for when a video mode change interrupt occurs.
+
| InstancePtr | is a pointer to the XDprx instance. | |
| CallbackFunc | is the address to the callback function. | |
| CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__selftest_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__selftest_8c.html new file mode 100644 index 00000000..45689b12 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdprx__selftest_8c.html @@ -0,0 +1,92 @@ + +
+ ++
+ MODIFICATION HISTORY:
+
Ver Who Date Changes + ----- ---- -------- ----------------------------------------------- + 1.0 als 01/20/15 Initial release. ++
+#include "xdprx.h"
+#include "xstatus.h"
+
Functions | |
| u32 | XDprx_SelfTest (XDprx *InstancePtr) |
Variables | |
| u32 | ResetValues [46][2] |
| u32 XDprx_SelfTest | +( | +XDprx * | +InstancePtr | +) | ++ |
+This function runs a self-test on the XDprx driver/device. The sanity test checks whether or not all tested registers hold their default reset values.
+
| InstancePtr | is a pointer to the XDprx instance. |
+
| u32 ResetValues[46][2] | +
+This table contains the default values for the DisplayPort TX core's general usage registers. +
+Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx_8c.html
index fdda4745..7ae1b14d 100755
--- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx_8c.html
+++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx_8c.html
@@ -68,9 +68,9 @@ Contains a minimal set of functions for the Functions
-u32 XDptx_InitializeTx (XDptx *InstancePtr) void XDptx_CfgInitialize (XDptx *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) void XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr) u32 XDptx_InitializeTx (XDptx *InstancePtr) u32 XDptx_GetRxCapabilities (XDptx *InstancePtr)
| - | XDptx_Config * | +XDp_Config * | ConfigPtr, | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| - | XDptx_TimerHandler | +XDp_TimerHandler | CallbackFunc, | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| InstancePtr | is a pointer to the XDptx instance. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Classes | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| struct | XDptx_Config | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| struct | XDptx_SinkConfig | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| struct | XDptx_LinkConfig | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| struct | XDptx | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Typedefs | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| typedef void(*) | XDptx_TimerHandler (void *InstancePtr, u32 MicroSeconds) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| typedef void(*) | XDptx_HpdEventHandler (void *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| typedef void(*) | XDptx_HpdPulseHandler (void *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Functions | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | XDptx_InitializeTx (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgInitialize (XDptx *InstancePtr, XDp_Config *ConfigPtr, u32 EffectiveAddr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgInitialize (XDptx *InstancePtr, XDptx_Config *ConfigPtr, u32 EffectiveAddr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | XDptx_InitializeTx (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | XDptx_GetRxCapabilities (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_ResetPhy (XDptx *InstancePtr, u32 Reset) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_SetUserTimerHandler (XDptx *InstancePtr, XDptx_TimerHandler CallbackFunc, void *CallbackRef) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_WaitUs (XDptx *InstancePtr, u32 MicroSeconds) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgMsaRecalculate (XDptx *InstancePtr, u8 Stream) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVid_VideoMode VideoMode) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgMsaUseStandardVideoMode (XDptx *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_CfgMsaUseEdidPreferredTiming (XDptx *InstancePtr, u8 Stream, u8 *Edid) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_SetMsaValues (XDptx *InstancePtr, u8 Stream) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_HpdInterruptHandler (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_HpdInterruptHandler (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| u32 | XDptx_SelfTest (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| XDptx_Config * | XDptx_LookupConfig (u16 DeviceId) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_MstCfgModeEnable (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| void | XDptx_MstCfgModeDisable (XDptx *InstancePtr) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| typedef void(*) XDptx_TimerHandler(void *InstancePtr, u32 MicroSeconds) | -
-Callback type which represents a custom timer wait handler. This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.
-
| InstancePtr | is a pointer to the XDptx instance. | |
| MicroSeconds | is the number of microseconds to be passed to the timer function. |
| - | XDptx_Config * | +XDp_Config * | ConfigPtr, | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| - | XVid_VideoMode | +XVidC_VideoMode | VideoMode | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| XDptx_Config* XDptx_LookupConfig | -( | -u16 | -DeviceId | -) | -- |
-This function looks for the device configuration based on the unique device ID. The table XDptx_ConfigTable[] contains the configuration information for each device in the system.
-
| DeviceId | is the unique device ID of the device being looked up. |
@@ -3616,7 +3543,7 @@ This function will map a stream to a downstream DisplayPort TX device determined
| - | XDptx_TimerHandler | +XDp_TimerHandler | CallbackFunc, | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| InstancePtr | is a pointer to the XDptx instance. | |||||
DPTX core registers: Link configuration field. | ||||||
| #define | XDPTX_TX_AUDIO_CHANNELS 0x0304 | |||||
| #define | XDPTX_TX_AUDIO_INFO_DATA 0x0308 | |||||
| #define | XDPTX_TX_AUDIO_INFO_DATA(NUM) (0x0308 + 4 * (NUM - 1)) | |||||
| #define | XDPTX_TX_AUDIO_MAUD 0x0328 | |||||
| #define | XDPTX_TX_AUDIO_NAUD 0x032C | |||||
| #define | XDPTX_TX_AUDIO_EXT_DATA 0x0330 | |||||
| #define | XDPTX_TX_AUDIO_EXT_DATA(NUM) (0x0330 + 4 * (NUM - 1)) | |||||
DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. | ||||||
| #define | XDPTX_STREAM2_MSA_START 0x0500 | |||||
| #define | XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 | |||||
| #define | XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x0000000F | |||||
| #define | XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF | |||||
| #define | XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0x00000F00 | |||||
| #define | XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 | |||||
| #define | XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 | |||||
| #define | XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C | |||||
| #define | XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 | |||||
| #define | XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 | |||||
| #define | XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 | |||||
| #define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0x00000F00 | +#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
| #define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x0000000F | +#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
-DisplayPort revision. +DisplayPort protocol version and revision.
@@ -8843,7 +8844,7 @@ Set TX_PHY_LOOPBACK.
-HOLD TX_PHY_PCS reset. +Hold TX_PHY_PCS reset.
@@ -9131,6 +9132,21 @@ Reset done for lanes 0 and 1. Reset done for lanes 2 and 3.
| #define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 | +
+Shift bits for reset done for lanes 2 and 3. +
| #define XDPTX_TX_AUDIO_EXT_DATA 0x0330 | +#define XDPTX_TX_AUDIO_EXT_DATA | +( | +NUM | ++ | ) | +(0x0330 + 4 * (NUM - 1)) |
| #define XDPTX_TX_AUDIO_INFO_DATA 0x0308 | +#define XDPTX_TX_AUDIO_INFO_DATA | +( | +NUM | ++ | ) | +(0x0308 + 4 * (NUM - 1)) |
-Core version. +Version and revision of the DisplayPort core.
diff --git a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx__intr_8c.html b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx__intr_8c.html index 32ce977a..c21bcc5d 100755 --- a/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx__intr_8c.html +++ b/XilinxProcessorIPLib/drivers/dp/doc/html/api/xdptx__intr_8c.html @@ -37,12 +37,12 @@ This file contains functions related to
Functions | |
| void | XDptx_HpdInterruptHandler (XDptx *InstancePtr) |
| void | XDptx_SetHpdEventHandler (XDptx *InstancePtr, XDptx_HpdEventHandler CallbackFunc, void *CallbackRef) |
| void | XDptx_SetHpdPulseHandler (XDptx *InstancePtr, XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef) |
| void | XDptx_HpdInterruptHandler (XDptx *InstancePtr) |
This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->MsaConfig. If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are: