From 99a46157ebd7dd767795b5de544f8afc8aa25757 Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Wed, 10 Jun 2015 17:27:22 +0530 Subject: [PATCH] bsp: a53: added support for 64bit addressing mode This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange and Xil_ICacheInvalidateRange API to add support for addresses higher than 4GB by not truncating the addresses to 32bit Signed-off-by: Kinjal Pravinbhai Patel --- .../src/cortexa53/64bit/xil_cache.c | 24 +++++++++---------- .../src/cortexa53/64bit/xil_cache.h | 6 ++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.c b/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.c index d5450c2b..55a761c7 100644 --- a/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.c +++ b/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.c @@ -265,12 +265,12 @@ void Xil_DCacheInvalidateLine(INTPTR adr) * @note None. * ****************************************************************************/ -void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len) { const u32 cacheline = 64U; - u32 end; - u32 tempadr = adr; - u32 tempend; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -456,12 +456,12 @@ void Xil_DCacheFlushLine(INTPTR adr) * ****************************************************************************/ -void Xil_DCacheFlushRange(INTPTR adr, u32 len) +void Xil_DCacheFlushRange(INTPTR adr, INTPTR len) { const u32 cacheline = 64U; - u32 end; - u32 tempadr = adr; - u32 tempend; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); @@ -618,12 +618,12 @@ void Xil_ICacheInvalidateLine(INTPTR adr) * @note None. * ****************************************************************************/ -void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len) { const u32 cacheline = 64U; - u32 end; - u32 tempadr = adr; - u32 tempend; + INTPTR end; + INTPTR tempadr = adr; + INTPTR tempend; u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); diff --git a/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.h b/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.h index 94013329..744263c3 100644 --- a/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.h +++ b/lib/bsp/standalone/src/cortexa53/64bit/xil_cache.h @@ -57,16 +57,16 @@ extern "C" { void Xil_DCacheEnable(void); void Xil_DCacheDisable(void); void Xil_DCacheInvalidate(void); -void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len); void Xil_DCacheInvalidateLine(INTPTR adr); void Xil_DCacheFlush(void); -void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheFlushRange(INTPTR adr, INTPTR len); void Xil_DCacheFlushLine(INTPTR adr); void Xil_ICacheEnable(void); void Xil_ICacheDisable(void); void Xil_ICacheInvalidate(void); -void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len); void Xil_ICacheInvalidateLine(INTPTR adr); #ifdef __cplusplus }