diff --git a/lib/bsp/standalone/src/cortexr5/mpu.c b/lib/bsp/standalone/src/cortexr5/mpu.c
index 15423989..ee18b2da 100644
--- a/lib/bsp/standalone/src/cortexr5/mpu.c
+++ b/lib/bsp/standalone/src/cortexr5/mpu.c
@@ -54,6 +54,7 @@
 #include "xreg_cortexr5.h"
 #include "xil_mpu.h"
 #include "xpseudo_asm.h"
+#include "xparameters.h"
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
@@ -63,6 +64,40 @@
 
 /************************** Variable Definitions *****************************/
 
+static const struct {
+	u64 size;
+	unsigned int encoding;
+}region_size[] = {
+	{ 0x20, REGION_32B },
+	{ 0x40, REGION_64B },
+	{ 0x80, REGION_128B },
+	{ 0x100, REGION_256B },
+	{ 0x200, REGION_512B },
+	{ 0x400, REGION_1K },
+	{ 0x800, REGION_2K },
+	{ 0x1000, REGION_4K },
+	{ 0x2000, REGION_8K },
+	{ 0x4000, REGION_16K },
+	{ 0x8000, REGION_32K },
+	{ 0x10000, REGION_64K },
+	{ 0x20000, REGION_128K },
+	{ 0x40000, REGION_256K },
+	{ 0x80000, REGION_512K },
+	{ 0x100000, REGION_1M },
+	{ 0x200000, REGION_2M },
+	{ 0x400000, REGION_4M },
+	{ 0x800000, REGION_8M },
+	{ 0x1000000, REGION_16M },
+	{ 0x2000000, REGION_32M },
+	{ 0x4000000, REGION_64M },
+	{ 0x8000000, REGION_128M },
+	{ 0x10000000, REGION_256M },
+	{ 0x20000000, REGION_512M },
+	{ 0x40000000, REGION_1G },
+	{ 0x80000000, REGION_2G },
+	{ 0x100000000, REGION_4G },
+};
+
 /************************** Function Prototypes ******************************/
 void Init_MPU(void);
 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
@@ -86,12 +121,26 @@ void Init_MPU(void)
 	u32 Addr;
 	u32 RegSize;
 	u32 Attrib;
-	u32 RegNum = 0;
+	u32 RegNum = 0, i;
+	u64 size;
 
 	Xil_DisableMPURegions();
 
 	Addr = 0x00000000U;
-	RegSize = REGION_2G;
+#ifdef	XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
+	/* If the DDR is present, configure region as per DDR size */
+	size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
+	/* Lookup the size.  */
+	for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+		if (size <= region_size[i].size) {
+			RegSize = region_size[i].encoding;
+			break;
+		}
+	}
+#else
+	/* For DDRless system, configure region for TCM */
+	RegSize = REGION_256K;
+#endif
 	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
 	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
 	RegNum++;