diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c index 5df69d2d..48109514 100644 --- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c +++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps.c @@ -339,6 +339,9 @@ void XEmacPs_Reset(XEmacPs *InstancePtr) if (InstancePtr->Version > 2) { XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | +#ifdef __aarch64__ + (u32)XEMACPS_DMACR_ADDR_WIDTH_64 | +#endif (u32)XEMACPS_DMACR_INCR4_AHB_BURST)); } #if EXTENDED_DESC_MODE diff --git a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h index a35ed337..76ba0c93 100644 --- a/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h +++ b/XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h @@ -386,6 +386,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, /** @name DMA control register bit definitions * @{ */ +#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ #define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ #define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ #define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer