From a36b777a401ff93d6a467797a2a986ccc1add3c1 Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Mon, 26 Jan 2015 12:35:31 -0800 Subject: [PATCH] dp: tx: When downshifting during link training, always issue training pattern 0. For compliance purposes, training pattern 0 needs to be sent between downshifting of lane count and link rates. Signed-off-by: Andrei-Liviu Simion --- XilinxProcessorIPLib/drivers/dp/src/xdp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdp.c b/XilinxProcessorIPLib/drivers/dp/src/xdp.c index a9d13540..184209f9 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdp.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdp.c @@ -1964,6 +1964,14 @@ static u32 XDp_TxRunTraining(XDp *InstancePtr) (TrainingState == XDP_TX_TS_ADJUST_LINK_RATE))) { return XST_FAILURE; } + if ((TrainingState == XDP_TX_TS_ADJUST_LINK_RATE) || + (TrainingState == XDP_TX_TS_ADJUST_LANE_COUNT)) { + Status = XDp_TxSetTrainingPattern(InstancePtr, + XDP_TX_TRAINING_PATTERN_SET_OFF); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } } /* Final status check. */