From a63b398f31c61f7ebf9467fee8f3192f13d242dc Mon Sep 17 00:00:00 2001 From: Andrei-Liviu Simion Date: Wed, 7 Jan 2015 13:51:04 -0800 Subject: [PATCH] dptx: Stream indices now start at 1 rather than 0. Following the naming convention used in the IP product guide and the IP hardware. Signed-off-by: Andrei-Liviu Simion --- .../drivers/dptx/src/xdptx_hw.h | 74 ++++---- .../drivers/dptx/src/xdptx_mst.c | 44 ++--- .../drivers/dptx/src/xdptx_selftest.c | 10 +- .../drivers/dptx/src/xdptx_spm.c | 168 +++++++++--------- 4 files changed, 149 insertions(+), 147 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h index 1081e922..ae3d8b98 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h @@ -144,11 +144,11 @@ in microseconds. */ /* @} */ -/** @name DPTX core registers: Main stream attributes for SST / MST STREAM0. +/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1. * @{ */ -#define XDPTX_STREAM0_MSA_START 0x0180 /**< Start of the MSA registers - for stream 0. */ +#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers + for stream 1. */ #define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in the horizontal framing period. */ @@ -212,16 +212,16 @@ logic, allowing enough data to be buffered in the input FIFO. */ -#define XDPTX_STREAM0 0x01D0 /**< Average stream symbol +#define XDPTX_STREAM1 0x01D0 /**< Average stream symbol timeslots per MTP config. */ -#define XDPTX_STREAM1 0x01D4 /**< Average stream symbol +#define XDPTX_STREAM2 0x01D4 /**< Average stream symbol timeslots per MTP config. */ -#define XDPTX_STREAM2 0x01D8 /**< Average stream symbol +#define XDPTX_STREAM3 0x01D8 /**< Average stream symbol timeslots per MTP config. */ -#define XDPTX_STREAM3 0x01DC /**< Average stream symbol +#define XDPTX_STREAM4 0x01DC /**< Average stream symbol timeslots per MTP config. */ /* @} */ @@ -297,33 +297,33 @@ extension packet. */ /* @} */ -/** @name DPTX core registers: Main stream attributes for MST STREAM1, 2, and 3. +/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. * @{ */ -#define XDPTX_STREAM1_MSA_START 0x0500 /**< Start of the MSA registers - for stream 1. */ -#define XDPTX_STREAM1_MSA_START_OFFSET (XDPTX_STREAM1_MSA_START - \ - XDPTX_STREAM0_MSA_START) /**< The MSA registers for - stream 1 are at an - offset from the - corresponding registers - of stream 0. */ -#define XDPTX_STREAM2_MSA_START 0x0550 /**< Start of the MSA registers +#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers for stream 2. */ #define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \ - XDPTX_STREAM0_MSA_START) /**< The MSA registers for + XDPTX_STREAM1_MSA_START) /**< The MSA registers for stream 2 are at an offset from the corresponding registers - of stream 0. */ -#define XDPTX_STREAM3_MSA_START 0x05A0 /**< Start of the MSA registers + of stream 1. */ +#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers for stream 3. */ #define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \ - XDPTX_STREAM0_MSA_START) /**< The MSA registers for + XDPTX_STREAM1_MSA_START) /**< The MSA registers for stream 3 are at an offset from the corresponding registers - of stream 0. */ + of stream 1. */ +#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers + for stream 4. */ +#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \ + XDPTX_STREAM1_MSA_START) /**< The MSA registers for + stream 4 are at an + offset from the + corresponding registers + of stream 1. */ /* @} */ #define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload @@ -365,13 +365,13 @@ 0x3 /**< Pseudo random bit sequence 7 transmitted. */ /* 0x01C: SOFTWARE_RESET */ -#define XDPTX_SOFT_RESET_VIDEO_STREAM0_MASK \ - 0x00000001 /**< Reset video logic. */ #define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK \ - 0x00000002 /**< Reset video logic. */ + 0x00000001 /**< Reset video logic. */ #define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK \ - 0x00000004 /**< Reset video logic. */ + 0x00000002 /**< Reset video logic. */ #define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK \ + 0x00000004 /**< Reset video logic. */ +#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK \ 0x00000008 /**< Reset video logic. */ #define XDPTX_SOFT_RESET_AUX_MASK \ 0x00000080 /**< Reset AUX logic. */ @@ -618,23 +618,23 @@ attribute. */ /* 0x200: PHY_CONFIG */ #define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \ - 0x0010000 /**< Release reset. */ + 0x0000000 /**< Release reset. */ #define XDPTX_PHY_CONFIG_PHY_RESET_MASK \ - 0x0010001 /**< Hold the PHY in reset. */ + 0x0000001 /**< Hold the PHY in reset. */ #define XDPTX_PHY_CONFIG_GTTX_RESET_MASK \ - 0x0010002 /**< Hold GTTXRESET in reset. */ + 0x0000002 /**< Hold GTTXRESET in reset. */ #define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \ - 0x0010100 /**< Hold TX_PHY_PMA reset. */ + 0x0000100 /**< Hold TX_PHY_PMA reset. */ #define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \ - 0x0010200 /**< HOLD TX_PHY_PCS reset. */ + 0x0000200 /**< HOLD TX_PHY_PCS reset. */ #define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \ - 0x0010400 /**< Set TX_PHY_POLARITY. */ + 0x0000400 /**< Set TX_PHY_POLARITY. */ #define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \ - 0x0011000 /**< Set TX_PHY_PRBSFORCEERR. */ + 0x0001000 /**< Set TX_PHY_PRBSFORCEERR. */ #define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK \ - 0x001E000 /**< Set TX_PHY_LOOPBACK. */ + 0x000E000 /**< Set TX_PHY_LOOPBACK. */ #define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK \ - 0x0010003 /**< Rest GT and PHY. */ + 0x0000003 /**< Rest GT and PHY. */ /* 0x234: PHY_CLOCK_SELECT */ #define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 /**< 1.62 Gbps link. */ #define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 /**< 2.70 Gbps link. */ @@ -709,6 +709,8 @@ #define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT \ 30 /**< Shift bits for TX error on lane 3. */ +#define XDPTX_PHY_STATUS_LANES_0_1_READY_MASK \ + 0x00000013 /**< Lanes 0 and 1 are ready. */ #define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK \ 0x0000003F /**< All lanes are ready. */ /* 0x2A0: XDPTX_GT_DRP_COMMAND */ @@ -1231,10 +1233,10 @@ /** @name Stream identification. * @{ */ -#define XDPTX_STREAM_ID0 0 #define XDPTX_STREAM_ID1 1 #define XDPTX_STREAM_ID2 2 #define XDPTX_STREAM_ID3 3 +#define XDPTX_STREAM_ID4 4 /* @} */ /** @name Sideband message codes when the driver is in MST mode. diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c index f5c4f9df..ba582db3 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_mst.c @@ -415,11 +415,11 @@ u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertNonvoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - return InstancePtr->MstStreamConfig[Stream].MstStreamEnable; + return InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable; } /******************************************************************************/ @@ -439,11 +439,11 @@ void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 1; + InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 1; } /******************************************************************************/ @@ -463,11 +463,11 @@ void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - InstancePtr->MstStreamConfig[Stream].MstStreamEnable = 0; + InstancePtr->MstStreamConfig[Stream - 1].MstStreamEnable = 0; } /******************************************************************************/ @@ -498,11 +498,11 @@ void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8 /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - MstStream = &InstancePtr->MstStreamConfig[Stream]; + MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; Topology = &InstancePtr->Topology; MstStream->LinkCountTotal = Topology->SinkList[SinkNum]->LinkCountTotal; @@ -539,13 +539,13 @@ void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Xil_AssertVoid(LinkCountTotal > 0); Xil_AssertVoid(RelativeAddress != NULL); - MstStream = &InstancePtr->MstStreamConfig[Stream]; + MstStream = &InstancePtr->MstStreamConfig[Stream - 1]; MstStream->LinkCountTotal = LinkCountTotal; for (Index = 0; Index < MstStream->LinkCountTotal - 1; Index++) { @@ -1224,7 +1224,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; MsaConfig = &InstancePtr->MsaConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) { + if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { Status = XDptx_AllocatePayloadVcIdTable(InstancePtr, StreamIndex + 1, MsaConfig->TransferUnitSize); if (Status != XST_SUCCESS) { @@ -1243,7 +1243,7 @@ u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr) for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) { MstStream = &InstancePtr->MstStreamConfig[StreamIndex]; - if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex)) { + if (XDptx_MstStreamIsEnabled(InstancePtr, StreamIndex + 1)) { Status = XDptx_SendSbMsgAllocatePayload(InstancePtr, MstStream->LinkCountTotal, MstStream->RelativeAddress, StreamIndex + 1, diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c index 61a1bcf3..c28a7cf6 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c @@ -87,10 +87,10 @@ u32 ResetValues[53][2] = {XDPTX_INTERRUPT_MASK, 0x3F}, {XDPTX_REPLY_DATA_COUNT, 0}, {XDPTX_REPLY_STATUS, 0x10}, - {XDPTX_STREAM0, 0}, {XDPTX_STREAM1, 0}, {XDPTX_STREAM2, 0}, {XDPTX_STREAM3, 0}, + {XDPTX_STREAM4, 0}, {XDPTX_PHY_CONFIG, 0x03}, {XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0}, {XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0}, @@ -188,14 +188,14 @@ u32 XDptx_SelfTest(XDptx *InstancePtr) StreamOffset = 0; } else if (StreamIndex == 1) { - StreamOffset = XDPTX_STREAM1_MSA_START_OFFSET; - } - else if (StreamIndex == 2) { StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET; } - else if (StreamIndex == 3) { + else if (StreamIndex == 2) { StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET; } + else if (StreamIndex == 3) { + StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET; + } for (Index = 0; Index < 20; Index++) { Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr, diff --git a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c index ab9b53be..89ea1ff0 100644 --- a/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c +++ b/XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c @@ -111,11 +111,11 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; LinkConfig = &InstancePtr->LinkConfig; /* Verify the rest of the values used. */ @@ -281,11 +281,11 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; /* Configure the MSA values from the display monitor DMT table. */ MsaConfig->Dmt.HResolution = XDptx_DmtModes[VideoMode].HResolution; @@ -332,12 +332,12 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream, u8 *Edid) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Xil_AssertVoid(Edid != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; Ptm = &Edid[XDPTX_EDID_PTM]; /* Configure the MSA values with the PTM information as @@ -441,12 +441,12 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Xil_AssertVoid(MsaConfigCustom != NULL); - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; /* Copy the MSA values from the user configuration structure. */ MsaConfig->Dmt.HResolution = MsaConfigCustom->Dmt.HResolution; @@ -501,14 +501,14 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor) { /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) || (BitsPerColor == 10) || (BitsPerColor == 12) || (BitsPerColor == 16)); - InstancePtr->MsaConfig[Stream].BitsPerColor = BitsPerColor; + InstancePtr->MsaConfig[Stream - 1].BitsPerColor = BitsPerColor; /* Calculate the rest of the MSA values. */ XDptx_CfgMsaRecalculate(InstancePtr, Stream); @@ -535,12 +535,12 @@ void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Xil_AssertVoid((Enable == 0) || (Enable == 1)); - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; MsaConfig->SynchronousClockMode = Enable; @@ -573,9 +573,9 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); XDptx_ClearMsaValues(InstancePtr, Stream); XDptx_SetMsaValues(InstancePtr, Stream); @@ -597,58 +597,58 @@ void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream) void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream) { XDptx_Config *Config; - u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET, - XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET}; + u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, + XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Config = &InstancePtr->Config; XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); - XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM0 + (Stream) * 4, 0); + XDptx_WriteReg(Config->BaseAddr, XDPTX_STREAM1 + (Stream - 1) * 4, 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + - StreamOffset[Stream], 0); + StreamOffset[Stream - 1], 0); } /******************************************************************************/ @@ -669,70 +669,70 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) { XDptx_Config *Config; XDptx_MainStreamAttributes *MsaConfig; - u32 StreamOffset[4] = {0, XDPTX_STREAM1_MSA_START_OFFSET, - XDPTX_STREAM2_MSA_START_OFFSET, XDPTX_STREAM3_MSA_START_OFFSET}; + u32 StreamOffset[4] = {0, XDPTX_STREAM2_MSA_START_OFFSET, + XDPTX_STREAM3_MSA_START_OFFSET, XDPTX_STREAM4_MSA_START_OFFSET}; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Stream == XDPTX_STREAM_ID0) || - (Stream == XDPTX_STREAM_ID1) || (Stream == XDPTX_STREAM_ID2) || - (Stream == XDPTX_STREAM_ID3)); + Xil_AssertVoid((Stream == XDPTX_STREAM_ID1) || + (Stream == XDPTX_STREAM_ID2) || (Stream == XDPTX_STREAM_ID3) || + (Stream == XDPTX_STREAM_ID4)); Config = &InstancePtr->Config; - MsaConfig = &InstancePtr->MsaConfig[Stream]; + MsaConfig = &InstancePtr->MsaConfig[Stream - 1]; /* Set the main stream attributes to the associated DisplayPort TX core * registers. */ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + - StreamOffset[Stream], MsaConfig->HClkTotal); + StreamOffset[Stream - 1], MsaConfig->HClkTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + - StreamOffset[Stream], MsaConfig->VClkTotal); + StreamOffset[Stream - 1], MsaConfig->VClkTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + - StreamOffset[Stream], MsaConfig->Dmt.HSyncPolarity | + StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPolarity | (MsaConfig->Dmt.VSyncPolarity << XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT)); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH + - StreamOffset[Stream], MsaConfig->Dmt.HSyncPulseWidth); + StreamOffset[Stream - 1], MsaConfig->Dmt.HSyncPulseWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH + - StreamOffset[Stream], MsaConfig->Dmt.VSyncPulseWidth); + StreamOffset[Stream - 1], MsaConfig->Dmt.VSyncPulseWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES + - StreamOffset[Stream], MsaConfig->Dmt.HResolution); + StreamOffset[Stream - 1], MsaConfig->Dmt.HResolution); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES + - StreamOffset[Stream], MsaConfig->Dmt.VResolution); + StreamOffset[Stream - 1], MsaConfig->Dmt.VResolution); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART + - StreamOffset[Stream], MsaConfig->HStart); + StreamOffset[Stream - 1], MsaConfig->HStart); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART + - StreamOffset[Stream], MsaConfig->VStart); + StreamOffset[Stream - 1], MsaConfig->VStart); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0 + - StreamOffset[Stream], MsaConfig->Misc0); + StreamOffset[Stream - 1], MsaConfig->Misc0); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1 + - StreamOffset[Stream], MsaConfig->Misc1); + StreamOffset[Stream - 1], MsaConfig->Misc1); XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID + - StreamOffset[Stream], MsaConfig->Dmt.PixelClkKhz); + StreamOffset[Stream - 1], MsaConfig->Dmt.PixelClkKhz); XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID + - StreamOffset[Stream], MsaConfig->NVid); + StreamOffset[Stream - 1], MsaConfig->NVid); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH + - StreamOffset[Stream], MsaConfig->UserPixelWidth); + StreamOffset[Stream - 1], MsaConfig->UserPixelWidth); XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE + - StreamOffset[Stream], MsaConfig->DataPerLane); + StreamOffset[Stream - 1], MsaConfig->DataPerLane); /* Set the transfer unit values to the associated DisplayPort TX core * registers. */ if (InstancePtr->MstEnable == 1) { XDptx_WriteReg(Config->BaseAddr, - XDPTX_STREAM0 + (Stream) * 4, + XDPTX_STREAM1 + (Stream - 1) * 4, ((MsaConfig->AvgBytesPerTU / 1000) << 16) | (MsaConfig->AvgBytesPerTU % 1000)); } XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE + - StreamOffset[Stream], MsaConfig->TransferUnitSize); + StreamOffset[Stream - 1], MsaConfig->TransferUnitSize); XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU + - StreamOffset[Stream], MsaConfig->AvgBytesPerTU / 1000); + StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU / 1000); XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU + - StreamOffset[Stream], MsaConfig->AvgBytesPerTU % 1000); + StreamOffset[Stream - 1], MsaConfig->AvgBytesPerTU % 1000); XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT + - StreamOffset[Stream], MsaConfig->InitWait); + StreamOffset[Stream - 1], MsaConfig->InitWait); } /******************************************************************************/ @@ -756,7 +756,7 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) { XDptx_MainStreamAttributes *MsaConfig = - &InstancePtr->MsaConfig[Stream]; + &InstancePtr->MsaConfig[Stream - 1]; XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig; double PeakPixelBw; u32 LinkBw; @@ -771,18 +771,18 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) LinkBw = (LinkConfig->LaneCount * LinkConfig->LinkRate * 27); /* Calculate the payload bandiwdth number (PBN). */ - InstancePtr->MstStreamConfig[Stream].MstPbn = + InstancePtr->MstStreamConfig[Stream - 1].MstPbn = 1.006 * PeakPixelBw * ((double)64 / 54); /* Ceil - round up if required, avoiding overhead of math.h. */ if ((double)(1.006 * PeakPixelBw * ((double)64 / 54)) > - ((double)InstancePtr->MstStreamConfig[Stream].MstPbn)) { - InstancePtr->MstStreamConfig[Stream].MstPbn++; + ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn)) { + InstancePtr->MstStreamConfig[Stream - 1].MstPbn++; } /* Calculate the average stream symbol time slots per MTP. */ Average_StreamSymbolTimeSlotsPerMTP = (64.0 * PeakPixelBw / LinkBw); MaximumTarget_Average_StreamSymbolTimeSlotsPerMTP = (54.0 * - ((double)InstancePtr->MstStreamConfig[Stream].MstPbn / + ((double)InstancePtr->MstStreamConfig[Stream - 1].MstPbn / LinkBw)); /* The target value to be found needs to follow the condition: @@ -827,7 +827,7 @@ static void XDptx_CalculateTs(XDptx *InstancePtr, u8 Stream, u8 BitsPerPixel) } /* Determine the PBN for the stream. */ - InstancePtr->MstStreamConfig[Stream].MstPbn = + InstancePtr->MstStreamConfig[Stream - 1].MstPbn = MsaConfig->TransferUnitSize * (LinkConfig->LaneCount * LinkConfig->LinkRate / 2); }