diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx.h b/XilinxProcessorIPLib/drivers/dp/src/xdptx.h index a8819b78..463c67ac 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx.h +++ b/XilinxProcessorIPLib/drivers/dp/src/xdptx.h @@ -290,9 +290,6 @@ typedef struct { XVid_VideoTimingMode Vtm; /**< The video timing. */ u32 PixelClockHz; /**< The pixel clock of the stream (in Hz). */ - u32 HClkTotal; /**< Horizontal total time (in - pixels). */ - u32 VClkTotal; /**< Vertical total time (in pixels). */ u32 HStart; /**< Horizontal blank start (in pixels). */ u32 VStart; /**< Vertical blank start (in lines). */ diff --git a/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c b/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c index c193fc08..50f2afc6 100644 --- a/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c +++ b/XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c @@ -163,14 +163,6 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream) MsaConfig->Vtm.Timing.HBackPorch; MsaConfig->VStart = MsaConfig->Vtm.Timing.F0PVSyncWidth + MsaConfig->Vtm.Timing.F0PVBackPorch; - MsaConfig->HClkTotal = (MsaConfig->Vtm.Timing.HSyncWidth + - MsaConfig->Vtm.Timing.HBackPorch + - MsaConfig->Vtm.Timing.HFrontPorch + - MsaConfig->Vtm.Timing.HActive); - MsaConfig->VClkTotal = (MsaConfig->Vtm.Timing.F0PVSyncWidth + - MsaConfig->Vtm.Timing.F0PVBackPorch + - MsaConfig->Vtm.Timing.F0PVFrontPorch + - MsaConfig->Vtm.Timing.VActive); /* Miscellaneous attributes. */ if (MsaConfig->BitsPerColor == 6) { @@ -548,8 +540,6 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream, MsaConfig->NVid = MsaConfigCustom->NVid; MsaConfig->HStart = MsaConfigCustom->HStart; MsaConfig->VStart = MsaConfigCustom->VStart; - MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal; - MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal; MsaConfig->Misc0 = MsaConfigCustom->Misc0; MsaConfig->Misc1 = MsaConfigCustom->Misc1; MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane; @@ -761,9 +751,10 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream) /* Set the main stream attributes to the associated DisplayPort TX core * registers. */ XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + - StreamOffset[Stream - 1], MsaConfig->HClkTotal); + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + - StreamOffset[Stream - 1], MsaConfig->VClkTotal); + StreamOffset[Stream - 1], + MsaConfig->Vtm.Timing.F0PVTotal); XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HSyncPolarity |