From a8514b175a55e6d4e4cb091ceaaa5cf8c4846ece Mon Sep 17 00:00:00 2001
From: P L Sai Krishna <lakshmi.sai.krishna.potthuri@xilinx.com>
Date: Thu, 5 Feb 2015 16:49:31 +0530
Subject: [PATCH] qspips_v3_2: Add QSPI Software reset in Abort.

This patch add QSPI software reset in Abort API.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
---
 .../drivers/qspips/src/xqspips.c              | 23 ++++++++------
 .../drivers/qspips/src/xqspips.h              |  3 ++
 .../drivers/qspips/src/xqspips_hw.h           | 31 +++++++++++++++++++
 3 files changed, 48 insertions(+), 9 deletions(-)

diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
index fe3beda7..91b22135 100644
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.c
@@ -95,6 +95,9 @@
 *                    change is done only when no transfer is in progress.
 * 3.1   hk  08/13/14 When writing to the configuration register, set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
 *
 * </pre>
 *
@@ -312,6 +315,17 @@ void XQspiPs_Abort(XQspiPs *InstancePtr)
 	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
 			 XQSPIPS_CR_OFFSET, ConfigReg);
 
+	/*
+	 * QSPI Software Reset
+	 */
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+			SLCR_UNLOCK_MASK);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+			LQSPI_RST_CTRL_MASK);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+			SLCR_LOCK_MASK);
+
 	/*
 	 * Set the RX and TX FIFO threshold to reset value (one)
 	 */
@@ -321,15 +335,6 @@ void XQspiPs_Abort(XQspiPs *InstancePtr)
 	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
 			XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
 
-	/*
-	 * Clear the RX FIFO and drop any data.
-	 */
-	while ((XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
-		 XQSPIPS_SR_OFFSET) & XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
-		XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
-				 XQSPIPS_RXD_OFFSET);
-	}
-
 	InstancePtr->RemainingBytes = 0;
 	InstancePtr->RequestedBytes = 0;
 	InstancePtr->IsBusy = FALSE;
diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
index e93f879d..dc84b647 100644
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips.h
@@ -265,6 +265,9 @@
 *                    CR#737760.
 * 3.1   hk  08/13/14 When writing to the configuration register, set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
 *
 * </pre>
 *
diff --git a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
index 08dc53c1..3f6e4191 100644
--- a/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
+++ b/XilinxProcessorIPLib/drivers/qspips/src/xqspips_hw.h
@@ -57,6 +57,9 @@
 *                    constant definitions.
 * 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
 *                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
 *
 * </pre>
 *
@@ -325,6 +328,34 @@ extern "C" {
 /* @} */
 
 
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/