From a88d54eb114c88cf0560fc6970561bb7e8933bc4 Mon Sep 17 00:00:00 2001 From: Rohit Consul Date: Wed, 27 May 2015 08:11:27 +0800 Subject: [PATCH] v_deinterlacer: Added new driver HLS generated driver along with manually written layer 2. driver tcl update pending Signed-off-by: Rohit Consul --- .../v_deinterlacer/data/v_deinterlacer.mdd | 18 ++ .../v_deinterlacer/data/v_deinterlacer.tcl | 23 ++ .../drivers/v_deinterlacer/src/Makefile | 34 +++ .../v_deinterlacer/src/xv_deinterlacer.c | 200 ++++++++++++++++++ .../v_deinterlacer/src/xv_deinterlacer.h | 111 ++++++++++ .../v_deinterlacer/src/xv_deinterlacer_hw.h | 54 +++++ .../v_deinterlacer/src/xv_deinterlacer_l2.c | 162 ++++++++++++++ .../v_deinterlacer/src/xv_deinterlacer_l2.h | 115 ++++++++++ .../src/xv_deinterlacer_linux.c | 150 +++++++++++++ .../src/xv_deinterlacer_sinit.c | 45 ++++ 10 files changed, 912 insertions(+) create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.mdd create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/Makefile create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.h create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.h create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_linux.c create mode 100644 XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_sinit.c diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.mdd b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.mdd new file mode 100644 index 00000000..955484f0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.mdd @@ -0,0 +1,18 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +OPTION psf_version = 2.1; + +BEGIN driver v_deinterlacer + + OPTION supported_peripherals = (v_deinterlacer_v5_0 ); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION name = v_deinterlacer; + OPTION version = 5.0; + +END driver diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl new file mode 100644 index 00000000..e7dc1e42 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/data/v_deinterlacer.tcl @@ -0,0 +1,23 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "XV_deinterlacer" \ + "NUM_INSTANCES" \ + "DEVICE_ID" \ + "C_S_AXI_AXILITES_BASEADDR" \ + "C_S_AXI_AXILITES_HIGHADDR" + + xdefine_config_file $drv_handle "xv_deinterlacer_g.c" "XV_deinterlacer" \ + "DEVICE_ID" \ + "C_S_AXI_AXILITES_BASEADDR" + + xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_deinterlacer" \ + "DEVICE_ID" \ + "C_S_AXI_AXILITES_BASEADDR" \ + "C_S_AXI_AXILITES_HIGHADDR" +} diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/Makefile b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/Makefile new file mode 100644 index 00000000..e85b9a77 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/Makefile @@ -0,0 +1,34 @@ +# ============================================================== +# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +# Version: 2015.1 +# Copyright (C) 2015 Xilinx Inc. All rights reserved. +# +# ============================================================== + +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + + +libs: + echo "Compiling v_deinterlacer" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c new file mode 100644 index 00000000..281bba27 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.c @@ -0,0 +1,200 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +/***************************** Include Files *********************************/ +#include "xv_deinterlacer.h" + +/************************** Function Implementation *************************/ +#ifndef __linux__ +int XV_deinterlacer_CfgInitialize(XV_deinterlacer *InstancePtr, XV_deinterlacer_Config *ConfigPtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + InstancePtr->Axilites_BaseAddress = ConfigPtr->Axilites_BaseAddress; + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} +#endif + +void XV_deinterlacer_Start(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL) & 0x80; + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, Data | 0x01); +} + +u32 XV_deinterlacer_IsDone(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + return (Data >> 1) & 0x1; +} + +u32 XV_deinterlacer_IsIdle(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + return (Data >> 2) & 0x1; +} + +u32 XV_deinterlacer_IsReady(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + // check ap_start to see if the pcore is ready for next input + return !(Data & 0x1); +} + +void XV_deinterlacer_EnableAutoRestart(XV_deinterlacer *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0x80); +} + +void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL, 0); +} + +void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA, Data); +} + +u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA); + return Data; +} + +void XV_deinterlacer_Set_write_fb(XV_deinterlacer *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA, Data); +} + +u32 XV_deinterlacer_Get_write_fb(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA); + return Data; +} + +void XV_deinterlacer_Set_colorFormat(XV_deinterlacer *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA, Data); +} + +u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA); + return Data; +} + +void XV_deinterlacer_Set_algo(XV_deinterlacer *InstancePtr, u32 Data) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA, Data); +} + +u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr) { + u32 Data; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Data = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA); + return Data; +} + +void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_GIE, 1); +} + +void XV_deinterlacer_InterruptGlobalDisable(XV_deinterlacer *InstancePtr) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_GIE, 0); +} + +void XV_deinterlacer_InterruptEnable(XV_deinterlacer *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER, Register | Mask); +} + +void XV_deinterlacer_InterruptDisable(XV_deinterlacer *InstancePtr, u32 Mask) { + u32 Register; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Register = XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER, Register & (~Mask)); +} + +void XV_deinterlacer_InterruptClear(XV_deinterlacer *InstancePtr, u32 Mask) { + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XV_deinterlacer_WriteReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ISR, Mask); +} + +u32 XV_deinterlacer_InterruptGetEnabled(XV_deinterlacer *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_IER); +} + +u32 XV_deinterlacer_InterruptGetStatus(XV_deinterlacer *InstancePtr) { + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XV_deinterlacer_ReadReg(InstancePtr->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_ISR); +} diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.h b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.h new file mode 100644 index 00000000..2cc8e8e2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer.h @@ -0,0 +1,111 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef XV_DEINTERLACER_H +#define XV_DEINTERLACER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#ifndef __linux__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_io.h" +#else +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif +#include "xv_deinterlacer_hw.h" + +/**************************** Type Definitions ******************************/ +#ifdef __linux__ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#else +typedef struct { + u16 DeviceId; + u32 Axilites_BaseAddress; +} XV_deinterlacer_Config; +#endif + +typedef struct { + u32 Axilites_BaseAddress; + u32 IsReady; +} XV_deinterlacer; + +/***************** Macros (Inline Functions) Definitions *********************/ +#ifndef __linux__ +#define XV_deinterlacer_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) +#define XV_deinterlacer_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) +#else +#define XV_deinterlacer_WriteReg(BaseAddress, RegOffset, Data) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data) +#define XV_deinterlacer_ReadReg(BaseAddress, RegOffset) \ + *(volatile u32*)((BaseAddress) + (RegOffset)) + +#define Xil_AssertVoid(expr) assert(expr) +#define Xil_AssertNonvoid(expr) assert(expr) + +#define XST_SUCCESS 0 +#define XST_DEVICE_NOT_FOUND 2 +#define XST_OPEN_DEVICE_FAILED 3 +#define XIL_COMPONENT_IS_READY 1 +#endif + +/************************** Function Prototypes *****************************/ +#ifndef __linux__ +int XV_deinterlacer_Initialize(XV_deinterlacer *InstancePtr, u16 DeviceId); +XV_deinterlacer_Config* XV_deinterlacer_LookupConfig(u16 DeviceId); +int XV_deinterlacer_CfgInitialize(XV_deinterlacer *InstancePtr, XV_deinterlacer_Config *ConfigPtr); +#else +int XV_deinterlacer_Initialize(XV_deinterlacer *InstancePtr, const char* InstanceName); +int XV_deinterlacer_Release(XV_deinterlacer *InstancePtr); +#endif + +void XV_deinterlacer_Start(XV_deinterlacer *InstancePtr); +u32 XV_deinterlacer_IsDone(XV_deinterlacer *InstancePtr); +u32 XV_deinterlacer_IsIdle(XV_deinterlacer *InstancePtr); +u32 XV_deinterlacer_IsReady(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_EnableAutoRestart(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_DisableAutoRestart(XV_deinterlacer *InstancePtr); + +void XV_deinterlacer_Set_read_fb(XV_deinterlacer *InstancePtr, u32 Data); +u32 XV_deinterlacer_Get_read_fb(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_Set_write_fb(XV_deinterlacer *InstancePtr, u32 Data); +u32 XV_deinterlacer_Get_write_fb(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_Set_colorFormat(XV_deinterlacer *InstancePtr, u32 Data); +u32 XV_deinterlacer_Get_colorFormat(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_Set_algo(XV_deinterlacer *InstancePtr, u32 Data); +u32 XV_deinterlacer_Get_algo(XV_deinterlacer *InstancePtr); + +void XV_deinterlacer_InterruptGlobalEnable(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_InterruptGlobalDisable(XV_deinterlacer *InstancePtr); +void XV_deinterlacer_InterruptEnable(XV_deinterlacer *InstancePtr, u32 Mask); +void XV_deinterlacer_InterruptDisable(XV_deinterlacer *InstancePtr, u32 Mask); +void XV_deinterlacer_InterruptClear(XV_deinterlacer *InstancePtr, u32 Mask); +u32 XV_deinterlacer_InterruptGetEnabled(XV_deinterlacer *InstancePtr); +u32 XV_deinterlacer_InterruptGetStatus(XV_deinterlacer *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h new file mode 100644 index 00000000..8ef6031c --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_hw.h @@ -0,0 +1,54 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +// AXILiteS +// 0x00 : Control signals +// bit 0 - ap_start (Read/Write/COH) +// bit 1 - ap_done (Read/COR) +// bit 2 - ap_idle (Read) +// bit 3 - ap_ready (Read) +// bit 7 - auto_restart (Read/Write) +// others - reserved +// 0x04 : Global Interrupt Enable Register +// bit 0 - Global Interrupt Enable (Read/Write) +// others - reserved +// 0x08 : IP Interrupt Enable Register (Read/Write) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x0c : IP Interrupt Status Register (Read/TOW) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x10 : Data signal of read_fb +// bit 31~0 - read_fb[31:0] (Read/Write) +// 0x14 : reserved +// 0x18 : Data signal of write_fb +// bit 31~0 - write_fb[31:0] (Read/Write) +// 0x1c : reserved +// 0x20 : Data signal of colorFormat +// bit 7~0 - colorFormat[7:0] (Read/Write) +// others - reserved +// 0x24 : reserved +// 0x28 : Data signal of algo +// bit 7~0 - algo[7:0] (Read/Write) +// others - reserved +// 0x2c : reserved +// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + +#define XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL 0x00 +#define XV_DEINTERLACER_AXILITES_ADDR_GIE 0x04 +#define XV_DEINTERLACER_AXILITES_ADDR_IER 0x08 +#define XV_DEINTERLACER_AXILITES_ADDR_ISR 0x0c +#define XV_DEINTERLACER_AXILITES_ADDR_READ_FB_DATA 0x10 +#define XV_DEINTERLACER_AXILITES_BITS_READ_FB_DATA 32 +#define XV_DEINTERLACER_AXILITES_ADDR_WRITE_FB_DATA 0x18 +#define XV_DEINTERLACER_AXILITES_BITS_WRITE_FB_DATA 32 +#define XV_DEINTERLACER_AXILITES_ADDR_COLORFORMAT_DATA 0x20 +#define XV_DEINTERLACER_AXILITES_BITS_COLORFORMAT_DATA 8 +#define XV_DEINTERLACER_AXILITES_ADDR_ALGO_DATA 0x28 +#define XV_DEINTERLACER_AXILITES_BITS_ALGO_DATA 8 diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c new file mode 100644 index 00000000..dda487d4 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_deinterlacer_l2.c +* +* The deint Layer-2 Driver. The functions in this file provides an abstraction +* from the register peek/poke methodology by implementing most common use-case +* provided by the sub-core. See xv_deinterlacer_l2.h for a detailed description +* of the layer-2 driver +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xv_deinterlacer_l2.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/**************************** Local Global *******************************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* This function starts the deinterlacer core +* +* @param InstancePtr is a pointer to the core instance to be worked on +* +* @return None +* +******************************************************************************/ +void XV_DeintStart(XV_deinterlacer *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_deinterlacer_EnableAutoRestart(InstancePtr); + XV_deinterlacer_Start(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function stops the deinterlacer core +* +* @param InstancePtr is a pointer to the core instance to be worked on +* +* @return None +* +******************************************************************************/ +void XV_DeintStop(XV_deinterlacer *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_deinterlacer_DisableAutoRestart(InstancePtr); +} + +/*****************************************************************************/ +/** +* This function sets the deinterlacer cores RD/WR field buffers addresses +* and color space +* +* @param InstancePtr is a pointer to the core instance to be worked on +* @param memAddr is the buffer address in DDR for RD/WR clients +* @param cformat is the input stream color format +* +* @return None +* +******************************************************************************/ +void XV_DeintSetFieldBuffers(XV_deinterlacer *InstancePtr, + u32 memAddr, + XVidC_ColorFormat cformat) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XV_deinterlacer_Set_read_fb(InstancePtr, memAddr); + XV_deinterlacer_Set_write_fb(InstancePtr, memAddr); + XV_deinterlacer_Set_colorFormat(InstancePtr, cformat); +} + +/*****************************************************************************/ +/** +* +* This function prints Deinterlacer status on console +* +* @param InstancePtr is the instance pointer to the IP instance. +* +* @return None +* +******************************************************************************/ +void XV_DeintDbgReportStatus(XV_deinterlacer *InstancePtr) +{ + XV_deinterlacer *pDeint = InstancePtr; + u32 done, idle, ready, ctrl; + u32 rfb, wfb, colformat, algo; + + /* + * Assert validates the input arguments + */ + Xil_AssertVoid(InstancePtr != NULL); + + xil_printf("\r\n\r\n----->Deinterlacer IP STATUS<----\r\n"); + + done = XV_deinterlacer_IsDone(pDeint); + idle = XV_deinterlacer_IsIdle(pDeint); + ready = XV_deinterlacer_IsReady(pDeint); + ctrl = XV_deinterlacer_ReadReg(pDeint->Axilites_BaseAddress, XV_DEINTERLACER_AXILITES_ADDR_AP_CTRL); + + rfb = XV_deinterlacer_Get_read_fb(pDeint); + wfb = XV_deinterlacer_Get_write_fb(pDeint); + colformat = XV_deinterlacer_Get_colorFormat(pDeint); + algo = XV_deinterlacer_Get_algo(pDeint); + + xil_printf("IsDone: %d\r\n", done); + xil_printf("IsIdle: %d\r\n", idle); + xil_printf("IsReady: %d\r\n", ready); + xil_printf("Ctrl: 0x%x\r\n\r\n", ctrl); + + xil_printf("Read Frame Buffer: 0x%x\r\n", rfb); + xil_printf("Write Frame Buffer: 0x%x\r\n", wfb); + xil_printf("Color Format: %d\r\n", colformat); + xil_printf("Algo Selected: %d\r\n", algo); +} diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.h b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.h new file mode 100644 index 00000000..f7407a05 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_l2.h @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xv_deinterlacer_l2.h +* +* This header file contains layer 2 API's of the deint sub-core driver. +* The functions contained herein provides a high level implementation of features +* provided by the IP, abstracting away the register level details from +* the user +* +* Deinterlacer IP Features +* +* Currently only 1080i input is supported +* +* Dependency +* +* This driver makes use of the video enumerations and data types defined in the +* Xilinx Video Common Driver (video_common_vX.x) and as such the common driver +* must be included as dependency to compile this driver +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the deint core. +* +* Before using the layer-2 API's user must initialize the core by calling +* Layer-1 API XV_deinterlacer_Initialize(). This function will look for a +* configuration structure for the device and initialize it to defined HW +* settings. After initialization Layer-2 API's can be used to configure +* the core. It is recommended user always make use of Layer-2 API to interact +* with core. +* Advanced users always have the capability to directly interact with the +* core using Layer-1 API's that perform low level register peek/poke. +* +* Interrupts +* +* This driver does not have any interrupts +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  rc   05/01/15   Initial Release
+
+*
+* +******************************************************************************/ +#ifndef XV_DEINTERALCER_L2_H /* prevent circular inclusions */ +#define XV_DEINTERALCER_L2_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xvidc.h" +#include "xv_deinterlacer.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ +void XV_DeintStart(XV_deinterlacer *InstancePtr); +void XV_DeintStop(XV_deinterlacer *InstancePtr); +void XV_DeintSetFieldBuffers(XV_deinterlacer *InstancePtr, + u32 memAddr, + XVidC_ColorFormat cformat); + +void XV_DeintDbgReportStatus(XV_deinterlacer *InstancePtr); + + +#endif /* XSS_DEINT_H_ */ diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_linux.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_linux.c new file mode 100644 index 00000000..a4d3cca0 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_linux.c @@ -0,0 +1,150 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifdef __linux__ + +/***************************** Include Files *********************************/ +#include "xv_deinterlacer.h" + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MAX_UIO_PATH_SIZE 256 +#define MAX_UIO_NAME_SIZE 64 +#define MAX_UIO_MAPS 5 +#define UIO_INVALID_ADDR 0 + +/**************************** Type Definitions ******************************/ +typedef struct { + u32 addr; + u32 size; +} XV_deinterlacer_uio_map; + +typedef struct { + int uio_fd; + int uio_num; + char name[ MAX_UIO_NAME_SIZE ]; + char version[ MAX_UIO_NAME_SIZE ]; + XV_deinterlacer_uio_map maps[ MAX_UIO_MAPS ]; +} XV_deinterlacer_uio_info; + +/***************** Variable Definitions **************************************/ +static XV_deinterlacer_uio_info uio_info; + +/************************** Function Implementation *************************/ +static int line_from_file(char* filename, char* linebuf) { + char* s; + int i; + FILE* fp = fopen(filename, "r"); + if (!fp) return -1; + s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp); + fclose(fp); + if (!s) return -2; + for (i=0; (*s)&&(iuio_num); + return line_from_file(file, info->name); +} + +static int uio_info_read_version(XV_deinterlacer_uio_info* info) { + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num); + return line_from_file(file, info->version); +} + +static int uio_info_read_map_addr(XV_deinterlacer_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + info->maps[n].addr = UIO_INVALID_ADDR; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].addr); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +static int uio_info_read_map_size(XV_deinterlacer_uio_info* info, int n) { + int ret; + char file[ MAX_UIO_PATH_SIZE ]; + sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n); + FILE* fp = fopen(file, "r"); + if (!fp) return -1; + ret = fscanf(fp, "0x%x", &info->maps[n].size); + fclose(fp); + if (ret < 0) return -2; + return 0; +} + +int XV_deinterlacer_Initialize(XV_deinterlacer *InstancePtr, const char* InstanceName) { + XV_deinterlacer_uio_info *InfoPtr = &uio_info; + struct dirent **namelist; + int i, n; + char* s; + char file[ MAX_UIO_PATH_SIZE ]; + char name[ MAX_UIO_NAME_SIZE ]; + int flag = 0; + + assert(InstancePtr != NULL); + + n = scandir("/sys/class/uio", &namelist, 0, alphasort); + if (n < 0) return XST_DEVICE_NOT_FOUND; + for (i = 0; i < n; i++) { + strcpy(file, "/sys/class/uio/"); + strcat(file, namelist[i]->d_name); + strcat(file, "/name"); + if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) { + flag = 1; + s = namelist[i]->d_name; + s += 3; // "uio" + InfoPtr->uio_num = atoi(s); + break; + } + } + if (flag == 0) return XST_DEVICE_NOT_FOUND; + + uio_info_read_name(InfoPtr); + uio_info_read_version(InfoPtr); + for (n = 0; n < MAX_UIO_MAPS; ++n) { + uio_info_read_map_addr(InfoPtr, n); + uio_info_read_map_size(InfoPtr, n); + } + + sprintf(file, "/dev/uio%d", InfoPtr->uio_num); + if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) { + return XST_OPEN_DEVICE_FAILED; + } + + // NOTE: slave interface 'Axilites' should be mapped to uioX/map0 + InstancePtr->Axilites_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); + assert(InstancePtr->Axilites_BaseAddress); + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +int XV_deinterlacer_Release(XV_deinterlacer *InstancePtr) { + XV_deinterlacer_uio_info *InfoPtr = &uio_info; + + assert(InstancePtr != NULL); + assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + munmap((void*)InstancePtr->Axilites_BaseAddress, InfoPtr->maps[0].size); + + close(InfoPtr->uio_fd); + + return XST_SUCCESS; +} + +#endif diff --git a/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_sinit.c b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_sinit.c new file mode 100644 index 00000000..b32f2891 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_deinterlacer/src/xv_deinterlacer_sinit.c @@ -0,0 +1,45 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2015.1 +// Copyright (C) 2015 Xilinx Inc. All rights reserved. +// +// ============================================================== + +#ifndef __linux__ + +#include "xstatus.h" +#include "xparameters.h" +#include "xv_deinterlacer.h" + +extern XV_deinterlacer_Config XV_deinterlacer_ConfigTable[]; + +XV_deinterlacer_Config *XV_deinterlacer_LookupConfig(u16 DeviceId) { + XV_deinterlacer_Config *ConfigPtr = NULL; + + int Index; + + for (Index = 0; Index < XPAR_XV_DEINTERLACER_NUM_INSTANCES; Index++) { + if (XV_deinterlacer_ConfigTable[Index].DeviceId == DeviceId) { + ConfigPtr = &XV_deinterlacer_ConfigTable[Index]; + break; + } + } + + return ConfigPtr; +} + +int XV_deinterlacer_Initialize(XV_deinterlacer *InstancePtr, u16 DeviceId) { + XV_deinterlacer_Config *ConfigPtr; + + Xil_AssertNonvoid(InstancePtr != NULL); + + ConfigPtr = XV_deinterlacer_LookupConfig(DeviceId); + if (ConfigPtr == NULL) { + InstancePtr->IsReady = 0; + return (XST_DEVICE_NOT_FOUND); + } + + return XV_deinterlacer_CfgInitialize(InstancePtr, ConfigPtr); +} + +#endif