diff --git a/XilinxProcessorIPLib/drivers/csudma/data/csudma.mdd b/XilinxProcessorIPLib/drivers/csudma/data/csudma.mdd new file mode 100755 index 00000000..632c878e --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/data/csudma.mdd @@ -0,0 +1,42 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +OPTION psf_version = 2.1; + +BEGIN driver canps + + OPTION supported_peripherals = (ps8_csudma pss_csudma); + OPTION driver_state = ACTIVE; + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = csudma; + +END driver diff --git a/XilinxProcessorIPLib/drivers/csudma/data/csudma.tcl b/XilinxProcessorIPLib/drivers/csudma/data/csudma.tcl new file mode 100755 index 00000000..032484e1 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/data/csudma.tcl @@ -0,0 +1,51 @@ +############################################################################### +# +# Copyright (C) 2014 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +# +############################################################################### +############################################################################## +# +# Modification History +# +# Ver Who Date Changes +# ----- ---- -------- ----------------------------------------------- +# 1.0 vnsld 22/10/14 First release +# +############################################################################## + +#uses "xillib.tcl" + +proc generate {drv_handle} { + xdefine_zynq_include_file $drv_handle "xparameters.h" "XCsuDma" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_CSUDMA_CLK_FREQ_HZ" + + xdefine_zynq_config_file $drv_handle "xcsudma_g.c" "XCsuDma" "DEVICE_ID" "C_S_AXI_BASEADDR" + + xdefine_zynq_canonical_xpars $drv_handle "xparameters.h" "XCsuDma" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_CSUDMA_CLK_FREQ_HZ" + +} diff --git a/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_intr_example.c b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_intr_example.c new file mode 100755 index 00000000..168d8da2 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_intr_example.c @@ -0,0 +1,477 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_intr_example.c +* +* This file contains a design example using the XCsuDma driver in interrupt +* mode. It sends data and expects to receive the same data through the device +* using the local loop back mode. +* +* @note +* The example contains an infinite loop such that if interrupts are not +* working it may hang. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" +#include "xscugic.h" +#include "xil_exception.h" + +/************************** Function Prototypes ******************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define CSUDMA_DEVICE_ID 0//XPAR_XCSUDMA_0_DEVICE_ID /* CSU DMA device Id */ +#define INTG_INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#define INTG_CSUDMA_INTR_DEVICE_ID 102+32 /**< Interrupt device ID + * of CSU DMA device ID */ + +#define CSU_SSS_CONFIG_OFFSET 0x008 /**< CSU SSS_CFG Offset */ +#define CSUDMA_LOOPBACK_CFG 0x00000050 /**< LOOP BACK configuration + * macro */ +#define SRC_ADDR 0x04200000 /**< Source Address */ +#define DST_ADDR 0x04300000 /**< Destination Address */ +#define SIZE 0x100 /**< Size of the data to be + * transfered */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +int XCsuDma_IntrExample(u16 DeviceId); +static int SetupInterruptSystem(XScuGic *IntcInstancePtr, + XCsuDma *CsuDmaInstance, + u16 CsuDmaIntrId); +void IntrHandler(void *CallBackRef); + +static void SrcHandler(void *CallBackRef, u32 Event); +static void DstHandler(void *CallBackRef, u32 Event); + +/************************** Variable Definitions *****************************/ + +XCsuDma CsuDma; /**_DEVICE_ID value from +* xparameters.h. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if failed. +* +* @note None. +* +******************************************************************************/ +int XCsuDma_IntrExample(u16 DeviceId) +{ + int Status; + XCsuDma_Config *Config; + u32 Index = 0; + u32 *SrcPtr = (u32 *)SRC_ADDR; + u32 *DstPtr = (u32 *)DST_ADDR; + u32 Test_Data = 0xABCD1234; + u32 *Ptr = (u32 *)SRC_ADDR; + u32 EnLast = 0; + /* + * Initialize the CsuDma driver so that it's ready to use + * look up the configuration in the config table, + * then initialize it. + */ + Config = XCsuDma_LookupConfig(DeviceId); + if (NULL == Config) { + return XST_FAILURE; + } + + Status = XCsuDma_CfgInitialize(&CsuDma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Performs the self-test to check hardware build. + */ + Status = XCsuDma_SelfTest(&CsuDma); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Connect to the interrupt controller. + */ + Status = SetupInterruptSystem(&Intc, &CsuDma, + INTG_CSUDMA_INTR_DEVICE_ID); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + /* Enable interrupts */ + XCsuDma_EnableIntr(&CsuDma, XCSUDMA_DST_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* + * Setting CSU_DMA in loop back mode. + */ + + Xil_Out32(XCSU_BASEADDRESS + CSU_SSS_CONFIG_OFFSET, + (Xil_In32(XCSU_BASEADDRESS + CSU_SSS_CONFIG_OFFSET) | + CSUDMA_LOOPBACK_CFG)); + + /* Data writing at source address location */ + + for(Index = 0; Index < SIZE; Index++) + { + *Ptr = Test_Data; + Test_Data += 0x1; + Ptr++; + } + + /* Data transfer in loop back mode */ + XCsuDma_Transfer(&CsuDma, XCSUDMA_DST_CHANNEL, DST_ADDR, SIZE, EnLast); + XCsuDma_Transfer(&CsuDma, XCSUDMA_SRC_CHANNEL, SRC_ADDR, SIZE, EnLast); + + /* Wait for generation of destination work is done */ + while(DstDone == 1); + /* Disable interrupts */ + XCsuDma_DisableIntr(&CsuDma, XCSUDMA_DST_CHANNEL, + XCSUDMA_IXR_DONE_MASK); + /* To acknowledge the transfer has completed */ + XCsuDma_IntrClear(&CsuDma, XCSUDMA_SRC_CHANNEL, XCSUDMA_IXR_DONE_MASK); + XCsuDma_IntrClear(&CsuDma, XCSUDMA_DST_CHANNEL, XCSUDMA_IXR_DONE_MASK); + + /* + * Verifying data of transfered by comparing data at + * source and address locations. + */ + + for (Index = 0; Index < SIZE; Index++) { + if (*SrcPtr != *DstPtr) { + return XST_FAILURE; + } + else { + SrcPtr++; + DstPtr++; + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* This function sets up the interrupt system so interrupts can occur for the +* CSU DMA. This function is application-specific. The user should modify this +* function to fit the application. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC. +* @param InstancePtr contains a pointer to the instance of the CSU DMA +* driver which is going to be connected to the interrupt +* controller. +* @param IntrId is the interrupt Id and is typically +* XPAR__INTR value from xparameters.h. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if failed +* +* @note None. + +* +****************************************************************************/ +static int SetupInterruptSystem(XScuGic *IntcInstancePtr, + XCsuDma *InstancePtr, + u16 IntrId) +{ + int Status; + +#ifndef TESTAPP_GEN + XScuGic_Config *IntcConfig; /* Config for interrupt controller */ + + /* + * Initialize the interrupt controller driver + */ + IntcConfig = XScuGic_LookupConfig(INTG_INTC_DEVICE_ID); + if (NULL == IntcConfig) { + return XST_FAILURE; + } + + Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, + IntcConfig->CpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Connect the interrupt controller interrupt handler to the + * hardware interrupt handling logic in the processor. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler) XScuGic_InterruptHandler, + IntcInstancePtr); +#endif + + /* + * Connect a device driver handler that will be called when an + * interrupt for the device occurs, the device driver handler + * performs the specific interrupt processing for the device + */ + Status = XScuGic_Connect(IntcInstancePtr, IntrId, + (Xil_ExceptionHandler) IntrHandler, + (void *) InstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Enable the interrupt for the device + */ + XScuGic_Enable(IntcInstancePtr, IntrId); + + + /* + * Enable interrupts + */ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); + + + return XST_SUCCESS; +} + + + +/*****************************************************************************/ +/** +* +* This function is the interrupt handler for the CSU_DMA driver. +* +* This handler reads the interrupt status from the Status register, determines +* the source of the interrupts, calls according callbacks, and finally clears +* the interrupts. +* +* @param CallBackRef is the callback reference passed from the interrupt +* handler, which in our case is a pointer to the driver instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void IntrHandler(void *CallBackRef) +{ + u32 SrcPending; + u32 DstPending; + XCsuDma *XCsuDmaPtr = NULL; + XCsuDmaPtr = (XCsuDma *)((void *)CallBackRef); + + /* Handling interrupt */ + + /* Getting pending interrupts of source */ + SrcPending = XCsuDma_IntrGetStatus(XCsuDmaPtr, XCSUDMA_SRC_CHANNEL); + XCsuDma_IntrClear(XCsuDmaPtr, XCSUDMA_SRC_CHANNEL, SrcPending); + SrcPending &= (~XCsuDma_GetIntrMask(XCsuDmaPtr, XCSUDMA_SRC_CHANNEL)); + + /* Getting pending interrupts of destination */ + DstPending = XCsuDma_IntrGetStatus(XCsuDmaPtr, XCSUDMA_DST_CHANNEL); + XCsuDma_IntrClear(XCsuDmaPtr, XCSUDMA_DST_CHANNEL, DstPending); + DstPending &= (~XCsuDma_GetIntrMask(XCsuDmaPtr, XCSUDMA_DST_CHANNEL)); + + + if (SrcPending != 0x00) { + SrcHandler(XCsuDmaPtr, SrcPending); + } + + if (DstPending != 0x00) { + DstHandler(XCsuDmaPtr, DstPending); + } +} + +/*****************************************************************************/ +/** +* This is static function which handlers source channel interrupts. +* +* @param CallBackRef is the callback reference passed from the interrupt +* handler, which in our case is a pointer to the driver instance. +* @param Event specifies which interrupts were occured. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void SrcHandler(void *CallBackRef, u32 Event) +{ + if (Event & XCSUDMA_IXR_INVALID_APB_MASK) { + /* + * Code to handle Invalid APB access + * Interrupt should be put here. + */ + } + + if (Event & XCSUDMA_IXR_FIFO_THRESHHIT_MASK) { + /* + * Code to handle FIFO Threshold hit + * Interrupt should be put here. + */ + } + + if (Event & (XCSUDMA_IXR_TIMEOUT_MEM_MASK | + XCSUDMA_IXR_TIMEOUT_STRM_MASK)) { + /* + * Code to handle Timeout + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_AXI_WRERR_MASK) { + /* + * Code to handle AXI read error + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_DONE_MASK) { + /* + * Code to handle Done + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_MEM_DONE_MASK) { + /* + * Code to handle Memory done + * Interrupt should be put here. + */ + } +} + +/*****************************************************************************/ +/** +* This static function handles destination channel interrupts. +* +* @param CallBackRef is the callback reference passed from the interrupt +* handler, which in our case is a pointer to the driver instance. +* @param Event specifies which interrupts were occured. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void DstHandler(void *CallBackRef, u32 Event) +{ + if (Event & XCSUDMA_IXR_FIFO_OVERFLOW_MASK) { + /* + * Code to handle FIFO overflow + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_INVALID_APB_MASK) { + /* + * Code to handle Invalid APB access + * Interrupt should be put here. + */ + } + + if (Event & XCSUDMA_IXR_FIFO_THRESHHIT_MASK) { + /* + * Code to handle FIFO Threshold hit + * Interrupt should be put here. + */ + } + + if (Event & (XCSUDMA_IXR_TIMEOUT_MEM_MASK | + XCSUDMA_IXR_TIMEOUT_STRM_MASK)) { + /* + * Code to handle Time out memory or stream + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_AXI_WRERR_MASK) { + /* + * Code to handle AXI read error + * Interrupt should be put here. + */ + } + if (Event & XCSUDMA_IXR_DONE_MASK) { + + DstDone = 1; + } +} diff --git a/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_polled_example.c b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_polled_example.c new file mode 100755 index 00000000..58795b48 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_polled_example.c @@ -0,0 +1,211 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_polled_example.c +* +* This file contains an example using the XCsuDma driver in polled mode. +* +* This function works in loop back mode and tests whether transfer of data is +* completed properly or not. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" + +/************************** Function Prototypes ******************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define CSUDMA_DEVICE_ID 0//XPAR_XCSUDMA_0_DEVICE_ID /* CSU DMA device Id */ +#define CSU_SSS_CONFIG_OFFSET 0x008 /**< CSU SSS_CFG Offset */ +#define CSUDMA_LOOPBACK_CFG 0x00000050 /**< LOOP BACK configuration + * macro */ + +#define SRC_ADDR 0x04200000 /**< Source Address */ +#define DST_ADDR 0x04300000 /**< Destination Address */ +#define SIZE 0x100 /**< Size of the data to be + * transfered */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +int XCsuDma_PolledExample(u16 DeviceId); + +/************************** Variable Definitions *****************************/ + + +XCsuDma CsuDma; /**_DEVICE_ID value from +* xparameters.h. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if failed. +* +* @note None. +* +******************************************************************************/ +int XCsuDma_PolledExample(u16 DeviceId) +{ + int Status; + XCsuDma_Config *Config; + u32 Index = 0; + u32 *SrcPtr = (u32 *)SRC_ADDR; + u32 *DstPtr = (u32 *)DST_ADDR; + u32 Test_Data = 0xABCD1234; + u32 *Ptr = (u32 *)SRC_ADDR; + u32 EnLast = 0; + /* + * Initialize the CsuDma driver so that it's ready to use + * look up the configuration in the config table, + * then initialize it. + */ + Config = XCsuDma_LookupConfig(DeviceId); + if (NULL == Config) { + return XST_FAILURE; + } + + Status = XCsuDma_CfgInitialize(&CsuDma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Performs the self-test to check hardware build. + */ + Status = XCsuDma_SelfTest(&CsuDma); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Setting CSU_DMA in loop back mode. + */ + + Xil_Out32(XCSU_BASEADDRESS + CSU_SSS_CONFIG_OFFSET, + ((Xil_In32(XCSU_BASEADDRESS + CSU_SSS_CONFIG_OFFSET) & 0xF0000) | + CSUDMA_LOOPBACK_CFG)); + + /* Data writing at source address location */ + + for(Index = 0; Index < SIZE; Index++) + { + *Ptr = Test_Data; + Test_Data += 0x1; + Ptr++; + } + + + /* Data transfer in loop back mode */ + XCsuDma_Transfer(&CsuDma, XCSUDMA_DST_CHANNEL, DST_ADDR, SIZE, EnLast); + XCsuDma_Transfer(&CsuDma, XCSUDMA_SRC_CHANNEL, SRC_ADDR, SIZE, EnLast); + + + /* Polling for transfer to be done */ + XCsuDma_WaitForDone(&CsuDma, XCSUDMA_DST_CHANNEL); + + /* To acknowledge the transfer has completed */ + XCsuDma_IntrClear(&CsuDma, XCSUDMA_SRC_CHANNEL, XCSUDMA_IXR_DONE_MASK); + XCsuDma_IntrClear(&CsuDma, XCSUDMA_DST_CHANNEL, XCSUDMA_IXR_DONE_MASK); + + /* + * Verifying data of transfered by comparing data at source + * and address locations. + */ + + for (Index = 0; Index < SIZE; Index++) { + if (*SrcPtr != *DstPtr) { + return XST_FAILURE; + } + else { + SrcPtr++; + DstPtr++; + } + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_selftest_example.c b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_selftest_example.c new file mode 100755 index 00000000..d6b3d172 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/examples/xcsudma_selftest_example.c @@ -0,0 +1,152 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_seltest_example.c +* +* This file contains an example using the XCsudma driver to do self test +* on the device. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" + +/************************** Function Prototypes ******************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define CSUDMA_DEVICE_ID 0//XPAR_XCSUDMA_0_DEVICE_ID /* CSU DMA device Id */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +int XCsuDma_SelfTestExample(u16 DeviceId); + +/************************** Variable Definitions *****************************/ + + +XCsuDma CsuDma; /**_DEVICE_ID value from +* xparameters.h. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if failed. +* +* @note None. +* +******************************************************************************/ +int XCsuDma_SelfTestExample(u16 DeviceId) +{ + int Status; + XCsuDma_Config *Config; + + /* + * Initialize the CsuDma driver so that it's ready to use + * look up the configuration in the config table, + * then initialize it. + */ + Config = XCsuDma_LookupConfig(DeviceId); + if (NULL == Config) { + return XST_FAILURE; + } + + Status = XCsuDma_CfgInitialize(&CsuDma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Performs the self-test to check hardware build. + */ + + Status = XCsuDma_SelfTest(&CsuDma); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.c b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.c new file mode 100755 index 00000000..1ada2320 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.c @@ -0,0 +1,764 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma.c +* +* This file contains the implementation of the interface functions for CSU_DMA +* driver. Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes an CSU_DMA core. This function must be called +* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting +* up the instance data and ensuring the hardware is in a quiescent state. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* @param CfgPtr is a reference to a structure containing information +* about a specific XCsuDma instance. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical +* base address unchanged once this function is invoked. +* Unexpected errors may occur if the address mapping changes +* after this function is called. If address translation is not +* used, pass in the physical address instead. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr) +{ + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0)); + + /* Setup the instance */ + (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr, + sizeof(XCsuDma_Config)); + InstancePtr->Config.BaseAddress = EffectiveAddr; + + XCsuDma_Reset(); + + InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); + + return (XST_SUCCESS); + +} + +/*****************************************************************************/ +/** +* +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Addr is a 64 bit variable which holds the starting address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer. +* +******************************************************************************/ +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u64 Addr, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Flushing cache memory */ + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT)); + } + /* Invalidating cache memory */ + else { + Xil_DCacheInvalidateRange(Addr, Size << + (u32)(XCSUDMA_SIZE_SHIFT)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) & + (u32)(XCSUDMA_MSB_ADDR_MASK))); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the current address location of the memory, from where +* it has to read the data(SRC) or the location where it has to write the data +* (DST) based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Address is a 64 bit variable which holds the current address. +* - From this location data has to be read(SRC) +* - At this location data has to be written(DST) +* +* @note None. +* +******************************************************************************/ +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u64 FullAddr; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) << + (u64)(XCSUDMA_MSB_ADDR_SHIFT)); + + return FullAddr; +} + +/*****************************************************************************/ +/** +* +* This function returns the size of the data yet to be transfered from memory +* to CSU_DMA or CSU_DMA to memory based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Size is amount of data yet to be transfered. +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Size; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >> + (u32)(XCSUDMA_SIZE_SHIFT); + + return Size; +} + +/*****************************************************************************/ +/** +* +* This function pause the Channel data tranfer to/from memory or to/from stream +* based on pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be enabled. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Pause Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) | + (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (Channel * (u32)XCSUDMA_OFFSET_DIFF))) | + (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This functions checks whether Channel's memory or stream is paused or not +* based on the given pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause which needs to be checked. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return Returns the pause status. +* - TRUE if it is in paused state. +* - FALSE if it is not in pause state. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + + u32 Data; + s32 PauseState; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + /* To know Pause condition of Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + else { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + + return (s32)PauseState; + +} + +/*****************************************************************************/ +/** +* +* This function resumes the channel if it is in paused state and continues +* where it has left or no effect if it is not in paused state, based on the +* type of pause. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be Resume if it is in pause +* state. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + u32 Data; + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Data & + (~(XCSUDMA_CTRL_PAUSE_MEM_MASK)))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))), + ( Data & + (~(XCSUDMA_CTRL_PAUSE_STRM_MASK)))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the sum of all the data read from AXI memory. It is +* valid only one we use CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* Valid only for source channel +* +******************************************************************************/ +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr) +{ + u32 ChkSum; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == + (u32)(XIL_COMPONENT_IS_READY)); + + ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET)); + + return ChkSum; + +} +/*****************************************************************************/ +/** +* +* This function clears the check sum of the data read from AXI memory. It is +* valid only for CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* +******************************************************************************/ +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr) +{ + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK)); +} + +/*****************************************************************************/ +/** +* This function cofigures all the values of CSU_DMA's Channels with the values +* of updated XCsuDma_Configure structure. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose values are used to configure CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read +* command allowed) +* +* @return None. +* +* @note To use timers timeout value Timeout enable field should be +* enabled. +* +******************************************************************************/ +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE)); + + Data = (((ConfigurValues->EndianType << + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) | + ((ConfigurValues->ApbErr << + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) & + (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) | + ((ConfigurValues->AxiBurstType << + (u32)(XCSUDMA_CTRL_BURST_SHIFT)) & + (u32)(XCSUDMA_CTRL_BURST_MASK)) | + ((ConfigurValues->TimeoutValue << + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) & + (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) | + ((ConfigurValues->FifoThresh << + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK))); + if(Channel == XCSUDMA_DST_CHANNEL) { + Data = Data | (u32)((ConfigurValues->SssFifoThesh << + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + + Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) & + (u32)(XCSUDMA_CTRL2_RESERVED_MASK)); + Data |= (((ConfigurValues->Acache << + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) | + ((ConfigurValues->RouteBit << + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) | + ((ConfigurValues->TimeoutEn << + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) | + ((ConfigurValues->TimeoutPre << + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) | + ((ConfigurValues->MaxOutCmds) & + (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); +} + +/*****************************************************************************/ +/** +* +* This function updates XCsuDma_Configure structure members with the cofigured +* values of CSU_DMA's Channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose members are updated with configurations of CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed based normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read command +* allowed) +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Channel == (XCSUDMA_DST_CHANNEL)) { + ConfigurValues->SssFifoThesh = + (u8)((Data & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)); + } + ConfigurValues->ApbErr = + (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >> + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)); + ConfigurValues->EndianType = + (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >> + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)); + ConfigurValues->AxiBurstType = + (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >> + (u32)(XCSUDMA_CTRL_BURST_SHIFT)); + ConfigurValues->TimeoutValue = + ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >> + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)); + ConfigurValues->FifoThresh = + (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + ConfigurValues->Acache = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)); + ConfigurValues->RouteBit = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)); + ConfigurValues->TimeoutEn = + (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)); + ConfigurValues->TimeoutPre = + (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)); + ConfigurValues->MaxOutCmds = + (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + +} diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.h b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.h new file mode 100755 index 00000000..4ad57d29 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma.h @@ -0,0 +1,414 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* The CSU_DMA is present inside CSU (Configuration Security Unit) module which +* is located within the Low-Power Subsystem (LPS) internal to the PS. +* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit +* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure +* Stream Switch (SSS). +* +* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC +* (read) channel and DST (write) channel. The DMA is effectively able to +* transfer data: +* - From PS-side to the SSS-side (SRC DMA only) +* - From SSS-side to the PS-side (DST DMA only) +* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CSU_DMA core. +* +* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. +* The user needs to first call the XCsuDma_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XCsuDma_CfgInitialize() API. +* +* Interrupts +* This driver will not support handling of interrupts user should write handler +* to handle the interrupts. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCsuDma driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* @file xcsudma.h +* +* This header file contains identifiers and register-level driver functions (or +* macros), range macros, structure typedefs that can be used to access the +* Xilinx CSU_DMA core instance. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_H_ +#define XCSUDMA_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xcsudma_hw.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_cache.h" + +/************************** Constant Definitions *****************************/ + +/** @name CSU_DMA Channels + * @{ + */ +typedef enum { + XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */ + XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */ +}XCsuDma_Channel; +/*@}*/ + +/** @name CSU_DMA pause types + * @{ + */ +typedef enum { + XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer + * to/from CSU_DMA */ + XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer + * to/from CSU_DMA */ +}XCsuDma_PauseType; + +/*@}*/ + + +/** @name Ranges of Size + * @{ + */ +#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */ + +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This function resets the CSU_DMA core. +* +* @param None. +* +* @return None. +* +* @note None. +* C-style signature: +* void XCsuDma_Reset() +* +******************************************************************************/ +#define XCsuDma_Reset() \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_SET_MASK)); \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_UNSET_MASK)); + +/*****************************************************************************/ +/** +* This function will be in busy while loop until the data transfer is +* completed. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return None. +* +* @note This function should be called after XCsuDma_Transfer in polled +* mode to wait until the data gets transfered completely. +* C-style signature: +* void XCsuDma_WaitForDone(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_WaitForDone(InstancePtr,Channel) \ + while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_I_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK)) + +/*****************************************************************************/ +/** +* +* This function returns the number of completed SRC/DST DMA transfers that +* have not been acknowledged by software based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count is number of completed DMA transfers but not acknowledged +* (Range is 0 to 7). +* - 000 - All finished transfers have been acknowledged. +* - Count - Count number of finished transfers are still +* outstanding. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetDoneCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \ + (u32)(XCSUDMA_STS_DONE_CNT_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current SRC/DST FIFO level in 32 bit words of the +* selected channel +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return FIFO level. (Range is 0 to 128) +* - 0 Indicates empty +* - Any number 1 to 128 indicates the number of entries in FIFO. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current number of read(src)/write(dst) outstanding +* commands based on the type of channel selected. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count of outstanding commands. (Range is 0 to 9). +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \ + (u32)(XCUSDMA_STS_OUTSTDG_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the status of Channel either it is busy or not. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Returns the current status of the core. +* - TRUE represents core is currently busy. +* - FALSE represents core is not involved in any transfers. +* +* @note None. +* C-style signature: +* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +* +******************************************************************************/ + +#define XCsuDma_IsBusy(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \ + (TRUE) : (FALSE) + + +/**************************** Type Definitions *******************************/ + +/** +* This typedef contains configuration information for a CSU_DMA core. +* Each CSU_DMA core should have a configuration structure associated. +*/ +typedef struct { + u16 DeviceId; /**< DeviceId is the unique ID of the + * device */ + u32 BaseAddress; /**< BaseAddress is the physical base address + * of the device's registers */ +} XCsuDma_Config; + + +/******************************************************************************/ +/** +* +* The XCsuDma driver instance data structure. A pointer to an instance data +* structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XCsuDma_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ +}XCsuDma; + + +/******************************************************************************/ +/** +* This typedef contains all the configuration feilds which needs to be set +* before the start of the data transfer. All these feilds of CSU_DMA can be +* configured by using XCsuDma_SetConfig API. +*/ +typedef struct { + u8 SssFifoThesh; /**< SSS FIFO threshold value */ + u8 ApbErr; /**< ABP invalid access error */ + u8 EndianType; /**< Type of endianess */ + u8 AxiBurstType; /**< Type of AXI bus */ + u32 TimeoutValue; /**< Time out value */ + u8 FifoThresh; /**< FIFO threshold value */ + u8 Acache; /**< AXI CACHE selection */ + u8 RouteBit; /**< Selection of Route */ + u8 TimeoutEn; /**< Enable of time out counters */ + u16 TimeoutPre; /**< Pre scaler value */ + u8 MaxOutCmds; /**< Maximum number of outstanding + * commands */ +}XCsuDma_Configure; + +/*****************************************************************************/ + + +/************************** Function Prototypes ******************************/ + +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId); + +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr); +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u64 Addr, u32 Size, u8 EnDataLast); +void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, + u32 Size); +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); + +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr); +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr); + +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value); +u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr); + +/* Interrupt related APIs */ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr); + +/******************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif /* End of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_g.c b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_g.c new file mode 100755 index 00000000..9f4e5604 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_g.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcsudma_g.c +* This file contains the ConfigTable +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +#include "xcsudma.h" + +XCsuDma_Config XCsuDma_ConfigTable[] = +{ + { + 0, + 0xFFC80000 + } +}; diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_hw.h b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_hw.h new file mode 100755 index 00000000..0615c742 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_hw.h @@ -0,0 +1,307 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcsudma_hw.h +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_HW_H_ +#define XCSUDMA_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Registers offsets + * @{ + */ +#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */ +#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */ +#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */ +#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */ +#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */ +#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register + * Offset */ +#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register + * Offset */ +#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register + * Offset */ +#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */ +#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2 + * Offset */ +#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */ +#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */ +#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */ +/*@}*/ + +/** @name CSU Base address and CSU_DMA reset offset + * @{ + */ +#define XCSU_BASEADDRESS 0xFFCA0000U /**< CSU Base Address */ +#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */ +/*@}*/ + +/** @name CSU_DMA Reset register bit masks + * @{ + */ +#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */ +#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/ +/*@}*/ + +/** @name Offset difference for Source and destination + * @{ + */ +#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for + * source and + * destination channels */ +/*@}*/ + +/** @name Address register bit masks + * @{ + */ +#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */ +#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check + * mask */ +/*@}*/ + +/** @name Size register bit masks and shifts + * @{ + */ +#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */ +#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/ +#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */ +/*@}*/ + +/** @name Status register bit masks and shifts + * @{ + */ +#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */ +#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */ +#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding + * read/write + * commands mask */ +#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */ +#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count + * done */ +#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO + * level */ +#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of + * outstanding + * read/write + * commands */ +/*@}*/ + +/** @name Control register bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold + * value mask */ +#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register + * access error + * mask */ +#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */ +#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type + * mask */ +#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value + * mask */ +#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold + * mask */ +#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause + * mask */ +#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause + * mask */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold + * shift */ +#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */ +#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */ +#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type + * shift */ +#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value + * shift */ +#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh + * shift */ +/*@}*/ + +/** @name CheckSum register bit masks + * @{ + */ +#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset + * value of + * check sum */ +/*@}*/ + +/** @name Interrupt Enable/Disable/Mask/Status registers bit masks + * @{ + */ +#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow + * mask, it is valid + * only to Destination + * Channel */ +#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access + * mask */ +#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit + * indicator mask */ +#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter + * expired to access + * memory mask */ +#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter + * expired to access + * stream mask */ +#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write + * error mask */ +#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */ +#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done + * mask, it is valid + * only for source + * channel*/ +#define XCSUDMA_IXR_SRC_MASK 0x0000007FU + /**< ((XCSUDMA_IXR_INVALID_APB_MASK)| + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK) | + (XCSUDMA_IXR_MEM_DONE_MASK)) */ + /**< All interrupt mask + * for source */ +#define XCSUDMA_IXR_DST_MASK 0x000000FEU + /**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | + (XCSUDMA_IXR_INVALID_APB_MASK) | + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK)) */ + /**< All interrupt mask + * for destination */ +/*@}*/ + +/** @name Control register 2 bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits + * mask */ +#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */ +#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters + * enable mask */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre + * mask */ +#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands + * mask */ +#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */ +#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for + * AXI R/W CACHE */ +#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout + * enable feild */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout + * pre feild */ +/*@}*/ + +/** @name MSB Address register bit masks and shifts + * @{ + */ +#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address + * mask */ +#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of + * address */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XCsuDma_In32 Xil_In32 /**< Input operation */ +#define XCsuDma_Out32 Xil_Out32 /**< Output operation */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XCsuDma_ReadReg(BaseAddress, RegOffset) \ + XCsuDma_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes the value into the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \ + XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + + +#ifdef __cplusplus +} + +#endif + + +#endif /* End of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_intr.c b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_intr.c new file mode 100755 index 00000000..50b41e54 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_intr.c @@ -0,0 +1,271 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_intr.c +* +* This file contains interrupt related functions of Xilinx CSU_DMA core. +* Please see xcsudma.h for more details of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld  22/10/14  First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function returns interrupt status read from Interrupt Status Register. +* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The pending interrupts of the CSU_DMA. Use th following masks +* to interpret the returned value. +* XCSUDMA_IXR_SRC_MASK - For Source channel +* XCSUDMA_IXR_DST_MASK - For Destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))); + + return Data; + +} + +/*****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCSUDMA_IXR_* bits +* defined in xcsudma_hw.h. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask) +{ + + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET), + (Mask & (u32)(XCSUDMA_IXR_SRC_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Mask & (u32)(XCSUDMA_IXR_DST_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be enabled. +* - Bit positions of 1 will be enabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK); + } + /* + * Write the mask to the IER Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_EN_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be disabled. +* - Bit positions of 1 will be disabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == XCSUDMA_SRC_CHANNEL) { + Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK); + } + + /* + * Write the mask to the IDR Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_DIS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function returns the interrupt mask to know which interrupts are +* enabled and which of them were disaled. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The current interrupt mask. The mask indicates which interrupts +* are enabled/disabled. +* 0 bit represents .....corresponding interrupt is enabled. +* 1 bit represents .....Corresponding interrupt is disabled. +* To interpret returned mask use +* XCSUDMA_IXR_SRC_MASK........For source channel +* XCSUDMA_IXR_DST_MASK........For destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + /* + * Read the Interrupt Mask register + */ + return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_MASK_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))))); +} diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_selftest.c b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_selftest.c new file mode 100755 index 00000000..f595151a --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_selftest.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_selftest.c +* +* This file contains a diagnostic self-test function for the CSU_DMA driver. +* Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Constant Definitions ****************************/ + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ + + +/************************** Function Prototypes *****************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. Performs +* reset of both source and destination channels and checks if reset is working +* properly or not. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* +* @return +* - XST_SUCCESS if the self-test passed. +* - XST_FAILURE otherwise. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr) +{ + u32 Data; + s32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)); + + /* Changing Endianess of Source channel */ + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), + ((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK))); + + if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) == + (XCSUDMA_CTRL_ENDIAN_MASK)) { + Status = (s32)(XST_SUCCESS); + } + else { + Status = (s32)(XST_FAILURE); + } + + /* Changes made are being reverted back */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), Data); + + return Status; + +} diff --git a/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_sinit.c b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_sinit.c new file mode 100755 index 00000000..4dc32707 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/csudma/src/xcsudma_sinit.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_sinit.c +* +* This file contains static initialization methods for Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSUDMA_NUM_INSTANCES 1 /**< XPAR_XCSUDMA_NUM_INSTANCES */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure +* based on the unique device id, DeviceId. The return value will refer +* to an entry in the device configuration table defined in the xcsudma_g.c +* file. +* +* @param DeviceId is the unique device ID of the device for the lookup +* operation. +* +* @return CfgPtr is a reference to a config record in the configuration +* table (in xcsudma_g.c) corresponding to DeviceId, or +* NULL if no match is found. +* +* @note None. +******************************************************************************/ +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId) +{ + extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_CSUDMA_NUM_INSTANCES]; + XCsuDma_Config *CfgPtr = NULL; + u32 Index; + + /* Checks all the instances */ + for (Index = (u32)0x0; Index < (u32)(XPAR_CSUDMA_NUM_INSTANCES); + Index++) { + if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCsuDma_ConfigTable[Index]; + break; + } + } + + return (XCsuDma_Config *)CfgPtr; +}