From ab0ce936b86c212c975e080efa2230eccb23fb9c Mon Sep 17 00:00:00 2001 From: Durga challa Date: Thu, 31 Jul 2014 14:23:52 +0530 Subject: [PATCH] cresample: Added files to cresample_v4_0. Added source files,example files, Modified .tcl file. Signed-off-by: Durga challa Acked-by: Srikanth Vemula --- .../drivers/cresample/data/cresample.tcl | 9 +- .../examples/cresample_conversion_example.c | 248 ++++ .../examples/cresample_selftest_example.c | 170 +++ .../drivers/cresample/examples/example.c | 222 ---- .../drivers/cresample/src/cresample.c | 582 --------- .../drivers/cresample/src/cresample.h | 359 ------ .../drivers/cresample/src/xcresample.c | 1067 +++++++++++++++++ .../drivers/cresample/src/xcresample.h | 714 +++++++++++ .../drivers/cresample/src/xcresample_g.c | 65 + .../drivers/cresample/src/xcresample_hw.h | 552 +++++++++ .../drivers/cresample/src/xcresample_intr.c | 212 ++++ .../cresample/src/xcresample_selftest.c | 108 ++ .../drivers/cresample/src/xcresample_sinit.c | 113 ++ 13 files changed, 3256 insertions(+), 1165 deletions(-) create mode 100755 XilinxProcessorIPLib/drivers/cresample/examples/cresample_conversion_example.c create mode 100755 XilinxProcessorIPLib/drivers/cresample/examples/cresample_selftest_example.c delete mode 100755 XilinxProcessorIPLib/drivers/cresample/examples/example.c delete mode 100755 XilinxProcessorIPLib/drivers/cresample/src/cresample.c delete mode 100755 XilinxProcessorIPLib/drivers/cresample/src/cresample.h create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample.c create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample.h create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample_g.c create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample_hw.h create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample_intr.c create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample_selftest.c create mode 100755 XilinxProcessorIPLib/drivers/cresample/src/xcresample_sinit.c diff --git a/XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl b/XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl index 05754bcb..643395da 100755 --- a/XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl +++ b/XilinxProcessorIPLib/drivers/cresample/data/cresample.tcl @@ -31,7 +31,12 @@ ############################################################################### proc generate {drv_handle} { - xdefine_include_file $drv_handle "xparameters.h" "CRESAMPLE" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH" - xdefine_canonical_xpars $drv_handle "xparameters.h" "CRESAMPLE" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH" + + xdefine_include_file $drv_handle "xparameters.h" "CRESAMPLE" "NUM_INSTANCES" "C_BASEADDR" "C_HIGHADDR" "DEVICE_ID" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH" "C_S_AXI_CLK_FREQ_HZ" + + xdefine_config_file $drv_handle "xcresample_g.c" "XCresample" "DEVICE_ID" "C_BASEADDR" "C_S_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_FORMAT" "C_S_AXI_CLK_FREQ_HZ" "C_HAS_INTC_IF" "C_HAS_DEBUG" "C_MAX_COLS" "C_ACTIVE_ROWS" "C_ACTIVE_COLS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH" + + xdefine_canonical_xpars $drv_handle "xparameters.h" "CRESAMPLE" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_DATA_WIDTH" "C_S_AXIS_VIDEO_FORMAT" "C_S_AXIS_VIDEO_TDATA_WIDTH" "C_M_AXIS_VIDEO_DATA_WIDTH" "C_M_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_TDATA_WIDTH" "C_HAS_AXI4_LITE" "C_HAS_DEBUG" "C_HAS_INTC_IF" "C_MAX_COLS" "C_ACTIVE_COLS" "C_ACTIVE_ROWS" "C_CHROMA_PARITY" "C_FIELD_PARITY" "C_INTERLACED" "C_NUM_H_TAPS" "C_NUM_V_TAPS" "C_CONVERT_TYPE" "C_COEF_WIDTH" "C_S_AXI_CLK_FREQ_HZ" + } diff --git a/XilinxProcessorIPLib/drivers/cresample/examples/cresample_conversion_example.c b/XilinxProcessorIPLib/drivers/cresample/examples/cresample_conversion_example.c new file mode 100755 index 00000000..b4269cfa --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/examples/cresample_conversion_example.c @@ -0,0 +1,248 @@ +/****************************************************************************** +* +* Copyright (C)2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file cresample_conversion_example.c +* +* This file contains an example how CRESAMPLE type conversions will be done +* on the device. +* +* @note +* +* None +* +* MODIFICATION HISTORY: +* 
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 4.0   adk    03/12/14 First release.
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcresample.h" +#include "xparameters.h" +#include "xil_printf.h" +#include "stdio.h" + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define CRESAMPLE_DEVICE_ID XPAR_CRESAMPLE_0_DEVICE_ID + /**< CRESAMPLE Device ID */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +int CresampleTypeConversion(u16 DeviceId); + +/************************** Variable Definitions *****************************/ + + +XCresample Cresample; /**BaseAddress); + /* Checking status */ + if (Status != (XST_SUCCESS)) { + return (XST_FAILURE); + } + + /* For 4:4:4 to 4:2:2 conversion */ + /* + * Horizontal filter phase 0 coefficients needs to be set. + * NumHTaps should be configured to odd numbers + * (3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23). + * API used is XCresample_SetHCoefs. + */ + if ((Cresample.Config.NumHTaps % 2) != 0) { + HPhases = 0; + /* Clear all Horizontal and Vertical coefficients before setting */ + XCresample_Clear_VCoef_Values(&Cresample); + XCresample_SetHCoefs(&Cresample, &CoefH, HPhases); + } + + /* For 4:2:2 to 4:4:4 conversion */ + /* + * Horizontal filter phase 1 coefficients needs to be set. + * NumHTaps should be configured to even numbers + * (2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24). + * API used is XCresample_SetHCoefs. + */ + if ((Cresample.Config.NumHTaps % 2) == 0) { + HPhases = 1; + /* Clear all Horizontal and Vertical coefficients before setting */ + XCresample_Clear_VCoef_Values(&Cresample); + XCresample_SetHCoefs(&Cresample, &CoefH, HPhases); + } + + /* For 4:2:2 to 4:2:0 conversion */ + /* + * Vertical filter phase 0 coefficients needs to be set. + * NumVTaps should be configured to even numbers(2, 4, 6, 8). + * API used is XCresample_SetVCoefs. + */ + if ((Cresample.Config.NumVTaps % 2) == 0) { + VPhases = 0; + /* Clear all Horizontal and Vertical coefficients before setting */ + XCresample_Clear_HCoef_Values(&Cresample); + XCresample_SetVCoefs(&Cresample, &CoefV, VPhases); + } + + /* For 4:2:0 to 4:2:2 conversion */ + /* + * Vertical filter phase 1 coefficients needs to be set. + * NumVTaps should be configured to even numbers(2, 4, 6, 8). + * API used is XCresample_SetVCoefs. + */ + if ((Cresample.Config.NumVTaps % 2) == 0) { + VPhases = 0; + /* Clear all Horizontal and Vertical coefficients before setting */ + XCresample_Clear_HCoef_Values(&Cresample); + XCresample_SetVCoefs(&Cresample, &CoefV, VPhases); + } + + /* For 4:4:4 to 4:2:0 conversion */ + /* + * Vertical filter phase 0 and Horizontal filter phase 0 + * coefficients needs to be set. + * NumVTaps should be configured to even numbers(2, 4, 6, 8). + * NumHTaps should be configured to odd numbers + * (3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23). + * APIs used are XCresample_SetHCoefs and XCresample_SetVCoefs. + */ + if (((Cresample.Config.NumVTaps % 2) == 0) && + ((Cresample.Config.NumHTaps % 2) != 0)) { + VPhases = 0; + HPhases = 0; + XCresample_SetHCoefs(&Cresample, &CoefH, HPhases); + XCresample_SetVCoefs(&Cresample, &CoefV, VPhases); + } + + /* For 4:2:0 to 4:4:4 conversion */ + /* + * Vertical filter phase 0 and 1 and Horizontal filter phase 1 + * coefficients needs to be set. + * NumVTaps should be configured to even numbers(2, 4, 6, 8). + * NumHTaps should be configured to even numbers + * (2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24). + * APIs used are XCresample_SetHCoefs and XCresample_SetVCoefs. + */ + if (((Cresample.Config.NumVTaps % 2) == 0) && + ((Cresample.Config.NumHTaps % 2) == 0)) { + VPhases = 2; + HPhases = 1; + XCresample_SetHCoefs(&Cresample, &CoefH, HPhases); + XCresample_SetVCoefs(&Cresample, &CoefV, VPhases); + } + + return (XST_SUCCESS); + +} diff --git a/XilinxProcessorIPLib/drivers/cresample/examples/cresample_selftest_example.c b/XilinxProcessorIPLib/drivers/cresample/examples/cresample_selftest_example.c new file mode 100755 index 00000000..cbb6cd1d --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/examples/cresample_selftest_example.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* +* Copyright (C)2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file cresample_selftest_example.c +* +* This file contains an example using the XCRESAMPLE driver to do self test +* on the device. +* +* @note +* +* None +* +* MODIFICATION HISTORY: +* 
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 4.0   adk    03/12/14 First release.
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcresample.h" +#include "xparameters.h" +#include "xil_printf.h" + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define CRESAMPLE_DEVICE_ID XPAR_CRESAMPLE_0_DEVICE_ID + /**< CRESAMPLE Device ID */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ + +/************************** Function Prototypes ******************************/ + + +int XCresampleSelfTestExample(u16 DeviceId); + +/************************** Variable Definitions *****************************/ + + +XCresample Cresample; /**_DEVICE_ID value from +* xparameters.h. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if failed. +* +* @note None. +* +******************************************************************************/ +int XCresampleSelfTestExample(u16 DeviceId) +{ + int Status; + XCresample_Config *Config; + + /* + * Initialize the CRESAMPLE driver so that it's ready to use + * Look up the configuration in the config table, + * then initialize it. + */ + Config = XCresample_LookupConfig(DeviceId); + + /* Checking Config variable */ + if (NULL == Config) { + return (XST_FAILURE); + } + + Status = XCresample_CfgInitialize(&Cresample, Config, + Config->BaseAddress); + /* Checking status */ + if (Status != (XST_SUCCESS)) { + return (XST_FAILURE); + } + + /* + * Perform a self-test to check hardware build. + */ + Status = XCresample_SelfTest(&Cresample); + + /* Checking status */ + if (Status != (XST_SUCCESS)) { + return (XST_FAILURE); + } + + return (XST_SUCCESS); + +} diff --git a/XilinxProcessorIPLib/drivers/cresample/examples/example.c b/XilinxProcessorIPLib/drivers/cresample/examples/example.c deleted file mode 100755 index 1520bdca..00000000 --- a/XilinxProcessorIPLib/drivers/cresample/examples/example.c +++ /dev/null @@ -1,222 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file example.c - * - * This file demonstrates how to use Xilinx Chroma Resampler (cresample) - * driver of the Xilinx Chroma Resampler core. This code does not - * cover the core setup and any other configuration which might be - * required to get the Chroma Resampler device working properly. - * - * 
- * MODIFICATION HISTORY:
- *
- * Ver   Who  Date     Changes
- * ----- ---- -------- -------------------------------------------------------
- * 2.00a vc   04/24/12 Updated for v2.00.a
- * 2.00a vc   10/16/12 Switched from Xuint32 to u32
- *                     Renamed example function to main()
- *                     Renamed reference to XPAR_CRESAMPLE_0_BASEADDR
- *
- * - * *************************************************************************** - */ - -#include "cresample.h" -#include "xparameters.h" - -/***************************************************************************/ -// Chroma Resampler Register Reading Example -// This function provides an example of how to read the current configuration -// settings of the Chroma Resampler core. -/***************************************************************************/ -void report_cresample_settings(u32 BaseAddress) { - - u32 reg_val; - unsigned char inchar=0; - - xil_printf("Chroma Resampler Core Configuration:\r\n"); - xil_printf(" Enable Bit: %1d\r\n", CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & CRESAMPLE_CTL_EN_MASK); - xil_printf(" Register Update Bit: %1d\r\n", (CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & CRESAMPLE_CTL_RU_MASK) >> 1); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL ); - xil_printf("CRESAMPLE_CONTROL : %8x\r\n", reg_val); - - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0 ); - xil_printf("CRESAMPLE6_COEF00_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0 ); - xil_printf("CRESAMPLE_COEF01_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0 ); - xil_printf("CRESAMPLE_COEF02_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0 ); - xil_printf("CRESAMPLE_COEF03_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0 ); - xil_printf("CRESAMPLE_COEF04_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0 ); - xil_printf("CRESAMPLECOEF05_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0 ); - xil_printf("CRESAMPLE_COEF06_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0 ); - xil_printf("CRESAMPLE_COEF07_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0 ); - xil_printf("CRESAMPLE_COEF08_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0 ); - xil_printf("CRESAMPLE_COEF09_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0 ); - xil_printf("CRESAMPLE_COEF10_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0 ); - xil_printf("CRESAMPLE_COEF11_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0 ); - xil_printf("CRESAMPLE_COEF12_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0 ); - xil_printf("CRESAMPLE_COEF13_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0 ); - xil_printf("CRESAMPLE_COEF14_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0 ); - xil_printf("CRESAMPLE_COEF15_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0 ); - xil_printf("CRESAMPLE_COEF16_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0 ); - xil_printf("CRESAMPLE_COEF17_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0 ); - xil_printf("CRESAMPLE_COEF18_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0 ); - xil_printf("CRESAMPLE_COEF19_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0 ); - xil_printf("CRESAMPLE_COEF20_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0 ); - xil_printf("CRESAMPLE_COEF21_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0 ); - xil_printf("CRESAMPLE_COEF22_HPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0 ); - xil_printf("CRESAMPLE_COEF23_HPHASE0 : %8d\r\n", reg_val); - - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1 ); - xil_printf("CRESAMPLE_COEF00_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1 ); - xil_printf("CRESAMPLE_COEF01_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1 ); - xil_printf("CRESAMPLE_COEF02_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1 ); - xil_printf("CRESAMPLE_COEF03_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1 ); - xil_printf("CRESAMPLE_COEF04_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1 ); - xil_printf("CRESAMPLE_COEF05_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1 ); - xil_printf("CRESAMPLE_COEF06_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1 ); - xil_printf("CRESAMPLE_COEF07_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1 ); - xil_printf("CRESAMPLE_COEF08_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1 ); - xil_printf("CRESAMPLE_COEF09_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1 ); - xil_printf("CRESAMPLE_COEF10_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1 ); - xil_printf("CRESAMPLE_COEF11_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1 ); - xil_printf("CRESAMPLE_COEF12_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1 ); - xil_printf("CRESAMPLE_COEF13_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1 ); - xil_printf("CRESAMPLE_COEF14_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1 ); - xil_printf("CRESAMPLE_COEF15_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1 ); - xil_printf("CRESAMPLE_COEF16_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1 ); - xil_printf("CRESAMPLE_COEF17_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1 ); - xil_printf("CRESAMPLE_COEF18_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1 ); - xil_printf("CRESAMPLE_COEF19_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1 ); - xil_printf("CRESAMPLE_COEF20_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1 ); - xil_printf("CRESAMPLE_COEF21_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1 ); - xil_printf("CRESAMPLE_COEF22_HPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1 ); - xil_printf("CRESAMPLE_COEF23_HPHASE1 : %8d\r\n", reg_val); - - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0 ); - xil_printf("CRESAMPLE_COEF00_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0 ); - xil_printf("CRESAMPLE_COEF01_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0 ); - xil_printf("CRESAMPLE_COEF02_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0 ); - xil_printf("CRESAMPLE_COEF03_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0 ); - xil_printf("CRESAMPLE_COEF04_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0 ); - xil_printf("CRESAMPLE_COEF05_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0 ); - xil_printf("CRESAMPLE_COEF06_VPHASE0 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0 ); - xil_printf("CRESAMPLE_COEF07_VPHASE0 : %8d\r\n", reg_val); - - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1 ); - xil_printf("CRESAMPLE_COEF00_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1 ); - xil_printf("CRESAMPLE_COEF01_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1 ); - xil_printf("CRESAMPLE_COEF02_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1 ); - xil_printf("CRESAMPLE_COEF03_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1 ); - xil_printf("CRESAMPLE_COEF04_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1 ); - xil_printf("CRESAMPLE_COEF05_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1 ); - xil_printf("CRESAMPLE_COEF06_VPHASE1 : %8d\r\n", reg_val); - reg_val = CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1 ); - xil_printf("CRESAMPLE_COEF07_VPHASE1 : %8d\r\n", reg_val); - - xil_printf("Press Space to continue!\r\n", reg_val); - while (inchar != ' ') inchar = inbyte(); -} - -/*****************************************************************************/ -// -// This is the main function for the Chroma Resampler example. -// -/*****************************************************************************/ -int main(void) -{ - //Print the current settings for the Chroma Resampler core - report_cresample_settings(XPAR_CRESAMPLE_0_BASEADDR); - - return 0; -} diff --git a/XilinxProcessorIPLib/drivers/cresample/src/cresample.c b/XilinxProcessorIPLib/drivers/cresample/src/cresample.c deleted file mode 100755 index 2d3a4b47..00000000 --- a/XilinxProcessorIPLib/drivers/cresample/src/cresample.c +++ /dev/null @@ -1,582 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -/** -* -* @file cresample.c -* -* This is main code of Xilinx Chroma Resampler (CRESAMPLE) -* device driver. Please see cresample.h for more details of the driver. -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a gaborz 08/04/11 Updated for CRESAMPLE V1.0 -* 2.00a vyc 04/24/12 Updated for CRESAMPLE V2.00.a -* 2.00a vyc 07/25/12 Switched from Xuint32 to u32 -* 2.00a vyc 10/16/12 Switch order of functions to remove compile warning -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "cresample.h" -#include "xenv.h" - -/*****************************************************************************/ -// Note: Many functions are currently implemented as high-performance macros -// within cresample.h -/*****************************************************************************/ - -void clear_coef_values(u32 BaseAddress) -{ - // set all coefficient values to 0 - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, 0); - - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, 0); - - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, 0); - - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, 0); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, 0); -} - -void configure_444_to_422(u32 BaseAddress, int NUM_H_TAPS, int *coef_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_H_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, coef_vector[0]); - } - if (NUM_H_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, coef_vector[1]); - } - if (NUM_H_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, coef_vector[2]); - } - if (NUM_H_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, coef_vector[3]); - } - if (NUM_H_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, coef_vector[4]); - } - if (NUM_H_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, coef_vector[5]); - } - if (NUM_H_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, coef_vector[6]); - } - if (NUM_H_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, coef_vector[7]); - } - if (NUM_H_TAPS > 8) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, coef_vector[8]); - } - if (NUM_H_TAPS > 9) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, coef_vector[9]); - } - if (NUM_H_TAPS > 10) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, coef_vector[10]); - } - if (NUM_H_TAPS > 11) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, coef_vector[11]); - } - if (NUM_H_TAPS > 12) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, coef_vector[12]); - } - if (NUM_H_TAPS > 13) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, coef_vector[13]); - } - if (NUM_H_TAPS > 14) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, coef_vector[14]); - } - if (NUM_H_TAPS > 15) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, coef_vector[15]); - } - if (NUM_H_TAPS > 16) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, coef_vector[16]); - } - if (NUM_H_TAPS > 17) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, coef_vector[17]); - } - if (NUM_H_TAPS > 18) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, coef_vector[18]); - } - if (NUM_H_TAPS > 19) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, coef_vector[19]); - } - if (NUM_H_TAPS > 20) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, coef_vector[20]); - } - if (NUM_H_TAPS > 21) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, coef_vector[21]); - } - if (NUM_H_TAPS > 22) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, coef_vector[22]); - } - if (NUM_H_TAPS > 23) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, coef_vector[23]); - } -} - -void configure_422_to_444(u32 BaseAddress, int NUM_H_TAPS, int *coef_phase1_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_H_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, coef_phase1_vector[0]); - } - if (NUM_H_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, coef_phase1_vector[1]); - } - if (NUM_H_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, coef_phase1_vector[2]); - } - if (NUM_H_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, coef_phase1_vector[3]); - } - if (NUM_H_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, coef_phase1_vector[4]); - } - if (NUM_H_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, coef_phase1_vector[5]); - } - if (NUM_H_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, coef_phase1_vector[6]); - } - if (NUM_H_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, coef_phase1_vector[7]); - } - if (NUM_H_TAPS > 8) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, coef_phase1_vector[8]); - } - if (NUM_H_TAPS > 9) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, coef_phase1_vector[9]); - } - if (NUM_H_TAPS > 10) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, coef_phase1_vector[10]); - } - if (NUM_H_TAPS > 11) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, coef_phase1_vector[11]); - } - if (NUM_H_TAPS > 12) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, coef_phase1_vector[12]); - } - if (NUM_H_TAPS > 13) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, coef_phase1_vector[13]); - } - if (NUM_H_TAPS > 14) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, coef_phase1_vector[14]); - } - if (NUM_H_TAPS > 15) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, coef_phase1_vector[15]); - } - if (NUM_H_TAPS > 16) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, coef_phase1_vector[16]); - } - if (NUM_H_TAPS > 17) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, coef_phase1_vector[17]); - } - if (NUM_H_TAPS > 18) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, coef_phase1_vector[18]); - } - if (NUM_H_TAPS > 19) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, coef_phase1_vector[19]); - } - if (NUM_H_TAPS > 20) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, coef_phase1_vector[20]); - } - if (NUM_H_TAPS > 21) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, coef_phase1_vector[21]); - } - if (NUM_H_TAPS > 22) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, coef_phase1_vector[22]); - } - if (NUM_H_TAPS > 23) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, coef_phase1_vector[23]); - } -} - -void configure_422_to_420(u32 BaseAddress, int NUM_V_TAPS, int *coef_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_V_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, coef_vector[0]); - } - if (NUM_V_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, coef_vector[1]); - } - if (NUM_V_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, coef_vector[2]); - } - if (NUM_V_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, coef_vector[3]); - } - if (NUM_V_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, coef_vector[4]); - } - if (NUM_V_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, coef_vector[5]); - } - if (NUM_V_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, coef_vector[6]); - } - if (NUM_V_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, coef_vector[7]); - } -} - -void configure_420_to_422(u32 BaseAddress, int NUM_V_TAPS, int *coef_phase0_vector, int *coef_phase1_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_V_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, coef_phase0_vector[0]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, coef_phase1_vector[0]); - } - if (NUM_V_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, coef_phase0_vector[1]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, coef_phase1_vector[1]); - } - if (NUM_V_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, coef_phase0_vector[2]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, coef_phase1_vector[2]); - } - if (NUM_V_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, coef_phase0_vector[3]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, coef_phase1_vector[3]); - } - if (NUM_V_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, coef_phase0_vector[4]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, coef_phase1_vector[4]); - } - if (NUM_V_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, coef_phase0_vector[5]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, coef_phase1_vector[5]); - } - if (NUM_V_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, coef_phase0_vector[6]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, coef_phase1_vector[6]); - } - if (NUM_V_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, coef_phase0_vector[7]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, coef_phase1_vector[7]); - } -} - -void configure_444_to_420(u32 BaseAddress, int NUM_H_TAPS, int NUM_V_TAPS, int *hcoef_vector, int *vcoef_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_H_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE0, hcoef_vector[0]); - } - if (NUM_H_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE0, hcoef_vector[1]); - } - if (NUM_H_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE0, hcoef_vector[2]); - } - if (NUM_H_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE0, hcoef_vector[3]); - } - if (NUM_H_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE0, hcoef_vector[4]); - } - if (NUM_H_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE0, hcoef_vector[5]); - } - if (NUM_H_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE0, hcoef_vector[6]); - } - if (NUM_H_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE0, hcoef_vector[7]); - } - if (NUM_H_TAPS > 8) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE0, hcoef_vector[8]); - } - if (NUM_H_TAPS > 9) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE0, hcoef_vector[9]); - } - if (NUM_H_TAPS > 10) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE0, hcoef_vector[10]); - } - if (NUM_H_TAPS > 11) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE0, hcoef_vector[11]); - } - if (NUM_H_TAPS > 12) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE0, hcoef_vector[12]); - } - if (NUM_H_TAPS > 13) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE0, hcoef_vector[13]); - } - if (NUM_H_TAPS > 14) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE0, hcoef_vector[14]); - } - if (NUM_H_TAPS > 15) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE0, hcoef_vector[15]); - } - if (NUM_H_TAPS > 16) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE0, hcoef_vector[16]); - } - if (NUM_H_TAPS > 17) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE0, hcoef_vector[17]); - } - if (NUM_H_TAPS > 18) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE0, hcoef_vector[18]); - } - if (NUM_H_TAPS > 19) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE0, hcoef_vector[19]); - } - if (NUM_H_TAPS > 20) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE0, hcoef_vector[20]); - } - if (NUM_H_TAPS > 21) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE0, hcoef_vector[21]); - } - if (NUM_H_TAPS > 22) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE0, hcoef_vector[22]); - } - if (NUM_H_TAPS > 23) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE0, hcoef_vector[23]); - } - - if (NUM_V_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, vcoef_vector[0]); - } - if (NUM_V_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, vcoef_vector[1]); - } - if (NUM_V_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, vcoef_vector[2]); - } - if (NUM_V_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, vcoef_vector[3]); - } - if (NUM_V_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, vcoef_vector[4]); - } - if (NUM_V_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, vcoef_vector[5]); - } - if (NUM_V_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, vcoef_vector[6]); - } - if (NUM_V_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, vcoef_vector[7]); - } -} - -void configure_420_to_444(u32 BaseAddress, int NUM_H_TAPS, int NUM_V_TAPS, int *hcoef_phase1_vector, int *vcoef_phase0_vector, int *vcoef_phase1_vector ) -{ - // clear out existing coefficient register values - clear_coef_values(BaseAddress); - - // set new coefficient register values from coef_vector - if (NUM_V_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE0, vcoef_phase0_vector[0]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_VPHASE1, vcoef_phase1_vector[0]); - } - if (NUM_V_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE0, vcoef_phase0_vector[1]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_VPHASE1, vcoef_phase1_vector[1]); - } - if (NUM_V_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE0, vcoef_phase0_vector[2]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_VPHASE1, vcoef_phase1_vector[2]); - } - if (NUM_V_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE0, vcoef_phase0_vector[3]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_VPHASE1, vcoef_phase1_vector[3]); - } - if (NUM_V_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE0, vcoef_phase0_vector[4]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_VPHASE1, vcoef_phase1_vector[4]); - } - if (NUM_V_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE0, vcoef_phase0_vector[5]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_VPHASE1, vcoef_phase1_vector[5]); - } - if (NUM_V_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE0, vcoef_phase0_vector[6]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_VPHASE1, vcoef_phase1_vector[6]); - } - if (NUM_V_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE0, vcoef_phase0_vector[7]); - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_VPHASE1, vcoef_phase1_vector[7]); - } - - if (NUM_H_TAPS > 0) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF00_HPHASE1, hcoef_phase1_vector[0]); - } - if (NUM_H_TAPS > 1) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF01_HPHASE1, hcoef_phase1_vector[1]); - } - if (NUM_H_TAPS > 2) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF02_HPHASE1, hcoef_phase1_vector[2]); - } - if (NUM_H_TAPS > 3) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF03_HPHASE1, hcoef_phase1_vector[3]); - } - if (NUM_H_TAPS > 4) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF04_HPHASE1, hcoef_phase1_vector[4]); - } - if (NUM_H_TAPS > 5) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF05_HPHASE1, hcoef_phase1_vector[5]); - } - if (NUM_H_TAPS > 6) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF06_HPHASE1, hcoef_phase1_vector[6]); - } - if (NUM_H_TAPS > 7) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF07_HPHASE1, hcoef_phase1_vector[7]); - } - if (NUM_H_TAPS > 8) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF08_HPHASE1, hcoef_phase1_vector[8]); - } - if (NUM_H_TAPS > 9) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF09_HPHASE1, hcoef_phase1_vector[9]); - } - if (NUM_H_TAPS > 10) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF10_HPHASE1, hcoef_phase1_vector[10]); - } - if (NUM_H_TAPS > 11) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF11_HPHASE1, hcoef_phase1_vector[11]); - } - if (NUM_H_TAPS > 12) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF12_HPHASE1, hcoef_phase1_vector[12]); - } - if (NUM_H_TAPS > 13) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF13_HPHASE1, hcoef_phase1_vector[13]); - } - if (NUM_H_TAPS > 14) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF14_HPHASE1, hcoef_phase1_vector[14]); - } - if (NUM_H_TAPS > 15) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF15_HPHASE1, hcoef_phase1_vector[15]); - } - if (NUM_H_TAPS > 16) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF16_HPHASE1, hcoef_phase1_vector[16]); - } - if (NUM_H_TAPS > 17) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF17_HPHASE1, hcoef_phase1_vector[17]); - } - if (NUM_H_TAPS > 18) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF18_HPHASE1, hcoef_phase1_vector[18]); - } - if (NUM_H_TAPS > 19) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF19_HPHASE1, hcoef_phase1_vector[19]); - } - if (NUM_H_TAPS > 20) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF20_HPHASE1, hcoef_phase1_vector[20]); - } - if (NUM_H_TAPS > 21) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF21_HPHASE1, hcoef_phase1_vector[21]); - } - if (NUM_H_TAPS > 22) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF22_HPHASE1, hcoef_phase1_vector[22]); - } - if (NUM_H_TAPS > 23) { - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_COEF23_HPHASE1, hcoef_phase1_vector[23]); - } -} - diff --git a/XilinxProcessorIPLib/drivers/cresample/src/cresample.h b/XilinxProcessorIPLib/drivers/cresample/src/cresample.h deleted file mode 100755 index 11db20a3..00000000 --- a/XilinxProcessorIPLib/drivers/cresample/src/cresample.h +++ /dev/null @@ -1,359 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -/** -* -* @file cresample.h -* -* This header file contains identifiers and register-level driver functions (or -* macros) that can be used to access the Xilinx Chroma Resampler core instance. -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 2.00a vy 04/24/12 Updated for version 2.00.a -* Converted from xio.h to xil_io.h, translating -* basic type, MB cache functions, exceptions and -* assertion to xil_io format. -* 1.00a vy 10/22/10 Initial version -* 3.0 adk 19/12/13 Updated as per the New Tcl API's -* -******************************************************************************/ - -#ifndef CRESAMPLE_DRIVER_H /* prevent circular inclusions */ -#define CRESAMPLE_DRIVER_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** - * Register Offsets - */ -/* General Control Registers */ -#define CRESAMPLE_CONTROL 0x0000 /**< Control */ -#define CRESAMPLE_STATUS 0x0004 /**< Status */ -#define CRESAMPLE_ERROR 0x0008 /**< Error */ -#define CRESAMPLE_IRQ_ENABLE 0x000C /**< IRQ Enable */ -#define CRESAMPLE_VERSION 0x0010 /**< Version */ -#define CRESAMPLE_SYSDEBUG0 0x0014 /**< System Debug 0 */ -#define CRESAMPLE_SYSDEBUG1 0x0018 /**< System Debug 1 */ -#define CRESAMPLE_SYSDEBUG2 0x001C /**< System Debug 2 */ -/* Timing Control Registers */ -#define CRESAMPLE_ACTIVE_SIZE 0x0020 /**< Horizontal and Vertical Active Frame Size */ -#define CRESAMPLE_ENCODING 0x0028 /**< Frame Encoding */ -/* Core Specific Registers */ -#define CRESAMPLE_COEF00_HPHASE0 0x0100 /**< Coefficient 00 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF01_HPHASE0 0x0104 /**< Coefficient 01 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF02_HPHASE0 0x0108 /**< Coefficient 02 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF03_HPHASE0 0x010C /**< Coefficient 03 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF04_HPHASE0 0x0110 /**< Coefficient 04 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF05_HPHASE0 0x0114 /**< Coefficient 05 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF06_HPHASE0 0x0118 /**< Coefficient 06 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF07_HPHASE0 0x011C /**< Coefficient 07 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF08_HPHASE0 0x0120 /**< Coefficient 08 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF09_HPHASE0 0x0124 /**< Coefficient 09 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF10_HPHASE0 0x0128 /**< Coefficient 10 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF11_HPHASE0 0x012C /**< Coefficient 11 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF12_HPHASE0 0x0130 /**< Coefficient 12 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF13_HPHASE0 0x0134 /**< Coefficient 13 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF14_HPHASE0 0x0138 /**< Coefficient 14 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF15_HPHASE0 0x013C /**< Coefficient 15 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF16_HPHASE0 0x0140 /**< Coefficient 16 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF17_HPHASE0 0x0144 /**< Coefficient 17 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF18_HPHASE0 0x0148 /**< Coefficient 18 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF19_HPHASE0 0x014C /**< Coefficient 19 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF20_HPHASE0 0x0150 /**< Coefficient 20 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF21_HPHASE0 0x0154 /**< Coefficient 21 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF22_HPHASE0 0x0158 /**< Coefficient 22 of Horizontal Phase 0 Filter */ -#define CRESAMPLE_COEF23_HPHASE0 0x015C /**< Coefficient 23 of Horizontal Phase 0 Filter */ - -#define CRESAMPLE_COEF00_HPHASE1 0x0160 /**< Coefficient 00 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF01_HPHASE1 0x0164 /**< Coefficient 01 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF02_HPHASE1 0x0168 /**< Coefficient 02 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF03_HPHASE1 0x016C /**< Coefficient 03 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF04_HPHASE1 0x0170 /**< Coefficient 04 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF05_HPHASE1 0x0174 /**< Coefficient 05 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF06_HPHASE1 0x0178 /**< Coefficient 06 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF07_HPHASE1 0x017C /**< Coefficient 07 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF08_HPHASE1 0x0180 /**< Coefficient 08 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF09_HPHASE1 0x0184 /**< Coefficient 09 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF10_HPHASE1 0x0188 /**< Coefficient 10 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF11_HPHASE1 0x018C /**< Coefficient 11 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF12_HPHASE1 0x0190 /**< Coefficient 12 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF13_HPHASE1 0x0194 /**< Coefficient 13 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF14_HPHASE1 0x0198 /**< Coefficient 14 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF15_HPHASE1 0x019C /**< Coefficient 15 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF16_HPHASE1 0x01A0 /**< Coefficient 16 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF17_HPHASE1 0x01A4 /**< Coefficient 17 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF18_HPHASE1 0x01A8 /**< Coefficient 18 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF19_HPHASE1 0x01AC /**< Coefficient 19 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF20_HPHASE1 0x01B0 /**< Coefficient 20 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF21_HPHASE1 0x01B4 /**< Coefficient 21 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF22_HPHASE1 0x01B8 /**< Coefficient 22 of Horizontal Phase 1 Filter */ -#define CRESAMPLE_COEF23_HPHASE1 0x01BC /**< Coefficient 23 of Horizontal Phase 1 Filter */ - -#define CRESAMPLE_COEF00_VPHASE0 0x01C0 /**< Coefficient 00 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF01_VPHASE0 0x01C4 /**< Coefficient 01 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF02_VPHASE0 0x01C8 /**< Coefficient 02 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF03_VPHASE0 0x01CC /**< Coefficient 03 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF04_VPHASE0 0x01D0 /**< Coefficient 04 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF05_VPHASE0 0x01D4 /**< Coefficient 05 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF06_VPHASE0 0x01D8 /**< Coefficient 06 of Vertical Phase 0 Filter */ -#define CRESAMPLE_COEF07_VPHASE0 0x01DC /**< Coefficient 07 of Vertical Phase 0 Filter */ - -#define CRESAMPLE_COEF00_VPHASE1 0x01E0 /**< Coefficient 00 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF01_VPHASE1 0x01E4 /**< Coefficient 01 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF02_VPHASE1 0x01E8 /**< Coefficient 02 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF03_VPHASE1 0x01EC /**< Coefficient 03 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF04_VPHASE1 0x01F0 /**< Coefficient 04 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF05_VPHASE1 0x01F4 /**< Coefficient 05 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF06_VPHASE1 0x01F8 /**< Coefficient 06 of Vertical Phase 1 Filter */ -#define CRESAMPLE_COEF07_VPHASE1 0x01FC /**< Coefficient 07 of Vertical Phase 1 Filter */ - -/*****************************************************************************/ -/** - * Control Register bit definition - */ -#define CRESAMPLE_CTL_EN_MASK 0x00000001 /**< Enable */ -#define CRESAMPLE_CTL_RU_MASK 0x00000002 /**< Register Update */ -#define CRESAMPLE_CTL_AUTORESET 0x40000000 /**< Software Reset - Auto-synchronize to SOF */ -#define CRESAMPLE_CTL_RESET 0x80000000 /**< Software Reset - Instantaneous */ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define CRESAMPLE_In32 Xil_In32 -#define CRESAMPLE_Out32 Xil_Out32 - -/*****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* @param RegOffset is the register offset of the register (defined at top of this file) -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 CRESAMPLE_ReadReg(u32 BaseAddress, u32 RegOffset) -* -******************************************************************************/ -#define CRESAMPLE_ReadReg(BaseAddress, RegOffset) \ - CRESAMPLE_In32((BaseAddress) + (RegOffset)) - -/*****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* @param RegOffset is the register offset of the register (defined at top of this file) -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* -******************************************************************************/ -#define CRESAMPLE_WriteReg(BaseAddress, RegOffset, Data) \ - CRESAMPLE_Out32((BaseAddress) + (RegOffset), (Data)) - -/*****************************************************************************/ -/** -* -* This macro enables a Chroma Resampler core instance. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_Enable(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_Enable(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \ - CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) | \ - CRESAMPLE_CTL_EN_MASK) - -/*****************************************************************************/ -/** -* -* This macro disables a Chroma Resampler core instance. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_Disable(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_Disable(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \ - CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & \ - ~CRESAMPLE_CTL_EN_MASK) - -/*****************************************************************************/ -/** -* -* This macro commits all the register value changes made so far by the software -* to the Chroma Resampler core instance. The registers will be automatically updated -* on the next rising-edge of the SOF signal on the core. -* It is up to the user to manually disable the register update after a sufficient -* amount of time. -* -* This function only works when the Chroma Resampler core is enabled. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_RegUpdateEnable(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_RegUpdateEnable(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \ - CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) | \ - CRESAMPLE_CTL_RU_MASK) - -/*****************************************************************************/ -/** -* -* This macro prevents the Chroma Resampler core instance from committing recent changes made -* so far by the software. When disabled, changes to other configuration registers -* are stored, but do not effect the behavior of the core. -* -* This function only works when the Chroma Resampler core is enabled. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_RegUpdateDisable(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_RegUpdateDisable(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, \ - CRESAMPLE_ReadReg(BaseAddress, CRESAMPLE_CONTROL) & \ - ~CRESAMPLE_CTL_RU_MASK) - -/*****************************************************************************/ - -/** -* -* This macro resets a Chroma Resampler core instance. This reset effects the core immediately, -* and may cause image tearing. -* -* This reset resets the Chroma Resampler's configuration registers, and holds the core's outputs -* in their reset state until CRESAMPLE_ClearReset() is called. -* -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_Reset(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_Reset(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, CRESAMPLE_CTL_RESET) \ - -/*****************************************************************************/ -/** -* -* This macro clears the Chroma Resampler's reset flag (which is set using CRESAMPLE_Reset(), and -* returns it to normal operation. This ClearReset effects the core immediately, -* and may cause image tearing. -* -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_ClearReset(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_ClearReset(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, 0) \ - -/*****************************************************************************/ -/** -* -* This macro resets a Chroma Resampler core instance, but differs from CRESAMPLE_Reset() in that it -* automatically synchronizes to the SOF input of the core to prevent tearing. -* -* On the next SOF following a call to CRESAMPLE_AutoSyncReset(), -* all of the core's configuration registers and outputs will be reset, then the -* reset flag will be immediately released, allowing the core to immediately resume -* default operation. -* -* @param BaseAddress is the Xilinx EDK base address of the Chroma Resampler core (from xparameters.h) -* -* @return None. -* -* @note -* C-style signature: -* void CRESAMPLE_AutoSyncReset(u32 BaseAddress); -* -******************************************************************************/ -#define CRESAMPLE_AutoSyncReset(BaseAddress) \ - CRESAMPLE_WriteReg(BaseAddress, CRESAMPLE_CONTROL, CRESAMPLE_CTL_AUTORESET) \ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample.c b/XilinxProcessorIPLib/drivers/cresample/src/xcresample.c new file mode 100755 index 00000000..fdbb58fa --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample.c @@ -0,0 +1,1067 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample.c +* +* This file contains the implementation of the interface functions for the +* Chroma Resampler core. Refer to the header file xcresample.h for more +* detailed information. +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------------
+* 1.00a gaborz 08/04/11 Updated for CRESAMPLE V1.0
+* 2.00a vyc    04/24/12 Updated for CRESAMPLE V2.00.a
+* 2.00a vyc    07/25/12 Switched from Xuu3232 to u32
+* 2.00a vyc    10/16/12 Switch order of functions to remove compile warning
+* 4.0   adk    03/12/14 Changed the filename cresample.c to xcresample.c.
+*                       The Following functions are removed:
+*                       clear_coef_values, configure_444_to_422,
+*                       configure_422_to_444, configure_422_to_420,
+*                       configure_420_to_422, configure_444_to_420 and
+*                       configure_420_to_444.
+*                       Implemented the following functions :
+*                       StubCallBack, StubErrorCallBack,
+*                       XCresample_CfgInitialize,
+*                       XCresample_GetVersion, XCresample_EnableDbgByPass,
+*                       XCresample_IsDbgByPassEnabled,
+*                       XCresample_DisableDbgByPass,
+*                       XCresample_SetDbgTestPattern,
+*                       XCresample_IsDbgTestPatternEnabled,
+*                       XCresample_DisableDbgTestPattern
+*                       XCresample_GetDbgFrameCount,
+*                       XCresample_GetDbgLineCount,
+*                       XCresample_GetDbgPixelCount,
+*                       XCresample_SetActiveSize, XCresample_GetActiveSize,
+*                       XCresample_SetFieldParity, XCresample_GetFieldParity,
+*                       XCresample_SetChromaParity,
+*                       XCresample_GetChromaParity
+*                       XCresample_SetHCoefs, XCresample_GetHCoefs,
+*                       XCresample_SetVCoefs, XCresample_GetVCoefs,
+*                       XCresample_Clear_HCoef_Values, and
+*                       XCresample_Clear_VCoef_Values.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcresample.h" + +/************************** Constant Definitions *****************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + +static void StubCallBack(void *CallBackRef); +static void StubErrCallBack(void *CallBackRef, u32 ErrorMask); +static float XCresample_FixedToFloatConv(u32 Input); +static s32 XCresample_FloatToFixedConv(float Input); + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes the Cresample core. This function must be called +* prior to using the Cresample core. Initialization of the Cresample includes +* setting up the instance data and ensuring the hardware is in a quiescent +* state. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param CfgPtr is a reference to a structure containing information +* about a specific Chroma Resampler driver. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical base +* address unchanged once this function is invoked. Unexpected +* errors may occur if the address mapping changes after this +* function is called. If address translation is not used, pass in +* the physical address instead. +* +* @return - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +int XCresample_CfgInitialize(XCresample *InstancePtr, + XCresample_Config *CfgPtr, u32 EffectiveAddr) +{ + /* Verify arguments. */ + Xil_AssertNonvoid(CfgPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0)); + + /* Setup the instance */ + (void)memset((void *)InstancePtr, 0, sizeof(XCresample)); + (void)memcpy((void *)(&(InstancePtr->Config)), (const void *)CfgPtr, + sizeof(XCresample_Config)); + InstancePtr->Config.BaseAddress = EffectiveAddr; + + /* + * Set all handlers to stub values, let user configure this data later. + */ + InstancePtr->ProcStartCallBack = + (XCresample_CallBack)((void *)StubCallBack); + InstancePtr->FrameDoneCallBack = + (XCresample_CallBack)((void *)StubCallBack); + InstancePtr->ErrCallBack = + (XCresample_ErrorCallBack)((void *)StubErrCallBack); + + /* + * Reset the hardware and set the flag to indicate the driver is + * ready. + */ + XCresample_Reset(InstancePtr); + InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); + + return (XST_SUCCESS); +} + +/*****************************************************************************/ +/** +* +* This function enables the bypass mode by setting bypass bit of the Control +* register to switch the core to bypass mode if debug feature is enabled in +* the core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +void XCresample_EnableDbgByPass(XCresample *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Config.HasDebug != (u16)0x0); + + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_BPE_MASK))); + +} + +/*****************************************************************************/ +/** +* +* This function returns the current bypass mode settings from Control register +* of the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return Core debug bypass mode. +* - TRUE = Bypass mode is enabled. +* - FALSE = Bypass mode is not enabled. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +int XCresample_IsDbgByPassEnabled(XCresample *InstancePtr) +{ + u32 DbgByPass; + int Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->Config.HasDebug != (u16)0x0); + + DbgByPass = (XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) & (XCRE_CTL_BPE_MASK); + if (DbgByPass == (XCRE_CTL_BPE_MASK)) { + Status = (TRUE); + } + else { + Status = (FALSE); + } + + return Status; +} + +/*****************************************************************************/ +/** +* +* This function disables bypass mode of the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +void XCresample_DisableDbgBypass(XCresample *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Config.HasDebug != (u16)0x0); + + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) & (~(XCRE_CTL_BPE_MASK)))); +} + +/*****************************************************************************/ +/** +* +* This function enables the test-pattern mode if debug feature is enabled +* by setting test-pattern bit of the Control register of the Chroma Resampler +* core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +void XCresample_EnableDbgTestPattern(XCresample *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Config.HasDebug != (u16)0x0); + + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_TPE_MASK))); +} + +/*****************************************************************************/ +/** +* +* This function returns the test-pattern mode (enabled or not) from Control +* register of the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to +* be worked on. +* +* @return Test-pattern generator mode. +* - TRUE = Test-pattern mode is enabled. +* - FALSE = Test-pattern mode is not enabled. +* +* @note Debug functionality should be enabled. +* +*****************************************************************************/ +int XCresample_IsDbgTestPatternEnabled(XCresample *InstancePtr) +{ + u32 DbgTestPattern; + int Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->Config.HasDebug != (u16)0x0); + + DbgTestPattern = (XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) & (XCRE_CTL_TPE_MASK); + if (DbgTestPattern == (XCRE_CTL_TPE_MASK)) { + Status = (TRUE); + } + else { + Status = (FALSE); + } + + return Status; +} + +/*****************************************************************************/ +/** +* +* This function disables debug test pattern mode in Control register of the +* Chroma Resampler core, if Debug feature is enabled. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +void XCresample_DisableDbgTestPattern(XCresample *InstancePtr) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Config.HasDebug != (u16)0x0); + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_CONTROL_OFFSET))) & (~(XCRE_CTL_TPE_MASK)))); +} + +/*****************************************************************************/ +/** +* +* This function returns the version of the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return Content of Version register is returned.. +* +* @note None. +* +******************************************************************************/ +u32 XCresample_GetVersion(XCresample *InstancePtr) + +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_VERSION_OFFSET)); + + return Data; +} + +/*****************************************************************************/ +/** +* +* This function returns the number of frames processed since power-up or last +* time the core is reset. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return FrameCount is the number of frames processed since power-up. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +u32 XCresample_GetDbgFrameCount(XCresample *InstancePtr) +{ + u32 FrameCount; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->Config.HasDebug != (u16)0x0); + + /* Frame throughput monitor */ + FrameCount = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_SYSDEBUG0_OFFSET)); + + return FrameCount; +} + +/*****************************************************************************/ +/** +* +* This function returns the number of lines processed since power-up or last +* time the core is reset. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return LineCount is the number of lines processed since power-up. +* +* @note Debug functionality should be enabled. +* +******************************************************************************/ +u32 XCresample_GetDbgLineCount(XCresample *InstancePtr) +{ + u32 LineCount; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->Config.HasDebug != (u16)0x0); + + /* Line throughput monitor */ + LineCount = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_SYSDEBUG1_OFFSET)); + + return LineCount; +} + +/*****************************************************************************/ +/** +* +* This function returns the number of pixels processed since power-up or last +* time the core is reset. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return PixelCount is the number of pixels processed since power-up. + +* @note Debug functionality should be enabled. +* +******************************************************************************/ +u32 XCresample_GetDbgPixelCount(XCresample *InstancePtr) +{ + u32 PixelCount; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->Config.HasDebug != (u16)0x0); + + /* Pixel throughput monitor */ + PixelCount = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_SYSDEBUG2_OFFSET)); + + return PixelCount; +} + +/*****************************************************************************/ +/** +* +* This function sets the active H/V sizes in the Active Size register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param HSize specifies the number of Active Pixels per Scan Line +* that needs to be set (Range is 32 to 7680). +* @param VSize specifies the number of Active Lines per Frame that +* needs to be set (Range is 32 to 7680). +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCresample_SetActiveSize(XCresample *InstancePtr, u16 HSize, u16 VSize) +{ + u32 Size; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VSize >= (u16)(XCRE_ACT_SIZE_FIRST)) && + (VSize <= (u16)(XCRE_ACT_SIZE_LAST))); + Xil_AssertVoid((HSize >= (u16)(XCRE_ACT_SIZE_FIRST)) && + (HSize <= (u16)(XCRE_ACT_SIZE_LAST))); + + Size = (((u32)VSize) << ((u32)(XCRE_ACTSIZE_NUM_LINE_SHIFT))) | + (HSize); + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_ACTIVE_SIZE_OFFSET), Size); +} + +/*****************************************************************************/ +/** +* +* This function gets the number of Active Pixels per Scan line and number of +* Active Lines per Frame from the Active Size register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param HSize is a pointer to 16-bit variable in which the number of +* Active Pixels per Scan Line is returned (Range is 32 to 7680). +* @param VSize is a pointer to 16-bit variable in which the number of +* Active Lines per Frame is returned (Range is 32 to 7680). +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCresample_GetActiveSize(XCresample *InstancePtr, u16 *HSize, u16 *VSize) +{ + u32 Data; + /* Verify arguments*/ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(HSize != NULL); + Xil_AssertVoid(VSize != NULL); + + Data = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ACTIVE_SIZE_OFFSET)); + + /* Number of active pixels per scan line */ + *HSize = (u16)(Data & (XCRE_ACTSIZE_NUM_PIXEL_MASK)); + + /* Number of active lines per frame */ + *VSize = (u16)((Data & (XCRE_ACTSIZE_NUM_LINE_MASK)) >> + (XCRE_ACTSIZE_NUM_LINE_SHIFT)); +} + +/*****************************************************************************/ +/** +* +* This functions sets the field parity value of the Chroma Resampler core in +* the Encoding register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param FieldParity specifies the parity value which needs to be +* set.(0 or 1). +* - 0 - for even or bottom field. +* - 1 - for odd or top field. +* +* @return None. +* +* @note To this feature need to use interlaced video. +* +******************************************************************************/ +void XCresample_SetFieldParity(XCresample *InstancePtr, u8 FieldParity) +{ + /* Verify arguments*/ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->Config.Interlaced == 1); + Xil_AssertVoid((FieldParity == (XCRE_PARITY_ODD)) || + (FieldParity == (XCRE_PARITY_EVEN))); + + /* Checking the type of field parity */ + if ((FieldParity) == (XCRE_PARITY_ODD)) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET))) | + ((u32)(XCRE_ENCODING_FIELD_MASK)))); + } + if ((FieldParity) == (XCRE_PARITY_EVEN)) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET))) & + ((u32)(~(XCRE_ENCODING_FIELD_MASK))))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the field parity value of the Chroma Resampler core +* from Encoding register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return Field parity value is returned. +* 0 - for even or bottom field. +* 1 - for odd or top field. +* +* @note None. +* +******************************************************************************/ +u8 XCresample_GetFieldParity(XCresample *InstancePtr) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET))) & (XCRE_ENCODING_FIELD_MASK)) >> + (XCRE_ENCODING_FIELD_SHIFT); + + return (u8)Data; +} + +/*****************************************************************************/ +/** +* +* This functions sets the Chroma parity value of the Chroma Resampler core in +* the Encoding register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param ChromaParity specifies the parity value which needs to be +* set.(0 or 1). +* - 0 - Chroma information on Odd or First line. +* - 1 - Chroma information on Even lines. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCresample_SetChromaParity(XCresample *InstancePtr, u8 ChromaParity) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((ChromaParity == (XCRE_PARITY_ODD)) || + (ChromaParity == (XCRE_PARITY_EVEN))); + + /* Checking type of ChromaParity value */ + if ((ChromaParity) == (XCRE_PARITY_ODD)) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET), + ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET))) | + ((u32)(XCRE_ENCODING_CHROMA_MASK)))); + } + if ((ChromaParity) == (XCRE_PARITY_EVEN)) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET), + (XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET)) & + (u32)(~(XCRE_ENCODING_CHROMA_MASK)))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the value of chroma parity of the Chroma Resampler core +* from Encoding register. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return Chroma parity value is returned. +* - 0 - Chroma information on Odd or First line. +* - 1 - Chroma information on Even lines. +* +* @note None. +* +******************************************************************************/ +u8 XCresample_GetChromaParity(XCresample *InstancePtr) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = ((XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_ENCODING_OFFSET))) & (XCRE_ENCODING_CHROMA_MASK)) >> + (XCRE_ENCODING_CHROMA_SHIFT); + + return (u8)Data; +} + +/*****************************************************************************/ +/** +* +* This function sets the horizontal coefficient values of the Chroma Resampler +* core for phase 0 or phase 1 or both phases. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param Coeff is a pointer to the structure XHorizontal_Coeffs which +* has horizontal coefficients of both phases (Phase 0 and Phase 1) +* which needs to be set. +* Range of coefficient values is [-2, 2). +* @param Phases specifies number of phases needs to be set. +* - 0 - Phase 0. +* - 1 - Phase 1. +* - 2 - Phase 0 and Phase 1. +* +* @return None. +* +* @note For pre defined fixed coefficients filter values, ConvertType +* should be set with 1. +* +******************************************************************************/ +void XCresample_SetHCoefs(XCresample *InstancePtr, XHorizontal_Coeffs *Coeff, + u32 Phases) +{ + u32 Index1; + u32 Index2; + u32 Offset; + s32 Data; + float Value; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Coeff != NULL); + Xil_AssertVoid(Phases <= XCRE_NUM_OF_PHASES); + Xil_AssertVoid(InstancePtr->Config.ConvertType == 1); + + XCresample_Clear_HCoef_Values(InstancePtr); + if ((Phases == 0) || (Phases == 2)) { + Offset = XCRE_COEF00_HPHASE0_OFFSET; + Index1 = 0; + } + if (Phases == 1) { + Offset = XCRE_COEF00_HPHASE1_OFFSET; + Index1 = 1; + } + /* Setting horizontal coefficients based on number of Phases */ + do { + for (Index2 = (u32)0x0; + Index2 < (InstancePtr->Config.NumHTaps); Index2++) { + Value = Coeff->HCoeff[Index1][Index2]; + Data = XCresample_FloatToFixedConv(Value); + Data = Data & (XCRE_COEFF_MASK); + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + Offset, Data); + Offset = Offset + (XCRE_OFFSET_DIFF); + } + Index1 = 2; + if (((Phases == 1) || (Phases == 2)) && (Index1 == 0)) { + Offset = XCRE_COEF00_HPHASE1_OFFSET; + Index1 = 1; + } + }while (Index1 < XCRE_NUM_OF_PHASES); + +} + +/*****************************************************************************/ +/** +* +* This function gets the coefficient values from all the Horizontal Coefficient +* registers of phase0 and phase1 of the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param Coeff is a pointer to the structure XHorizontal_Coeffs which +* has horizontal coefficients of both phases.(Phase 0 and Phase 1) +* in which coefficients are updated. +* Range of coefficient values is [-2, 2). +* +* @return None. +* +* @note For pre defined fixed coefficients filter values, ConvertType +* should be set with 1. +* +******************************************************************************/ +void XCresample_GetHCoefs(XCresample *InstancePtr, XHorizontal_Coeffs *Coeff) +{ + u32 Index1; + u32 Index2; + u32 Offset; + s32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Coeff != NULL); + Xil_AssertVoid(InstancePtr->Config.ConvertType == 1); + + Offset = (u32)(XCRE_COEF00_HPHASE0_OFFSET); + + /* + * Getting coefficient values from all Horizontal Coefficient + * registers + */ + for (Index1 = (u32)0x0; Index1 < (XCRE_NUM_OF_PHASES); Index1++) { + for (Index2 = (u32)0x0; Index2 < (XCRE_NUM_HCOEFS); + Index2++ ) { + Data = + (s32)(XCresample_ReadReg( + InstancePtr->Config.BaseAddress, Offset)); + Coeff->HCoeff[Index1][Index2] = + XCresample_FixedToFloatConv(Data); + Offset = Offset + (XCRE_OFFSET_DIFF); + } + } +} + +/*****************************************************************************/ +/** +* +* This function sets the vertical coefficient values of the Chroma Resampler +* for phase 0 or for phase 1 or for both phases. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param Coeff is a pointer to the structure XHorizontal_Coeffs which +* has vertical coefficients of both phases (Phase 0 and Phase 1) +* which needs to be set. +* @param Phases specifies number of phases needs to be set. +* - 0 - Phase 0. +* - 1 - Phase 1. +* - 2 - Phase 0 and Phase 1. +* +* @return None. +* +* @note For pre defined fixed coefficients filter values, ConvertType +* should be set with 1. +* +******************************************************************************/ +void XCresample_SetVCoefs(XCresample *InstancePtr, XVertical_Coeffs *Coeff, + u32 Phases) +{ + u32 Index1; + u32 Index2; + u32 Offset; + s32 Data; + float Value; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Coeff != NULL); + Xil_AssertVoid(Phases <= XCRE_NUM_OF_PHASES); + Xil_AssertVoid(InstancePtr->Config.ConvertType == 1); + + XCresample_Clear_VCoef_Values(InstancePtr); + + /* + * Setting coefficient values in all Vertical + * Coefficient registers + */ + + if ((Phases == 0) || (Phases == 2)) { + Offset = XCRE_COEF00_VPHASE0_OFFSET; + Index1 = 0; + } + if (Phases == 1) { + Index1 = 1; + Offset = XCRE_COEF00_VPHASE1_OFFSET; + } + /* Setting Vertical Coefficients based on number of Phases */ + do { + for (Index2 = (u32)0x0; + Index2 < (InstancePtr->Config.NumVTaps); Index2++) { + Value = Coeff->VCoeff[Index1][Index2]; + Data = XCresample_FloatToFixedConv(Value); + Data = Data & (XCRE_COEFF_MASK); + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + Offset, Data); + Offset = Offset + (XCRE_OFFSET_DIFF); + } + Index1 = 2; + if (((Phases == 1) || (Phases == 2)) && (Index1 == 0)) { + Index1 = 1; + Offset = XCRE_COEF00_VPHASE1_OFFSET; + } + } while (Index1 < XCRE_NUM_OF_PHASES); + +} + +/*****************************************************************************/ +/** +* +* This function gets the vertical coefficient values of the Chroma Resampler +* core from all Vertical Coefficient registers of phase0 and phase1. +* +* @param InstancePtr is a pointer to the XCresample instance. +* @param Coeff is a pointer to the structure XVertical_Coeffs which has +* vertical coefficients of both phases.(Phase 0 and Phase 1) in +* which coefficients are updated. +* Range of coefficient values is [-2, 2). +* +* @return None. +* +* @note For pre defined fixed coefficients filter values, ConvertType +* should be set with 1. +* +******************************************************************************/ +void XCresample_GetVCoefs(XCresample *InstancePtr, XVertical_Coeffs *Coeff) +{ + u32 Index1; + u32 Index2; + u32 Offset; + s32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Coeff != NULL); + Xil_AssertVoid(InstancePtr->Config.ConvertType == 1); + + Offset = (u32)(XCRE_COEF00_VPHASE0_OFFSET); + + /* + * Getting coefficient values from all Vertical + * Coefficient registers + */ + for (Index1 = (u32)0x0; Index1 < (XCRE_NUM_OF_PHASES); Index1++) { + for (Index2 = (u32)0x0; Index2 < (XCRE_NUM_VCOEFS); + Index2++) { + Data = + (s32)(XCresample_ReadReg( + InstancePtr->Config.BaseAddress, + Offset)); + Coeff->VCoeff[Index1][Index2] = + XCresample_FixedToFloatConv(Data); + Offset = Offset + (XCRE_OFFSET_DIFF); + } + } +} + +/*****************************************************************************/ +/** +* +* This function clears all horizontal coefficients of the Chroma Resampler core +* which are previously set. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCresample_Clear_HCoef_Values (XCresample *InstancePtr) +{ + u32 Index1; + u32 Index2; + u32 Offset; + + /* Verify argument. */ + Xil_AssertVoid(InstancePtr != NULL); + + Offset = XCRE_COEF00_HPHASE0_OFFSET; + /* Set all horizontal coefficient values to 0 */ + for (Index1 = 0; Index1 < XCRE_NUM_OF_PHASES; Index1++) { + for (Index2 = 0; Index2 < XCRE_NUM_HCOEFS; Index2++) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + Offset, 0x00); + Offset = Offset + XCRE_OFFSET_DIFF; + } + } +} + +/*****************************************************************************/ +/** +* +* This function clears all vertical coefficients of a the Chroma Resampler +* which are previously set. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCresample_Clear_VCoef_Values (XCresample *InstancePtr) +{ + u32 Index1; + u32 Index2; + u32 Offset; + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + Offset = XCRE_COEF00_VPHASE0_OFFSET; + /* Set all vertical coefficient values to 0 */ + for (Index1 = 0; Index1 < XCRE_NUM_OF_PHASES; Index1++) { + for (Index2 = 0; Index2 < XCRE_NUM_VCOEFS; Index2++) { + XCresample_WriteReg(InstancePtr->Config.BaseAddress, + Offset, 0x00); + Offset = Offset + XCRE_OFFSET_DIFF; + } + } +} + +/*****************************************************************************/ +/** +* This function converts 18.14 fixed point format numbers to floating point +* numbers. +* +* @param Input is a 32-bit variable which should be given in 18.14 fixed +* point number. +* +* @return Value is returned after converting 18.14 to floating point. +* +* @note None. +* +******************************************************************************/ +static float XCresample_FixedToFloatConv(u32 Input) +{ + float Value; + u32 Sign; + Sign = 0; + + if ((Input & XCRE_COEFF_MASK) == XCRE_COEF_SIGN_MASK) { + return (XCRE_COEF_FIRST); + } + if ((Input & XCRE_COEF_SIGN_MASK) != 0) { + Sign = 1; + Input = (Input << XCRE_COEFF_SIGN_SHIFT) >> + (XCRE_COEFF_SIGN_SHIFT); + Input = (~Input) + 1; + } + Value = (float)((Input & XCRE_COEF_DECI_MASK) >> XCRE_COEFF_SHIFT); + Value = Value + + ((float)(Input & XCRE_COEFF_FRAC_MASK) / + (float)(1 << XCRE_COEFF_SHIFT)); + if (Sign == 1) { + Value = (Value) * (float)(XCRE_SIGN_MUL); + } + + return Value; +} + +/*****************************************************************************/ +/** +* This function converts floating point numbers to 18.14 fixed point format. +* +* @param Input is a 32-bit variable which should be given in 18.14 fixed +* point number. +* +* @return Value is returned after converting 18.14 to floating point. +* +* @note None. +* +******************************************************************************/ +static s32 XCresample_FloatToFixedConv(float Input) +{ + s32 Value; + Value = (s32)(Input * (float)(1 << XCRE_COEFF_SHIFT)); + if ((Value & XCRE_SIGNBIT_MASK) != 0) { + Value = XCRE_MAX_VALUE + Value + 1; + } + + return Value; +} +/*****************************************************************************/ +/** +* +* This routine is a stub for the asynchronous callbacks. The stub is here in +* case the upper layer forgot to set the handlers. On initialization, All +* handlers except error handler are set to this callback. It is considered as +* an error for this handler to be invoked. +* +* @param CallBackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. +* +* @return None. +* +******************************************************************************/ +static void StubCallBack(void *CallBackRef) +{ + (void)CallBackRef; + /* Verify arguments. */ + Xil_AssertVoidAlways(); +} + +/*****************************************************************************/ +/** +* This routine is a stub for the asynchronous error interrupt callback. The +* stub is here in case the upper layer forgot to set the handler. On +* initialization, Error interrupt handler is set to this callback. +* +* @param CallBackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. +* @param ErrorMask is a bit mask indicating the cause of the error. Its +* value equals 'OR'ing one or more XCRE_IXR_* values defined +* in xcresample_hw.h. +* +* @return None. +* +******************************************************************************/ +static void StubErrCallBack(void *CallBackRef, u32 ErrorMask) +{ + (void)CallBackRef; + (void)ErrorMask; + /* Verify arguments. */ + Xil_AssertVoidAlways(); +} diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample.h b/XilinxProcessorIPLib/drivers/cresample/src/xcresample.h new file mode 100755 index 00000000..92e00888 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample.h @@ -0,0 +1,714 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample.h +* +* This header file contains identifiers and register-level driver functions +* (or macros), that can be used to access the Xilinx Chroma Resampler +* (Cresample) core instance. +* +* The Chroma Resampler core converts between chroma sub-sampling formats of +* 4:4:4, 4:2:2,and 4:2:0. There are a total of six conversions available for +* the three supported sub-sampling formats. +* Conversion is achieved using a FIR filter approach. Some conversions require +* filtering in only the horizontal dimension, only the vertical dimension, +* or both. +* Interpolation operations are implemented using a two-phase polyphase +* FIR filter. Decimation operations are implemented using a low-pass FIR filter +* to suppress chroma aliasing. +* +* Features of Chroma Resampler core are +* - Configurable filters sizes with programmable filter coefficients for +* high performance applications. +* - Replicate or drop pixels. +* - Static, predefined, powers-of-two coefficients for low-footprint +* applications +* - Converts between YCbCr: 4:4:4, 4:2:2,and 4:2:0. +* - Supports both progressive and interlaced video. +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the Cresample core. +* +* XCresample_CfgInitialize() API is used to initialize the Cresample core. +* The user needs to first call the XCresample_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XCresample_CfgInitialize() API. +* +* Interrupts +* +* The driver provides an interrupt handler XCresample_IntrHandler for handling +* the interrupt from the Cresample core. The users of this driver have to +* register this handler with the interrupt system and provide the callback +* functions by using XCresample_SetCallBack API. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The Cresample driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary.* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- -------------------------------------------------------
+* 2.00a vy      04/24/12 Updated for version 2.00.a
+*                        Converted from xio.h to xil_io.h, translating
+*                        basic type, MB cache functions, exceptions and
+*                        assertion to xil_io format.
+* 1.00a vy      10/22/10 Initial version
+* 3.0   adk     19/12/13 Updated as per the New Tcl API's.
+* 4.0   adk     03/12/14 Changed the file name cresample.h to xcresample.h.
+*                        Macros of register offsets, bit definitions,
+*                        ReadReg and WriteReg macros which are the part of
+*                        xcresample_hw.h.were moved to xcresample_hw.h.
+*                        Removed file inclusion of Xil_io.h.
+*
+*                        Removed the following functional macros:
+*                        CRESAMPLE_Enable, CRESAMPLE_Disable,
+*                        CRESAMPLE_RegUpdateEnable, CRESAMPLE_RegUpdateDisable,
+*                        CRESAMPLE_Reset, CRESAMPLE_ClearReset,
+*                        CRESAMPLe_AutoSyncReset.
+*                        Defined the following functional macros:
+*                        XCresample_Enable, XCresample_Disable,
+*                        XCresample_RegUpdateEnable,XCresample_RegUpdateDisable
+*                        XCresample_Reset, XCresample_ClearReset,
+*                        XCresample_SyncReset, XCresample_IntrDisable,
+*                        XCresample_IntrEnable, XCresample_StatusGetPending
+*                        XCresample_IntrGetPending, XCresample_IntrClear.
+*                        Declared following structures:
+*                        XCresample_Config and XCresample of Chroma Resampler.
+*
+*                        Defined the following range macros:
+*                        XCRE_VSIZE_FIRST, XCRE_VSIZE_LAST, XCRE_HSIZE_FIRST,
+*                        XCRE_HSIZE_FIRST, XCRE_HSIZE_LAST, XCRE_PARITY_ODD,
+*                        XCRE_PARITY_EVEN, XCRE_COEF_FIRST, XCRE_COEF_LAST,
+*                        XCRE_OFFSET_DIFF, XCRE_NUM_OF_PHASES, XCRE_NUM_HCOEFS,
+*                        and XCRE_NUM_VCOEFS.
+*
+*                        Modifications in the file xcresample_hw.h are:
+*                        Added the register offsets and bit masks for the
+*                        registers and added backward compatibility for macros.
+*
+*                        Modifications in the file xcresample.c are:
+*                        Changed the filename cresample.c to xcresample.c.
+*                        The Following functions are removed:
+*                        clear_coef_values, configure_444_to_422,
+*                        configure_422_to_444, configure_422_to_420,
+*                        configure_420_to_422, configure_444_to_420 and
+*                        configure_420_to_444.
+*                        Implemented the following functions :
+*                        StubCallBack, StubErrorCallBack,
+*                        XCresample_CfgInitialize,
+*                        XCresample_GetVersion, XCresample_EnableDbgByPass,
+*                        XCresample_IsDbgByPassEnabled,
+*                        XCresample_DisableDbgByPass,
+*                        XCresample_SetDbgTestPattern,
+*                        XCresample_IsDbgTestPatternEnabled,
+*                        XCresample_DisableDbgTestPattern
+*                        XCresample_GetDbgFrameCount,
+*                        XCresample_GetDbgLineCount,
+*                        XCresample_GetDbgPixelCount,
+*                        XCresample_SetActiveSize, XCresample_GetActiveSize,
+*                        XCresample_SetFieldParity, XCresample_GetFieldParity,
+*                        XCresample_SetChromaParity,
+*                        XCresample_GetChromaParity
+*                        XCresample_SetHCoefs, XCresample_GetHCoefs,
+*                        XCresample_SetVCoefs, XCresample_GetVCoefs,
+*                        XCresample_Clear_HCoef_Values, and
+*                        XCresample_Clear_VCoef_Values.
+*
+*                        Modifications in the file xcresample_intr.c are:
+*                        Implemented XCresample_IntrHandler and
+*                        XCresample_SetCallBack functions.
+*
+*                        Modifications in the file xcresample_selftest.c are:
+*                        Implemented XCresample_SelfTest function.
+*
+*                        Modifications in the file xcresample_sinit.c are:
+*                        Implemented XCresample_LookupConfig function.
+
+*
+* +******************************************************************************/ + +#ifndef XCRESAMPLE_H_ +#define XCRESAMPLE_H_ /**< Prevent circular inclusions by using + * protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_assert.h" +#include "xstatus.h" +#include "xcresample_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types for setting up callbacks +* @{ +*/ +/** + * These constants specify different types of handler and used to differentiate + * interrupt requests from core. + * + */ +enum { + XCRE_HANDLER_PROCSTART = 1, /**< A processing start event interrupt + * type */ + XCRE_HANDLER_FRAMEDONE, /**< A frame done event interrupt + * type */ + XCRE_HANDLER_ERROR /**< An error condition interrupt + * type */ +} ; +/*@}*/ + +/** @name Active size ranges +* @{ +*/ +#define XCRE_ACT_SIZE_FIRST 32 /**< Active Size starting value */ +#define XCRE_ACT_SIZE_LAST 7680 /**< Active Size ending value */ +/*@}*/ + +/** @name Parity valid values +* @{ +*/ +#define XCRE_PARITY_ODD 1 /**< For odd (or top) + * field it is 1 */ +#define XCRE_PARITY_EVEN 0 /**< For even (or bottom) + * field it is 0 */ +/*@}*/ + +/** @name Coefficient ranges +* @{ +*/ +#define XCRE_COEF_FIRST -2.0 /**< Coefficient start value */ +#define XCRE_COEF_LAST 2.0 /**< Coefficient end value */ +#define XCRE_OFFSET_DIFF 4 /**< Coefficient offset + * difference */ +/*@}*/ + +/** @name Number of phases +* @{ +*/ +#define XCRE_NUM_OF_PHASES 2 /**< Number of phases */ +/*@}*/ + +/** @name Number of coefficients +* @{ +*/ +#define XCRE_NUM_HCOEFS 24 /**< Number of horizontal + * coefficients */ +#define XCRE_NUM_VCOEFS 8 /**< Number of vertical + * coefficients */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This macro enables the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_Enable(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_Enable(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_SW_EN_MASK))) + +/*****************************************************************************/ +/** +* +* This macro disables the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_Disable(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_Disable(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) & (~(XCRE_CTL_SW_EN_MASK)))) + +/*****************************************************************************/ +/** +* +* This macro enables/starts the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_Start(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_Start XCresample_Enable + +/*****************************************************************************/ +/** +* +* This macro disables/stops the Chroma Resampler core. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_Stop(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_Stop XCresample_Disable + +/*****************************************************************************/ +/** +* +* This macro commits all the register value changes made so far +* by the software to the Chroma Resampler core. +* +* This macro only works when the Chroma Resampler core is enabled. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_RegUpdateEnable(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_RegUpdateEnable(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) | (XCRE_CTL_RUE_MASK))) + +/*****************************************************************************/ +/** +* +* This macro prevents the Chroma Resampler core from committing +* recent changes made so far by the software. When disabled, changes to other +* configuration registers are stored, but do not effect the behavior of the +* core. +* +* This macro only works when the Chroma Resampler core is enabled. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_RegUpdateDisable(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_RegUpdateDisable(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET))) & (u32)(~(XCRE_CTL_RUE_MASK)))) + +/*****************************************************************************/ +/** +* +* This macro resets a Chroma Resampler core instance, but differs from +* XCresample_Reset() in that it automatically synchronizes to the SOF input of +* the core to prevent tearing. +* +* On the next raising edge of SOF following a call to XCresample_SyncReset(), +* all of the core's configuration registers and outputs will be reset, then +* the reset flag will be immediately released, allowing the core to immediately +* resume default operation. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_SyncReset(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_SyncReset(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), (XCRE_CTL_AUTORESET_MASK)) + +/*****************************************************************************/ +/** +* +* This macro resets the Chroma Resampler core. This reset effects the core +* immediately, and may cause image tearing. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return None. +* +* @note C-style signature: +* void XCresample_Reset(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_Reset(InstancePtr) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_CONTROL_OFFSET), (XCRE_CTL_RESET_MASK)) + +/*****************************************************************************/ +/** +* +* This macro enables individual interrupts of the Cresample core by +* updating the IRQ_ENABLE register. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* @param IntrType is the type of the interrupts to enable. Use OR'ing of +* XCRE_IXR_*_MASK constants defined in xcresample_hw.h to create +* this parameter value. +* +* @return None +* +* @note The existing enabled interrupt(s) will remain enabled. +* C-style signature: +* void XCresample_IntrEnable(XCresample *InstancePtr, + u32 IntrType) +* +******************************************************************************/ +#define XCresample_IntrEnable(InstancePtr, IntrType) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET), \ + (((IntrType) & (XCRE_IXR_ALLINTR_MASK)) | \ + (XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET))))) + +/*****************************************************************************/ +/** +* +* This macro disables individual interrupts of the Cresample core by +* updating the IRQ_ENABLE register. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* @param IntrType is the type of the interrupts to disable. Use OR'ing +* of XCRE_IXR_*_MASK constants defined in xcresample_hw.h to +* create this parameter value. +* +* @return None +* +* @note Any other interrupt not covered by parameter IntrType, +* if enabled before this macro is called, will remain enabled. +* C-style signature: +* void XCresample_IntrDisable(XCresample *InstancePtr, +* u32 IntrType) +* +******************************************************************************/ +#define XCresample_IntrDisable(InstancePtr, IntrType) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET), \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET))) \ + & ((~(IntrType)) & (XCRE_IXR_ALLINTR_MASK)))) + +/*****************************************************************************/ +/** +* +* This macro returns the pending interrupt status of the Cresample +* core read from the Status register. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return The pending interrupts of the Chroma Resampler. Use +* XCRE_IXR_*_MASK constants defined in xcresample_hw.h to +* interpret this value. +* +* @note C-style signature: +* u32 XCresample_StatusGePending(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_StatusGetPending(InstancePtr) \ + XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS)) & (XCRE_IXR_ALLINTR_MASK) + +/*****************************************************************************/ +/** +* +* This macro returns the pending interrupts of the Cresample core for +* the interrupts that have been enabled. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* +* @return The pending interrupts of the Chroma Resampler. Use +* XCRE_IXR_*_MASK constants defined in xcresample_hw.h to +* interpret this value. +* +* @note C-style signature: +* u32 XCresample_IntrGetPending(XCresample *InstancePtr) +* +******************************************************************************/ +#define XCresample_IntrGetPending(InstancePtr) \ + XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_IRQ_EN_OFFSET)) & \ + ((XCresample_ReadReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS_OFFSET))) & ((u32)(XCRE_IXR_ALLINTR_MASK))) + +/*****************************************************************************/ +/** +* +* This macro clears/acknowledges pending interrupts of the Cresample +* core in the Status register. Bit positions of 1 will be cleared. +* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* @param IntrType is the pending interrupts to clear/acknowledge. +* Use OR'ing of XCRE_IXR_*_MASK constants defined in +* xcresample_hw.h to create this parameter value. +* +* @return None +* @note C-style signature: +* void XCresample_IntrClear(XCresample *InstancePtr, +* u32 IntrType) +* +******************************************************************************/ +#define XCresample_IntrClear(InstancePtr, IntrType) \ + XCresample_WriteReg((InstancePtr)->Config.BaseAddress, \ + (XCRE_STATUS_OFFSET), \ + ((IntrType) & ((u32)(XCRE_IXR_ALLINTR_MASK)))) + +/**************************** Type Definitions *******************************/ +/** +* +* This typedef contains configuration information for a Video device. +* Each Video device should have a configuration structure associated +*/ +typedef struct { + u16 DeviceId; /**< DeviceId is the unique ID of + * the device */ + u32 BaseAddress; /**< BaseAddress is the physical + * base address of the device's + * registers */ + u32 SlaveAxisVideoFormat; /**< Slave axis video format */ + u32 MasterAxisVideoFormat; /**< Master axis video format */ + u32 SlaveAxiClkFreqHz; /**< Slave clock frequency */ + u16 HasIntcIf; /**< Has interrupt control */ + u16 HasDebug; /**< Has debug GUI specified */ + u32 MaxColumns; /**< Maximum columns */ + u32 ActiveRows; /**< Active rows */ + u32 ActiveColumns; /**< Active columns */ + u8 ChromaParity; /**< Chroma parity */ + u8 FieldParity; /**< Chroma parity */ + u32 Interlaced; /**< Interlaced value */ + u32 NumHTaps; /**< Horizontal taps */ + u32 NumVTaps; /**< Vertical taps */ + u32 ConvertType; /**< Convert type */ + u32 CoefWidth; /**< Coefficient width */ +} XCresample_Config; + +/*****************************************************************************/ +/** +* +* Callback type for all interrupts except error interrupt. +* +* @param CallBackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. +*/ +typedef void (*XCresample_CallBack)(void *CallBackRef); + +/*****************************************************************************/ +/** +* +* Callback type for Error interrupt. +* +* @param CallBackRef is a callback reference passed in by the upper +* layer when setting the callback functions, and passed back +* to the upper layer when the callback is invoked. +* @param ErrorMask is a bit mask indicating the cause of the error. Its +* value equals 'OR'ing one or more XCRE_IXR_* values +* defined in xcresample_hw.h +*/ +typedef void (*XCresample_ErrorCallBack)(void *CallBackRef, u32 ErrorMask); + +/*****************************************************************************/ +/** +* +* The XCresample driver instance data structure. A pointer to an instance +* data structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XCresample_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ + u16 HSize; /**< Active video horizontal size */ + u16 VSize; /**< Active video vertical size */ + + /* IRQ Callbacks Here */ + XCresample_CallBack ProcStartCallBack; /**< Call back for processing + * start interrupt */ + void *ProcStartRef; /**< To be passed to the process start + * interrupt callback */ + + XCresample_CallBack FrameDoneCallBack; /**< Call back for frame done + * interrupt */ + + void *FrameDoneRef; /**< To be passed to the frame done + * interrupt callback */ + + XCresample_ErrorCallBack ErrCallBack; /**< Call back for error + * interrupt */ + void *ErrRef; /**< To be passed to the error + * interrupt callback */ + u32 CoefH[XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS]; /**< Horizontal filter + * coefficients */ + u32 CoefV[XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS]; /**< Vertical filter + * coefficients */ +} XCresample; + +/*****************************************************************************/ +/** +* +* The XCoeffs is a structure contains predefined fixed coefficient values for +* Horizontal filter of two phases (phase 0 and phase 1). +* This can be used for setting or getting coefficient values from +* XCresample_SetHCoefs and XCresample_GetHCoefs APIs. +*/ +typedef struct { + float HCoeff[XCRE_NUM_OF_PHASES][XCRE_NUM_HCOEFS];/**< Matrix for + * Horizontal + * Coefficients */ +} XHorizontal_Coeffs; +/*****************************************************************************/ +/** +* +* The XCoeffs is a structure contains predefined fixed coefficient values for +* Vertical filter of two phases (phase 0 and phase 1). +* This can be used for setting or getting coefficient values from +* XCresample_SetVCoefs and XCresample_GetVCoefs APIs. +*/ +typedef struct { + float VCoeff[XCRE_NUM_OF_PHASES][XCRE_NUM_VCOEFS];/**< Matrix for + * Vertical + * Coefficients */ +} XVertical_Coeffs; + +/************************** Function Prototypes ******************************/ + +/* Initialization and control functions implemented in xcresample.c */ +int XCresample_CfgInitialize(XCresample *InstancePtr, + XCresample_Config *CfgPtr, u32 EffectiveAddr); +u32 XCresample_GetVersion(XCresample *InstancePtr); +void XCresample_EnableDbgByPass(XCresample *InstancePtr); +int XCresample_IsDbgByPassEnabled(XCresample *InstancePtr); +void XCresample_DisableDbgBypass(XCresample *InstancePtr); +void XCresample_EnableDbgTestPattern(XCresample *InstancePtr); +int XCresample_IsDbgTestPatternEnabled(XCresample *InstancePtr); +void XCresample_DisableDbgTestPattern(XCresample *InstancePtr); +u32 XCresample_GetDbgFrameCount(XCresample *InstancePtr); +u32 XCresample_GetDbgLineCount(XCresample *InstancePtr); +u32 XCresample_GetDbgPixelCount(XCresample *InstancePtr); +void XCresample_SetActiveSize(XCresample *InstancePtr, u16 HSize, u16 VSize); +void XCresample_GetActiveSize(XCresample *InstancePtr, u16 *HSize, u16 *VSize); +void XCresample_SetFieldParity(XCresample *InstancePtr, u8 FieldParity); +void XCresample_SetChromaParity(XCresample *InstancePtr, u8 ChromaParity); +u8 XCresample_GetFieldParity(XCresample *InstancePtr); +u8 XCresample_GetChromaParity(XCresample *InstancePtr); +void XCresample_SetHCoefs(XCresample *InstancePtr, XHorizontal_Coeffs *Coeff, + u32 Phases); +void XCresample_SetVCoefs(XCresample *InstancePtr, XVertical_Coeffs *Coeff, + u32 Phases); +void XCresample_GetHCoefs(XCresample *InstancePtr, XHorizontal_Coeffs *Coeff); +void XCresample_GetVCoefs(XCresample *InstancePtr, XVertical_Coeffs *Coeff); + +/* Static lookup function implemented in xcresample_sinit.c */ +XCresample_Config *XCresample_LookupConfig(u16 DeviceId); + +/* Self - Test functions in xcresample_selftest.c */ +int XCresample_SelfTest(XCresample *InstancePtr); + +/* Interrupt related functions in xcresample_intr.c */ +int XCresample_SetCallBack(XCresample *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); +void XCresample_IntrHandler(void *InstancePtr); + +/* Clear coefficients function */ +void XCresample_Clear_HCoef_Values(XCresample *InstancePtr); +void XCresample_Clear_VCoef_Values (XCresample *InstancePtr); + +/************************** Variable Declarations ****************************/ + + +#ifdef __cplusplus +} + +#endif + +#endif /* end of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample_g.c b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_g.c new file mode 100755 index 00000000..2ec839ab --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_g.c @@ -0,0 +1,65 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSM. +* Version: +* DO NOT EDIT. +* +* v (64-bit) +SW Build (by ) on +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcresample.h" + +/* +* The configuration table for devices +*/ + +XCresample_Config XCresample_ConfigTable[] = +{ + { + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_DEVICE_ID, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_BASEADDR, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_S_AXIS_VIDEO_FORMAT, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_M_AXIS_VIDEO_FORMAT, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_S_AXI_CLK_FREQ_HZ, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_HAS_INTC_IF, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_HAS_DEBUG, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_MAX_COLS, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_ACTIVE_ROWS, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_ACTIVE_COLS, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_CHROMA_PARITY, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_FIELD_PARITY, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_INTERLACED, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_NUM_H_TAPS, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_NUM_V_TAPS, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_CONVERT_TYPE, + XPAR_FMC_SENSOR_INPUT_V_CRESAMPLE_1_COEF_WIDTH + }, + { + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_DEVICE_ID, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_BASEADDR, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_S_AXIS_VIDEO_FORMAT, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_M_AXIS_VIDEO_FORMAT, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_S_AXI_CLK_FREQ_HZ, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_HAS_INTC_IF, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_HAS_DEBUG, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_MAX_COLS, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_ACTIVE_ROWS, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_ACTIVE_COLS, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_CHROMA_PARITY, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_FIELD_PARITY, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_INTERLACED, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_NUM_H_TAPS, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_NUM_V_TAPS, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_CONVERT_TYPE, + XPAR_HDMI_OUTPUT_V_CRESAMPLE_1_COEF_WIDTH + } +}; + + diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample_hw.h b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_hw.h new file mode 100755 index 00000000..bda4d8cd --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_hw.h @@ -0,0 +1,552 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample_hw.h +* +* This header file contains identifiers and register-level driver functions +* (or macros) that can be used to access the Xilinx Chroma Resampler core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- -------------------------------------------------------
+* 4.0   adk     03/12/14 First release
+*                        Added the register offsets and bit masks for the
+*                        registers and added backward compatibility for macros.
+*
+*
+* +******************************************************************************/ + +#ifndef XCRESAMPLE_HW_H_ +#define XCRESAMPLE_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name register offsets + * @{ + */ +/* General control registers */ +#define XCRE_CONTROL_OFFSET 0x0000 /**< Control */ +#define XCRE_STATUS_OFFSET 0x0004 /**< Status */ +#define XCRE_ERROR_OFFSET 0x0008 /**< Error */ +#define XCRE_IRQ_EN_OFFSET 0x000C /**< IRQ enable */ +#define XCRE_VERSION_OFFSET 0x0010 /**< Version */ +#define XCRE_SYSDEBUG0_OFFSET 0x0014 /**< System debug 0 */ +#define XCRE_SYSDEBUG1_OFFSET 0x0018 /**< System debug 1 */ +#define XCRE_SYSDEBUG2_OFFSET 0x001C /**< System debug 2 */ +/*@}*/ + +/* Timing control registers */ +#define XCRE_ACTIVE_SIZE_OFFSET 0x0020 /**< Horizontal and vertical + * active frame size */ +#define XCRE_ENCODING_OFFSET 0x0028 /**< Frame encoding */ + +/* Core specific registers */ +/* Coefficient Registers for Horizontal Filter Phase 0 */ +#define XCRE_COEF00_HPHASE0_OFFSET 0x0100 /**< Coefficient 00 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF01_HPHASE0_OFFSET 0x0104 /**< Coefficient 01 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF02_HPHASE0_OFFSET 0x0108 /**< Coefficient 02 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF03_HPHASE0_OFFSET 0x010C /**< Coefficient 03 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF04_HPHASE0_OFFSET 0x0110 /**< Coefficient 04 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF05_HPHASE0_OFFSET 0x0114 /**< Coefficient 05 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF06_HPHASE0_OFFSET 0x0118 /**< Coefficient 06 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF07_HPHASE0_OFFSET 0x011C /**< Coefficient 07 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF08_HPHASE0_OFFSET 0x0120 /**< Coefficient 08 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF09_HPHASE0_OFFSET 0x0124 /**< Coefficient 09 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF10_HPHASE0_OFFSET 0x0128 /**< Coefficient 10 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF11_HPHASE0_OFFSET 0x012C /**< Coefficient 11 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF12_HPHASE0_OFFSET 0x0130 /**< Coefficient 12 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF13_HPHASE0_OFFSET 0x0134 /**< Coefficient 13 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF14_HPHASE0_OFFSET 0x0138 /**< Coefficient 14 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF15_HPHASE0_OFFSET 0x013C /**< Coefficient 15 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF16_HPHASE0_OFFSET 0x0140 /**< Coefficient 16 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF17_HPHASE0_OFFSET 0x0144 /**< Coefficient 17 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF18_HPHASE0_OFFSET 0x0148 /**< Coefficient 18 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF19_HPHASE0_OFFSET 0x014C /**< Coefficient 19 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF20_HPHASE0_OFFSET 0x0150 /**< Coefficient 20 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF21_HPHASE0_OFFSET 0x0154 /**< Coefficient 21 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF22_HPHASE0_OFFSET 0x0158 /**< Coefficient 22 of + * horizontal phase 0 + * filter */ +#define XCRE_COEF23_HPHASE0_OFFSET 0x015C /**< Coefficient 23 of + * horizontal phase 0 + * filter */ +/* Coefficient Registers for Horizontal Filter Phase 1 */ +#define XCRE_COEF00_HPHASE1_OFFSET 0x0160 /**< Coefficient 00 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF01_HPHASE1_OFFSET 0x0164 /**< Coefficient 01 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF02_HPHASE1_OFFSET 0x0168 /**< Coefficient 02 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF03_HPHASE1_OFFSET 0x016C /**< Coefficient 03 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF04_HPHASE1_OFFSET 0x0170 /**< Coefficient 04 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF05_HPHASE1_OFFSET 0x0174 /**< Coefficient 05 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF06_HPHASE1_OFFSET 0x0178 /**< Coefficient 06 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF07_HPHASE1_OFFSET 0x017C /**< Coefficient 07 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF08_HPHASE1_OFFSET 0x0180 /**< Coefficient 08 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF09_HPHASE1_OFFSET 0x0184 /**< Coefficient 09 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF10_HPHASE1_OFFSET 0x0188 /**< Coefficient 10 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF11_HPHASE1_OFFSET 0x018C /**< Coefficient 11 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF12_HPHASE1_OFFSET 0x0190 /**< Coefficient 12 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF13_HPHASE1_OFFSET 0x0194 /**< Coefficient 13 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF14_HPHASE1_OFFSET 0x0198 /**< Coefficient 14 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF15_HPHASE1_OFFSET 0x019C /**< Coefficient 15 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF16_HPHASE1_OFFSET 0x01A0 /**< Coefficient 16 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF17_HPHASE1_OFFSET 0x01A4 /**< Coefficient 17 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF18_HPHASE1_OFFSET 0x01A8 /**< Coefficient 18 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF19_HPHASE1_OFFSET 0x01AC /**< Coefficient 19 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF20_HPHASE1_OFFSET 0x01B0 /**< Coefficient 20 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF21_HPHASE1_OFFSET 0x01B4 /**< Coefficient 21 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF22_HPHASE1_OFFSET 0x01B8 /**< Coefficient 22 of + * horizontal phase 1 + * filter */ +#define XCRE_COEF23_HPHASE1_OFFSET 0x01BC /**< Coefficient 23 of + * horizontal phase 1 + * filter */ +/* Coefficient Registers for Vertical Filter Phase 0 */ +#define XCRE_COEF00_VPHASE0_OFFSET 0x01C0 /**< Coefficient 00 of + * vertical phase 0 + * filter */ +#define XCRE_COEF01_VPHASE0_OFFSET 0x01C4 /**< Coefficient 01 of + * vertical phase 0 + * filter */ +#define XCRE_COEF02_VPHASE0_OFFSET 0x01C8 /**< Coefficient 02 of + * vertical phase 0 + * filter */ +#define XCRE_COEF03_VPHASE0_OFFSET 0x01CC /**< Coefficient 03 of + * vertical phase 0 + * filter */ +#define XCRE_COEF04_VPHASE0_OFFSET 0x01D0 /**< Coefficient 04 of + * vertical phase 0 + * filter */ +#define XCRE_COEF05_VPHASE0_OFFSET 0x01D4 /**< Coefficient 05 of + * vertical phase 0 + * filter */ +#define XCRE_COEF06_VPHASE0_OFFSET 0x01D8 /**< Coefficient 06 of + * vertical phase 0 + * filter */ +#define XCRE_COEF07_VPHASE0_OFFSET 0x01DC /**< Coefficient 07 of + * vertical phase 0 + * filter */ +/* Coefficient Registers for Vertical Filter Phase 1 */ +#define XCRE_COEF00_VPHASE1_OFFSET 0x01E0 /**< Coefficient 00 of + * vertical phase 1 + * filter */ +#define XCRE_COEF01_VPHASE1_OFFSET 0x01E4 /**< Coefficient 01 of + * vertical phase 1 + * filter */ +#define XCRE_COEF02_VPHASE1_OFFSET 0x01E8 /**< Coefficient 02 of + * vertical phase 1 + * filter */ +#define XCRE_COEF03_VPHASE1_OFFSET 0x01EC /**< Coefficient 03 of + * vertical phase 1 + * filter */ +#define XCRE_COEF04_VPHASE1_OFFSET 0x01F0 /**< Coefficient 04 of + * vertical phase 1 + * filter */ +#define XCRE_COEF05_VPHASE1_OFFSET 0x01F4 /**< Coefficient 05 of + * vertical phase 1 + * filter */ +#define XCRE_COEF06_VPHASE1_OFFSET 0x01F8 /**< Coefficient 06 of + * vertical phase 1 + * filter */ +#define XCRE_COEF07_VPHASE1_OFFSET 0x01FC /**< Coefficient 07 of + * vertical phase 1 + * filter */ +/*@}*/ + +/** @name Control register bit masks + * @{ + */ +#define XCRE_CTL_SW_EN_MASK 0x00000001 /**< Enable mask */ +#define XCRE_CTL_RUE_MASK 0x00000002 /**< Register update mask */ +#define XCRE_CTL_BPE_MASK 0x00000010 /**< Bypass mask */ +#define XCRE_CTL_TPE_MASK 0x00000020 /**< Test pattern mask */ +#define XCRE_CTL_AUTORESET_MASK 0x40000000 /**< Software reset - + * Auto-synchronize to SOF + * mask */ +#define XCRE_CTL_RESET_MASK 0x80000000 /**< Software reset - + * instantaneous mask */ +/*@}*/ + +/** @name Interrupt register bit masks. It is applicable for + * Status and IRQ_ENABLE Registers + * @{ + */ +#define XCRE_IXR_PROCS_STARTED_MASK 0x00000001 /**< Proc started mask */ +#define XCRE_IXR_EOF_MASK 0x00000002 /**< End-Of-Frame mask */ +#define XCRE_IXR_SE_MASK 0x00010000 /**< Slave Error mask */ +#define XCRE_IXR_ALLINTR_MASK 0x00010003U /**< OR of all mask */ + /* ((XCRE_IXR_PROCS_MASK) | (XCRE_IXR_EOF_MASK) | \ + * (XCRE_IXR_SE_MASK)) */ + +/*@}*/ + +/** @name Error register bit masks + * @{ + */ +#define XCRE_ERR_EOL_EARLY_MASK 0x00000001 /**< Error: End of Line + * Early mask */ +#define XCRE_ERR_EOL_LATE_MASK 0x00000002 /**< Error: End of Line + * Late mask */ +#define XCRE_ERR_SOF_EARLY_MASK 0x00000004 /**< Error: Start of + * Frame Early mask */ +#define XCRE_ERR_SOF_LATE_MASK 0x00000008 /**< Error: Start of + * Frame Late mask */ +/*@}*/ + +/** @name Version register bit masks and shifts + * @{ + */ +#define XCRE_VER_REV_NUM_MASK 0x000000FF /**< Revision Number mask */ +#define XCRE_VER_PID_MASK 0x00000F00 /**< Patch ID mask */ +#define XCRE_VER_REV_MASK 0x0000F000 /**< Version Revision mask */ +#define XCRE_VER_MINOR_MASK 0x00FF0000 /**< Version Minor mask */ +#define XCRE_VER_MAJOR_MASK 0xFF000000 /**< Version Major mask */ + +#define XCRE_VER_INTERNAL_SHIFT 0x00000008 /**< Patch ID shift */ +#define XCRE_VER_REV_SHIFT 0x0000000C /**< Version Revision shift */ +#define XCRE_VER_MINOR_SHIFT 0x00000010 /**< Version Minor shift */ +#define XCRE_VER_MAJOR_SHIFT 0x00000018 /**< Version Major shift */ + +/*@}*/ + +/** @name Active size register bit masks and shifts + * @{ + */ +#define XCRE_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF /**< Number of Active pixels + * per scan line (horizontal) + * mask */ +#define XCRE_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 /**< Number of Active lines per + * frame (Vertical) mask */ +#define XCRE_ACTSIZE_NUM_LINE_SHIFT 16 /**< Shift for number of + * lines */ +/*@}*/ + +/** @name Encoding register bit masks and shifts + * @{ + */ +#define XCRE_ENCODING_FIELD_MASK 0x00000080 /**< Field parity mask */ +#define XCRE_ENCODING_CHROMA_MASK 0x00000100 /**< Chroma parity mask */ +#define XCRE_ENCODING_FIELD_SHIFT 7 /**< Field parity shift */ +#define XCRE_ENCODING_CHROMA_SHIFT 8 /**< Chroma parity shift */ +/*@}*/ + +/** @name Coefficient bit mask and shift + * @{ + */ +#define XCRE_COEFF_FRAC_MASK 0x00003FFF /**< Mask of Fractional part */ +#define XCRE_COEF_DECI_MASK 0x00004000 /**< Mask of Decimal part */ +#define XCRE_COEF_SIGN_MASK 0x00008000 /**< Mask for Coefficient sign + * bit */ +#define XCRE_COEFF_MASK 0x0000FFFF /**< Coefficient mask */ +#define XCRE_COEFF_SHIFT 14 /**< Shift for decimal value */ +#define XCRE_COEFF_SIGN_SHIFT 16 /**< Coefficient shift */ + +/*@}*/ + +/** @name General purpose macros + * @{ + */ +#define XCRE_SIGN_MUL -1 /**< Macro for sign + * multiplication */ +#define XCRE_SIGNBIT_MASK 0x10000000 /** Mask for sign bit of 32 + * bit number */ +#define XCRE_MAX_VALUE 0xFFFFFFFF /**< 32 bit maximum value */ + +/*@}*/ +/** @name backward compatibility macros + * + * To support backward compatibility following macro definition are + * re-defined. + * @{ + */ +#define CRESAMPLE_CONTROL XCRE_CONTROL_OFFSET +#define CRESAMPLE_STATUS XCRE_STATUS_OFFSET +#define CRESAMPLE_ERROR XCRE_ERROR_OFFSET +#define CRESAMPLE_IRQ_ENABLE XCRE_IRQ_EN_OFFSET +#define CRESAMPLE_VERSION XCRE_VERSION_OFFSET +#define CRESAMPLE_SYSDEBUG0 XCRE_SYSDEBUG0_OFFSET +#define CRESAMPLE_SYSDEBUG1 XCRE_SYSDEBUG1_OFFSET +#define CRESAMPLE_SYSDEBUG2 XCRE_SYSDEBUG2_OFFSET + +#define CRESAMPLE_ACTIVE_SIZE XCRE_ACTIVE_SIZE_OFFSET +#define CRESAMPLE_ENCODING XCRE_ENCODING_OFFSET + +#define CRESAMPLE_COEF00_HPHASE0 XCRE_COEF00_HPHASE0_OFFSET +#define CRESAMPLE_COEF01_HPHASE0 XCRE_COEF01_HPHASE0_OFFSET +#define CRESAMPLE_COEF02_HPHASE0 XCRE_COEF02_HPHASE0_OFFSET +#define CRESAMPLE_COEF03_HPHASE0 XCRE_COEF03_HPHASE0_OFFSET +#define CRESAMPLE_COEF04_HPHASE0 XCRE_COEF04_HPHASE0_OFFSET +#define CRESAMPLE_COEF05_HPHASE0 XCRE_COEF05_HPHASE0_OFFSET +#define CRESAMPLE_COEF06_HPHASE0 XCRE_COEF06_HPHASE0_OFFSET +#define CRESAMPLE_COEF07_HPHASE0 XCRE_COEF07_HPHASE0_OFFSET +#define CRESAMPLE_COEF08_HPHASE0 XCRE_COEF08_HPHASE0_OFFSET +#define CRESAMPLE_COEF09_HPHASE0 XCRE_COEF09_HPHASE0_OFFSET +#define CRESAMPLE_COEF10_HPHASE0 XCRE_COEF10_HPHASE0_OFFSET +#define CRESAMPLE_COEF11_HPHASE0 XCRE_COEF11_HPHASE0_OFFSET +#define CRESAMPLE_COEF12_HPHASE0 XCRE_COEF12_HPHASE0_OFFSET +#define CRESAMPLE_COEF13_HPHASE0 XCRE_COEF13_HPHASE0_OFFSET +#define CRESAMPLE_COEF14_HPHASE0 XCRE_COEF14_HPHASE0_OFFSET +#define CRESAMPLE_COEF15_HPHASE0 XCRE_COEF15_HPHASE0_OFFSET +#define CRESAMPLE_COEF16_HPHASE0 XCRE_COEF16_HPHASE0_OFFSET +#define CRESAMPLE_COEF17_HPHASE0 XCRE_COEF17_HPHASE0_OFFSET +#define CRESAMPLE_COEF18_HPHASE0 XCRE_COEF18_HPHASE0_OFFSET +#define CRESAMPLE_COEF19_HPHASE0 XCRE_COEF19_HPHASE0_OFFSET +#define CRESAMPLE_COEF20_HPHASE0 XCRE_COEF20_HPHASE0_OFFSET +#define CRESAMPLE_COEF21_HPHASE0 XCRE_COEF21_HPHASE0_OFFSET +#define CRESAMPLE_COEF22_HPHASE0 XCRE_COEF22_HPHASE0_OFFSET +#define CRESAMPLE_COEF23_HPHASE0 XCRE_COEF23_HPHASE0_OFFSET + +#define CRESAMPLE_COEF00_HPHASE1 XCRE_COEF00_HPHASE1_OFFSET +#define CRESAMPLE_COEF01_HPHASE1 XCRE_COEF01_HPHASE1_OFFSET +#define CRESAMPLE_COEF02_HPHASE1 XCRE_COEF02_HPHASE1_OFFSET +#define CRESAMPLE_COEF03_HPHASE1 XCRE_COEF03_HPHASE1_OFFSET +#define CRESAMPLE_COEF04_HPHASE1 XCRE_COEF04_HPHASE1_OFFSET +#define CRESAMPLE_COEF05_HPHASE1 XCRE_COEF05_HPHASE1_OFFSET +#define CRESAMPLE_COEF06_HPHASE1 XCRE_COEF06_HPHASE1_OFFSET +#define CRESAMPLE_COEF07_HPHASE1 XCRE_COEF07_HPHASE1_OFFSET +#define CRESAMPLE_COEF08_HPHASE1 XCRE_COEF08_HPHASE1_OFFSET +#define CRESAMPLE_COEF09_HPHASE1 XCRE_COEF09_HPHASE1_OFFSET +#define CRESAMPLE_COEF10_HPHASE1 XCRE_COEF10_HPHASE1_OFFSET +#define CRESAMPLE_COEF11_HPHASE1 XCRE_COEF11_HPHASE1_OFFSET +#define CRESAMPLE_COEF12_HPHASE1 XCRE_COEF12_HPHASE1_OFFSET +#define CRESAMPLE_COEF13_HPHASE1 XCRE_COEF13_HPHASE1_OFFSET +#define CRESAMPLE_COEF14_HPHASE1 XCRE_COEF14_HPHASE1_OFFSET +#define CRESAMPLE_COEF15_HPHASE1 XCRE_COEF15_HPHASE1_OFFSET +#define CRESAMPLE_COEF16_HPHASE1 XCRE_COEF16_HPHASE1_OFFSET +#define CRESAMPLE_COEF17_HPHASE1 XCRE_COEF17_HPHASE1_OFFSET +#define CRESAMPLE_COEF18_HPHASE1 XCRE_COEF18_HPHASE1_OFFSET +#define CRESAMPLE_COEF19_HPHASE1 XCRE_COEF19_HPHASE1_OFFSET +#define CRESAMPLE_COEF20_HPHASE1 XCRE_COEF20_HPHASE1_OFFSET +#define CRESAMPLE_COEF21_HPHASE1 XCRE_COEF21_HPHASE1_OFFSET +#define CRESAMPLE_COEF22_HPHASE1 XCRE_COEF22_HPHASE1_OFFSET +#define CRESAMPLE_COEF23_HPHASE1 XCRE_COEF23_HPHASE1_OFFSET + +#define CRESAMPLE_COEF00_VPHASE0 XCRE_COEF00_VPHASE0_OFFSET +#define CRESAMPLE_COEF01_VPHASE0 XCRE_COEF01_VPHASE0_OFFSET +#define CRESAMPLE_COEF02_VPHASE0 XCRE_COEF02_VPHASE0_OFFSET +#define CRESAMPLE_COEF03_VPHASE0 XCRE_COEF03_VPHASE0_OFFSET +#define CRESAMPLE_COEF04_VPHASE0 XCRE_COEF04_VPHASE0_OFFSET +#define CRESAMPLE_COEF05_VPHASE0 XCRE_COEF05_VPHASE0_OFFSET +#define CRESAMPLE_COEF06_VPHASE0 XCRE_COEF06_VPHASE0_OFFSET +#define CRESAMPLE_COEF07_VPHASE0 XCRE_COEF07_VPHASE0_OFFSET + +#define CRESAMPLE_COEF00_VPHASE1 XCRE_COEF00_VPHASE1_OFFSET +#define CRESAMPLE_COEF01_VPHASE1 XCRE_COEF01_VPHASE1_OFFSET +#define CRESAMPLE_COEF02_VPHASE1 XCRE_COEF02_VPHASE1_OFFSET +#define CRESAMPLE_COEF03_VPHASE1 XCRE_COEF03_VPHASE1_OFFSET +#define CRESAMPLE_COEF04_VPHASE1 XCRE_COEF04_VPHASE1_OFFSET +#define CRESAMPLE_COEF05_VPHASE1 XCRE_COEF05_VPHASE1_OFFSET +#define CRESAMPLE_COEF06_VPHASE1 XCRE_COEF06_VPHASE1_OFFSET +#define CRESAMPLE_COEF07_VPHASE1 XCRE_COEF07_VPHASE1_OFFSET + +#define CRESAMPLE_CTL_EN_MASK XCRE_CTL_SW_EN_MASK +#define CRESAMPLE_CTL_RU_MASK XCRE_CTL_RUE_MASK +#define CRESAMPLE_CTL_AUTORESET XCRE_CTL_AUTORESET_MASK +#define CRESAMPLE_CTL_RESET XCRE_CTL_RESET_MASK + +#define CRESAMPLE_In32 XCresample_In32 +#define CRESAMPLE_Out32 XCresample_Out32 + +#define CRESAMPLE_ReadReg XCresample_ReadReg +#define CRESAMPLE_WriteReg XCresample_WriteReg +/*@}*/ + +/** @name Interrupt registers + * @{ + */ +#define XCRE_ISR_OFFSET XCRE_STATUS_OFFSET /**< Interrupt status + * register */ +#define XCRE_IER_OFFSET XCRE_IRQ_EN_OFFSET /**< Interrupt enable + .*..register + * corresponds to + * status bits */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XCresample_In32 Xil_In32 /**< Input operations */ +#define XCresample_Out32 Xil_Out32 /**< Output operations */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the Chroma +* Resampler core +* @param RegOffset is the register offset of the register (defined at +* top of this file) +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XCresample_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XCresample_ReadReg(BaseAddress, RegOffset) \ + XCresample_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes into the given register. +* +* @param BaseAddress is the Xilinx base address of the Chroma +* Resampler core +* @param RegOffset is the register offset of the register +* (defined at top of this file) +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XCresample_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +******************************************************************************/ +#define XCresample_WriteReg(BaseAddress, RegOffset, Data) \ + XCresample_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Declarations ****************************/ + + +#ifdef __cplusplus +} + +#endif +#endif /* End of protection macro */ diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample_intr.c b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_intr.c new file mode 100755 index 00000000..996efc66 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_intr.c @@ -0,0 +1,212 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample_intr.c +* +* This file contains interrupt related functions of Chroma Resampler core +* Please see xcresample.h for more details of the core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 4.0   adk     03/12/14 First Release.
+*                        Implemented XCresample_IntrHandler and
+*                        XCresample_SetCallBack functions.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcresample.h" + +/************************** Constant Definitions *****************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function is the interrupt handler for the Chroma Resampler driver. +* +* This handler reads the pending interrupt from the STATUS register, +* determines the source of the interrupts and calls the respective +* callbacks for the interrupts that are enabled in IRQ_ENABLE register, +* and finally clears the interrupts. +* +* The application is responsible for connecting this function to the interrupt +* system. Application beyond this driver is also responsible for providing +* callbacks to handle interrupts and installing the callbacks using +* Xcresample_SetCallBack() during initialization phase. +* +* @param InstancePtr is a pointer to the XCresample instance that just +* interrupted. +* +* @return None. +* +* @note Interrupt interface should be enabled. +* +******************************************************************************/ +void XCresample_IntrHandler(void *InstancePtr) +{ + u32 PendingIntr; + u32 ErrorStatus; + XCresample *XCresamplePtr = NULL; + XCresamplePtr = (XCresample *)((void *)InstancePtr); + + /* Verify Arguments. */ + Xil_AssertVoid(XCresamplePtr != NULL); + Xil_AssertVoid(XCresamplePtr->IsReady == + (u32)(XIL_COMPONENT_IS_READY)); + Xil_AssertVoid(XCresamplePtr->Config.HasIntcIf != (u16)0x0); + + /* Get pending interrupts */ + PendingIntr = (u32)XCresample_IntrGetPending(XCresamplePtr); + + /* A Slave Error interrupt has happened */ + if (((PendingIntr) & (XCRE_IXR_SE_MASK)) == + (XCRE_IXR_SE_MASK)) { + ErrorStatus = (PendingIntr) & ((u32)(XCRE_IXR_SE_MASK)); + XCresamplePtr->ErrCallBack(XCresamplePtr->ErrRef, ErrorStatus); + } + + /* A processing start has happened */ + if (((PendingIntr) & (XCRE_IXR_PROCS_STARTED_MASK)) == + (XCRE_IXR_PROCS_STARTED_MASK)) { + XCresamplePtr->ProcStartCallBack + (XCresamplePtr->ProcStartRef); + } + + /* A frame done interrupt has happened */ + if (((PendingIntr) & (XCRE_IXR_EOF_MASK)) == + (XCRE_IXR_EOF_MASK)) { + XCresamplePtr->FrameDoneCallBack + (XCresamplePtr->FrameDoneRef); + } + + /* Clear pending interrupt(s) */ + XCresample_IntrClear(XCresamplePtr, PendingIntr); +} + +/*****************************************************************************/ +/** +* +* This routine installs an asynchronous callback function for the given +* HandlerType: +* +* 
+* HandlerType              Callback Function Type
+* -----------------------  --------------------------------------------------
+* XCRE_HANDLER_FRAMEDONE   FrameDoneCallBack
+* XCRE_HANDLER_PROCSTART   ProcStartCallBack
+* XCRE_HANDLER_ERROR       ErrCallBack
+*
+*
+* +* @param InstancePtr is a pointer to the XCresample instance to be +* worked on. +* @param HandlerType specifies which callback is to be attached. +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return +* - XST_SUCCESS when handler is installed. +* - XST_INVALID_PARAM when HandlerType is invalid. +* +* @note Invoking this function for a handler that already has been +* installed replaces it with the new handler. +* +******************************************************************************/ +int XCresample_SetCallBack(XCresample *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef) +{ + int Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == + (u32)(XIL_COMPONENT_IS_READY)); + Xil_AssertNonvoid(CallBackFunc != NULL); + Xil_AssertNonvoid(CallBackRef != NULL); + Xil_AssertNonvoid((HandlerType >= XCRE_HANDLER_PROCSTART) && + (HandlerType <= XCRE_HANDLER_ERROR)); + + /* Calls the respective call backs according to handler type */ + switch (HandlerType) { + case XCRE_HANDLER_PROCSTART: + InstancePtr->ProcStartCallBack = + (XCresample_CallBack)((void *)CallBackFunc); + InstancePtr->ProcStartRef = CallBackRef; + Status = (XST_SUCCESS); + break; + + case XCRE_HANDLER_FRAMEDONE: + InstancePtr->FrameDoneCallBack = + (XCresample_CallBack)((void *)CallBackFunc); + InstancePtr->FrameDoneRef = CallBackRef; + Status = (XST_SUCCESS); + break; + + case XCRE_HANDLER_ERROR: + InstancePtr->ErrCallBack = + (XCresample_ErrorCallBack)((void *)CallBackFunc); + InstancePtr->ErrRef = CallBackRef; + Status = (XST_SUCCESS); + break; + + default: + Status = (XST_INVALID_PARAM); + break; + + } + + return Status; +} diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample_selftest.c b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_selftest.c new file mode 100755 index 00000000..a12a70c7 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_selftest.c @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample_selftest.c +* +* This file contains the self-test functions for the Chroma Resampler core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -------------------------------------------------
+* 4.0   adk     03/12/14 First release
+*                        Implemented XCresample_SelfTest function.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcresample.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function reads version register of Chroma Resampler core and compares +* with zero as part of self test. +* +* @param InstancePtr is a pointer to the XCresample instance. +* +* @return +* - XST_SUCCESS if the test is successful. +* - XST_FAILURE if the test is failed. +* +* @note None. +* +******************************************************************************/ +int XCresample_SelfTest(XCresample *InstancePtr) +{ + u32 Version; + int Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Version = XCresample_ReadReg(InstancePtr->Config.BaseAddress, + (XCRE_VERSION_OFFSET)); + + /* Comparing Version with zero */ + if (Version != (u32)0x0) { + Status = (XST_SUCCESS); + } + else { + Status = (XST_FAILURE); + } + + return Status; +} diff --git a/XilinxProcessorIPLib/drivers/cresample/src/xcresample_sinit.c b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_sinit.c new file mode 100755 index 00000000..92bc0689 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/cresample/src/xcresample_sinit.c @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcresample_sinit.c +* +* This file contains initialization methods for Xilinx Chroma Resampler core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- --------------------------------------------------
+* 4.0   adk     03/12/14 First release.
+*                        Implemented XCresample_LookupConfig function.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xcresample.h" + + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Declaration *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function returns a reference to an XCresample_Config structure based on +* the unique device id, DeviceId. The return value will refer to an +* entry in the device configuration table defined in the xcresample_g.c file. +* +* @param DeviceId is the unique device ID of the device for the lookup +* operation. +* +* @return XCresample_LookupConfig returns a reference to a config record +* in the configuration table (in xcresample_g.c) corresponding to +* DeviceId, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XCresample_Config *XCresample_LookupConfig(u16 DeviceId) +{ + extern XCresample_Config + XCresample_ConfigTable[XPAR_CRESAMPLE_NUM_INSTANCES]; + u32 Index; + XCresample_Config *CfgPtr = NULL; + + /* + * Checking for which instance's device id is + * matching with our device id + */ + for (Index = (u32)0x0; Index < (u32)(XPAR_CRESAMPLE_NUM_INSTANCES); + Index++) { + + /* If device ids are equal assign address to CfgPtr */ + if (XCresample_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCresample_ConfigTable[Index]; + break; + } + } + + return (XCresample_Config *)CfgPtr; +}