From b016d1f766ba8f23ab0dadea63f9db1ad784fd1f Mon Sep 17 00:00:00 2001 From: Venkata Naga Sai Krishna Kolapalli Date: Fri, 10 Apr 2015 17:17:28 +0530 Subject: [PATCH] uartps_v3_1 : Removed status register bit defines. This patch removes the status register bit definations that are not available on the RTL. Signed-off-by: Venkata Naga Sai Krishna Kolapalli --- XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h b/XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h index 9f3db703..b71684f7 100644 --- a/XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h +++ b/XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h @@ -296,11 +296,6 @@ extern "C" { #define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ #define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ #define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ -#define XUARTPS_SR_DMS 0x00000200U /**< Delta modem status change */ -#define XUARTPS_SR_TOUT 0x00000100U /**< RX timeout */ -#define XUARTPS_SR_PARITY 0x00000080U /**< RX parity error */ -#define XUARTPS_SR_FRAME 0x00000040U /**< RX frame error */ -#define XUARTPS_SR_OVER 0x00000020U /**< RX overflow error */ #define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ #define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ #define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */