From b239d6a0db85eafaa176e6f8bfde5620dabcb709 Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Fri, 16 Oct 2015 18:06:37 +0530 Subject: [PATCH] bsp: a53: asm instructions have been modified to return proper value This patch modifies asm instruction ldr and mfcp for a53 64bit mode to return 64bit values Signed-off-by: Kinjal Pravinbhai Patel Acked-by: Anirudha Sarangi --- lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h b/lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h index 2b38c8ff..58dd8abc 100644 --- a/lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h +++ b/lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h @@ -110,7 +110,7 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({u32 rval; \ +#define ldr(adr) ({u64 rval; \ __asm__ __volatile__(\ "ldr %0,[%1]"\ : "=r" (rval) : "r" (adr)\ @@ -151,7 +151,7 @@ extern "C" { #define mtcptlbi(reg) asm("tlbi " #reg) #define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ -#define mfcp(reg) ({u32 rval;\ +#define mfcp(reg) ({u64 rval;\ asm("mrs %0, " #reg : "=r" (rval));\ rval;\ })