From b276c691217b9f897f6cb10342d6e4fb0cfc49c2 Mon Sep 17 00:00:00 2001 From: Rohit Consul Date: Thu, 16 Jul 2015 17:04:58 -0700 Subject: [PATCH] v_hscaler: Updated driver to align with hip flow This patch supports HIP based video processing subsystem by reorganizing the HLS generated code to align with xilinx driver guidelines. Signed-off-by: Rohit Consul Reviewed-by: Andrei Simion --- .../drivers/v_hscaler/data/v_hscaler.mdd | 0 .../drivers/v_hscaler/data/v_hscaler.tcl | 79 ++++++++++------ .../drivers/v_hscaler/src/xv_hscaler.c | 93 ++++++++++--------- .../drivers/v_hscaler/src/xv_hscaler.h | 16 ++-- .../drivers/v_hscaler/src/xv_hscaler_g.c | 63 +++++++++++++ .../drivers/v_hscaler/src/xv_hscaler_l2.c | 8 +- .../drivers/v_hscaler/src/xv_hscaler_l2.h | 3 +- .../drivers/v_hscaler/src/xv_hscaler_linux.c | 18 ++-- .../drivers/v_hscaler/src/xv_hscaler_sinit.c | 40 ++++---- 9 files changed, 214 insertions(+), 106 deletions(-) mode change 100644 => 100755 XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.mdd mode change 100644 => 100755 XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.tcl create mode 100644 XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_g.c diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.mdd b/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.mdd old mode 100644 new mode 100755 diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.tcl b/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.tcl old mode 100644 new mode 100755 index 926a0c15..128d084f --- a/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.tcl +++ b/XilinxProcessorIPLib/drivers/v_hscaler/data/v_hscaler.tcl @@ -1,9 +1,33 @@ -# ============================================================== -# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -# Version: 2015.1 -# Copyright (C) 2015 Xilinx Inc. All rights reserved. +############################################################################## # -# ============================================================== +# Copyright (C) 2015 Xilinx, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"),to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# Use of the Software is limited solely to applications: +# (a) running on a Xilinx device, or +# (b) that interact with a Xilinx device through a bus or interconnect. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Except as contained in this notice, the name of the Xilinx shall not be used +# in advertising or otherwise to promote the sale, use or other dealings in +# this Software without prior written authorization from Xilinx. +############################################################################### proc generate {drv_handle} { xdefine_include_file $drv_handle "xparameters.h" "XV_hscaler" \ @@ -11,36 +35,39 @@ proc generate {drv_handle} { "DEVICE_ID" \ "C_S_AXI_CTRL_BASEADDR" \ "C_S_AXI_CTRL_HIGHADDR" \ - "SAMPLES_PER_CLOCK" \ - "MAX_COLS" \ - "MAX_ROWS" \ - "MAX_DATA_WIDTH" \ - "PHASE_SHIFT" \ - "SCALE_MODE" \ - "TAPS" + "SAMPLES_PER_CLOCK" \ + "NUM_VIDEO_COMPONENTS" \ + "MAX_COLS" \ + "MAX_ROWS" \ + "MAX_DATA_WIDTH" \ + "PHASE_SHIFT" \ + "SCALE_MODE" \ + "TAPS" xdefine_config_file $drv_handle "xv_hscaler_g.c" "XV_hscaler" \ "DEVICE_ID" \ "C_S_AXI_CTRL_BASEADDR" \ - "SAMPLES_PER_CLOCK" \ - "MAX_COLS" \ - "MAX_ROWS" \ - "MAX_DATA_WIDTH" \ - "PHASE_SHIFT" \ - "SCALE_MODE" \ - "TAPS" + "SAMPLES_PER_CLOCK" \ + "NUM_VIDEO_COMPONENTS" \ + "MAX_COLS" \ + "MAX_ROWS" \ + "MAX_DATA_WIDTH" \ + "PHASE_SHIFT" \ + "SCALE_MODE" \ + "TAPS" xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_hscaler" \ "DEVICE_ID" \ "C_S_AXI_CTRL_BASEADDR" \ "C_S_AXI_CTRL_HIGHADDR" \ - "SAMPLES_PER_CLOCK" \ - "MAX_COLS" \ - "MAX_ROWS" \ - "MAX_DATA_WIDTH" \ - "PHASE_SHIFT" \ - "SCALE_MODE" \ - "TAPS" + "SAMPLES_PER_CLOCK" \ + "NUM_VIDEO_COMPONENTS" \ + "MAX_COLS" \ + "MAX_ROWS" \ + "MAX_DATA_WIDTH" \ + "PHASE_SHIFT" \ + "SCALE_MODE" \ + "TAPS" } diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.c index 2cdb1b86..d3ad2c24 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.c +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.c @@ -11,16 +11,21 @@ /************************** Function Implementation *************************/ #ifndef __linux__ -int XV_hscaler_CfgInitialize(XV_hscaler *InstancePtr, XV_hscaler_Config *ConfigPtr) { +int XV_hscaler_CfgInitialize(XV_hscaler *InstancePtr, + XV_hscaler_Config *ConfigPtr, + u32 EffectiveAddr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != (u32)0x0); - /* Setup the instance */ - (void)memset((void *)InstancePtr, 0, sizeof(XV_hscaler)); - (void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr, - sizeof(XV_hscaler_Config)); + /* Setup the instance */ + (void)memset((void *)InstancePtr, 0, sizeof(XV_hscaler)); + (void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr, + sizeof(XV_hscaler_Config)); - InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress; + InstancePtr->Config.BaseAddress = EffectiveAddr; + + /* Set the flag to indicate the driver is ready */ InstancePtr->IsReady = XIL_COMPONENT_IS_READY; return XST_SUCCESS; @@ -33,8 +38,8 @@ void XV_hscaler_Start(XV_hscaler *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL) & 0x80; - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, Data | 0x01); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL) & 0x80; + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, Data | 0x01); } u32 XV_hscaler_IsDone(XV_hscaler *InstancePtr) { @@ -43,7 +48,7 @@ u32 XV_hscaler_IsDone(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); return (Data >> 1) & 0x1; } @@ -53,7 +58,7 @@ u32 XV_hscaler_IsIdle(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); return (Data >> 2) & 0x1; } @@ -63,7 +68,7 @@ u32 XV_hscaler_IsReady(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); // check ap_start to see if the pcore is ready for next input return !(Data & 0x1); } @@ -72,21 +77,21 @@ void XV_hscaler_EnableAutoRestart(XV_hscaler *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, 0x80); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, 0x80); } void XV_hscaler_DisableAutoRestart(XV_hscaler *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, 0); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL, 0); } void XV_hscaler_Set_HwReg_Height(XV_hscaler *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_HEIGHT_DATA, Data); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_HEIGHT_DATA, Data); } u32 XV_hscaler_Get_HwReg_Height(XV_hscaler *InstancePtr) { @@ -95,7 +100,7 @@ u32 XV_hscaler_Get_HwReg_Height(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_HEIGHT_DATA); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_HEIGHT_DATA); return Data; } @@ -103,7 +108,7 @@ void XV_hscaler_Set_HwReg_WidthIn(XV_hscaler *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHIN_DATA, Data); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHIN_DATA, Data); } u32 XV_hscaler_Get_HwReg_WidthIn(XV_hscaler *InstancePtr) { @@ -112,7 +117,7 @@ u32 XV_hscaler_Get_HwReg_WidthIn(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHIN_DATA); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHIN_DATA); return Data; } @@ -120,7 +125,7 @@ void XV_hscaler_Set_HwReg_WidthOut(XV_hscaler *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHOUT_DATA, Data); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHOUT_DATA, Data); } u32 XV_hscaler_Get_HwReg_WidthOut(XV_hscaler *InstancePtr) { @@ -129,7 +134,7 @@ u32 XV_hscaler_Get_HwReg_WidthOut(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHOUT_DATA); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_WIDTHOUT_DATA); return Data; } @@ -137,7 +142,7 @@ void XV_hscaler_Set_HwReg_ColorMode(XV_hscaler *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_COLORMODE_DATA, Data); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_COLORMODE_DATA, Data); } u32 XV_hscaler_Get_HwReg_ColorMode(XV_hscaler *InstancePtr) { @@ -146,7 +151,7 @@ u32 XV_hscaler_Get_HwReg_ColorMode(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_COLORMODE_DATA); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_COLORMODE_DATA); return Data; } @@ -154,7 +159,7 @@ void XV_hscaler_Set_HwReg_PixelRate(XV_hscaler *InstancePtr, u32 Data) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_PIXELRATE_DATA, Data); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_PIXELRATE_DATA, Data); } u32 XV_hscaler_Get_HwReg_PixelRate(XV_hscaler *InstancePtr) { @@ -163,7 +168,7 @@ u32 XV_hscaler_Get_HwReg_PixelRate(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Data = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_PIXELRATE_DATA); + Data = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_HWREG_PIXELRATE_DATA); return Data; } @@ -171,14 +176,14 @@ u32 XV_hscaler_Get_HwReg_hfltCoeff_BaseAddress(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return (InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE); + return (InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE); } u32 XV_hscaler_Get_HwReg_hfltCoeff_HighAddress(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return (InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_HIGH); + return (InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_HIGH); } u32 XV_hscaler_Get_HwReg_hfltCoeff_TotalBytes(XV_hscaler *InstancePtr) { @@ -212,7 +217,7 @@ u32 XV_hscaler_Write_HwReg_hfltCoeff_Words(XV_hscaler *InstancePtr, int offset, return 0; for (i = 0; i < length; i++) { - *(int *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + (offset + i)*4) = *(data + i); + *(int *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + (offset + i)*4) = *(data + i); } return length; } @@ -227,7 +232,7 @@ u32 XV_hscaler_Read_HwReg_hfltCoeff_Words(XV_hscaler *InstancePtr, int offset, i return 0; for (i = 0; i < length; i++) { - *(data + i) = *(int *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + (offset + i)*4); + *(data + i) = *(int *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + (offset + i)*4); } return length; } @@ -242,7 +247,7 @@ u32 XV_hscaler_Write_HwReg_hfltCoeff_Bytes(XV_hscaler *InstancePtr, int offset, return 0; for (i = 0; i < length; i++) { - *(char *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + offset + i) = *(data + i); + *(char *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + offset + i) = *(data + i); } return length; } @@ -257,7 +262,7 @@ u32 XV_hscaler_Read_HwReg_hfltCoeff_Bytes(XV_hscaler *InstancePtr, int offset, c return 0; for (i = 0; i < length; i++) { - *(data + i) = *(char *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + offset + i); + *(data + i) = *(char *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE + offset + i); } return length; } @@ -266,14 +271,14 @@ u32 XV_hscaler_Get_HwReg_phasesH_V_BaseAddress(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return (InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE); + return (InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE); } u32 XV_hscaler_Get_HwReg_phasesH_V_HighAddress(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return (InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_HIGH); + return (InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_HIGH); } u32 XV_hscaler_Get_HwReg_phasesH_V_TotalBytes(XV_hscaler *InstancePtr) { @@ -307,7 +312,7 @@ u32 XV_hscaler_Write_HwReg_phasesH_V_Words(XV_hscaler *InstancePtr, int offset, return 0; for (i = 0; i < length; i++) { - *(int *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + (offset + i)*4) = *(data + i); + *(int *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + (offset + i)*4) = *(data + i); } return length; } @@ -322,7 +327,7 @@ u32 XV_hscaler_Read_HwReg_phasesH_V_Words(XV_hscaler *InstancePtr, int offset, i return 0; for (i = 0; i < length; i++) { - *(data + i) = *(int *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + (offset + i)*4); + *(data + i) = *(int *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + (offset + i)*4); } return length; } @@ -337,7 +342,7 @@ u32 XV_hscaler_Write_HwReg_phasesH_V_Bytes(XV_hscaler *InstancePtr, int offset, return 0; for (i = 0; i < length; i++) { - *(char *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + offset + i) = *(data + i); + *(char *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + offset + i) = *(data + i); } return length; } @@ -352,7 +357,7 @@ u32 XV_hscaler_Read_HwReg_phasesH_V_Bytes(XV_hscaler *InstancePtr, int offset, c return 0; for (i = 0; i < length; i++) { - *(data + i) = *(char *)(InstancePtr->Ctrl_BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + offset + i); + *(data + i) = *(char *)(InstancePtr->Config.BaseAddress + XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE + offset + i); } return length; } @@ -361,14 +366,14 @@ void XV_hscaler_InterruptGlobalEnable(XV_hscaler *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_GIE, 1); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_GIE, 1); } void XV_hscaler_InterruptGlobalDisable(XV_hscaler *InstancePtr) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_GIE, 0); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_GIE, 0); } void XV_hscaler_InterruptEnable(XV_hscaler *InstancePtr, u32 Mask) { @@ -377,8 +382,8 @@ void XV_hscaler_InterruptEnable(XV_hscaler *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Register = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_IER); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_IER, Register | Mask); + Register = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_IER); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_IER, Register | Mask); } void XV_hscaler_InterruptDisable(XV_hscaler *InstancePtr, u32 Mask) { @@ -387,27 +392,27 @@ void XV_hscaler_InterruptDisable(XV_hscaler *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Register = XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_IER); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_IER, Register & (~Mask)); + Register = XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_IER); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_IER, Register & (~Mask)); } void XV_hscaler_InterruptClear(XV_hscaler *InstancePtr, u32 Mask) { Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - XV_hscaler_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_ISR, Mask); + XV_hscaler_WriteReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_ISR, Mask); } u32 XV_hscaler_InterruptGetEnabled(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_IER); + return XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_IER); } u32 XV_hscaler_InterruptGetStatus(XV_hscaler *InstancePtr) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - return XV_hscaler_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_ISR); + return XV_hscaler_ReadReg(InstancePtr->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_ISR); } diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.h b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.h index b43a671c..bf84e02c 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.h +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler.h @@ -45,14 +45,15 @@ typedef uint32_t u32; */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 Ctrl_BaseAddress; /**< The base address of the core instance. */ - int PixPerClk; /**< Samples Per Clock supported by core instance */ + u32 BaseAddress; /**< The base address of the core instance. */ + u16 PixPerClk; /**< Samples Per Clock supported by core instance */ + u16 NumVidComponents; /**< Number of Video Components */ u16 MaxWidth; /**< Maximum columns supported by core instance */ u16 MaxHeight; /**< Maximum rows supported by core instance */ - int MaxDataWidth; /**< Maximum Data width of each channel */ + u16 MaxDataWidth; /**< Maximum Data width of each channel */ u16 PhaseShift; /**< Max num of phases (2^PhaseShift) */ - int ScalerType; /**< Scaling Algorithm Selected */ - int NumTaps; /**< Number of taps */ + u16 ScalerType; /**< Scaling Algorithm Selected */ + u16 NumTaps; /**< Number of taps */ } XV_hscaler_Config; #endif @@ -61,7 +62,6 @@ typedef struct { */ typedef struct { XV_hscaler_Config Config; /**< Hardware Configuration */ - u32 Ctrl_BaseAddress; /**< The base address of the core instance. */ u32 IsReady; /**< Device is initialized and ready */ } XV_hscaler; @@ -90,7 +90,9 @@ typedef struct { #ifndef __linux__ int XV_hscaler_Initialize(XV_hscaler *InstancePtr, u16 DeviceId); XV_hscaler_Config* XV_hscaler_LookupConfig(u16 DeviceId); -int XV_hscaler_CfgInitialize(XV_hscaler *InstancePtr, XV_hscaler_Config *ConfigPtr); +int XV_hscaler_CfgInitialize(XV_hscaler *InstancePtr, + XV_hscaler_Config *ConfigPtr, + u32 EffectiveAddr); #else int XV_hscaler_Initialize(XV_hscaler *InstancePtr, const char* InstanceName); int XV_hscaler_Release(XV_hscaler *InstancePtr); diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_g.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_g.c new file mode 100644 index 00000000..3958ab10 --- /dev/null +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_g.c @@ -0,0 +1,63 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xv_hscaler.h" + +/* +* The configuration table for devices +*/ + +XV_hscaler_Config XV_hscaler_ConfigTable[] = +{ + { +#ifdef XPAR_XV_HSCALER_NUM_INSTANCES + XPAR_V_PROC_SS_0_V_HSCALER_DEVICE_ID, + XPAR_V_PROC_SS_0_V_HSCALER_S_AXI_CTRL_BASEADDR, + XPAR_V_PROC_SS_0_V_HSCALER_SAMPLES_PER_CLOCK, + XPAR_V_PROC_SS_0_V_HSCALER_NUM_VIDEO_COMPONENTS, + XPAR_V_PROC_SS_0_V_HSCALER_MAX_COLS, + XPAR_V_PROC_SS_0_V_HSCALER_MAX_ROWS, + XPAR_V_PROC_SS_0_V_HSCALER_MAX_DATA_WIDTH, + XPAR_V_PROC_SS_0_V_HSCALER_PHASE_SHIFT, + XPAR_V_PROC_SS_0_V_HSCALER_SCALE_MODE, + XPAR_V_PROC_SS_0_V_HSCALER_TAPS +#endif + } +}; diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c index a01c455f..5f6177ad 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c @@ -35,6 +35,7 @@ * @file xv_hscaler_l2.c * @addtogroup v_hscaler_v1_0 * @{ +* @details * * The Horizontal Scaler Layer-2 Driver. * The functions in this file provides an abstraction from the register peek/poke @@ -46,7 +47,7 @@ * * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- -* 1.00 rc 05/01/15 Initial Release +* 1.00 rco 07/21/15 Initial Release * * @@ -487,6 +488,9 @@ void XV_HScalerSetup(XV_hscaler *InstancePtr, */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(pHscL2Data != NULL); + Xil_AssertVoid((HeightIn>0) && (HeightIn<=InstancePtr->Config.MaxHeight)); + Xil_AssertVoid((WidthIn>0) && (WidthIn<=InstancePtr->Config.MaxWidth)); + Xil_AssertVoid((WidthOut>0) && (WidthOut<=InstancePtr->Config.MaxWidth)); PixelRate = (u32) ((float)((WidthIn * STEP_PRECISION) + (WidthOut/2))/(float)WidthOut); @@ -549,7 +553,7 @@ void XV_HScalerDbgReportStatus(XV_hscaler *InstancePtr) done = XV_hscaler_IsDone(pHsc); idle = XV_hscaler_IsIdle(pHsc); ready = XV_hscaler_IsReady(pHsc); - ctrl = XV_hscaler_ReadReg(pHsc->Ctrl_BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); + ctrl = XV_hscaler_ReadReg(pHsc->Config.BaseAddress, XV_HSCALER_CTRL_ADDR_AP_CTRL); heightin = XV_hscaler_Get_HwReg_Height(pHsc); widthin = XV_hscaler_Get_HwReg_WidthIn(pHsc); diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.h b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.h index 7442ef1f..99bbf83d 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.h +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.h @@ -35,6 +35,7 @@ * @file xv_hscaler_l2.h * @addtogroup v_hscaler_v1_0 * @{ +* @details * * This header file contains layer 2 API's of the horizontal scaler sub-core * driver.The functions contained herein provides a high level implementation of @@ -98,7 +99,7 @@ * * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- -* 1.00 rc 05/01/15 Initial Release +* 1.00 rco 07/21/15 Initial Release * * diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_linux.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_linux.c index 85b468d3..5aebccb9 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_linux.c +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_linux.c @@ -87,8 +87,8 @@ static int uio_info_read_map_size(XV_hscaler_uio_info* info, int n) { } int XV_hscaler_Initialize(XV_hscaler *InstancePtr, const char* InstanceName) { - XV_hscaler_uio_info *InfoPtr = &uio_info; - struct dirent **namelist; + XV_hscaler_uio_info *InfoPtr = &uio_info; + struct dirent **namelist; int i, n; char* s; char file[ MAX_UIO_PATH_SIZE ]; @@ -100,9 +100,9 @@ int XV_hscaler_Initialize(XV_hscaler *InstancePtr, const char* InstanceName) { n = scandir("/sys/class/uio", &namelist, 0, alphasort); if (n < 0) return XST_DEVICE_NOT_FOUND; for (i = 0; i < n; i++) { - strcpy(file, "/sys/class/uio/"); - strcat(file, namelist[i]->d_name); - strcat(file, "/name"); + strcpy(file, "/sys/class/uio/"); + strcat(file, namelist[i]->d_name); + strcat(file, "/name"); if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) { flag = 1; s = namelist[i]->d_name; @@ -126,8 +126,8 @@ int XV_hscaler_Initialize(XV_hscaler *InstancePtr, const char* InstanceName) { } // NOTE: slave interface 'Ctrl' should be mapped to uioX/map0 - InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); - assert(InstancePtr->Ctrl_BaseAddress); + InstancePtr->Config.BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); + assert(InstancePtr->Config.BaseAddress); InstancePtr->IsReady = XIL_COMPONENT_IS_READY; @@ -135,12 +135,12 @@ int XV_hscaler_Initialize(XV_hscaler *InstancePtr, const char* InstanceName) { } int XV_hscaler_Release(XV_hscaler *InstancePtr) { - XV_hscaler_uio_info *InfoPtr = &uio_info; + XV_hscaler_uio_info *InfoPtr = &uio_info; assert(InstancePtr != NULL); assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size); + munmap((void*)InstancePtr->Config.BaseAddress, InfoPtr->maps[0].size); close(InfoPtr->uio_fd); diff --git a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_sinit.c b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_sinit.c index 5cb3af01..2719a2c7 100644 --- a/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_sinit.c +++ b/XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_sinit.c @@ -11,35 +11,41 @@ #include "xparameters.h" #include "xv_hscaler.h" +#ifndef XPAR_XV_HSCALER_NUM_INSTANCES +#define XPAR_XV_HSCALER_NUM_INSTANCES 0 +#endif + extern XV_hscaler_Config XV_hscaler_ConfigTable[]; XV_hscaler_Config *XV_hscaler_LookupConfig(u16 DeviceId) { - XV_hscaler_Config *ConfigPtr = NULL; + XV_hscaler_Config *ConfigPtr = NULL; - int Index; + int Index; - for (Index = 0; Index < XPAR_XV_HSCALER_NUM_INSTANCES; Index++) { - if (XV_hscaler_ConfigTable[Index].DeviceId == DeviceId) { - ConfigPtr = &XV_hscaler_ConfigTable[Index]; - break; - } - } + for (Index = 0; Index < XPAR_XV_HSCALER_NUM_INSTANCES; Index++) { + if (XV_hscaler_ConfigTable[Index].DeviceId == DeviceId) { + ConfigPtr = &XV_hscaler_ConfigTable[Index]; + break; + } + } - return ConfigPtr; + return ConfigPtr; } int XV_hscaler_Initialize(XV_hscaler *InstancePtr, u16 DeviceId) { - XV_hscaler_Config *ConfigPtr; + XV_hscaler_Config *ConfigPtr; - Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr != NULL); - ConfigPtr = XV_hscaler_LookupConfig(DeviceId); - if (ConfigPtr == NULL) { - InstancePtr->IsReady = 0; - return (XST_DEVICE_NOT_FOUND); - } + ConfigPtr = XV_hscaler_LookupConfig(DeviceId); + if (ConfigPtr == NULL) { + InstancePtr->IsReady = 0; + return (XST_DEVICE_NOT_FOUND); + } - return XV_hscaler_CfgInitialize(InstancePtr, ConfigPtr); + return XV_hscaler_CfgInitialize(InstancePtr, + ConfigPtr, + ConfigPtr->BaseAddress); } #endif