diff --git a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c
index 8997285e..66fb9e30 100644
--- a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c
+++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c
@@ -45,6 +45,7 @@
 * 1.0   hk  08/21/14 First release
 *       sk  03/13/15 Added IO mode support.
 *       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
 *
 * </pre>
 *
@@ -245,14 +246,28 @@ void XQspiPsu_Reset(XQspiPsu *InstancePtr)
 void XQspiPsu_Abort(XQspiPsu *InstancePtr)
 {
 
-	u32 ConfigReg;
+	u32 IntrStatus, ConfigReg;
+
+	IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_ISR_OFFSET);
+
 	/* Clear and disable interrupts */
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_ISR_OFFSET,
+		XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
 		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
-		XQSPIPSU_ISR_OFFSET) | XQSPIPSU_ISR_WR_TO_CLR_MASK);
+				XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
+				XQSPIPSU_QSPIDMA_DST_STS_WTC);
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 		XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
 
 	/* Clear FIFO */
 	if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
diff --git a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h
index e785a402..3e0fd364 100644
--- a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h
+++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h
@@ -87,6 +87,7 @@
 * 1.0   hk  08/21/14 First release
 *       sk  03/13/15 Added IO mode support.
 *       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
 *
 * </pre>
 *
diff --git a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h
index 086ada50..9baf8d5f 100644
--- a/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h
+++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h
@@ -43,6 +43,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------.
 * 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
 *
 * </pre>
 *
@@ -540,6 +541,8 @@ extern "C" {
 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001
 
+#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000
+
 /**
  * Register: XQSPIPSU_QSPIDMA_DST_CTRL
  */
@@ -577,7 +580,7 @@ extern "C" {
 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001
 
-#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x403FFA00
+#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x803FFA00
 
 /**
  * Register: XQSPIPSU_QSPIDMA_DST_I_STS
@@ -613,6 +616,7 @@ extern "C" {
 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002
 
 #define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FC
+#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FE
 
 /**
  * Register: XQSPIPSU_QSPIDMA_DST_I_EN