diff --git a/ThirdParty/sw_services/xilopenamp/src/bm_env.c b/ThirdParty/sw_services/xilopenamp/src/bm_env.c index 1b6096eb..c2b9d892 100644 --- a/ThirdParty/sw_services/xilopenamp/src/bm_env.c +++ b/ThirdParty/sw_services/xilopenamp/src/bm_env.c @@ -47,10 +47,6 @@ #include #include -#include "xil_exception.h" -#include "xpseudo_asm.h" -#include "bm_env.h" -#include "xscugic.h" #if (defined(__CC_ARM)) #define MEM_BARRIER() __schedule_barrier() @@ -59,9 +55,20 @@ #else #define MEM_BARRIER() #endif + static void acquire_spin_lock(void *plock); static void release_spin_lock(void *plock); +extern void restore_global_interrupts(); +extern void disable_global_interrupts(); +extern void platform_interrupt_enable(unsigned int vector,unsigned int polarity, unsigned int priority); +extern void platform_interrupt_disable(unsigned int vector); +extern void platform_cache_all_flush_invalidate(); +extern void platform_cache_disable(); +extern void platform_map_mem_region(unsigned int va,unsigned int pa, unsigned int size,int is_mem_mapped,int cache_type); +extern unsigned long platform_vatopa(unsigned long addr); +extern void *platform_patova(unsigned long addr); + struct isr_info isr_table[ISR_COUNT]; int Intr_Count = 0; /* Flag to show status of global interrupts. 0 for disabled and 1 for enabled. This @@ -69,7 +76,6 @@ int Intr_Count = 0; */ int Intr_Enable_Flag = 1; -unsigned int old_value = 0; /** * env_init * @@ -429,7 +435,7 @@ void env_enable_interrupt(unsigned int vector , unsigned int priority , { isr_table[idx].priority = priority; isr_table[idx].type = polarity; - XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR,vector); + platform_interrupt_enable(vector, polarity, priority); break; } } @@ -447,7 +453,7 @@ void env_enable_interrupt(unsigned int vector , unsigned int priority , void env_disable_interrupt(unsigned int vector) { - XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR,vector); + platform_interrupt_disable(vector); } /** @@ -465,22 +471,6 @@ void env_map_memory(unsigned int pa, unsigned int va, unsigned int size, unsigned int flags) { int is_mem_mapped = 0; int cache_type = 0; - - if ((flags & (0x0f << 4 )) == MEM_MAPPED) - { - is_mem_mapped = 1; - } - - if ((flags & 0x0f) == WB_CACHE) { - cache_type = WRITEBACK; - } - else if((flags & 0x0f) == WT_CACHE) { - cache_type = WRITETHROUGH; - } - else { - cache_type = NOCACHE; - } - platform_map_mem_region(va, pa, size, is_mem_mapped, cache_type); } @@ -579,31 +569,3 @@ static void release_spin_lock(void *plock) xchg(plock, 1); } - -/* - * restore global interrupts - */ -void restore_global_interrupts() { - - ARM_AR_INT_BITS_SET(old_value); - -} - -/* - * disable global interrupts - */ -void disable_global_interrupts() { - - unsigned int value = 0; - - ARM_AR_INT_BITS_GET(&value); - - if (value != old_value) { - - ARM_AR_INT_BITS_SET(CORTEXR5_CPSR_INTERRUPTS_BITS); - - old_value = value; - - } - -} diff --git a/ThirdParty/sw_services/xilopenamp/src/bm_env.h b/ThirdParty/sw_services/xilopenamp/src/bm_env.h deleted file mode 100644 index 716f3655..00000000 --- a/ThirdParty/sw_services/xilopenamp/src/bm_env.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2014, Mentor Graphics Corporation - * All rights reserved. - * - * Copyright (C) 2015 Xilinx, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _BM_ENV_H -#define _BM_ENV_H - -#include "xil_cache.h" -#include "xreg_cortexr5.h" -#include "xpseudo_asm_gcc.h" -#include "xparameters.h" - -/* IPI REGs OFFSET */ -#define IPI_TRIG_OFFSET 0x00000000 /* IPI trigger register offset */ -#define IPI_OBS_OFFSET 0x00000004 /* IPI observation register offset */ -#define IPI_ISR_OFFSET 0x00000010 /* IPI interrupt status register offset */ -#define IPI_IMR_OFFSET 0x00000014 /* IPI interrupt mask register offset */ -#define IPI_IER_OFFSET 0x00000018 /* IPI interrupt enable register offset */ -#define IPI_IDR_OFFSET 0x0000001C /* IPI interrupt disable register offset */ - -#ifndef BAREMETAL_MASTER -#define BAREMETAL_MASTER 0 -#endif - -/* The vector table address is the same as image entry point */ -#define RAM_VECTOR_TABLE_ADDR ELF_START - -typedef enum { - TRIG_NOT_SUPPORTED, - TRIG_RISING_EDGE, - TRIG_FALLING_EDGE, - TRIG_LEVEL_LOW, - TRIG_LEVEL_HIGH, - TRIG_RISING_FALLING_EDGES, - TRIG_HIGH_LOW_RISING_FALLING_EDGES -} INT_TRIG_TYPE; - -typedef enum { - NOCACHE, - WRITEBACK, - WRITETHROUGH -} CACHE_TYPE; - -#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE) - -/* This macro writes the current program status register (CPSR - all fields) */ -#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \ - { \ - asm volatile(" MSR CPSR_cxsf, %0" \ - : /* No outputs */ \ - : "r" (cpsr_cxsf_value) ); \ - } - -/* This macro sets the interrupt related bits in the status register / control - register to the specified value. */ -#define ARM_AR_INT_BITS_SET(set_bits) \ - { \ - int tmp_val; \ - tmp_val = mfcpsr(); \ - tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \ - tmp_val |= set_bits; \ - ARM_AR_CPSR_CXSF_WRITE(tmp_val); \ - } - -/* This macro gets the interrupt related bits from the status register / control - register. */ -#define ARM_AR_INT_BITS_GET(get_bits_ptr) \ - { \ - int tmp_val; \ - tmp_val = mfcpsr(); \ - tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \ - *get_bits_ptr = tmp_val; \ - } - -#define SWITCH_TO_SYS_MODE() \ - { \ - mtcpsr((mfcpsr() | XREG_CPSR_SYSTEM_MODE) & ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS));\ - } - -void restore_global_interrupts(); -void disable_global_interrupts(); - -/* define function macros for OpenAMP API */ -#define platform_cache_all_flush_invalidate() \ - { \ - Xil_DCacheFlush(); \ - Xil_DCacheInvalidate(); \ - Xil_ICacheInvalidate(); \ - } - -#define platform_cache_disable() \ - { \ - Xil_DCacheDisable(); \ - Xil_ICacheDisable(); \ - } - -#define platform_dcache_all_flush() { Xil_DCacheFlush(); } - -#define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); } - -#define platform_map_mem_region(...) - -#define platform_vatopa(addr) ((unsigned long)addr) -#define platform_patova(addr) ((void *)addr) - -#endif /* _BAREMETAL_H */