From b9158b38d7b4bb8c9b5eba9bdcd24b45981a1dcf Mon Sep 17 00:00:00 2001 From: P L Sai Krishna Date: Mon, 1 Jun 2015 14:24:22 +0800 Subject: [PATCH] qspipsu: Renamed v1.1 as v1.0 This patch renames v1.1 as v1.0 and removed all 1.1 instances inside driver. Signed-off-by: P L Sai Krishna --- .../data/qspipsu.mdd | 2 +- .../data/qspipsu.tcl | 2 +- ...xqspipsu_generic_flash_interrupt_example.c | 0 .../xqspipsu_generic_flash_polled_example.c | 0 .../{qspipsu_v1_1 => qspipsu}/src/Makefile | 0 .../{qspipsu_v1_1 => qspipsu}/src/xqspipsu.c | 2 +- .../{qspipsu_v1_1 => qspipsu}/src/xqspipsu.h | 2 +- .../src/xqspipsu_g.c | 2 +- .../src/xqspipsu_hw.h | 2 +- .../src/xqspipsu_options.c | 2 +- .../src/xqspipsu_sinit.c | 0 .../qspipsu_v1_1/doc/html/api/annotated.html | 30 - .../qspipsu_v1_1/doc/html/api/doxygen.png | Bin 1281 -> 0 bytes .../doc/html/api/driver_api_doxygen.css | 334 - .../qspipsu_v1_1/doc/html/api/files.html | 32 - .../qspipsu_v1_1/doc/html/api/functions.html | 63 - .../doc/html/api/functions_vars.html | 63 - .../qspipsu_v1_1/doc/html/api/globals.html | 47 - .../doc/html/api/globals_0x78.html | 543 -- .../doc/html/api/globals_defs.html | 47 - .../doc/html/api/globals_defs_0x78.html | 527 -- .../doc/html/api/globals_func.html | 51 - .../doc/html/api/globals_type.html | 38 - .../doc/html/api/globals_vars.html | 38 - .../qspipsu_v1_1/doc/html/api/index.html | 21 - .../html/api/struct_options_map-members.html | 27 - .../doc/html/api/struct_options_map.html | 65 - .../html/api/struct_x_qspi_psu-members.html | 43 - .../doc/html/api/struct_x_qspi_psu.html | 342 - .../struct_x_qspi_psu___config-members.html | 30 - .../html/api/struct_x_qspi_psu___config.html | 121 - .../api/struct_x_qspi_psu___msg-members.html | 30 - .../doc/html/api/struct_x_qspi_psu___msg.html | 121 - .../qspipsu_v1_1/doc/html/api/tab_b.gif | Bin 35 -> 0 bytes .../qspipsu_v1_1/doc/html/api/tab_l.gif | Bin 706 -> 0 bytes .../qspipsu_v1_1/doc/html/api/tab_r.gif | Bin 2585 -> 0 bytes .../qspipsu_v1_1/doc/html/api/tabs.css | 102 - .../doc/html/api/xqspipsu_8c.html | 337 - .../doc/html/api/xqspipsu_8h.html | 1289 --- .../doc/html/api/xqspipsu__g_8c.html | 65 - .../doc/html/api/xqspipsu__hw_8h.html | 7679 ----------------- .../doc/html/api/xqspipsu__options_8c.html | 310 - .../doc/html/api/xqspipsu__sinit_8c.html | 91 - 43 files changed, 7 insertions(+), 12493 deletions(-) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/data/qspipsu.mdd (98%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/data/qspipsu.tcl (98%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/examples/xqspipsu_generic_flash_interrupt_example.c (100%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/examples/xqspipsu_generic_flash_polled_example.c (100%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/Makefile (100%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu.c (99%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu.h (99%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu_g.c (97%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu_hw.h (99%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu_options.c (99%) rename XilinxProcessorIPLib/drivers/{qspipsu_v1_1 => qspipsu}/src/xqspipsu_sinit.c (100%) delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/annotated.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/doxygen.png delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/driver_api_doxygen.css delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/files.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/functions.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/functions_vars.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_0x78.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs_0x78.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_func.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_type.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_vars.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/index.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map-members.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu-members.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config-members.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg-members.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/tab_b.gif delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/tab_l.gif delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/tab_r.gif delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/tabs.css delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu_8c.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu_8h.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__g_8c.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__hw_8h.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__options_8c.html delete mode 100755 XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__sinit_8c.html diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.mdd b/XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.mdd similarity index 98% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.mdd rename to XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.mdd index 50d8046b..f2a67478 100755 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.mdd +++ b/XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.mdd @@ -36,7 +36,7 @@ BEGIN driver qspipsu OPTION supported_peripherals = (psu_qspi); OPTION driver_state = ACTIVE; OPTION copyfiles = all; - OPTION VERSION = 1.1; + OPTION VERSION = 1.0; OPTION NAME = qspipsu; END driver diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.tcl b/XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.tcl similarity index 98% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.tcl rename to XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.tcl index dbf1ddb2..6da286b1 100755 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.tcl +++ b/XilinxProcessorIPLib/drivers/qspipsu/data/qspipsu.tcl @@ -36,7 +36,7 @@ # Ver Who Date Changes # ----- ---- -------- ----------------------------------------------- # 1.0 hk 08/21/14 First release -# 1.1 sk 05/06/15 Imported Bus Width Parameter. +# sk 05/06/15 Imported Bus Width Parameter. # ############################################################################## diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_interrupt_example.c b/XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_interrupt_example.c similarity index 100% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_interrupt_example.c rename to XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_interrupt_example.c diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_polled_example.c b/XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_polled_example.c similarity index 100% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_polled_example.c rename to XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_polled_example.c diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/Makefile b/XilinxProcessorIPLib/drivers/qspipsu/src/Makefile similarity index 100% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/Makefile rename to XilinxProcessorIPLib/drivers/qspipsu/src/Makefile diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.c b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c similarity index 99% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.c rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c index 27613ea2..2014ff87 100644 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.c +++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.c @@ -47,7 +47,7 @@ * hk 03/18/15 Switch to I/O mode before clearing RX FIFO. * Clear and disbale DMA interrupts/status in abort. * Use DMA DONE bit instead of BUSY as recommended. -* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012. +* sk 04/24/15 Modified the code according to MISRAC-2012. * * * diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.h b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h similarity index 99% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.h rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h index 627b0167..53d67c62 100644 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.h +++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu.h @@ -89,7 +89,7 @@ * hk 03/18/15 Switch to I/O mode before clearing RX FIFO. * Clear and disbale DMA interrupts/status in abort. * Use DMA DONE bit instead of BUSY as recommended. -* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012. +* sk 04/24/15 Modified the code according to MISRAC-2012. * * * diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_g.c b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_g.c similarity index 97% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_g.c rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_g.c index 3c7e93b6..e58796c1 100644 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_g.c +++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_g.c @@ -43,7 +43,7 @@ * Ver Who Date Changes * ----- --- -------- ----------------------------------------------- * 1.0 hk 08/21/14 First release -* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012. +* sk 04/24/15 Modified the code according to MISRAC-2012. * * ******************************************************************************/ diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_hw.h b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h similarity index 99% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_hw.h rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h index 707273ac..427ef51a 100644 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_hw.h +++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.h @@ -44,7 +44,7 @@ * ----- --- -------- -----------------------------------------------. * 1.0 hk 08/21/14 First release * hk 03/18/15 Add DMA status register masks required. -* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012. +* sk 04/24/15 Modified the code according to MISRAC-2012. * * * diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_options.c b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_options.c similarity index 99% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_options.c rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_options.c index c82ecb92..62a3d205 100644 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_options.c +++ b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_options.c @@ -44,7 +44,7 @@ * ----- --- -------- ----------------------------------------------- * 1.0 hk 08/21/14 First release * sk 03/13/15 Added IO mode support. -* 1.1 sk 04/24/15 Modified the code according to MISRAC-2012. +* sk 04/24/15 Modified the code according to MISRAC-2012. * * * diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_sinit.c b/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_sinit.c similarity index 100% rename from XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_sinit.c rename to XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_sinit.c diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/annotated.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/annotated.html deleted file mode 100755 index e1cb4407..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/annotated.html +++ /dev/null @@ -1,30 +0,0 @@ - - - - - Class List - - - -

Xilinx Processor IP Library

-Software Drivers -
- -
-
-
-
-

Class List

Here are the classes, structs, unions and interfaces with brief descriptions: - - - - -
OptionsMap
XQspiPsu
XQspiPsu_Config
XQspiPsu_Msg
-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/doxygen.png b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/doxygen.png deleted file mode 100755 index f0a274bbaffdd67f6d784c894d9cf28729db0e14..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1281 zcmaJ>ZA?>F7(Vx-ms?uoS`b@hdRtpo6o^%HU>M$hfGrBvQnk$LE?p^P!kn&ikhyq! zX~V@&tPF5Qt@V?oTL96Bi%aRiwbe1)9DWQI#?)=HxS7QSw`J`5fAJ*eJbB;uNuKA& zdERDo*{Y<(If(#(B$Lr#;nB(8Y#ia=ZCeW?JfPLuQY`=@cW$k}Rivq|vbxGrRq1Tl9;+(gNt?}UtVKM2`T5t1jLzuL@0UIs`S#vlhl4)^ zLgSYrPj@$+`|j?eSbXTmiHGkWxV8V}BzNR?pl9k_s4pDu9vd5a_UzZEPk)}Ad{AV_ zzddrjrh4=Imr`E06;LY{)YYt?o}L~H@7C}F^WB!Ra=v`Q0bj{>5&$66CWF>mf6vjP z2N>RRY6ZYa=K`76>+|_)Xdwko+7wv}7cN|btOhWb(*{sta~6b?S8Omrxw}!4`NhGr zZVpNqpu1@BE`QGWNTpEpcJVW5izu~2B^GlM?1(OPg)zwW;QcP@Ltcclm>XbJL9C|j z=9!2?ua=uIlf0%AndzHsRC}IyTL$EhAee(fdKB`?27KeS^2M8M_7b~PiCFO&r5LC7 z7gl1*a<8;SjNaw#h=843_AV9iZbWQOAp5YOC^&_F*9K0> zB|6%IDb?aM#3viTxkLU4aXg&@+CkNTOnQ1iMP*^?b|^lJy$4C)Zk4isV!|RZ*XhXh zw8q3$=*0LeGC!XI_Wc?dkT~3+*Gu%%yIqP+Wr3H$=&ROMQU6q}Ag^P~>c5vAEO;a- z_dK-3PPeKar%)6$j~vI2#*-YH!1h6HYVtwCX5_wM`iF#UKz&&@9Oo5w3%XGYrX zW>dY~)SG-((Yim%`InwgTvyRC?e=Wh^8KCao!R6Eg&TpVWUY1sN~4G}V?nFnEGo-; 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Xilinx Processor IP Library

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File List

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xqspipsu.c
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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/functions.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/functions.html deleted file mode 100755 index a2c4e861..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/functions.html +++ /dev/null @@ -1,63 +0,0 @@ - - - - - Class Members - - - -

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Xilinx Processor IP Library

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_0x78.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_0x78.html deleted file mode 100755 index 123b9bed..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_0x78.html +++ /dev/null @@ -1,543 +0,0 @@ - - - - - Class Members - - - -

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs.html deleted file mode 100755 index 0a306378..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs.html +++ /dev/null @@ -1,47 +0,0 @@ - - - - - Class Members - - - -

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs_0x78.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs_0x78.html deleted file mode 100755 index ea05cd41..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_defs_0x78.html +++ /dev/null @@ -1,527 +0,0 @@ - - - - - Class Members - - - -

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_func.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_func.html deleted file mode 100755 index 7c32f15a..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/globals_func.html +++ /dev/null @@ -1,51 +0,0 @@ - - - - - Class Members - - - -

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map-members.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map-members.html deleted file mode 100755 index c6bd1491..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map-members.html +++ /dev/null @@ -1,27 +0,0 @@ - - - - - Member List - - - -

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OptionsMap Member List

This is the complete list of members for OptionsMap, including all inherited members.

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MaskOptionsMap
OptionOptionsMap
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map.html deleted file mode 100755 index 3bf4cb29..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_options_map.html +++ /dev/null @@ -1,65 +0,0 @@ - - - - - OptionsMap Struct Reference - - - -

Xilinx Processor IP Library

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OptionsMap Struct Reference

List of all members. - - - - - - -

Public Attributes

u32 Option
u32 Mask
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Member Data Documentation

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u32 OptionsMap::Mask
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u32 OptionsMap::Option
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The documentation for this struct was generated from the following file: -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu-members.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu-members.html deleted file mode 100755 index db3f025a..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu-members.html +++ /dev/null @@ -1,43 +0,0 @@ - - - - - Member List - - - -

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XQspiPsu Member List

This is the complete list of members for XQspiPsu, including all inherited members.

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ConfigXQspiPsu
GenFifoBufferPtrXQspiPsu
GenFifoBusXQspiPsu
GenFifoCSXQspiPsu
GenFifoEntriesXQspiPsu
IsBusyXQspiPsu
IsReadyXQspiPsu
IsUnalignedXQspiPsu
MsgXQspiPsu
MsgCntXQspiPsu
NumMsgXQspiPsu
ReadModeXQspiPsu
RecvBufferPtrXQspiPsu
RxBytesXQspiPsu
SendBufferPtrXQspiPsu
StatusHandlerXQspiPsu
StatusRefXQspiPsu
TxBytesXQspiPsu
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu.html deleted file mode 100755 index dca99ac3..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu.html +++ /dev/null @@ -1,342 +0,0 @@ - - - - - XQspiPsu Struct Reference - - - -

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XQspiPsu Struct Reference

#include <xqspipsu.h> -

-List of all members.

Detailed Description

-The XQspiPsu driver instance data. The user is required to allocate a variable of this type for every QSPIPSU device in the system. A pointer to a variable of this type is then passed to the driver API functions. -

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Public Attributes

XQspiPsu_Config Config
u32 IsReady
u8 * SendBufferPtr
u8 * RecvBufferPtr
u8 * GenFifoBufferPtr
int TxBytes
int RxBytes
int GenFifoEntries
u32 IsBusy
u32 ReadMode
u32 GenFifoCS
u32 GenFifoBus
int NumMsg
int MsgCnt
int IsUnaligned
XQspiPsu_Msg * Msg
XQspiPsu_StatusHandler StatusHandler
void * StatusRef
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Member Data Documentation

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XQspiPsu_Config XQspiPsu::Config
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-Configuration structure -

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u8* XQspiPsu::GenFifoBufferPtr
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-Gen FIFO entries -

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u32 XQspiPsu::GenFifoBus
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int XQspiPsu::GenFifoEntries
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-Number of Gen FIFO entries remaining -

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u32 XQspiPsu::IsBusy
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-A transfer is in progress (state) -

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u32 XQspiPsu::IsReady
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-Device is initialized and ready -

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int XQspiPsu::IsUnaligned
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XQspiPsu_Msg* XQspiPsu::Msg
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int XQspiPsu::MsgCnt
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int XQspiPsu::NumMsg
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u32 XQspiPsu::ReadMode
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-DMA or IO mode -

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u8* XQspiPsu::RecvBufferPtr
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-Buffer to receive (state) -

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int XQspiPsu::RxBytes
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-Number of bytes left to transfer(state) -

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u8* XQspiPsu::SendBufferPtr
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-Buffer to send (state) -

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XQspiPsu_StatusHandler XQspiPsu::StatusHandler
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void* XQspiPsu::StatusRef
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-Callback reference for status handler -

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int XQspiPsu::TxBytes
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-Number of bytes to transfer (state) -

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The documentation for this struct was generated from the following file: -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config-members.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config-members.html deleted file mode 100755 index cf5c6b01..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config-members.html +++ /dev/null @@ -1,30 +0,0 @@ - - - - - Member List - - - -

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XQspiPsu_Config Member List

This is the complete list of members for XQspiPsu_Config, including all inherited members.

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BaseAddressXQspiPsu_Config
BusWidthXQspiPsu_Config
ConnectionModeXQspiPsu_Config
DeviceIdXQspiPsu_Config
InputClockHzXQspiPsu_Config
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config.html deleted file mode 100755 index 9dbe0163..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___config.html +++ /dev/null @@ -1,121 +0,0 @@ - - - - - XQspiPsu_Config Struct Reference - - - -

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XQspiPsu_Config Struct Reference

#include <xqspipsu.h> -

-List of all members.

Detailed Description

-This typedef contains configuration information for the device. -

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Public Attributes

u16 DeviceId
u32 BaseAddress
u32 InputClockHz
u8 ConnectionMode
u8 BusWidth
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Member Data Documentation

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u32 XQspiPsu_Config::BaseAddress
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-Base address of the device -

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u8 XQspiPsu_Config::BusWidth
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-Bus width available on board -

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u8 XQspiPsu_Config::ConnectionMode
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-Single, Stacked and Parallel mode -

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u16 XQspiPsu_Config::DeviceId
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-Unique ID of device -

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u32 XQspiPsu_Config::InputClockHz
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-Input clock frequency -

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The documentation for this struct was generated from the following file: -Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg-members.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg-members.html deleted file mode 100755 index 3669ed74..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg-members.html +++ /dev/null @@ -1,30 +0,0 @@ - - - - - Member List - - - -

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XQspiPsu_Msg Member List

This is the complete list of members for XQspiPsu_Msg, including all inherited members.

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BusWidthXQspiPsu_Msg
ByteCountXQspiPsu_Msg
FlagsXQspiPsu_Msg
RxBfrPtrXQspiPsu_Msg
TxBfrPtrXQspiPsu_Msg
Copyright @ 1995-2014 Xilinx, Inc. All rights reserved. diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg.html deleted file mode 100755 index 49276925..00000000 --- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/struct_x_qspi_psu___msg.html +++ /dev/null @@ -1,121 +0,0 @@ - - - - - XQspiPsu_Msg Struct Reference - - - -

Xilinx Processor IP Library

-Software Drivers -
- -
-
-
-
-

XQspiPsu_Msg Struct Reference

#include <xqspipsu.h> -

-List of all members.

Detailed Description

-This typedef contains configuration information for a flash message. -

- - - - - - - - - - - - - -

Public Attributes

u8 * TxBfrPtr
u8 * RxBfrPtr
u32 ByteCount
u32 BusWidth
u32 Flags
-

Member Data Documentation

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u32 XQspiPsu_Msg::BusWidth
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u32 XQspiPsu_Msg::ByteCount
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u32 XQspiPsu_Msg::Flags
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u8* XQspiPsu_Msg::RxBfrPtr
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u8* XQspiPsu_Msg::TxBfrPtr
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The documentation for this struct was generated from the following file: -Copyright @ 1995-2014 Xilinx, Inc. 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Xilinx Processor IP Library

-Software Drivers -
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xqspipsu.c File Reference

Detailed Description

-This file implements the functions required to use the QSPIPSU hardware to perform a transfer. These are accessible to the user via xqspipsu.h.

-

- MODIFICATION HISTORY:

-

 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------
- 1.0   hk  08/21/14 First release
-       sk  03/13/15 Added IO mode support.

-
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-#include "xqspipsu.h"
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Functions

int XQspiPsu_CfgInitialize (XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, u32 EffectiveAddr)
void XQspiPsu_Reset (XQspiPsu *InstancePtr)
void XQspiPsu_Abort (XQspiPsu *InstancePtr)
int XQspiPsu_PolledTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, unsigned NumMsg)
int XQspiPsu_InterruptTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, unsigned NumMsg)
int XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)
void XQspiPsu_SetStatusHandler (XQspiPsu *InstancePtr, void *CallBackRef, XQspiPsu_StatusHandler FuncPtr)
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Function Documentation

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void XQspiPsu_Abort (XQspiPsu *  InstancePtr  ) 
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-Aborts a transfer in progress by

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InstancePtr is a pointer to the XQspiPsu instance.
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None.
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int XQspiPsu_CfgInitialize (XQspiPsu *  InstancePtr,
XQspiPsu_Config *  ConfigPtr,
u32  EffectiveAddr 
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-Initializes a specific XQspiPsu instance such that the driver is ready to use.

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Parameters:
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InstancePtr is a pointer to the XQspiPsu instance.
ConfigPtr is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddr is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.
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  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.
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int XQspiPsu_InterruptHandler (XQspiPsu *  InstancePtr  ) 
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-Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

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InstancePtr is a pointer to the XQspiPsu instance.
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  • XST_FAILURE if transfer fails.
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int XQspiPsu_InterruptTransfer (XQspiPsu *  InstancePtr,
XQspiPsu_Msg *  Msg,
unsigned  NumMsg 
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-This function initiates a transfer on the bus and enables interrupts. The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.

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InstancePtr is a pointer to the XQspiPsu instance.
Msg is a pointer to the structure containing transfer data.
NumMsg is the number of messages to be transferred.
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  • XST_FAILURE if transfer fails.
  • XST_DEVICE_BUSY if a transfer is already in progress.
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int XQspiPsu_PolledTransfer (XQspiPsu *  InstancePtr,
XQspiPsu_Msg *  Msg,
unsigned  NumMsg 
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-This function performs a transfer on the bus in polled mode. The messages passed are all transferred on the bus between one CS assert and de-assert.

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InstancePtr is a pointer to the XQspiPsu instance.
Msg is a pointer to the structure containing transfer data.
NumMsg is the number of messages to be transferred.
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  • XST_FAILURE if transfer fails.
  • XST_DEVICE_BUSY if a transfer is already in progress.
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void XQspiPsu_Reset (XQspiPsu *  InstancePtr  ) 
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-Resets the QSPIPSU device. Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

-The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.

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InstancePtr is a pointer to the XQspiPsu instance.
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None.
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None.
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void XQspiPsu_SetStatusHandler (XQspiPsu *  InstancePtr,
void *  CallBackRef,
XQspiPsu_StatusHandler  FuncPtr 
)
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-Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

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 XST_SPI_TRANSFER_DONE		The requested data transfer is done

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 XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
-				but there were none available in the transmit
-				register/FIFO. This typically means the slave
-				application did not issue a transfer request
-				fast enough, or the processor/driver could not
-				fill the transmit register/FIFO fast enough.

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 XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
-				but the receive data register/FIFO was full.

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Parameters:

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InstancePtr is a pointer to the XQspiPsu instance. 
CallBackRef is the upper layer callback reference passed back when the callback function is invoked. 
FuncPtr is the pointer to the callback function.

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Returns:
None.

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Note:

-The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.
-

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu_8h.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu_8h.html
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Xilinx Processor IP Library

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xqspipsu.h File Reference
Detailed Description

-This is the header file for the implementation of QSPIPSU driver. Generic QSPI interface allows for communication to any QSPI slave device. GQSPI contains a GENFIFO into which the bus transfers required are to be pushed with appropriate configuration. The controller provides TX and RX FIFO's and a DMA to be used for RX transfers. The controller executes each GENFIFO entry noting the configuration and places data on the bus as required

-The different options in GENFIFO are as follows: IMM_DATA : Can be one byte of data to be transmitted, number of clocks or number of bytes in transfer. DATA_XFER : Indicates that data/clocks need to be transmitted or received. EXPONENT : e when 2^e bytes are involved in transfer. SPI_MODE : SPI/Dual SPI/Quad SPI CS : Lower or Upper CS or Both Bus : Lower or Upper Bus or Both TX : When selected, controller transmits data in IMM or fetches number of bytes mentioned form TX FIFO. If not selected, dummies are pumped. RX : When selected, controller receives and fills the RX FIFO/allows RX DMA of requested number of bytes. If not selected, RX data is discarded. Stripe : Byte stripe over lower and upper bus or not. Poll : Polls response to match for to a set value (used along with POLL_CFG registers) and then proceeds to next GENFIFO entry. This feature is not currently used in the driver.

-GENFIFO has manual and auto start options. All DMA requests need a 4-byte aligned destination address buffer and size of transfer should also be a multiple of 4. This driver supports DMA RX and IO RX.

-Initialization: This driver uses the GQSPI controller with RX DMA. It supports both interrupt and polled transfers. Manual start of GENFIFO is used. XQspiPsu_CfgInitialize() initializes the instance variables. Additional setting can be done using SetOptions/ClearOptions functions and SelectSlave function.

-Transfer: Polled or Interrupt transfers can be done. The transfer function needs the message(s) to be transmitted in the form of an array of type XQspiPsu_Msg. This is supposed to contain the byte count and any TX/RX buffers as required. Flags can be used indicate further information such as whether the message should be striped. The transfer functions form and write GENFIFO entries, check the status of the transfer and report back to the application when done.

-
- MODIFICATION HISTORY:

-
 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------.
- 1.0   hk  08/21/14 First release
-       sk  03/13/15 Added IO mode support.

-
 

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-#include "xstatus.h"

-#include "xqspipsu_hw.h"

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Classes
struct  XQspiPsu_Msg
struct  XQspiPsu_Config
struct  XQspiPsu

Defines
#define _XQSPIPSU_H_
#define XQSPIPSU_READMODE_DMA   0x0
#define XQSPIPSU_READMODE_IO   0x1
#define XQSPIPSU_SELECT_FLASH_CS_LOWER   0x1
#define XQSPIPSU_SELECT_FLASH_CS_UPPER   0x2
#define XQSPIPSU_SELECT_FLASH_CS_BOTH   0x3
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER   0x1
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER   0x2
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH   0x3
#define XQSPIPSU_SELECT_MODE_SPI   0x1
#define XQSPIPSU_SELECT_MODE_DUALSPI   0x2
#define XQSPIPSU_SELECT_MODE_QUADSPI   0x4
#define XQSPIPSU_GENFIFO_CS_SETUP   0x04
#define XQSPIPSU_GENFIFO_CS_HOLD   0x03
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION   0x2
#define XQSPIPSU_CLK_PHASE_1_OPTION   0x4
#define XQSPIPSU_MANUAL_START_OPTION   0x8
#define XQSPIPSU_GENFIFO_EXP_START   0x100
#define XQSPIPSU_DMA_BYTES_MAX   0x10000000
#define XQSPIPSU_CLK_PRESCALE_2   0x00
#define XQSPIPSU_CLK_PRESCALE_4   0x01
#define XQSPIPSU_CLK_PRESCALE_8   0x02
#define XQSPIPSU_CLK_PRESCALE_16   0x03
#define XQSPIPSU_CLK_PRESCALE_32   0x04
#define XQSPIPSU_CLK_PRESCALE_64   0x05
#define XQSPIPSU_CLK_PRESCALE_128   0x06
#define XQSPIPSU_CLK_PRESCALE_256   0x07
#define XQSPIPSU_CR_PRESC_MAXIMUM   7
#define XQSPIPSU_CONNECTION_MODE_SINGLE   0
#define XQSPIPSU_CONNECTION_MODE_STACKED   1
#define XQSPIPSU_CONNECTION_MODE_PARALLEL   2
#define XQSPIPSU_MSG_FLAG_STRIPE   0x1
#define XQspiPsu_Select(InstancePtr)   XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
#define XQspiPsu_Enable(InstancePtr)   XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
#define XQspiPsu_Disable(InstancePtr)   XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)
#define XQspiPsu_IsManualStart(InstancePtr)   ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)

Typedefs
typedef void(*) XQspiPsu_StatusHandler (void *CallBackRef, u32 StatusEvent, unsigned ByteCount)

Functions
XQspiPsu_Config * XQspiPsu_LookupConfig (u16 DeviceId)
int XQspiPsu_CfgInitialize (XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, u32 EffectiveAddr)
void XQspiPsu_Reset (XQspiPsu *InstancePtr)
void XQspiPsu_Abort (XQspiPsu *InstancePtr)
int XQspiPsu_PolledTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, unsigned NumMsg)
int XQspiPsu_InterruptTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, unsigned NumMsg)
int XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)
void XQspiPsu_SetStatusHandler (XQspiPsu *InstancePtr, void *CallBackRef, XQspiPsu_StatusHandler FuncPtr)
int XQspiPsu_SetClkPrescaler (XQspiPsu *InstancePtr, u8 Prescaler)
void XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
int XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)
int XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)
u32 XQspiPsu_GetOptions (XQspiPsu *InstancePtr)
int XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)

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Define Documentation

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#define _XQSPIPSU_H_          

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#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION   0x2          

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#define XQSPIPSU_CLK_PHASE_1_OPTION   0x4          

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#define XQSPIPSU_CLK_PRESCALE_128   0x06          

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#define XQSPIPSU_CLK_PRESCALE_16   0x03          

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#define XQSPIPSU_CLK_PRESCALE_2   0x00          

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#define XQSPIPSU_CLK_PRESCALE_256   0x07          

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#define XQSPIPSU_CLK_PRESCALE_32   0x04          

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#define XQSPIPSU_CLK_PRESCALE_4   0x01          

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#define XQSPIPSU_CLK_PRESCALE_64   0x05          

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#define XQSPIPSU_CLK_PRESCALE_8   0x02          

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#define XQSPIPSU_CONNECTION_MODE_PARALLEL   2          

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#define XQSPIPSU_CONNECTION_MODE_SINGLE   0          

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#define XQSPIPSU_CONNECTION_MODE_STACKED   1          

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#define XQSPIPSU_CR_PRESC_MAXIMUM   7          

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#define XQspiPsu_Disable          (InstancePtr            )    XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)

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#define XQSPIPSU_DMA_BYTES_MAX   0x10000000          

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#define XQspiPsu_Enable          (InstancePtr            )    XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)

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#define XQSPIPSU_GENFIFO_CS_HOLD   0x03          

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#define XQSPIPSU_GENFIFO_CS_SETUP   0x04          

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#define XQSPIPSU_GENFIFO_EXP_START   0x100          

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#define XQspiPsu_IsManualStart          (InstancePtr            )    ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)

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#define XQSPIPSU_MANUAL_START_OPTION   0x8          

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#define XQSPIPSU_MSG_FLAG_STRIPE   0x1          

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#define XQSPIPSU_READMODE_DMA   0x0          

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#define XQSPIPSU_READMODE_IO   0x1          

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#define XQspiPsu_Select          (InstancePtr            )    XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)

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#define XQSPIPSU_SELECT_FLASH_BUS_BOTH   0x3          

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#define XQSPIPSU_SELECT_FLASH_BUS_LOWER   0x1          

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#define XQSPIPSU_SELECT_FLASH_BUS_UPPER   0x2          

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#define XQSPIPSU_SELECT_FLASH_CS_BOTH   0x3          

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#define XQSPIPSU_SELECT_FLASH_CS_LOWER   0x1          

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#define XQSPIPSU_SELECT_FLASH_CS_UPPER   0x2          

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#define XQSPIPSU_SELECT_MODE_DUALSPI   0x2          

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#define XQSPIPSU_SELECT_MODE_QUADSPI   0x4          

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#define XQSPIPSU_SELECT_MODE_SPI   0x1          

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Typedef Documentation

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typedef void(*) XQspiPsu_StatusHandler(void *CallBackRef, u32 StatusEvent, unsigned ByteCount)          

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-The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

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Parameters:

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CallBackRef is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer. 
StatusEvent holds one or more status events that have occurred. See the XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback. 
ByteCount indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error. 

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Function Documentation

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void XQspiPsu_Abort           (XQspiPsu *  InstancePtr           ) 

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-Aborts a transfer in progress by

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InstancePtr is a pointer to the XQspiPsu instance.

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None.

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Note:

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int XQspiPsu_CfgInitialize           (XQspiPsu *  InstancePtr, 
XQspiPsu_Config *  ConfigPtr, 
u32  EffectiveAddr 
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-Initializes a specific XQspiPsu instance such that the driver is ready to use.

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InstancePtr is a pointer to the XQspiPsu instance. 
ConfigPtr is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config. 
EffectiveAddr is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.

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  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

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Note:
None. 

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int XQspiPsu_ClearOptions           (XQspiPsu *  InstancePtr, 
u32  Options 
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-This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

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InstancePtr is a pointer to the XQspiPsu instance. 
Options contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

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u32 XQspiPsu_GetOptions           (XQspiPsu *  InstancePtr           ) 

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-This function gets the options for the QSPIPSU device. The options control how the device behaves relative to the QSPIPSU bus.

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InstancePtr is a pointer to the XQspiPsu instance.

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Note:
None. 

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int XQspiPsu_InterruptHandler           (XQspiPsu *  InstancePtr           ) 

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-Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

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InstancePtr is a pointer to the XQspiPsu instance.

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int XQspiPsu_InterruptTransfer           (XQspiPsu *  InstancePtr, 
XQspiPsu_Msg *  Msg, 
unsigned  NumMsg 
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InstancePtr is a pointer to the XQspiPsu instance. 
Msg is a pointer to the structure containing transfer data. 
NumMsg is the number of messages to be transferred.

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  • XST_DEVICE_BUSY if a transfer is already in progress.

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None. 

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XQspiPsu_Config* XQspiPsu_LookupConfig           (u16  DeviceId           ) 

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-Looks up the device configuration based on the unique device ID. A table contains the configuration info for each device in the system.

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DeviceId contains the ID of the device to look up the configuration for.

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-A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.

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Note:
None. 

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int XQspiPsu_PolledTransfer           (XQspiPsu *  InstancePtr, 
XQspiPsu_Msg *  Msg, 
unsigned  NumMsg 
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-This function performs a transfer on the bus in polled mode. The messages passed are all transferred on the bus between one CS assert and de-assert.

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Msg is a pointer to the structure containing transfer data. 
NumMsg is the number of messages to be transferred.

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  • XST_FAILURE if transfer fails.
  • XST_DEVICE_BUSY if a transfer is already in progress.

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void XQspiPsu_Reset           (XQspiPsu *  InstancePtr           ) 

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-Resets the QSPIPSU device. Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

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InstancePtr is a pointer to the XQspiPsu instance.

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None. 

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void XQspiPsu_SelectFlash           (XQspiPsu *  InstancePtr, 
u8  FlashCS, 
u8  FlashBus 
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-This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used. This API should be called atleast once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

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InstancePtr is a pointer to the XQspiPsu instance. 
FlashCS - Flash Chip Select. 
FlashBus - Flash Bus (Upper, Lower or Both).

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  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

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If this funciton is not called atleast once in the application, the driver assumes there is a single flash connected to the lower bus and CS line. 

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int XQspiPsu_SetClkPrescaler           (XQspiPsu *  InstancePtr, 
u8  Prescaler 
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-Configures the clock according to the prescaler passed.

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InstancePtr is a pointer to the XQspiPsu instance. 
Prescaler - clock prescaler to be set.

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int XQspiPsu_SetOptions           (XQspiPsu *  InstancePtr, 
u32  Options 
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-This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

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Parameters:

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InstancePtr is a pointer to the XQspiPsu instance. 
Options contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

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  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

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int XQspiPsu_SetReadMode           (XQspiPsu *  InstancePtr, 
u32  Mode 
)

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-This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.

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InstancePtr is a pointer to the XQspiPsu instance. 
Mode contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.

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  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.

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This function is not thread-safe. 

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void XQspiPsu_SetStatusHandler           (XQspiPsu *  InstancePtr, 
void *  CallBackRef, 
XQspiPsu_StatusHandler  FuncPtr 
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-Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

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 XST_SPI_TRANSFER_DONE		The requested data transfer is done

-
 XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
-				but there were none available in the transmit
-				register/FIFO. This typically means the slave
-				application did not issue a transfer request
-				fast enough, or the processor/driver could not
-				fill the transmit register/FIFO fast enough.

-
 XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
-				but the receive data register/FIFO was full.

-
 
 
Parameters:

-  
-    
-    
-    
-  
InstancePtr is a pointer to the XQspiPsu instance. 
CallBackRef is the upper layer callback reference passed back when the callback function is invoked. 
FuncPtr is the pointer to the callback function.

-

-
Returns:
None.

-
Note:

-The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.
-

-

-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__g_8c.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__g_8c.html
deleted file mode 100755
index 26263be9..00000000
--- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__g_8c.html
+++ /dev/null
@@ -1,65 +0,0 @@
-
-
-   
-
-   xqspipsu_g.c File Reference
-
-
-
-
Xilinx Processor IP Library

-Software Drivers
-

-
-

-  

-

-  

-
xqspipsu_g.c File Reference
Detailed Description

-This file contains a configuration table that specifies the configuration of QSPIPSU devices in the system.

-
- MODIFICATION HISTORY:

-
 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------
- 1.0   hk  08/21/14 First release
- 

-

-#include "xqspipsu.h"

-#include "xparameters.h"

-
-
-
-
-
-

Variables
XQspiPsu_Config XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]

-
Variable Documentation

-
-

-

-      
-        
-          
-        
-      
XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]          

-

-

-
-

-Initial value:
 {
-        {
-                XPAR_XQSPIPSU_0_DEVICE_ID,
-                XPAR_XQSPIPSU_0_BASEADDR,
-                XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
-                XPAR_XQSPIPSU_0_QSPI_MODE
-        },
-}
-
This table contains configuration information for each QSPIPSU device in the system.
-

-

-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__hw_8h.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__hw_8h.html
deleted file mode 100755
index e9f009b4..00000000
--- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__hw_8h.html
+++ /dev/null
@@ -1,7679 +0,0 @@
-
-
-   
-
-   xqspipsu_hw.h File Reference
-
-
-
-
Xilinx Processor IP Library

-Software Drivers
-

-
-

-  

-

-  

-
xqspipsu_hw.h File Reference
Detailed Description

-This file contains low level access funcitons using the base address directly without an instance.

-
- MODIFICATION HISTORY:

-
 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------.
- 1.0   hk  08/21/14 First release

-
 

-

-#include "xil_types.h"

-#include "xil_assert.h"

-#include "xil_io.h"

-#include "xparameters.h"

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Defines
#define _XQSPIPSU_HW_H_
#define XQSPIPS_BASEADDR   0XFF0F0000
#define XQSPIPSU_BASEADDR   0xFF0F0100
#define XQSPIPSU_OFFSET   0x100
#define XQSPIPS_EN_REG   ( ( XQSPIPS_BASEADDR ) + 0X00000014 )
#define XQSPIPS_EN_SHIFT   0
#define XQSPIPS_EN_WIDTH   1
#define XQSPIPS_EN_MASK   0X00000001
#define XQSPIPSU_CFG_OFFSET   0X00000000
#define XQSPIPSU_CFG_MODE_EN_SHIFT   30
#define XQSPIPSU_CFG_MODE_EN_WIDTH   2
#define XQSPIPSU_CFG_MODE_EN_MASK   0XC0000000
#define XQSPIPSU_CFG_MODE_EN_DMA_MASK   0X80000000
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK   0X20000000
#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28
#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK   0X10000000
#define XQSPIPSU_CFG_ENDIAN_SHIFT   26
#define XQSPIPSU_CFG_ENDIAN_WIDTH   1
#define XQSPIPSU_CFG_ENDIAN_MASK   0X04000000
#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20
#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1
#define XQSPIPSU_CFG_EN_POLL_TO_MASK   0X00100000
#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19
#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1
#define XQSPIPSU_CFG_WP_HOLD_MASK   0X00080000
#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK   0X00000038
#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2
#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1
#define XQSPIPSU_CFG_CLK_PHA_MASK   0X00000004
#define XQSPIPSU_CFG_CLK_POL_SHIFT   1
#define XQSPIPSU_CFG_CLK_POL_WIDTH   1
#define XQSPIPSU_CFG_CLK_POL_MASK   0X00000002
#define XQSPIPSU_ISR_OFFSET   0X00000004
#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11
#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1
#define XQSPIPSU_ISR_RXEMPTY_MASK   0X00000800
#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10
#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1
#define XQSPIPSU_ISR_GENFIFOFULL_MASK   0X00000400
#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9
#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK   0X00000200
#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8
#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1
#define XQSPIPSU_ISR_TXEMPTY_MASK   0X00000100
#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7
#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK   0X00000080
#define XQSPIPSU_ISR_RXFULL_SHIFT   5
#define XQSPIPSU_ISR_RXFULL_WIDTH   1
#define XQSPIPSU_ISR_RXFULL_MASK   0X00000020
#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4
#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1
#define XQSPIPSU_ISR_RXNEMPTY_MASK   0X00000010
#define XQSPIPSU_ISR_TXFULL_SHIFT   3
#define XQSPIPSU_ISR_TXFULL_WIDTH   1
#define XQSPIPSU_ISR_TXFULL_MASK   0X00000008
#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2
#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1
#define XQSPIPSU_ISR_TXNOT_FULL_MASK   0X00000004
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK   0X00000002
#define XQSPIPSU_ISR_WR_TO_CLR_MASK   0X00000002
#define XQSPIPSU_IER_OFFSET   0X00000008
#define XQSPIPSU_IER_RXEMPTY_SHIFT   11
#define XQSPIPSU_IER_RXEMPTY_WIDTH   1
#define XQSPIPSU_IER_RXEMPTY_MASK   0X00000800
#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10
#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1
#define XQSPIPSU_IER_GENFIFOFULL_MASK   0X00000400
#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9
#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK   0X00000200
#define XQSPIPSU_IER_TXEMPTY_SHIFT   8
#define XQSPIPSU_IER_TXEMPTY_WIDTH   1
#define XQSPIPSU_IER_TXEMPTY_MASK   0X00000100
#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7
#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK   0X00000080
#define XQSPIPSU_IER_RXFULL_SHIFT   5
#define XQSPIPSU_IER_RXFULL_WIDTH   1
#define XQSPIPSU_IER_RXFULL_MASK   0X00000020
#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4
#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1
#define XQSPIPSU_IER_RXNEMPTY_MASK   0X00000010
#define XQSPIPSU_IER_TXFULL_SHIFT   3
#define XQSPIPSU_IER_TXFULL_WIDTH   1
#define XQSPIPSU_IER_TXFULL_MASK   0X00000008
#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2
#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1
#define XQSPIPSU_IER_TXNOT_FULL_MASK   0X00000004
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK   0X00000002
#define XQSPIPSU_IDR_OFFSET   0X0000000C
#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11
#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1
#define XQSPIPSU_IDR_RXEMPTY_MASK   0X00000800
#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10
#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1
#define XQSPIPSU_IDR_GENFIFOFULL_MASK   0X00000400
#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9
#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK   0X00000200
#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8
#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1
#define XQSPIPSU_IDR_TXEMPTY_MASK   0X00000100
#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7
#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK   0X00000080
#define XQSPIPSU_IDR_RXFULL_SHIFT   5
#define XQSPIPSU_IDR_RXFULL_WIDTH   1
#define XQSPIPSU_IDR_RXFULL_MASK   0X00000020
#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4
#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1
#define XQSPIPSU_IDR_RXNEMPTY_MASK   0X00000010
#define XQSPIPSU_IDR_TXFULL_SHIFT   3
#define XQSPIPSU_IDR_TXFULL_WIDTH   1
#define XQSPIPSU_IDR_TXFULL_MASK   0X00000008
#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2
#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1
#define XQSPIPSU_IDR_TXNOT_FULL_MASK   0X00000004
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK   0X00000002
#define XQSPIPSU_IDR_ALL_MASK   0X0FBE
#define XQSPIPSU_IMR_OFFSET   0X00000010
#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11
#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1
#define XQSPIPSU_IMR_RXEMPTY_MASK   0X00000800
#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10
#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1
#define XQSPIPSU_IMR_GENFIFOFULL_MASK   0X00000400
#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9
#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK   0X00000200
#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8
#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1
#define XQSPIPSU_IMR_TXEMPTY_MASK   0X00000100
#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7
#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK   0X00000080
#define XQSPIPSU_IMR_RXFULL_SHIFT   5
#define XQSPIPSU_IMR_RXFULL_WIDTH   1
#define XQSPIPSU_IMR_RXFULL_MASK   0X00000020
#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4
#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1
#define XQSPIPSU_IMR_RXNEMPTY_MASK   0X00000010
#define XQSPIPSU_IMR_TXFULL_SHIFT   3
#define XQSPIPSU_IMR_TXFULL_WIDTH   1
#define XQSPIPSU_IMR_TXFULL_MASK   0X00000008
#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2
#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1
#define XQSPIPSU_IMR_TXNOT_FULL_MASK   0X00000004
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK   0X00000002
#define XQSPIPSU_EN_OFFSET   0X00000014
#define XQSPIPSU_EN_SHIFT   0
#define XQSPIPSU_EN_WIDTH   1
#define XQSPIPSU_EN_MASK   0X00000001
#define XQSPIPSU_TXD_OFFSET   0X0000001C
#define XQSPIPSU_TXD_SHIFT   0
#define XQSPIPSU_TXD_WIDTH   32
#define XQSPIPSU_TXD_MASK   0XFFFFFFFF
#define XQSPIPSU_TXD_DEPTH   32
#define XQSPIPSU_RXD_OFFSET   0X00000020
#define XQSPIPSU_RXD_SHIFT   0
#define XQSPIPSU_RXD_WIDTH   32
#define XQSPIPSU_RXD_MASK   0XFFFFFFFF
#define XQSPIPSU_TX_THRESHOLD_OFFSET   0X00000028
#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0
#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6
#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK   0X0000003F
#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL   0X01
#define XQSPIPSU_RX_THRESHOLD_OFFSET   0X0000002C
#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0
#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6
#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK   0X0000003F
#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL   0X01
#define XQSPIPSU_RXFIFO_THRESHOLD_OPT   32
#define XQSPIPSU_GPIO_OFFSET   0X00000030
#define XQSPIPSU_GPIO_WP_N_SHIFT   0
#define XQSPIPSU_GPIO_WP_N_WIDTH   1
#define XQSPIPSU_GPIO_WP_N_MASK   0X00000001
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET   0X00000038
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK   0X00000020
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK   0X00000018
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK   0X00000007
#define XQSPIPSU_GEN_FIFO_OFFSET   0X00000040
#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0
#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20
#define XQSPIPSU_GEN_FIFO_DATA_MASK   0X000FFFFF
#define XQSPIPSU_SEL_OFFSET   0X00000044
#define XQSPIPSU_SEL_SHIFT   0
#define XQSPIPSU_SEL_WIDTH   1
#define XQSPIPSU_SEL_MASK   0X00000001
#define XQSPIPSU_FIFO_CTRL_OFFSET   0X0000004C
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK   0X00000004
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK   0X00000002
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK   0X00000001
#define XQSPIPSU_GF_THRESHOLD_OFFSET   0X00000050
#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0
#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5
#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK   0X0000001F
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL   0X10
#define XQSPIPSU_POLL_CFG_OFFSET   0X00000054
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK   0X80000000
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK   0X40000000
#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8
#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8
#define XQSPIPSU_POLL_CFG_MASK_EN_MASK   0X0000FF00
#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0
#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8
#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK   0X000000FF
#define XQSPIPSU_P_TO_OFFSET   0X00000058
#define XQSPIPSU_P_TO_VALUE_SHIFT   0
#define XQSPIPSU_P_TO_VALUE_WIDTH   32
#define XQSPIPSU_P_TO_VALUE_MASK   0XFFFFFFFF
#define XQSPIPSU_XFER_STS_OFFSET   0X0000005C
#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0
#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32
#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK   0XFFFFFFFF
#define XQSPIPSU_GF_SNAPSHOT_OFFSET   0X00000060
#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0
#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20
#define XQSPIPSU_GF_SNAPSHOT_MASK   0X000FFFFF
#define XQSPIPSU_RX_COPY_OFFSET   0X00000064
#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8
#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8
#define XQSPIPSU_RX_COPY_UPPER_MASK   0X0000FF00
#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0
#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8
#define XQSPIPSU_RX_COPY_LOWER_MASK   0X000000FF
#define XQSPIPSU_MOD_ID_OFFSET   0X000000FC
#define XQSPIPSU_MOD_ID_SHIFT   0
#define XQSPIPSU_MOD_ID_WIDTH   32
#define XQSPIPSU_MOD_ID_MASK   0XFFFFFFFF
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET   0X00000700
#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30
#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK   0XFFFFFFFC
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET   0X00000704
#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27
#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK   0X1FFFFFFC
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET   0X00000708
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK   0X0000E000
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK   0X00001FE0
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK   0X0000001E
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK   0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET   0X0000070C
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK   0XFE000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK   0X01000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK   0X00800000
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK   0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK   0X003FFC00
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK   0X000003FC
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK   0X00000002
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK   0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL   0x403FFA00
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET   0X00000714
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK   0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK   0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK   0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK   0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK   0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK   0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK   0X00000002
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK   0X000000FC
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET   0X00000718
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK   0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK   0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK   0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK   0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK   0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK   0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK   0X00000002
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET   0X0000071C
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK   0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK   0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK   0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK   0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK   0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK   0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK   0X00000002
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET   0X00000720
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK   0X00000080
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK   0X00000040
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK   0X00000020
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK   0X00000010
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK   0X00000008
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK   0X00000004
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK   0X00000002
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET   0X00000724
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK   0X08000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK   0X07000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK   0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK   0X00380000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK   0X00070000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK   0X0000FFF0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK   0X0000000F
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET   0X00000728
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK   0X00000FFF
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET   0X00000EFC
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK   0XFFFFFFFF
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK   0xFF
#define XQSPIPSU_GENFIFO_DATA_XFER   0x100
#define XQSPIPSU_GENFIFO_EXP   0x200
#define XQSPIPSU_GENFIFO_MODE_SPI   0x400
#define XQSPIPSU_GENFIFO_MODE_DUALSPI   0x800
#define XQSPIPSU_GENFIFO_MODE_QUADSPI   0xC00
#define XQSPIPSU_GENFIFO_MODE_MASK   0xC00
#define XQSPIPSU_GENFIFO_CS_LOWER   0x1000
#define XQSPIPSU_GENFIFO_CS_UPPER   0x2000
#define XQSPIPSU_GENFIFO_BUS_LOWER   0x4000
#define XQSPIPSU_GENFIFO_BUS_UPPER   0x8000
#define XQSPIPSU_GENFIFO_BUS_BOTH   0xC000
#define XQSPIPSU_GENFIFO_BUS_MASK   0xC000
#define XQSPIPSU_GENFIFO_TX   0x10000
#define XQSPIPSU_GENFIFO_RX   0x20000
#define XQSPIPSU_GENFIFO_STRIPE   0x40000
#define XQSPIPSU_GENFIFO_POLL   0x80000
#define XQspiPsu_In32   Xil_In32
#define XQspiPsu_Out32   Xil_Out32
#define XQspiPsu_ReadReg(BaseAddress, RegOffset)   XQspiPsu_In32((BaseAddress) + (RegOffset))
#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue)   XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

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#define _XQSPIPSU_HW_H_          

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#define XQSPIPS_BASEADDR   0XFF0F0000          

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-QSPI Base Address
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-      
#define XQSPIPS_EN_MASK   0X00000001          

-

-

-
-

-
-

-

-
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-        
-          
-        
-      
#define XQSPIPS_EN_REG   ( ( XQSPIPS_BASEADDR ) + 0X00000014 )          

-

-

-
-

-Register: XQSPIPS_EN_REG
-

-

-
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-        
-          
-        
-      
#define XQSPIPS_EN_SHIFT   0          

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-

-
-

-
-

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-
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-          
-        
-      
#define XQSPIPS_EN_WIDTH   1          

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-
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-
-

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-
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-          
-        
-      
#define XQSPIPSU_BASEADDR   0xFF0F0100          

-

-

-
-

-GQSPI Base Address
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK   0X00000038          

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-

-
-

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-

-
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-          
-        
-      
#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3          

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-

-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3          

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-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_CFG_CLK_PHA_MASK   0X00000004          

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-

-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2          

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-
-

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-

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-          
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-      
#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1          

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-

-
-

-
-

-

-
-

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-          
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-      
#define XQSPIPSU_CFG_CLK_POL_MASK   0X00000002          

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-
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-
-

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-
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-          
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#define XQSPIPSU_CFG_CLK_POL_SHIFT   1          

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-

-
-

-
-

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-          
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#define XQSPIPSU_CFG_CLK_POL_WIDTH   1          

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-

-
-

-
-

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-
-

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-          
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#define XQSPIPSU_CFG_EN_POLL_TO_MASK   0X00100000          

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-

-
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#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20          

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#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1          

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-
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#define XQSPIPSU_CFG_ENDIAN_MASK   0X04000000          

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-
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#define XQSPIPSU_CFG_ENDIAN_SHIFT   26          

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#define XQSPIPSU_CFG_ENDIAN_WIDTH   1          

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#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK   0X20000000          

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-

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#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29          

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-

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-      
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1          

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-
-

-
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#define XQSPIPSU_CFG_MODE_EN_DMA_MASK   0X80000000          

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-
-

-
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#define XQSPIPSU_CFG_MODE_EN_MASK   0XC0000000          

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-
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#define XQSPIPSU_CFG_MODE_EN_SHIFT   30          

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-
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-
-

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#define XQSPIPSU_CFG_MODE_EN_WIDTH   2          

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-
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-
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-      
#define XQSPIPSU_CFG_OFFSET   0X00000000          

-

-

-
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-Register: XQSPIPSU_CFG
-

-

-
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-      
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK   0X10000000          

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-

-
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-
-

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#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28          

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-

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-

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-

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#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1          

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-

-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_CFG_WP_HOLD_MASK   0X00080000          

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-

-
-

-
-

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-
-

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-          
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-      
#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19          

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-

-
-

-
-

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-

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-          
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-      
#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1          

-

-

-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_EN_MASK   0X00000001          

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-

-
-

-
-

-

-
-

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-          
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-      
#define XQSPIPSU_EN_OFFSET   0X00000014          

-

-

-
-

-Register: XQSPIPSU_EN_REG
-

-

-
-

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-        
-          
-        
-      
#define XQSPIPSU_EN_SHIFT   0          

-

-

-
-

-
-

-

-
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-          
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-      
#define XQSPIPSU_EN_WIDTH   1          

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-
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-

-
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-          
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-      
#define XQSPIPSU_FIFO_CTRL_OFFSET   0X0000004C          

-

-

-
-

-Register: XQSPIPSU_FIFO_CTRL
-

-

-
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-        
-          
-        
-      
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK   0X00000001          

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-
-

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-          
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#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0          

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-

-
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#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1          

-

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-
-

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-
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-      
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK   0X00000004          

-

-

-
-

-
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-

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-          
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-      
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2          

-

-

-
-

-
-

-

-
-

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-          
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-      
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1          

-

-

-
-

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-

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-          
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-      
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1          

-

-

-
-

-
-

-

-
-

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-        
-          
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-      
#define XQSPIPSU_GEN_FIFO_DATA_MASK   0X000FFFFF          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GEN_FIFO_OFFSET   0X00000040          

-

-

-
-

-Register: XQSPIPSU_GEN_FIFO
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK   0X0000001F          

-

-

-
-

-
-

-

-
-

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-        
-          
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-      
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL   0X10          

-

-

-
-

-
-

-

-
-

-

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-          
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-      
#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5          

-

-

-
-

-
-

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-
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-          
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-      
#define XQSPIPSU_GENFIFO_BUS_BOTH   0xC000          

-

-

-
-

-
-

-

-
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-          
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-      
#define XQSPIPSU_GENFIFO_BUS_LOWER   0x4000          

-

-

-
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-
-

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-      
#define XQSPIPSU_GENFIFO_BUS_MASK   0xC000          

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-

-
-

-
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-          
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-      
#define XQSPIPSU_GENFIFO_BUS_UPPER   0x8000          

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-

-
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-
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-      
#define XQSPIPSU_GENFIFO_CS_LOWER   0x1000          

-

-

-
-

-
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-

-
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-      
#define XQSPIPSU_GENFIFO_CS_UPPER   0x2000          

-

-

-
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-
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-
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-          
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-      
#define XQSPIPSU_GENFIFO_DATA_XFER   0x100          

-

-

-
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-
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-      
#define XQSPIPSU_GENFIFO_EXP   0x200          

-

-

-
-

-
-

-

-
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-          
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-      
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK   0xFF          

-

-

-
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-
-

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-
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-          
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-      
#define XQSPIPSU_GENFIFO_MODE_DUALSPI   0x800          

-

-

-
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-
-

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-      
#define XQSPIPSU_GENFIFO_MODE_MASK   0xC00          

-

-

-
-

-
-

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-      
#define XQSPIPSU_GENFIFO_MODE_QUADSPI   0xC00          

-

-

-
-

-
-

-

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-          
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-      
#define XQSPIPSU_GENFIFO_MODE_SPI   0x400          

-

-

-
-

-
-

-

-
-

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-        
-          
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-      
#define XQSPIPSU_GENFIFO_POLL   0x80000          

-

-

-
-

-
-

-

-
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-

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-          
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-      
#define XQSPIPSU_GENFIFO_RX   0x20000          

-

-

-
-

-
-

-

-
-

-

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-          
-        
-      
#define XQSPIPSU_GENFIFO_STRIPE   0x40000          

-

-

-
-

-
-

-

-
-

-

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-          
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-      
#define XQSPIPSU_GENFIFO_TX   0x10000          

-

-

-
-

-
-

-

-
-

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-          
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-      
#define XQSPIPSU_GF_SNAPSHOT_MASK   0X000FFFFF          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GF_SNAPSHOT_OFFSET   0X00000060          

-

-

-
-

-Register: XQSPIPSU_GF_SNAPSHOT
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GF_THRESHOLD_OFFSET   0X00000050          

-

-

-
-

-Register: XQSPIPSU_GF_THRESHOLD
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_GPIO_OFFSET   0X00000030          

-

-

-
-

-Register: XQSPIPSU_GPIO
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_GPIO_WP_N_MASK   0X00000001          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GPIO_WP_N_SHIFT   0          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_GPIO_WP_N_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_ALL_MASK   0X0FBE          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK   0X00000080          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOFULL_MASK   0X00000400          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK   0X00000200          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_OFFSET   0X0000000C          

-

-

-
-

-Register: XQSPIPSU_IDR
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXEMPTY_MASK   0X00000800          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXFULL_MASK   0X00000020          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXFULL_SHIFT   5          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXNEMPTY_MASK   0X00000010          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXEMPTY_MASK   0X00000100          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXFULL_MASK   0X00000008          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXFULL_SHIFT   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXNOT_FULL_MASK   0X00000004          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK   0X00000080          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOFULL_MASK   0X00000400          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK   0X00000200          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_OFFSET   0X00000008          

-

-

-
-

-Register: XQSPIPSU_IER
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXEMPTY_MASK   0X00000800          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXEMPTY_SHIFT   11          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXFULL_MASK   0X00000020          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXFULL_SHIFT   5          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXNEMPTY_MASK   0X00000010          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXEMPTY_MASK   0X00000100          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXEMPTY_SHIFT   8          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXFULL_MASK   0X00000008          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXFULL_SHIFT   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXNOT_FULL_MASK   0X00000004          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK   0X00000080          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOFULL_MASK   0X00000400          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK   0X00000200          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_OFFSET   0X00000010          

-

-

-
-

-Register: XQSPIPSU_IMR
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXEMPTY_MASK   0X00000800          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXFULL_MASK   0X00000020          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXFULL_SHIFT   5          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXNEMPTY_MASK   0X00000010          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXEMPTY_MASK   0X00000100          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXFULL_MASK   0X00000008          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXFULL_SHIFT   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXNOT_FULL_MASK   0X00000004          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQspiPsu_In32   Xil_In32          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK   0X00000080          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOFULL_MASK   0X00000400          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK   0X00000200          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_OFFSET   0X00000004          

-

-

-
-

-Register: XQSPIPSU_ISR
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXEMPTY_MASK   0X00000800          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXFULL_MASK   0X00000020          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXFULL_SHIFT   5          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXNEMPTY_MASK   0X00000010          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXEMPTY_MASK   0X00000100          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXFULL_MASK   0X00000008          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXFULL_SHIFT   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXFULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXNOT_FULL_MASK   0X00000004          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_ISR_WR_TO_CLR_MASK   0X00000002          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK   0X00000007          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK   0X00000018          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET   0X00000038          

-

-

-
-

-Register: XQSPIPSU_LPBK_DLY_ADJ
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK   0X00000020          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5          

-

-

-
-

-
-

-

-
-

-

-      
-        
-          
-        
-      
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

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#define XQSPIPSU_MOD_ID_MASK   0XFFFFFFFF          

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#define XQSPIPSU_MOD_ID_OFFSET   0X000000FC          

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-
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-Register: XQSPIPSU_MOD_ID
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#define XQSPIPSU_MOD_ID_SHIFT   0          

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#define XQSPIPSU_MOD_ID_WIDTH   32          

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#define XQSPIPSU_OFFSET   0x100          

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#define XQspiPsu_Out32   Xil_Out32          

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#define XQSPIPSU_P_TO_OFFSET   0X00000058          

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-Register: XQSPIPSU_P_TIMEOUT
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#define XQSPIPSU_P_TO_VALUE_MASK   0XFFFFFFFF          

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#define XQSPIPSU_P_TO_VALUE_SHIFT   0          

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#define XQSPIPSU_P_TO_VALUE_WIDTH   32          

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#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK   0X000000FF          

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#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0          

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#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8          

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#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK   0X40000000          

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#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30          

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#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1          

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#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK   0X80000000          

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#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31          

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#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1          

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#define XQSPIPSU_POLL_CFG_MASK_EN_MASK   0X0000FF00          

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#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8          

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#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8          

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#define XQSPIPSU_POLL_CFG_OFFSET   0X00000054          

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-
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-Register: XQSPIPSU_POLL_CFG
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#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK   0XFFFFFFFC          

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#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK   0X00000FFF          

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#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET   0X00000728          

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-Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
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#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0          

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#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12          

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#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET   0X00000700          

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-Register: XQSPIPSU_QSPIDMA_DST_ADDR
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#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2          

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#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK   0X07000000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK   0X0000000F          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET   0X00000724          

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-
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-Register: XQSPIPSU_QSPIDMA_DST_CTRL2
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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK   0X00070000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK   0X00380000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK   0X08000000          

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-
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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1          

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-

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-
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-
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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK   0X00400000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK   0X0000FFF0          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4          

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#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK   0X01000000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK   0X00400000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK   0X00800000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK   0XFE000000          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK   0X000003FC          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET   0X0000070C          

-

-

-
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-Register: XQSPIPSU_QSPIDMA_DST_CTRL
-

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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK   0X00000001          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK   0X00000002          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1          

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-
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#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1          

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-
-

-
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#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL   0x403FFA00          

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-
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#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK   0X003FFC00          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10          

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#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12          

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK   0X00000004          

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2          

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1          

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-

-
-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK   0X00000002          

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-
-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1          

-

-

-
-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1          

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-

-
-

-
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-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK   0X00000080          

-

-

-
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-
-

-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7          

-

-

-
-

-
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-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1          

-

-

-
-

-
-

-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK   0X00000040          

-

-

-
-

-
-

-

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6          

-

-

-
-

-
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-

-
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-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1          

-

-

-
-

-
-

-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET   0X0000071C          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_I_DIS
-

-

-
-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK   0X00000020          

-

-

-
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-
-

-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5          

-

-

-
-

-
-

-

-
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-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK   0X00000010          

-

-

-
-

-
-

-

-
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#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4          

-

-

-
-

-
-

-

-
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-

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1          

-

-

-
-

-
-

-

-
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-

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK   0X00000008          

-

-

-
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-
-

-

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#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3          

-

-

-
-

-
-

-

-
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-

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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1          

-

-

-
-

-
-

-

-
-

-

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-        
-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK   0X00000004          

-

-

-
-

-
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-

-
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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2          

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-
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-          
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#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1          

-

-

-
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-
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-

-
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-        
-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK   0X00000002          

-

-

-
-

-
-

-

-
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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1          

-

-

-
-

-
-

-

-
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-

-      
-        
-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1          

-

-

-
-

-
-

-

-
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-        
-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK   0X00000080          

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-

-
-

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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7          

-

-

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-

-
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-
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-

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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1          

-

-

-
-

-
-

-

-
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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK   0X00000040          

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-

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#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6          

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-

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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1          

-

-

-
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-

-
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-          
-        
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#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET   0X00000718          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_I_EN
-

-

-
-

-

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-        
-          
-        
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#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK   0X00000020          

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-

-
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-
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#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5          

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-

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-

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#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK   0X00000010          

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-

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4          

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK   0X00000008          

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3          

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#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1          

-

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#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK   0X00000004          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK   0X00000002          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1          

-

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-          
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#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK   0X00000080          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7          

-

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#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK   0X00000040          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET   0X00000714          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_I_STS
-

-

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-        
-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK   0X00000020          

-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5          

-

-

-
-

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-          
-        
-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1          

-

-

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-

-

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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK   0X00000010          

-

-

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-

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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4          

-

-

-
-

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-

-

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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1          

-

-

-
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-
-

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-
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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK   0X00000008          

-

-

-
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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3          

-

-

-
-

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-
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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1          

-

-

-
-

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-

-

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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK   0X00000004          

-

-

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-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1          

-

-

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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK   0X00000002          

-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1          

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#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK   0X00000080          

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#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7          

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#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1          

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK   0X00000040          

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#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6          

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#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET   0X00000720          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_IMR
-

-

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-          
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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK   0X00000020          

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5          

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1          

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK   0X00000010          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4          

-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1          

-

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK   0X00000008          

-

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#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK   0X000000FC          

-

-

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-

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#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK   0X1FFFFFFC          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET   0X00000704          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_SIZE
-

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-      
#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2          

-

-

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-

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-      
#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27          

-

-

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-      
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK   0X00000001          

-

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#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0          

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#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1          

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#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK   0X0000E000          

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#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13          

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#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3          

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#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK   0X00001FE0          

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#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5          

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-      
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8          

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#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET   0X00000708          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_DST_STS
-

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-        
-          
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-      
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK   0X0000001E          

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#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1          

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-      
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4          

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-      
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET   0X00000EFC          

-

-

-
-

-Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
-

-

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-

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-        
-          
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-      
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK   0XFFFFFFFF          

-

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-      
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0          

-

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-      
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32          

-

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-

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-          
-          
-          
-          
-          
-          
-          
-          
-        
-      
#define XQspiPsu_ReadReg          (BaseAddress,         
RegOffset            )    XQspiPsu_In32((BaseAddress) + (RegOffset))

-

-

-
-

-Read a register.

-
Parameters:

-  
-    
-    
-  
BaseAddress contains the base address of the device. 
RegOffset contains the offset from the 1st register of the device to the target register.

-

-
Returns:
The value read from the register.

-
Note:
C-Style signature: u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset) 

-
-

-

-
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-      
#define XQSPIPSU_RX_COPY_LOWER_MASK   0X000000FF          

-

-

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-          
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-      
#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0          

-

-

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-      
#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8          

-

-

-
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-          
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-      
#define XQSPIPSU_RX_COPY_OFFSET   0X00000064          

-

-

-
-

-Register: XQSPIPSU_RX_COPY
-

-

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-

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-        
-          
-        
-      
#define XQSPIPSU_RX_COPY_UPPER_MASK   0X0000FF00          

-

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-      
#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8          

-

-

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-      
#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8          

-

-

-
-

-
-

-

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#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK   0X0000003F          

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#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL   0X01          

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#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0          

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#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6          

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#define XQSPIPSU_RX_THRESHOLD_OFFSET   0X0000002C          

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#define XQSPIPSU_RXD_MASK   0XFFFFFFFF          

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#define XQSPIPSU_RXD_OFFSET   0X00000020          

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#define XQSPIPSU_RXD_SHIFT   0          

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#define XQSPIPSU_RXD_WIDTH   32          

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#define XQSPIPSU_RXFIFO_THRESHOLD_OPT   32          

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#define XQSPIPSU_SEL_MASK   0X00000001          

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#define XQSPIPSU_SEL_OFFSET   0X00000044          

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#define XQSPIPSU_SEL_SHIFT   0          

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#define XQSPIPSU_SEL_WIDTH   1          

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#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK   0X0000003F          

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#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL   0X01          

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#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0          

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#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6          

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#define XQSPIPSU_TX_THRESHOLD_OFFSET   0X00000028          

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-Register: XQSPIPSU_TX_THRESHOLD
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#define XQSPIPSU_TXD_DEPTH   32          

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#define XQSPIPSU_TXD_MASK   0XFFFFFFFF          

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#define XQSPIPSU_TXD_OFFSET   0X0000001C          

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-Register: XQSPIPSU_TXD
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#define XQSPIPSU_TXD_SHIFT   0          

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#define XQSPIPSU_TXD_WIDTH   32          

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#define XQspiPsu_WriteReg          (BaseAddress,         
RegOffset,         
RegisterValue            )    XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

-

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-Write to a register.

-
Parameters:

-  
-    
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BaseAddress contains the base address of the device. 
RegOffset contains the offset from the 1st register of the device to target register. 
RegisterValue is the value to be written to the register.

-

-
Returns:
None.

-
Note:
C-Style signature: void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) 

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#define XQSPIPSU_XFER_STS_OFFSET   0X0000005C          

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-Register: XQSPIPSU_XFER_STS
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#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK   0XFFFFFFFF          

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#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0          

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#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32          

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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__options_8c.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__options_8c.html
deleted file mode 100755
index 76f54f48..00000000
--- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__options_8c.html
+++ /dev/null
@@ -1,310 +0,0 @@
-
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-   
-
-   xqspipsu_options.c File Reference
-
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-
Xilinx Processor IP Library

-Software Drivers
-

-
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-  

-

-  

-
xqspipsu_options.c File Reference
Detailed Description

-This file implements funcitons to configure the QSPIPSU component, specifically some optional settings, clock and flash related information.

-
- MODIFICATION HISTORY:

-
 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------
- 1.0   hk  08/21/14 First release
-       sk  03/13/15 Added IO mode support.

-
 

-

-#include "xqspipsu.h"

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Classes
struct  OptionsMap

Defines
#define XQSPIPSU_NUM_OPTIONS   (sizeof(OptionsTable) / sizeof(OptionsMap))

Functions
int XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)
int XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)
u32 XQspiPsu_GetOptions (XQspiPsu *InstancePtr)
int XQspiPsu_SetClkPrescaler (XQspiPsu *InstancePtr, u8 Prescaler)
void XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
int XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)

-
Define Documentation

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#define XQSPIPSU_NUM_OPTIONS   (sizeof(OptionsTable) / sizeof(OptionsMap))          

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Function Documentation

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int XQspiPsu_ClearOptions           (XQspiPsu *  InstancePtr, 
u32  Options 
)

-

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-This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

-
Parameters:

-  
-    
-    
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InstancePtr is a pointer to the XQspiPsu instance. 
Options contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

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Returns:
    
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  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

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Note:
This function is not thread-safe. 

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u32 XQspiPsu_GetOptions           (XQspiPsu *  InstancePtr           ) 

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-This function gets the options for the QSPIPSU device. The options control how the device behaves relative to the QSPIPSU bus.

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Parameters:

-  
-    
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InstancePtr is a pointer to the XQspiPsu instance.

-

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Returns:

-Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.

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Note:
None. 

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void XQspiPsu_SelectFlash           (XQspiPsu *  InstancePtr, 
u8  FlashCS, 
u8  FlashBus 
)

-

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-

-This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used. This API should be called atleast once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

-
Parameters:

-  
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InstancePtr is a pointer to the XQspiPsu instance. 
FlashCS - Flash Chip Select. 
FlashBus - Flash Bus (Upper, Lower or Both).

-

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Returns:
    
-
  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

-

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Note:
If this funciton is not called atleast once in the application, the driver assumes there is a single flash connected to the lower bus and CS line. 

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int XQspiPsu_SetClkPrescaler           (XQspiPsu *  InstancePtr, 
u8  Prescaler 
)

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-Configures the clock according to the prescaler passed.

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Parameters:

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InstancePtr is a pointer to the XQspiPsu instance. 
Prescaler - clock prescaler to be set.

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Returns:
    
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  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

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Note:
None. 

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int XQspiPsu_SetOptions           (XQspiPsu *  InstancePtr, 
u32  Options 
)

-

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-This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

-
Parameters:

-  
-    
-    
-  
InstancePtr is a pointer to the XQspiPsu instance. 
Options contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

-

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Returns:
    
-
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

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Note:
This function is not thread-safe. 

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int XQspiPsu_SetReadMode           (XQspiPsu *  InstancePtr, 
u32  Mode 
)

-

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-This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.

-
Parameters:

-  
-    
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InstancePtr is a pointer to the XQspiPsu instance. 
Mode contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.

-

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Returns:
    
-
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.

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Note:
This function is not thread-safe. 

-
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-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
diff --git a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__sinit_8c.html b/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__sinit_8c.html
deleted file mode 100755
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--- a/XilinxProcessorIPLib/drivers/qspipsu_v1_1/doc/html/api/xqspipsu__sinit_8c.html
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@@ -1,91 +0,0 @@
-
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-   
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-   xqspipsu_sinit.c File Reference
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Xilinx Processor IP Library

-Software Drivers
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-  

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-  

-
xqspipsu_sinit.c File Reference
Detailed Description

-The implementation of the XQspiPsu component's static initialization functionality.

-
- MODIFICATION HISTORY:

-
 Ver   Who Date     Changes
- ----- --- -------- -----------------------------------------------
- 1.0   hk  08/21/14 First release
- 

-

-#include "xstatus.h"

-#include "xqspipsu.h"

-#include "xparameters.h"

-
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Functions
XQspiPsu_Config * XQspiPsu_LookupConfig (u16 DeviceId)

Variables
XQspiPsu_Config XQspiPsu_ConfigTable []

-
Function Documentation

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XQspiPsu_Config* XQspiPsu_LookupConfig           (u16  DeviceId           ) 

-

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-Looks up the device configuration based on the unique device ID. A table contains the configuration info for each device in the system.

-
Parameters:

-  
-    
-  
DeviceId contains the ID of the device to look up the configuration for.

-

-
Returns:

-A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.

-
Note:
None. 

-
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Variable Documentation

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XQspiPsu_Config XQspiPsu_ConfigTable[]          

-

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-This table contains configuration information for each QSPIPSU device in the system.
-

-

-Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.