From ba8cacf8f0357306f7271b84f0e2349c3c1e5a62 Mon Sep 17 00:00:00 2001 From: Kinjal Pravinbhai Patel Date: Fri, 9 Jan 2015 15:00:44 +0530 Subject: [PATCH] BSP: R5: clean up xparamters_ps.h This patch removes the non-required definitions of XPS_*_BASEADDR in xparameters_ps.h Signed-off-by: Kinjal Pravinbhai Patel --- .../standalone/src/cortexr5/xparameters_ps.h | 78 ------------------- 1 file changed, 78 deletions(-) diff --git a/lib/bsp/standalone/src/cortexr5/xparameters_ps.h b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h index 9616644b..1feffe08 100644 --- a/lib/bsp/standalone/src/cortexr5/xparameters_ps.h +++ b/lib/bsp/standalone/src/cortexr5/xparameters_ps.h @@ -118,22 +118,6 @@ extern "C" { #define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID #define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID - -#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR -#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR - - - -/* Canonical definitions for DMAC */ - - -/* Canonical definitions for WDT */ - -/* Canonical definitions for SLCR */ -#define XPAR_XSLCR_NUM_INSTANCES 1U -#define XPAR_XSLCR_0_DEVICE_ID 0U -#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR - /* Canonical definitions for SCU GIC */ #define XPAR_SCUGIC_NUM_INSTANCES 1U #define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U @@ -141,17 +125,6 @@ extern "C" { #define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) #define XPAR_SCUGIC_ACK_BEFORE 0U -/* Canonical definitions for Global Timer */ -#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U -#define XPAR_GLOBAL_TMR_DEVICE_ID 0U -#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) -#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID - - -/* Xilinx Parallel Flash Library (XilFlash) User Settings */ -#define XPAR_AXI_EMC - - #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ @@ -160,59 +133,8 @@ extern "C" { * within the hardblock. These have been put for bacwards compatibilty */ -#define XPS_PERIPHERAL_BASEADDR 0xE0000000U -#define XPS_UART0_BASEADDR 0xFF000000U -#define XPS_UART1_BASEADDR 0xFF010000U -#define XPS_I2C0_BASEADDR 0xFF020000U -#define XPS_I2C1_BASEADDR 0xFF030000U -#define XPS_SPI0_BASEADDR 0xFF040000U -#define XPS_SPI1_BASEADDR 0xFF050000U -#define XPS_CAN0_BASEADDR 0xFF060000U -#define XPS_CAN1_BASEADDR 0xFF070000U -#define XPS_GPIO_BASEADDR 0xFF0A0000U -#define XPS_GEM0_BASEADDR 0xFF0B0000U -#define XPS_GEM1_BASEADDR 0xFF0C0000U -#define XPS_GEM2_BASEADDR 0xFF0D0000U -#define XPS_GEM3_BASEADDR 0xFF0E0000U -#define XPS_QSPI_BASEADDR 0xFF0F0000U -#define XPS_NAND_BASEADDR 0xFF100000U -#define XPS_TTC0_BASEADDR 0xFF110000U -#define XPS_TTC1_BASEADDR 0xFF120000U -#define XPS_TTC2_BASEADDR 0xFF130000U -#define XPS_TTC3_BASEADDR 0xFF140000U -#define XPS_WDT_BASEADDR 0xFF150000U -#define XPS_SDIO0_BASEADDR 0xFF160000U -#define XPS_SDIO1_BASEADDR 0xFF170000U #define XPS_SYS_CTRL_BASEADDR 0xFF180000U -/*#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000U */ - - -#define XPS_PARPORT_CRTL_BASEADDR 0x0000000U -#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U -#define XPS_PARPORT0_BASEADDR 0xE2000000U -#define XPS_PARPORT1_BASEADDR 0xE4000000U -#define XPS_QSPI_LINEAR_BASEADDR 0xF0000000U -#define XPS_DMAC0_NON_SEC_BASEADDR 0xFE507000U -#define XPS_DMAC0_SEC_BASEADDR 0xFE5F0000U -#define XPS_DDR_CTRL_BASEADDR 0xF8006000U -#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U -#define XPS_AFI0_BASEADDR 0xF8008000U -#define XPS_AFI1_BASEADDR 0xF8009000U -#define XPS_AFI2_BASEADDR 0xF800A000U -#define XPS_AFI3_BASEADDR 0xF800B000U -#define XPS_OCM_BASEADDR 0xF800C000U -#define XPS_EFUSE_BASEADDR 0xF800D000U -#define XPS_CORESIGHT_BASEADDR 0xF8800000U -#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U #define XPS_SCU_PERIPH_BASE 0xF9000000U -#define XPS_L2CC_BASEADDR 0xFD3FD000U -#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U -#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U -#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U -#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U -#define XPS_PERIPH_APB_BASEADDR 0xF8000000U -#define XPS_USB0_BASEADDR 0xE0002000U -#define XPS_USB1_BASEADDR 0xE0003000U /* Shared Peripheral Interrupts (SPI) */